ANALOG DEVICES AD9225

Complete 12-Bit, 25 MSPS Monolithic A/D Converter AD9225 FEATURES FUNCTIONAL BLOCK DIAGRAM Monolithic 12-Bit, 25 MSPS ADC CLK AVDD DRVDD Low Power Dissipation: 280 mW Single 5 V Supply SHA VINA MDAC1 MDAC2 MDAC3 No Missing Codes Guaranteed GAIN = 16 GAIN = 4 GAIN = 4 VINB Differential Nonlinearity Error: �0.4 LSB 5 3 3 ADC ADC ADC ADC Complete On-Chip Sample-and-Hold Amplifier and CAPT 5 3 3 4 Voltage Reference CAPB DIGITAL CORRECTION LOGIC Signal-to-Noise and Distortion Ratio: 71 dB 12 VREF Spurious-Free Dynamic Range: –85 dB OUTPUT BUFFERS OTR SENSE Out-of-Range Indicator BIT 1 (MSB) 1V MODE Straight Binary Output Data BIT 12 SELECT AD9225 28-Lead SOIC (LSB) 28-Lead SSOP REFCOM AVSS CML DRVSS Compatible with 3 V Logic A single clock input is used to control all internal conversion GENERAL DESCRIPTION cycles. The digital output data is presented in straight binary The AD9225 is a monolithic, single-supply, 12-bit, 25 MSPS output format. An out-of-range signal indicates an overflow analog-to-digital converter with an on-chip, high performance condition that can be used with the most significant bit to deter- sample-and-hold amplifier and voltage reference. The AD9225 mine low or high overflow. uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 25 MSPS PRODUCT HIGHLIGHTS data rates, and guarantees no missing codes over the full operat- The AD9225 is fabricated on a very cost effective CMOS pro- ing temperature range. cess. High speed precision analog circuits are combined with The AD9225 combines a low cost, high speed CMOS process high density logic circuits. and a novel architecture to achieve the resolution and speed of The AD9225 offers a complete, single-chip sampling, 12-bit, existing bipolar implementations at a fraction of the power 25 MSPS analog-to-digital conversion function in 28-lead consumption and cost. SOIC and SSOP packages. The input of the AD9225 allows for easy interfacing to both Low Power—The AD9225 at 280 mW consumes a fraction of imaging and communications systems. With the device’s truly the power presently available in monolithic solutions. differential input structure, the user can select a variety of input ranges and offsets, including single-ended applications. The On-Board Sample-and-Hold Amplifier (SHA)—The versa- dynamic performance is excellent. tile SHA input can be configured for either single-ended or differential inputs. The sample-and-hold amplifier (SHA) is well suited for both multiplexed systems that switch full-scale voltage levels in succes- Out-of-Range (OTR)—The OTR output bit indicates when sive channels and sampling single-channel inputs at frequencies the input signal is beyond the AD9225’s input range. up to and well beyond the Nyquist rate. Single Supply—The AD9225 uses a single 5 V power supply, The AD9225’s wideband input, combined with the power and simplifying system power supply design. It also features a sepa- cost savings over previously available monolithics, suits applica- rate digital driven supply line to accommodate 3 V and 5 V logic tions in communications, imaging, and medical ultrasound. families. The AD9225 has an on-board programmable reference. An Pin Compatibility—The AD9225 is pin compatible with the external reference can also be chosen to suit the dc accuracy AD9220, AD9221, AD9223, and AD9224 ADCs. and temperature drift requirements of an application. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. 781/461-3113 AD9225–SPECIFICATIONS (AVDD = 5 V, DRVDD = 5 V, f = 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T to T , SAMPLE MIN MAX DC SPECIFICATIONS unless otherwise noted.) Parameter Min Typ Max Unit RESOLUTION 12 Bits MAX CONVERSION RATE 25 MHz INPUT REFERRED NOISE VREF = 1.0 V 0.35 LSB rms VREF = 2.0 V 0.17 LSB rms ACCURACY Integral Nonlinearity (INL) ±1.0 ±2.5 LSB Differential Nonlinearity (DNL) ±0.4 ±1.0 LSB No Missing Codes 12 Bits Guaranteed Zero Error (@ 25∞C) ±0.3 ±0.6 % FSR 1 Gain Error (@ 25∞C) ±0.5 ±2.2 % FSR 2 Gain Error (@ 25∞C) ±0.4 ±1.7 % FSR TEMPERATURE DRIFT Zero Error ±2 ppm/∞C 1 Gain Error ±26 ppm/∞C 2 Gain Error ±0.4 ppm/∞C POWER SUPPLY REJECTION AVDD (+5 V ± 0.25 V) ±0.1 ±0.35 % FSR ANALOG INPUT Input Span 2 V p-p 4V p-p Input (VINA or VINB) Range 0 V AVDD V Input Capacitance 10 pF INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) 1.0 V Output Voltage Tolerance (1 V Mode) ±5 ±17 mV Output Voltage (2.0 V Mode) 2.0 V Output Voltage Tolerance (2.0 V Mode) ±10 ±35 mV Output Current (Available for External Loads) 1.0 mA 3 Load Regulation 1.0 3.4 mV REFERENCE INPUT RESISTANCE 8 kW POWER SUPPLIES Supply Voltages AVDD 4.75 5 5.25 V (±5% AVDD Operating) DRVDD 2.85 5.25 V (±5% DRVDD Operating) Supply Currents IAVDD 65 72.5 mA IDRVDD 2.0 4.0 mA POWER CONSUMPTION External Reference 280 310 mW (VREF = 1 V) 335 373 mW (VREF = 2 V) Internal Reference 290 mW (VREF = 1 V) 345 mW (VREF = 2 V) NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9225). Specifications subject to change without notice. –2– Rev. C AD9225 (AVDD = 5 V, DRVDD = 5 V, f = 25 MSPS, VREF = 2.0 V, T to T , Differential Input unless SAMPLE MIN MAX AC SPECIFICATIONS otherwise noted.) Parameter Min Typ Max Unit SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) f = 2.5 MHz 67.4 70.7 dB INPUT f = 10 MHz 66.7 69.6 dB INPUT SIGNAL-TO-NOISE RATIO (SNR) f = 2.5 MHz 69.0 71 dB INPUT f = 10 MHz 68.2 70 dB INPUT TOTAL HARMONIC DISTORTION (THD) f = 2.5 MHz –82 –72 dB INPUT f = 10 MHz –81 –71.5 dB INPUT SPURIOUS FREE DYNAMIC RANGE f = 2.5 MHz 73 –85 dB INPUT f = 10 MHz 72.5 –83 dB INPUT Full Power Bandwidth 105 MHz Small Signal Bandwidth 105 MHz Aperture Delay 1 ns Aperture Jitter 1 ps rms Acquisition to Full-Scale Step 10 ns Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVDD = 5 V, DRVDD = 5 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage V 3.5 V IH Low Level Input Voltage V 1.0 V IL High Level Input Current (V = DRVDD) I –10 +10 mA IN IH Low Level Input Current (V = 0 V) I –10 +10 mA IN IL Input Capacitance C 5pF IN LOGIC OUTPUTS High Level Output Voltage (I = 50 mA) V 4.5 V OH OH High Level Output Voltage (I = 0.5 mA) V 2.4 V OH OH Low Level Output Voltage (I = 1.6 mA) V 0.4 V OL OL Low Level Output Voltage (I = 50 mA) V 0.1 V OL OL Output Capacitance C 5pF OUT LOGIC OUTPUTS (with DRVDD = 3 V) High Level Output Voltage (I = 50 mA) V 2.95 V OH OH High Level Output Voltage (I = 0.5 mA) V 2.80 V OH OH Low Level Output Voltage (I = 1.6 mA) V 0.4 V OL OL Low Level Output Voltage (I = 50 mA) V 0.05 V OL OL Specifications subject to change without notice. (T to T with AVDD = 5 V, DRVDD = 5 V, C = 20 pF) SWITCHING SPECIFICATIONS MIN MAX L Parameter Symbol Min Typ Max Unit Clock Period* t 40 ns C CLOCK Pulse Width High t 18 ns CH CLOCK Pulse Width Low t 18 ns CL Output Delay t 13 ns OD Pipeline Delay (Latency) 3 Clock Cycles *The clock period may be extended to 1 ms without degradation in specified performance @ 25∞C. Specifications subject to change without notice. –3– Rev. C AD9225 ABSOLUTE MAXIMUM RATINGS* With Pin Name Respect to Min Max Unit AVDD AVSS –0.3 +6.5 V DRVDD DRVSS –0.3 +6.5 V AVSS DRVSS –0.3 +0.3 V AVDD DRVDD –6.5 +6.5 V REFCOM AVSS –0.3 +0.3 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V VINA, VINB AVSS –0.3 AVDD + 0.3 V VREF AVSS –0.3 AVDD + 0.3 V SENSE AVSS –0.3 AVDD + 0.3 V CAPB, CAPT AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 ∞C Storage Temperature –65 +150 ∞C Lead Temperature (10 sec) 300 ∞C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. S1 S2 PIN CONFIGURATION ANALOG S4 t C INPUT 28-Lead SOIC and SSOP S3 t t CH CL INPUT CLOCK CLK DRVDD 1 28 t OD (LSB) BIT 12 2 27 DRVSS DATA DATA 1 OUTPUT BIT 11 3 26 AVDD BIT 10 4 25 AVSS Figure 1. Timing Diagram BIT 9 5 24 VINB BIT 8 6 23 VINA AD9225 BIT 7 7 22 CML TOP VIEW (Not to Scale) BIT 6 8 21 CAPT BIT 5 CAPB 9 20 BIT 4 10 19 REFCOM BIT 3 11 18 VREF BIT 2 12 17 SENSE (MSB) BIT 1 13 16 AVSS OTR 14 15 AVDD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9225 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– Rev. C AD9225 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Description 1 CLK Clock Input Pin 2BIT 12 Least Significant Data Bit (LSB) 3–12 BIT 11–2 Data Output Bit 13 BIT 1 Most Significant Data Bit (MSB) 14 OTR Out of Range 15, 26 AVDD 5 V Analog Supply 16, 25 AVSS Analog Ground 17 SENSE Reference Select 18 VREF Input Span Select (Reference I/O) 19 REFCOM Reference Common (AVSS) 20 CAPB Noise Reduction Pin 21 CAPT Noise Reduction Pin 22 CML Common-Mode Level (Midsupply) 23 VINA Analog Input Pin (+) 24 VINB Analog Input Pin (–) 27 DRVSS Digital Output Driver Ground 28 DRVDD 3 V to 5 V Digital Output Driver Supply Aperture Delay TERMINOLOGY Aperture delay is a measure of the sample-and-hold amplifier Integral Nonlinearity (INL) (SHA) performance and is measured from the rising edge of the INL refers to the deviation of each individual code from a line clock input to when the input signal is held for conversion. drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first Signal-to-Noise and Distortion Ratio (S/N+D, SINAD) code transition. Positive full scale is defined as a level 1 1/2 LSB S/N+D is the ratio of the rms value of the measured input beyond the last code transition. The deviation is measured from signal to the rms sum of all other spectral components below the middle of each particular code to the true straight line. the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB Effective Number of Bits (ENOB) apart. DNL is the deviation from this ideal value. Guaranteed For a sine wave, SINAD can be expressed in terms of the num- no missing codes to 12-bit resolution indicates that all 4096 ber of bits. Using the following formula, codes, respectively, must be present over all operating ranges. N = (SINAD – 1.76)/6.02 Zero Error it is possible to get a measure of performance expressed as N, The major carry transition should occur for an analog value the effective number of bits. 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. The effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its mea- Gain Error sured SINAD. The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an Total Harmonic Distortion (THD) analog value 1 1/2 LSB below the nominal full scale. Gain error THD is the ratio of the rms sum of the first six harmonic com- is the deviation of the actual difference between first and last ponents to the rms value of the measured input signal and is code transitions and the ideal difference between first and last expressed as a percentage or in decibels. code transitions. Signal-to-Noise Ratio (SNR) Temperature Drift SNR is the ratio of the rms value of the measured input signal to The temperature drift for zero error and gain error specifies the the rms sum of all other spectral components below the Nyquist maximum change from the initial (25∞C) value to the value at frequency, excluding the first six harmonics and dc. The value T or T . MIN MAX for SNR is expressed in decibels. Power Supply Rejection Spurious-Free Dynamic Range (SFDR) The specification shows the maximum change in full scale from SFDR is the difference in dB between the rms amplitude of the the value with the supply at the minimum limit to the value with input signal and the peak spurious signal. the supply at its maximum limit. Aperture Jitter Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC. –5– Rev. C AD9225–Typical Performance Characteristics (AVDD, DRVDD = 5 V, f = 25 MHz (50% Duty Cycle), unless otherwise noted.) S 2.00 1.00 1.50 0.75 1.00 0.50 0.50 0.25 0 0.00 �0.50 –0.25 �1.00 –0.50 �1.50 –0.75 �2.00 –1.00 04 511 1022 1533 2044 2555 3066 3577095 0 511 1022 1533 2044 2555 3066 3577 4095 TITLE Title TPC 1. Typical DNL TPC 4. Typical INL 70 75 �0.5dB INT 1V �0.5dB 2V INT REF 70 65 �6dB 2V INT REF �6dB INT 1V 65 60 55 60 �20dB INT 1V 55 50 �20dB 2V INT REF 45 50 1 10 1 10 FREQUENCY (MHz) FREQUENCY (MHz) TPC 2. SINAD vs. Input Frequency (Input Span = 4.0 V p-p, TPC 5. SINAD vs. Input Frequency (Input Span = 2 V p-p V = 2.5 V Differential Input) V = 2.5 V Differential Input) CM CM –60 –60 �20dB INT 1V –65 –65 �20.0dB 2V INT REF –70 –70 –75 –75 �6dB INT 1V �6.0dB 2V INT REF –80 –80 �0.5dB INT 1V �0.5dB 2V INT REF –85 –85 1 10 1 10 FREQUENCY (MHz) FREQUENCY (MHz) TPC 3. THD vs. Input Frequency (Input Span = 4.0 V p-p, TPC 6. THD vs. Input Frequency (Input Span = 2 V p-p, V = 2.5 V Differential Input) V = 2.5 V Differential Input) CM CM –6– Rev. C Title THD (dB) SINAD (dB) THD (dB) SINAD (dB) AD9225 90 –70 80 SFDR INT 2V REF –75 70 60 –80 SNR INT 2V REF INT 1V REF 50 –85 INT 2V REF 40 30 –90 –40 –35 –30 –25 –20 –15 –10 –5 0 10 A (dB) IN FREQUENCY (MHz) TPC 7. SNR/SFDR vs. A (Input Amplitude) IN TPC 10. THD vs. Sample Rate, (A = –0.5 dB, IN (f = 12.5 MHz, Input Span = 4.0 V p-p, V = 2.5 V IN CM V = 2.5 V, Input Span = 4.0 V p-p Differential Input) CM Differential Input) –65 75 �20.0dB 2V INT REF �0.5dB 2V INT REF –70 70 �6.0dB 2V INT REF –75 65 �6.0dB 2V INT REF –80 60 �0.5dB 2V INT REF –85 55 �20.0dB 2V INT REF –90 50 10 1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) TPC 8. THD vs. Input Frequency (Input Span = TPC 11. SNR vs. Input Frequency (Input Span = 4.0 V p-p, V = 2.5 V Single-Ended Input) 4.0 V p-p, V = 2.5 V Single-Ended Input) CM CM 246447 3299 4206 N – 1 N N + 1 B IN TPC 9. Grounded-Input Histogram (Input Span = 40 V p-p) –7– Rev. C SNR AND SFDR (dBFS) THD (dB) H ITS THD (dB) SNR (dB) AD9225 INTRODUCTION the difference of the voltages applied at the VINA and VINB The AD9225 is a high performance, complete single-supply input pins. Therefore, the equation 12-bit ADC. The analog input range of the AD9225 is highly VCORE = VINA – VINB (1) flexible, allowing for both single-ended or differential inputs defines the output of the differential input stage and provides of varying amplitudes that can be ac-coupled or dc-coupled. the input to the ADC core. The AD9225 utilizes a four-stage pipeline architecture with a The voltage, VCORE, must satisfy the condition wideband input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, –VREF £ VCORE £ VREF (2) excluding the last stage, consists of a low resolution flash ADC where VREF is the voltage at the VREF pin. connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the differ- While an infinite combination of VINA and VINB inputs exist ence between the reconstructed DAC output and the flash input that satisfy Equation 2, there is an additional limitation placed for the next stage in the pipeline. One bit of redundancy is used on the inputs by the power supply voltages of the AD9225. The in each of the stages to facilitate digital correction of flash errors. power supplies bound the valid operating range for VINA and The last stage simply consists of a flash ADC. VINB. The condition The pipeline architecture allows a greater throughput rate at the AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) expense of pipeline delay or latency. This means that while the AVSS – 0.3 V < VINB < AVDD + 0.3 V converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to where AVSS is nominally 0 V and AVDD is nominally 5 V, be fully processed and appear at the output. This latency is not defines this requirement. The range of valid inputs for VINA a concern in most applications. The digital output, together and VINB is any combination that satisfies both Equations with the out-of-range indicator (OTR), is latched into an 2 and 3. output buffer to drive the output pins. The output drivers of For additional information showing the relationships among the AD9225 can be configured to interface with 5 V or 3.3 V VINA, VINB, VREF, and the digital output of the AD9225, see logic families. Table IV. The AD9225 uses both edges of the clock in its internal timing Refer to Table I and Table II at the end of this section for a sum- circuitry (see Figure 1 and Specifications tables for exact timing mary of the various analog input and reference configurations. requirements). The ADC samples the analog input on the rising edge of the clock input. During the clock low time (between the ANALOG INPUT OPERATION falling edge and rising edge of the clock), the input SHA is in Figure 3 shows the equivalent analog input of the AD9225, the sample mode; during the clock high time it is in hold mode. which consists of a differential sample-and-hold amplifier. The System disturbances just prior to the rising edge of the clock differential input structure of the SHA is highly flexible, allow- and/or excessive clock jitter may cause the input SHA to acquire ing the devices to be easily configured for either a differential or the wrong value, and should be minimized. single-ended input. The dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single-supply or ANALOG INPUT AND REFERENCE OVERVIEW dual-supply systems. Also, note that the analog inputs, VINA Figure 2 is a simplified model of the AD9225. It highlights the and VINB, are interchangeable, with the exception that revers- relationship between the analog inputs, VINA and VINB, and the ing the inputs to the VINA and VINB pins results in a polarity reference voltage, VREF. Like the voltage applied to the top of inversion. the resistor ladder in a flash ADC, the value VREF defines the maximum input voltage to the ADC core. The minimum input C H voltage to the ADC core is automatically defined to be –VREF. Q S2 + C PIN AD9225 Q C S S1 C PAR VINA +VREF VINA Q C Q H1 S S1 V 12 CORE ADC VINB CORE – C PIN Q S2 C PAR –VREF VINB C H Figure 2. Equivalent Functional Input Circuit Figure 3. Simplified Input Circuit The addition of a differential input structure gives the user an The AD9225 has a wide input range. The input peaks may be additional level of flexibility that is not possible with traditional moved to AVDD or AVSS before performance is compromised. flash converters. The input stage allows the user to easily config- This allows for much greater flexibility when selecting single- ure the inputs for either single-ended operation or differential ended drive schemes. Op amps and ac coupling clamps can be operation. The A/D converter’s input structure allows the dc set to available reference levels rather than be dictated according offset of the input signal to be varied independently of the input to what the ADC needs. span of the converter. Specifically, the input to the ADC core is –8– Rev. C AD9225 V CC Due to the high degree of symmetry within the SHA topology, a AD9225 significant improvement in distortion performance for differen- R S VINA tial input signals with frequencies up to and beyond Nyquist can R S be realized. This inherent symmetry provides excellent cancella- VINB V tion of both common-mode distortion and noise. Also, the EE VREF required input signal voltage span is reduced by a half, which 10�F 0.1�F further reduces the degree of R modulation and its effects ON SENSE on distortion. REFCOM The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest Figure 4. Series Resistor Isolates Switched Capacitor input signal voltage span (i.e., 4 V input span) and matched SHA Input from Op Amp. Matching Resistors Improve input impedance for VINA and VINB. Only a slight degrada- SNR Performance. tion in dc linearity performance exists between the 2 V and 4 V The optimum size of this resistor is dependent on several fac- input spans. tors, which include the ADC sampling rate, the selected op Referring to Figure 3, the differential SHA is implemented amp, and the particular application. In most applications, a using a switched capacitor topology. Its input impedance and its 30 W to 100 W resistor is sufficient. However, some applica- switching effects on the input drive source should be considered tions may require a larger resistor value to reduce the noise in order to maximize the converter’s performance. The combi- bandwidth or possibly to limit the fault current in an overvolt- nation of the pin capacitance, C , parasitic capacitance, C , PIN PAR age condition. Other applications may require a larger resistor and the sampling capacitance, C , is typically less than 5 pF. S value as part of an antialiasing filter. In any case, since the THD When the SHA goes into track mode, the input source must performance is dependent on the series resistance and the above charge or discharge the voltage stored on C to the new input S mentioned factors, optimizing this resistor value for a given voltage. This action of charging and discharging C , averaged S application is encouraged. over a period of time and for a given sampling frequency, f , S The source impedance driving VINA and VINB should be makes the input impedance appear to have a benign resistive matched. Failure to provide that matching will result in degra- component. However, if this action is analyzed within a sampling dation of the AD9225’s superb SNR, THD, and SFDR. period (i.e., T = 1/f ), the input impedance is dynamic and S therefore certain precautions on the input drive source should For noise sensitive applications, the very high bandwidth of the be observed. AD9225 may be detrimental. The addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the The resistive component to the input impedance can be com- ADC’s input by forming a low-pass filter. Note, however, that puted by calculating the average charge that gets drawn by C H the combination of this series resistance with the equivalent from the input drive source. It can be shown that if C is al- S input capacitance of the AD9225 should be evaluated for lowed to fully charge up to the input voltage before switches those time domain applications that are sensitive to the input Q are opened, then the average current into the input would S1 signal’s absolute settling time. In applications where harmonic be the same as it would if there were a resistor of 1/(C f ) Ohms S S distortion is not a primary concern, the series resistance may be connected between the inputs. This means that the input im- selected in combination with the SHA’s nominal 10 pF of input pedance is inversely proportional to the converter’s sample capacitance to set the filter’s 3 dB cutoff frequency. rate. Since C is only 5 pF, this resistive component is typically S much larger than that of the drive source (i.e., 8 kW at f = S A better method of reducing the noise bandwidth, while possi- 25 MSPS). bly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., The SHA’s input impedance over a sampling period appears as VINA and/or VINB) and analog ground. Since this additional a dynamic input impedance to the input drive source. When the shunt capacitance combines with the equivalent input capaci- SHA goes into the track mode, the input source ideally should tance of the AD9225, a lower series resistance can be selected to provide the charging current through R of switch Q in an ON S1 establish the filter’s cutoff frequency while not degrading the exponential manner. The requirement of exponential charging distortion performance of the device. The shunt capacitance means that the most common input source, an op amp, must also acts like a charge reservoir, sinking or sourcing the addi- exhibit a source impedance that is both low and resistive up to tional charge required by the hold capacitor, C , and further and beyond the sampling frequency. H reducing current transients seen at the op amp’s output. The output impedance of an op amp can be modeled with a The effect of this increased capacitive load on the op amp driv- series inductor and resistor. When a capacitive load is switched ing the AD9225 should be evaluated. To optimize performance onto the output of the op amp, the output will momentarily when noise is the primary consideration, increase the shunt drop due to its effective output impedance. As the output recov- capacitance as much as the transient response of the input signal ers, ringing may occur. To remedy the situation, a series resistor will allow. Increasing the capacitance too much may adversely can be inserted between the op amp and the SHA input as affect the op amp’s settling time, frequency response, and dis- shown in Figure 4. The series resistance helps isolate the op tortion performance. amp from the switched capacitor load. –9– Rev. C AD9225 REFERENCE OPERATION The actual reference voltages used by the internal circuitry of The AD9225 contains an on-board band gap reference that the AD9225 appears on the CAPT and CAPB pins. For proper provides a pin strappable option to generate either a 1 V or 2 V operation when using the internal or an external reference, it is output. With the addition of two external resistors, the user can necessary to add a capacitor network to decouple these pins. generate reference voltages other than 1 V and 2 V. Another Figure 6 shows the recommended decoupling network. This alternative is to use an external reference for designs requiring capacitive network performs the following three functions: (1) enhanced accuracy and/or drift performance. See Table II for along with the reference amplifier, A2, it provides a low source a summary of the pin strapping options for the AD9225 refer- impedance over a large frequency range to drive the ADC inter- ence configurations. nal circuitry, (2) it provides the necessary compensation for A2, and (3) it bandlimits the noise contribution from the reference. Figure 5 shows a simplified model of the internal voltage The turn-on time of the reference voltage appearing between reference of the AD9225. A pin strappable reference amplifier CAPT and CAPB is approximately 15 ms and should be evalu- buffers a 1 V fixed reference. The output from the reference ated in any power-down mode of operation. amplifier, A1, appears on the VREF pin. The voltage on the VREF pin determines the full-scale input span of the ADC. 0.1�F This input span equals CAPT Full-Scale Input Span = 2 ¥ VREF 0.1�F 10�F AD9225 CAPB The voltage appearing at the VREF pin as well as the state of 0.1�F the internal reference amplifier, A1, are determined by the volt- age appearing at the SENSE pin. The logic circuitry contains Figure 6. Recommended CAPT/CAPB two comparators that monitor the voltage at the SENSE pin. Decoupling Network The comparator with the lowest set point (approximately 0.3 V) The ADC’s input span may be varied dynamically by changing the controls the position of the switch within the feedback path of differential reference voltage appearing across CAPT and CAPB A1. If the SENSE pin is tied to AVSS (AGND), the switch is symmetrically around 2.5 V (i.e., midsupply). To change the refer- connected to the internal resistor network thus providing a ence at speeds beyond the capabilities of A2, it will be necessary to VREF of 2.0 V. If the SENSE pin is tied to the VREF pin via drive CAPT and CAPB with two high speed, low noise amplifiers. a short or resistor, the switch will connect to the SENSE pin. In this case, both internal amplifiers (i.e., A1 and A2) must be This short will provide a VREF of 1.0 V. An external resistor disabled by connecting SENSE to AVDD, connecting VREF to network will provide an alternative VREF between 1.0 V and AVSS and removing the capacitive decoupling network. The exter- 2.0 V. The other comparator controls internal circuitry that will nal voltages applied to CAPT and CAPB must be 2.0 V + Input disable the reference amplifier if the SENSE pin is tied AVDD. Span/4 and 2.0 V – Input Span/4, respectively, in which the input Disabling the reference amplifier allows the VREF pin to be span can be varied between 2 V and 4 V. Note that those samples driven by an external voltage reference. within the pipeline ADC during any reference transition will be corrupted and should be discarded. AD9225 TO A/D DRIVING THE ANALOG INPUTS 5k� The AD9225 has a highly flexible input structure allowing it to CAPT 5k� interface with single ended or differential input interface cir- A2 cuitry. The applications shown in this section and the Reference 5k� CAPB Configurations section along with the information presented in 5k� the Input and Reference Overview give examples of single- DISABLE LOGIC A2 ended and differential operation. Refer to Tables I and II for a list of the different possible input and reference configurations VREF and their associated figures in the data sheet. A1 1V 6.25k� The optimum mode of operation, analog input range, and asso- ciated interface circuitry will be determined by the particular SENSE DISABLE applications performance requirements as well as power supply LOGIC 6.25k� A1 options. For example, a dc-coupled single-ended input would REFCOM be appropriate for most data acquisition and imaging applica- tions. Many communication applications, which require a Figure 5. Equivalent Reference Circuit dc-coupled input for proper demodulation, can take advantage of the excellent single-ended distortion performance of the AD9225. The input span should be configured so the system’s performance objectives and the headroom requirements of the driving op amp are simultaneously met. –10– Rev. C AD9225 Table I. Analog Input Configuration Summary Input Input Input Range (V) Figure Connection Coupling Span (V) VINA* VINB* No. Comments Single-Ended DC 2 0 to 2 1 8, 9 Best for stepped input response applications; requires ±5 V op amp. 2 ¥ VREF 0 to VREF 8, 9 Same as above but with improved noise 2 ¥ VREF performance due to increase in dynamic range. Headroom/settling time requirements of ±5 V op amp should be evaluated. 40 to 4 2.0 8, 9 Optimum noise performance, excellent THD performance, often requires low distortion op amp with VCC > +5 V due to its headroom issues. 2 ¥ VREF 2.0 – VREF 2.0 21 Optimum THD performance with VREF = 1. to Single-supply operation (i.e., +5 V) for many 2.0 + VREF op amps. Single-Ended AC 2 or 0 to 1 or 1 or VREF 10, 11 2 ¥ VREF 0 to 2 ¥ VREF 4 0.5 to 4.5 2.0 11 Optimum noise performance, excellent THD performance; ability to use ±5 V op amp. 2 ¥ VREF 2.0 – VREF 2.0 10 Flexible input range, optimum THD perfor- to mance with VREF = 1. Ability to use either 2.0 + VREF +5 V or ±5 V op amp. Differential AC/DC 2 2 to 3 3 to 2 12, 13 Optimum full-scale THD and SFDR perfor- (via Transformer) mance well beyond the ADC’s Nyquist or Amplifier frequency. Preferred mode for under- sampling applications. 2 ¥ VREF 2.0 – VREF/2 2.0 + VREF/2 12, 13 Same as above with the exception that full- to to scale THD and SFDR performance can be 2.0 + VREF/2 2.0 – VREF/2 traded off for better noise performance. 4.0 1.5 to 3.5 3.5 to 1.5 12, 13 Optimum noise performance. *VINA and VINB can be interchanged if signal inversion is required. Table II. Reference Configuration Summary Reference Input Span (VINA–VINB) Operating Mode (V p-p) Required VREF (V) Connect To Internal 2 1 SENSE VREF Internal 4 2 SENSE REFCOM Internal 2 £ SPAN £ 4 and 1 £ VREF £ 2.0 and R1 VREF and SENSE SPAN = 2 � VREF VREF = (1 + R1/R2) R2 SENSE and REFCOM External 2 £ SPAN £ 41 £ VREF £ 2.0 SENSE AVDD (Nondynamic) VREF External Reference External 2 £ SPAN £ 4 CAPT and CAPB SENSE AVDD (Dynamic) Externally Driven VREF AVSS External Reference CAPT External Reference CAPB –11– Rev. C AD9225 Differential modes of operation (ac-coupled or dc-coupled input) Single-ended operation is often limited by the availability of driving provide the best THD and SFDR performance over a wide fre- op amps. Very low distortion op amps that provide great perfor- quency range. Differential operation should be considered for the mance out to the Nyquist frequency of the converter are hard to most demanding spectral based applications (e.g., direct IF-to- find. Compounding the problem, for dc-coupled, single-ended digital conversion). See Figures 12 and 13 and the Differential applications, is the inability of many high performance amplifiers Mode of Operation section. Differential input characterization was to maintain low distortions as their outputs approach their positive performed for this data sheet using the configuration shown in output voltage limit (i.e., 1 dB compression point). For this reason, Figure 13. it is recommended that applications requiring high performance dc coupling use the single-ended-to-differential circuit shown in Single-ended operation requires that VINA be ac-coupled or dc- Figure 12. coupled to the input signal source while VINB of the AD9225 be biased to the appropriate voltage corresponding to a midscale code DC COUPLING AND INTERFACE ISSUES transition. Note that signal inversion may be easily accomplished Many applications require the analog input signal to be dc-coupled by transposing VINA and VINB. Most of the single-ended specifi- to the AD9225. An operational amplifier can be configured to cations for the AD9225 are characterized using Figure 21 circuitry rescale and level shift the input signal so that it is compatible with with input spans of 4 V and 2 V as well as VINB = 2.5 V. the selected input range of the ADC. The input range to the ADC Differential operation requires that VINA and VINB be simulta- should be selected on the basis of system performance objectives, neously driven with two equal signals that are in and out of phase as well as the analog power supply availability since this will place versions of the input signal. Differential operation of the AD9225 certain constraints on the op amp selection. offers the following benefits: (1) Signal swings are smaller and, Many of the new high performance op amps are specified for only therefore, linearity requirements placed on the input signal source ±5 V operation and have limited input/output swing capabilities. may be easier to achieve, (2) Signal swings are smaller and there- The selected input range of the AD9225 should be considered with fore may allow the use of op amps which may otherwise have been the headroom requirements of the particular op amp to prevent constrained by headroom limitations, (3) Differential operation clipping of the signal. Since the output of a dual supply amplifier minimizes even-order harmonic products, and (4) Differential can swing below –0.3 V, clamping its output should be considered operation offers noise immunity based on the device’s common- in some applications. mode rejection. In some applications, it may be advantageous to use an op amp As is typical of most IC devices, exceeding the supply limits will specified for single-supply +5 V operation since it will inherently turn on internal parasitic diodes resulting in transient currents limit its output swing to within the power supply rails. Amplifiers within the device. Figure 7 shows a simple means of clamping an like the AD8041 and AD8011 are useful for this purpose but their ac-coupled or dc-coupled single-ended input with the addition of low bandwidths will limit the AD9225’s performance. High perfor- two series resistors and two diodes. An optional capacitor is shown mance amplifiers, such as the AD9631, AD9632, AD8056, or for ac-coupled applications. Note that a larger series resistor could AD8055, allow the AD9225 to be configured for larger input spans be used to limit the fault current through D1 and D2 but should which will improve the ADC’s noise performance. be evaluated since it can cause a degradation in overall perfor- mance. A similar clamping circuit could also be used for each input Op amp circuits using a noninverting and inverting topology are if a differential input signal is being applied. The diodes might discussed in the next section. Although not shown, the non- cause nonlinearities in the signal. Careful evaluation should be inverting and inverting topologies can be easily configured as part performed on the diodes used. of an antialiasing filter by using a Sallen-Key or multiple-feedback topology. An additional R-C network can be inserted between the OPTIONAL op amp output and the AD9225 input to provide a filter pole. AC COUPLING AVDD V CAPACITOR CC Simple Op Amp Buffer D2 R R S1 S2 1N4148 30� 20� In the simplest case, the input signal to the AD9225 will already be AD9225 biased at levels in accordance with the selected input range. It is D1 1N4148 simply necessary to provide an adequately low source impedance V EE for the VINA and VINB analog pins of the ADC. Figure 8 shows the recommended configuration a single-ended drive using an op Figure 7. Simple Clamping Circuit amp. In this case, the op amp is shown in a noninverting unity gain configuration driving the VINA pin. The internal reference drives SINGLE-ENDED MODE OF OPERATION the VINB pin. Note that the addition of a small series resistor of The AD9225 can be configured for single-ended operation using 30 W to 50 W connected to VINA and VINB will be beneficial in dc-coupling or ac-coupling. In either case, the input of the ADC nearly all cases. Refer to the Analog Input Operation section on a must be driven from an operational amplifier that will not degrade discussion on resistor selection. Figure 8 shows the proper connec- the ADC’s performance. Because the ADC operates from a single tion for a 0 V to 4 V input range. Alternative single-ended ranges supply, it will be necessary to level shift ground based bipolar of 0 V to 2 ¥ VREF can also be realized with the proper configura- signals to comply with its input requirements. Both dc and ac tion of VREF (refer to the Using the Internal Reference section). coupling provide this necessary function, but each method results Headroom limitations of the op amp must always be considered. in different interface issues that may influence the system design and performance. –12– Rev. C AD9225 +V impedance over a wide frequency range. The combination of the 4V AD9225 R capacitor and the resistor form a high-pass filter with a high-pass – S 0V U1 VINA 3 dB frequency determined by the equation R S VINB f = 1/(2 ¥ � ¥ R ¥ (C1 + C2)) –3 dB –V 2.0V VREF The low impedance VREF voltage source biases both the VINB 10�F 0.1�F input and provides the bias voltage for the VINA input. Figure 10 SENSE shows the VREF configured for 2.0 V thus the input range of the ADC is 0 V to 4 V. Other input ranges could be selected by chang- Figure 8. Single-Ended AD9225 Op Amp Drive Circuit ing VREF. Op Amp with DC Level Shifting C1 Figure 9 shows a dc-coupled level shifting circuit employing an op +V +V 10�F +5V amp, A1, to sum the input signal with the desired dc set. Configur- 4.5 +2V 2.5 R R AD9225 AD9631 ing the op amp in the inverting mode with the given resistor values R V 0V IN S 0.5 –2V VINA results in an ac signal gain of –1. If the signal inversion is undesir- C2 able, interchange the VINA and VINB connections to re-establish 0.1�F –5V R S the original signal polarity. The dc voltage at VREF sets the VINB common-mode voltage of the AD9225. For example, when R R 0.1�F 10�F VREF = 2.0 V, the input level from the op amp will also be cen- tered around 2.0 V. The use of ratio matched, thin-film resistor networks will minimize gain and offset errors. Also, an optional Figure 10. AC-Coupled Input pull-up resistor, RP, may be used to reduce the output load on Alternative AC Interface VREF to less than its 1 mA maximum. Figure 11 shows a flexible ac-coupled circuit that can be config- ured for different input spans. Since the common-mode voltage of 500�* VINA and VINB are biased to midsupply independent of VREF, +V CC VREF can be pin strapped or reconfigured to achieve input spans 0.1�F between 2 V and 4 V p-p. The AD9225’s CMRR along with the NC symmetrical coupling R-C networks will reject both power supply +VREF 500�* 7 0V DC 2 variations and noise. The resistors, R, establish the common-mode –VREF 1 R S 6 voltage. They may have a high value (e.g., 5 kW) to minimize A1 VINA R ** P 500�* 5 power consumption and establish a low cutoff frequency. The 3 +V 4 capacitors, C1 and C2, are typically a 0.1 mF ceramic and 10 mF 0.1�F 500�* AD9225 NC tantalum capacitor in parallel to achieve a low cutoff frequency R S while maintaining a low impedance over a wide frequency range. VREF VINB R isolates the buffer amplifier from the ADC input. The optimum S *OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D performance is achieved when VINA and VINB are driven via **OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE symmetrical networks. The f point can be approximated by –3 dB Figure 9. Single-Ended Input with DC-Coupled Level Shift the equation 1 AC COUPLING AND INTERFACE ISSUES f = –3dB For applications where ac coupling is appropriate, the op amp 2p¥6K +(C1+ C2) output can be easily level-shifted via a coupling capacitor. This has C2 the advantage of allowing the op amp common-mode level to be 0.1�F symmetrically biased to its midsupply level (i.e., (V + V )/2). CC EE AD9225 R V S Op amps that operate symmetrically with respect to their power IN VINA supplies typically provide the best ac performance as well as great- C1 1k� 10�F est input/output span. Various high speed/performance amplifiers VCM which are restricted to +5 V/–5 V operation and/or specified for C3 0.1�F 1k� +5 V single-supply operation can be easily configured for the 4 V R S VINB or 2 V input span of the AD9225. Note that differential trans- C1 C2 10�F 0.1�F former coupling, which is another form of ac coupling, should be considered for optimum ac performance. Figure 11. AC-Coupled Input-Flexible Input Span, Simple AC Interface V = 2.5 V CM Figure 10 shows a typical example of an ac-coupled, single-ended configuration. The bias voltage shifts the bipolar, ground-refer- enced input signal to approximately AVDD/2. The value for C1 and C2 will depend on the size of the resistor, R. The capacitors, C1 and C2, are a 0.1 mF ceramic and 10 mF tantalum capacitor in parallel to achieve a low cutoff frequency while maintaining a low –13– Rev. C AD9225 500� OP AMP SELECTION GUIDE 500� Op amp selection for the AD9225 is highly dependent on the 50� VREF particular application. In general, the performance requirements of VINA 500� 0V any given application can be characterized by either time domain 500� or frequency domain parameters. In either case, one should care- AD9225 fully select an op amp that preserves the performance of the ADC. 500� This task becomes challenging when the AD9225’s high perfor- 500� +V 50� mance capabilities are coupled with other extraneous system level VINB 500� CML requirements such as power consumption and cost. R* 500� The ability to select the optimal op amp may be further compli- 10�F 0.1�F *OPTIONAL cated by either limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high performance op amps typically have input and output range limitations in Figure 12. Direct Coupled Drive Circuit with accordance with their lower supply voltages. As a result, some op AD8056 Dual Op Amp amps will be more appropriate in systems where ac coupling is The circuit shown in Figure 12 is an ideal method of applying a allowable. When dc coupling is required, op amps without head- differential dc drive to the AD9225. We have used this configura- room constraints such as rail-to-rail op amps or the ones where tion to drive the AD9225 from 2 V to 4 V spans at frequencies larger supplies can be used should be considered. The following approaching Nyquist with performance numbers matching those section describes some op amps currently available from Analog listed in the Specifications tables (gathered through a transformer). Devices, Inc. The system designer is always encouraged to contact The dc input is shifted to a dc point swinging symmetrically about the factory or local sales office to be updated on Analog Devices’ the reference voltage. The optional resistor will provide additional latest amplifier product offerings. Highlights of the areas where the current if more reference drive is required. op amps excel and where they may limit the performance of the The driver circuit shown in Figure 12 is optimized for dc coupling AD9225 is also included. applications requiring optimum distortion performance. This AD8055: f = 300 MHz. –3 dB differential op amp driver circuit is configured to convert and level Low cost. Best used for driving single-ended ac- shift a 2 V p-p single-ended, ground referenced signal to a 4 V p-p coupled configuration. differential signal centered at the VREF level of the ADC. The Limit: THD is compromised when output is not circuit is based on two op amps that are configured as matched swinging about 0 V. unity gain difference amplifiers. The single-ended input signal is AD8056: Dual Version of above amp. applied to opposing inputs of the difference amplifiers, thus provid- Perfect for single-ended to differential configuration ing differential drive. The common-mode offset voltage is applied (see Figure 12). Harmonics cancel each other in to the noninverting resistor leg of each difference amplifier provid- differential drive, making this amplifier highly rec- ing the required offset voltage. The common-mode offset can be ommended for a single-ended input signal source. varied over a wide span without any serious degradation in distor- Handles input signals past the 20 MHz Nyquist tion performance as shown in Figures 14 and 15, thus providing frequency. some flexibility in improving output compression distortion from some ±5 V op amps with limited positive voltage swing. AD9631: f = 250 MHz. –3 dB Moderate cost. To protect the AD9225 from an undervoltage fault condition from Good for single-ended drive applications when op amps specified for ±5 V operation, two diodes to AGND can be signal is anywhere between 0 V and 3 V. inserted between each op amp output and the AD9225 inputs. Limits: THD is compromised above 8 MHz. The AD9225 will inherently be protected against any overvoltage condition if the op amps share the same positive power supply (i.e., DIFFERENTIAL MODE OF OPERATION AVDD) as the AD9225. Note that the gain accuracy and com- Since not all applications have a signal preconditioned for mon-mode rejection of each difference amplifier in this driver differential operation, there is often a need to perform a single- circuit can be enhanced by using a matched thin-film resistor ended-to-differential conversion. In systems that do not need to be network (i.e., Ohmtek ORNA5000F) for the op amps. Recall that dc-coupled, an RF transformer with a center tap is the best method the AD9225’s small signal bandwidth is 105 MHz and therefore, to generate differential inputs for the AD9225. It provides all the any noise falling within the baseband bandwidth of the AD9225 benefits of operating the ADC in the differential mode without will degrade its overall noise performance. contributing additional noise or distortion. An RF transformer also The noise performance of each unity gain differential driver circuit has the added benefit of providing electrical isolation between the is limited by its inherent noise gain of 2. For unity gain op amps signal source and the ADC. ONLY, the noise gain can be reduced from 2 to 1 beyond the An improvement in THD and SFDR performance can be realized input signals passband by adding a shunt capacitor, C , across F by operating the AD9225 in the differential mode. The perfor- each op amp’s feedback resistor. This will essentially establish a mance enhancement between the differential and single-ended low-pass filter, which reduces the noise gain to 1 beyond the filter’s mode is most noteworthy as the input frequency approaches and f while simultaneously bandlimiting the input signal to f . –3 dB –3 dB goes beyond the Nyquist frequency (i.e., f > f /2). Note that the pole established by this filter can also be used as the IN S real pole of an antialiasing filter. –14– Rev. C AD9225 –76 Figure 13 shows the schematic of the suggested transformer circuit. The circuit uses a minicircuits RF transformer, model #T4-1T, which has an impedance ratio of 4 (turns ratio of 2). The sche- –78 matic assumes that the signal source has a 50 W source impedance. The 1:4 impedance ratio requires the 200 W secondary termination for optimum power transfer and VSWR. The center tap of the –80 transformer provides a convenient means of level-shifting the input f = 10MHz IN signal to a desired common-mode voltage. –82 R f = 2.5MHz S IN 33� VINA –84 49.9� CML 0.1�F 200� AD9225 C –86 S 05 1 23 4 VINB COMMON-MODE VOLTAGE (V) MINICIRCUITS R S T4-1T 33� Figure 14. Common-Mode Voltage vs. THD (A = 2 V Differential) IN Figure 13. Transformer Coupled Input –76 The configuration in Figure 13 was used to gather the differential data on the Specifications tables. Transformers with other turns ratios may also be selected to opti- –78 mize the performance of a given application. For example, a given input signal source or amplifier may realize an improvement in –80 distortion performance at reduced output power levels and signal f = 10MHz IN swings. For example, selecting a transformer with a higher imped- ance ratio (e.g., Minicircuits T16-6T with a 1:16 impedance ratio) –82 effectively steps up the signal level further reducing the driving f = 2.5MHz IN requirements of the signal source. –84 Referring to Figure 13, a series resistors, R , and shunt capacitor, S C , were inserted between the AD9225 and the secondary of the S transformer. The value of 33 W was selected to specifically opti- –86 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 mize both the THD and SNR performance of the ADC. R and S COMMON-MODE VOLTAGE (V) C help provide a low-pass filter to block high frequency noise. S Figure 15. Common-Mode Voltage vs. THD The AD9225 can be easily configured for either a 2 V p-p input (A = 4 V Differential) IN span or a 4.0 V p-p input span by setting the internal reference (see Table II). Other input spans can be realized with two external gain 0.0 FUND setting resistors as shown in Figure 19. Figures 14 and 15 demon- f = 2.5MHz IN –10.0 strate how both spans of the AD9225 achieve the high degree of f = 25MHz S –20.0 linearity and SFDR over a wide range of amplitudes required by –30.0 the most demanding communication applications. –40.0 Figures 14 and 15 demonstrate the flexibility of common-mode –50.0 voltage (transformer center tap) with respect to THD. –60.0 –70.0 –80.0 2ND 4TH 3RD –90.0 –100.0 –110.0 –119.7 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.5E+6 Figure 16. Single-Tone Frequency Domain Plot Common-Mode Voltage = 2.5 V (A = 4 V IN Differential) –15– Rev. C THD (dB) THD (dB) AD9225 REFERENCE CONFIGURATIONS This reference configuration could also be used for a differential The figures associated with this section on internal and external input in which VINA and VINB are driven via a transformer as reference operation do not show recommended matching series shown in Figure 13. In this case, the common-mode voltage, resistors for VINA and VINB for the purpose of simplicity. Refer VCM , is set at midsupply by connecting the transformer’s center to the Driving the Analog Inputs and Introduction sections for a tap to CML of the AD9225. VREF can be configured for 1.0 V discussion of this topic. The figures do not show the decoupling or 2.0 V by connecting SENSE to either VREF or REFCOM, network associated with the CAPT and CAPB pins. Refer to the respectively. Note that the valid input range for each of the differ- Reference Operation section for a discussion of the internal refer- ential inputs is one half of the single-ended input and thus becomes ence circuitry and the recommended decoupling network shown VCM – VREF/2 to VCM + VREF/2. in Figure 16. 3.5V VINA 1.5V USING THE INTERNAL REFERENCE VCM Single-Ended Input with 0 to 2 3 VREF Range AD9225 VINB Figure 16 shows how to connect the AD9225 for a 0 V to 2 V or 1V VREF 0 V to 4 V input range via pin strapping the SENSE pin. An inter- 10�F SENSE 0.1�F mediate input range of 0 to 2 ¥ VREF can be established using the resistor programmable configuration in Figure 19. REFCOM In either case, both the midscale voltage and input span are directly dependent on the value of VREF. More specifically, the midscale Figure 18. Internal Reference—2 V p-p Input Span, voltage is equal to VREF while the input span is equal to 2 ¥ VREF. V = 2.5 V CM Thus, the valid input range extends from 0 to 2 ¥ VREF. When Resistor Programmable Reference VINA is £ 0 V, the digital output will be 0x000; when VINA is Figure 19 shows an example of how to generate a reference voltage ≥ 2 ¥ VREF, the digital output will be 0xFFF. other than 1.0 V or 2.0 V with the addition of two external resistors Shorting the VREF pin directly to the SENSE pin places the inter- and a bypass capacitor. Use the equation nal reference amplifier in unity-gain mode and the resulting VREF VREF = 1 V ¥ (1 + R1/R2) output is 1 V. Therefore, the valid input range is 0 V to 2 V. However, shorting the SENSE pin directly to the REFCOM pin to determine appropriate values for R1 and R2. These resistors configures the internal reference amplifier for a gain of 2.0 and the should be in the 2 kW to 100 kW range. For the example shown, resulting VREF output is 2.0 V. Therefore, the valid input range R1 equals 2.5 kW and R2 equals 5 kW. From the equation above, becomes 0 V to 4 V. The VREF pin should be bypassed to the the resultant reference voltage on the VREF pin is 1.5 V. This REFCOM pin with a 10 mF tantalum capacitor in parallel with a sets the input span to be 3 V p-p. To assure stability, place a 0.1 mF low inductance 0.1 mF ceramic capacitor. ceramic capacitor in parallel with R1. The midscale voltage can be set to VREF by connecting VINB to 2 � VREF VINA VREF to provide an input span of 0 to 2 ¥ VREF. Alternatively, 0V VINB the midscale voltage can be set to 2.5 V by connecting VINB to a 10�F 0.1�F low impedance 2.5 V source. For the example shown, the valid VREF input single-ended range for VINA is 1 V to 4 V since VINB is set SHORT FOR 0V TO 2V AD9225 INPUT SPAN to an external, low impedance 2.5 V source. The VREF pin should SENSE be bypassed to the REFCOM pin with a 10 mF tantalum capacitor in parallel with a low inductance 0.1 mF ceramic capacitor. SHORT FOR 0V TO 4V INPUT SPAN REFCOM 4V VINA 1V AD9225 2.5V VINB Figure 17. Internal Reference—2 V p-p Input Span, 1.5V V = 1 V, or 4 V p-p Input Span CM VREF C1 R1 10�F 0.1�F Figure 18 shows the single-ended configuration that gives good 0.1�F 2.5k� SENSE dynamic performance (SINAD, SFDR). To optimize dynamic R2 specifications, center the common-mode voltage of the analog 5k� input at approximately by 2.5 V by connecting VINB to a low REFCOM impedance 2.5 V source. As described above, shorting the VREF pin directly to the SENSE pin results in a 1 V reference voltage and a 2 V p-p input span. The valid range for input signals is 1.5 V Figure 19. Resistor Programmable Reference to 3.5 V. The VREF pin should be bypassed to the REFCOM pin 3 V p-p Input Span, V = 2.5 V CM with a 10 mF tantalum capacitor in parallel with a low-inductance 0.1 mF ceramic capacitor. –16– Rev. C AD9225 2 � REF USING AN EXTERNAL REFERENCE VINA 0V Using an external reference may enhance the dc performance of the AD9225 by improving drift and accuracy. Figures 20 and 21 +5V VREF VINB show examples of how to use an external reference with the ADC. 0.1�F 10�F 0.1�F AD9225 Table III is a list of suitable voltage references from Analog Devices. To use an external reference, the user must disable the VREF internal reference amplifier and drive the VREF pin. Connecting 0.1�F the SENSE pin to AVDD disables the internal reference amplifier. +5V SENSE Table III. Suitable Voltage References Figure 21. Input Range = 0 V to 2 ¥ VREF Initial Output Drift Accuracy Operating DIGITAL INPUTS AND OUTPUTS Voltage (ppm/∞C) % (max) Current Digital Outputs The AD9225 output data is presented in positive true straight Internal 1.00 26 1.4 1 mA binary for all input ranges. Table IV indicates the output data AD589 1.235 10–100 1.2–2.8 50 mA formats for various input ranges regardless of the selected input AD1580 1.225 50–100 0.08–0.8 50 mA range. A twos complement output data format can be created by REF191 2.048 5–25 0.1–0.5 45 mA inverting the MSB. Internal 2.0 26 1.4 1 mA Table IV. Output Data Format The AD9225 contains an internal reference buffer, A2 (see Figure 5), that simplifies the drive requirements of an external Input (V) Condition (V) Digital Output OTR reference. The external reference must be able to drive about 5 kW (±20%) load. Note that the bandwidth of the reference VINA–VINB < – VREF 0000 0000 0000 1 buffer is deliberately left small to minimize the reference noise VINA–VINB = – VREF 0000 0000 0000 0 contribution. As a result, it is not possible to change the refer- VINA–VINB = 0 1000 0000 0000 0 ence voltage rapidly in this mode. VINA–VINB = + VREF – 1 LSB 1111 1111 1111 0 VINA–VINB ≥ + VREF 1111 1111 1111 1 2.5V+VREF VINA 2.5V 2.5V–VREF +FS –1 1/2 LSB AD9225 OTR DATA OUTPUTS 2.5V +5V VINB 1 1111 1111 1111 OTR REF 22�F 0 1111 1111 1111 0.1�F R1 0.1�F 0 1111 1111 1110 –FS+1/2 LSB VREF A1 0.1�F R2 0 0000 0000 0001 0 0000 0000 0000 SENSE +5V 1 0000 0000 0000 –FS +FS Figure 20. External Reference –FS –1/2 LSB +FS –1/2 LSB Variable Input Span with V = 2.5 V CM Figure 22. Output Data Format Figure 20 shows an example of the AD9225 configured for an Out-Of-Range (OTR) input span of 2 ¥ VREF centered at 2.5 V. An external 2.5 V refer- An out-of-range condition exists when the analog input voltage is ence drives the VINB pin thus setting the common-mode voltage beyond the input range of the converter. OTR is a digital output at 2.5 V. The input span can be independently set by a voltage that is updated along with the data output corresponding to the divider consisting of R1 and R2, which generates the VREF signal. particular sampled analog input voltage. OTR has the same pipe- A1 buffers this resistor network and drives VREF. Choose this op line delay (latency) as the digital data. It is low when the analog amp based on accuracy requirements. It is essential that a mini- input voltage is within the analog input range. It is high when the mum of a 10 mF capacitor in parallel with a 0.1 mF low inductance analog input voltage exceeds the input range as shown in Figure ceramic capacitor decouple A1’s output to ground. 23. OTR will remain high until the analog input returns within Single-Ended Input with 0 to 2 ¥ ¥ ¥ ¥ ¥ VREF Range the input range and another conversion is completed. By logical Figure 21 shows an example of an external reference driving both ANDing OTR with the MSB and its complement, overrange high VINB and VREF. In this case, both the common-mode voltage or underrange low conditions can be detected. Table V is a truth and input span are directly dependent on the value of VREF. More table for the overrange circuit in Figure 24 which uses NAND specifically, the common-mode voltage is equal to VREF while the gates. Systems requiring programmable gain conditioning of the input span is equal to 2 ¥ VREF. The valid input range extends AD9225 input signal can immediately detect an out-of-range from 0 to 2 ¥ VREF. For example, if the REF191, a 2.048 V exter- condition, eliminating gain selection iterations. OTR can also be nal reference was selected, the valid input range extends from 0 to used for digital offset and gain calibration. 4.096 V. In this case, 1 LSB of the AD9225 corresponds to 1 mV. It is essential that a minimum of a 10 mF capacitor in parallel with a 0.1 mF low inductance ceramic capacitor decouple the reference output to ground. –17– Rev. C AD9225 Table V. Out-of-Range Truth Table The AD9225 has a clock tolerance of 5% at 25 MHz. One way to obtain a 50% duty cycle clock is to divide down a clock of higher OTR MSB Analog Input Is frequency, as shown in Figure 24. This configuration will also decrease the jitter of the source clock. 00 In Range 01 In Range +5V 10 Underrange 11 Overrange R D Q MSB OVER = “1” 25MHz 50MHz Q OTR S UNDER = “1” MSB +5V Figure 23. Overrange or Underrange Logic Figure 24. Divide-by-Two Clock Circuit Digital Output Driver Considerations (DRVDD) In this case, a 50 MHz clock is divided by two to produce the The AD9225 output drivers can be configured to interface with 25 MHz clock input for the AD9225. In this configuration, the 5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V, duty cycle of the 50 MHz clock is irrelevant. respectively. The output drivers are sized to provide sufficient The input circuitry for the CLOCK pin is designed to accommo- output current to drive a wide variety of logic families. However, date CMOS inputs. The quality of the logic input, particularly large drive currents tend to cause glitches on the supplies and may the rising edge, is critical in realizing the best possible jitter affect SINAD performance. Applications requiring the ADC to performance of the part; the faster the rising edge, the better drive large capacitive loads or large fanout may require additional the jitter performance. decoupling capacitors on DRVDD. In extreme cases, external buffers or latches may be required. As a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is impor- Clock Input and Considerations tant. Jitter-induced errors become more predominant at higher The AD9225 internal timing uses the two edges of the clock input frequency and large amplitude inputs, where the input slew rate to generate a variety of internal timing signals. The clock input is greatest. must meet or exceed the minimum specified pulse width high and low (t and t ) specifications for the given ADC as defined in Most of the power dissipated by the AD9225 is from the analog CH CL the Switching Specifications table to meet the rated performance power supplies. However, lower clock speeds will reduce digital specifications. For example, the clock input to the AD9225 operat- current. Figure 25 shows the relationship between power and ing at 25 MSPS may have a duty cycle between 45% to 55% to clock rate. meet this timing requirement since the minimum specified t and CH 380 t is 18 ns. For low clock rates, the duty cycle may deviate from CL 360 this range to the extent that both t and t are satisfied. CH CL 340 All high speed high resolution ADCs are sensitive to the quality of 2V 320 the clock input. The degradation in SNR at a given full-scale input INTERNAL REFERENCE frequency (f ) due to only aperture jitter (t ) can be calculated IN A 300 with the following equation: 280 È ˘ 1 260 SNR= 20 log 10 Í ˙ 2p f t IN A 1V 240 Î ˚ INTERNAL REFERENCE 220 In the equation, the rms aperture jitter, t , represents the root- A sum square of all the jitter sources, which include the clock 200 input, analog input signal, and ADC aperture jitter specification. 180 03 5 10 15 20 25 305 Undersampling applications are particularly sensitive to jitter. SAMPLE RATE Clock input should be treated as an analog signal in cases where Figure 25. Power Consumption vs. Clock Rate aperture jitter may affect the dynamic range of the AD9225. Power supplies for clock drivers should be separated from the ADC out- Direct IF Down Conversion Using the AD9225 put driver supplies to avoid modulating the clock signal with digital Sampling IF signals above an ADC’s baseband region (i.e., noise. Low jitter crystal controlled oscillators make the best clock dc to f /2) is becoming increasingly popular in communication S sources. If the clock is generated from another type of source (by applications. This process is often referred to as direct IF down gating, dividing, or other method), it should be retimed by the conversion or undersampling. There are several potential benefits original clock at the last step. in using the ADC to alias (i.e., or mix) down a narrowband or wideband IF signal. First and foremost is the elimination of a The clock input is referred to as the analog supply. Its logic thresh- complete mixer stage with its associated baseband amplifiers and old is AVDD/2. If the clock is being generated by 3 V logic, it will filters, reducing cost and power dissipation. Second is the ability to have to be level shifted into 5 V CMOS logic levels. This can also apply various DSP techniques to perform such functions as filter- be accomplished by ac coupling and level-shifting the clock signal. ing, channel selection, quadrature demodulation, data reduction, –18– Rev. C POWER (mW) AD9225 and detection, among other things. See Application Note AN-302 The distortion and noise performance of an ADC at the given IF on using this technique in digital receivers. frequency is of particular concern when evaluating an ADC for a narrowband IF sampling application. Both single-tone and dual- In direct IF down conversion applications, one exploits the tone SFDR versus amplitude are very useful in assessing an inherent sampling process of an ADC in which an IF signal lying ADC’s dynamic and static nonlinearities. SNR versus amplitude outside the baseband region can be aliased back into the baseband performance at the given IF is useful in assessing the ADC’s noise region in a similar manner that a mixer will down-convert an IF performance and noise contribution due to aperture jitter. In any signal. Similar to the mixer topology, an image rejection filter application, one is advised to test several units of the same device is required to limit other potential interferring signals from also under the same conditions to evaluate the given applications sensi- aliasing back into the ADC’s baseband region. A trade-off exists tivity to that particular device. between the complexity of this image rejection filter and the ADC’s sample rate as well as dynamic range. Figures 27 to 30 combine the dual-tone SFDR as well as single- tone SFDR and SNR performances at IF frequencies of 35 MHz, The AD9225 is well suited for various IF sampling applications. 45 MHz, 70 MHz, and 85 MHz. Note that the SFDR versus The AD9225’s low distortion input SHA has a full-power band- amplitude data is referenced to dBFS while the single-tone SNR width extending beyond 130 MHz thus encompassing many data is referenced to dBc. The performance characteristics in these popular IF frequencies. A DNL of ±0.4 LSB (typ) combined figures are representative of the AD9225 without any preceding with low thermal input referred noise allows the AD9225 in the gain stage. The AD9225 was operated in the differential mode (via 2 V span to provide 69 dB of SNR for a baseband input sine transformer) with a 2 V span and a sample rate between 28 MSPS wave. Its low aperture jitter of 0.8 ps rms ensures minimum and 36 MSPS. The analog supply (AVDD) and the digital supply SNR degradation at higher IF frequencies. In fact, the AD9225 (DRVDD) were set to 5 V and 3.3. V, respectively. is capable of still maintaining 68 dB of SNR at an IF of 71 MHz with a 2 V input span. Although the AD9225 can yield a 1 dB 100 SFDR to 2 dB improvement in SNR when configured for the larger 95 SINGLE-TONE 4 V span, the 2 V span achieves the optimum full-scale distor- (dBFS) 90 tion performance at these higher input frequencies. The 2 V span reduces only the performance requirements of the input 85 driver circuitry (i.e., IP3) and thus may also be more attractive SFDR 80 DUAL-TONE from a system implementation perspective. (dBFS) 75 SNR Figure 26 shows a simplified schematic of the AD9225 config- SINGLE-TONE 70 ured in an IF sampling application. To reduce the complexity of (dBc) the digital demodulator in many quadrature demodulation 65 applications, the IF frequency and/or sample rate are strategi- 60 cally selected such that the band-limited IF signal aliases back 55 into the center of the ADC’s baseband region (i.e., f /4). This S demodulation technique typically reduces the complexity of the 50 –15 –10 –5 0 post digital demodulator ASIC that follows the ADC. A (dBFS) IN HIGH Figure 27. IF Undersampling at 35 MHz (F = 34.63 MHz, 1 LINEARITY OPTIONAL RF BANDPASS SAW F = 35.43 MHz, CLOCK = 20 MHz) 2 AMPLIFIER FILTER FILTER AD9225 MINICIRCUITS FROM T4-6T 20� 100 PREVIOUS VINA STAGES SFDR 200� MIXER 95 SINGLE-TONE RF2317 VINB (dBFS) 20� RF2312 90 CML 0.1�F 85 VREF SFDR DUAL-TONE 80 SENSE (dBFS) 0.1�F 10�F 75 REFCOM SNR SINGLE-TONE 70 (dBc) Figure 26. Example of AD9225 IF Sampling Circuit 65 To maximize its distortion performance, the AD9225 is configured 60 in the differential mode with a 2 V span using a transformer. The 55 center tap of the transformer is biased at midsupply via the CML 50 output of the AD9225. Preceding the AD9225 and transformer is –15 –10 –5 0 A (dBFS) an optional band-pass filter as well as a gain stage. A low Q passive IN band-pass filter can be inserted to reduce the out-of-band distor- Figure 28. IF Undersampling at 45 MHz (F = 44.81 MHz, 1 tion and noise that lies within the AD9225’s 130 MHz bandwidth. F = 45.23 MHz, CLOCK = 20 MHz) 2 A large gain stage(s) is often required to compensate for the high insertion losses of a SAW filter used for channel selection and image rejection. The gain stage will also provide adequate isolation for the SAW filter from the charge kickback currents associated with the AD9225’s switched capacitor input stage. –19– Rev. C SNR/SFDR (dBFS) SNR/SFDR (dBFS) AD9225 100 carefully managed. Alternatively, the ground plane under the 95 ADC may contain serrations to steer currents in predictable SFDR directions where cross coupling between analog and digital 90 SINGLE-TONE (dBFS) would otherwise be unavoidable. The AD9225/AD9225EB 85 ground layout, shown in Figure 38, depicts the serrated type 80 of arrangement. 75 The board is built primarily over a common ground plane. It SFDR has a slit to route currents near the clock driver. Figure 31 illus- 70 DUAL-TONE (dBFS) trates a general scheme of ground and power implementation, in 65 and around the AD9225. 60 SNR SINGLE-TONE LOGIC 55 (dBc) AVDD SUPPLY DVDD 50 A A D –15 –10 –5 0 A (dBFS) IN Figure 29. IF Undersampling at 70 MHz (F = 69.50 MHz, ADC DIGITAL 1 IC LOGIC C STRAY F = 70.11 MHz, CLOCK = 25 MHz) 2 ICs 100 ANALOG DIGITAL CIRCUITS CIRCUITS V IN 95 A B C A STRAY SFDR I I 90 A D SINGLE-TONE (dBFS) 85 GND AVSS DVSS 80 = ANALOG A 75 �V D A A D = DIGITAL 70 SFDR DUAL-TONE 65 (dBFS) Figure 31. Ground and Power Consideration SNR 60 Analog and Digital Driver Supply Decoupling SINGLE-TONE (dBc) The AD9225 features separate analog and driver supply and 55 ground pins, helping to minimize digital corruption of sensitive 50 analog signals. In general, AVDD, the analog supply, should –15 –10 –5 0 A (dBFS) IN be decoupled to AVSS, the analog common, as close to the chip as physically possible. Figure 32 shows the recommended Figure 30. IF Undersampling at 85 MHz (F = 84.81 MHz, 1 decoupling for the analog supplies; 0.1 mF ceramic chip and F = 85.23 MHz, CLOCK = 20 MHz) 2 10 mF tantalum capacitors should provide adequately low imped- ance over a wide frequency range. Note that the AVDD and GROUNDING AND DECOUPLING AVSS pins are co-located on the AD9225 to simplify the layout Analog and Digital Grounding of the decoupling capacitors and provide the shortest possible Proper grounding is essential in any high speed, high resolution PCB trace lengths. The AD9225/AD9225EB power plane layout, system. Multilayer printed circuit boards (PCBs) are recom- shown in Figure 39 depicts a typical arrangement using a multi- mended to provide optimal grounding and power schemes. The layer PCB. use of ground and power planes offers distinct advantages: •The minimization of the loop area encompassed by a signal AVDD and its return path. 10�F 0.1�F AD9225 •The minimization of the impedance associated with ground AVSS and power paths. •The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. Figure 32. Analog Supply Decoupling These characteristics result in both a reduction of electro- The CML is an internal analog bias point used internally by magnetic interference (EMI) and an overall improvement the AD9225. This pin must be decoupled with at least a 0.1 mF in performance. capacitor as shown in Figure 33. The dc level of CML is approximately AVDD/2. This voltage should be buffered if it is It is important to design a layout that prevents noise from cou- to be used for any external biasing. pling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9225 features separate analog CML and driver ground pins, it should be treated as an analog com- 0.1�F AD9225 ponent. The AVSS and DRVSS pins must be joined together directly under the AD9225. A solid ground plane under the Figure 33. CML Decoupling ADC is acceptable if the power and ground return currents are –20– Rev. C SNR/SFDR (dBFS) SNR/SFDR (dBFS) AD9225 The digital activity on the AD9225 chip falls into two general DRVDD categories: correction logic and output drivers. The internal 10�F 0.1�F AD9225 correction logic draws relatively small surges of current, mainly DRVSS during the clock transitions. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the Figure 34. Digital Supply Decoupling output bits; large capacitive loads are to be avoided. Note that A complete decoupling scheme will also include large tantalum the internal correction logic of the AD9225 is referenced to or electrolytic capacitors on the PCB to reduce low frequency AVDD while the output drivers are referenced to DRVDD. ripple to negligible levels. Refer to the AD9225/AD9225EB The decoupling shown in Figure 34, a 0.1 mF ceramic chip schematic and layouts in Figures 35 to 41 for more information capacitor and a 10 mF tantalum capacitor, are appropriate for a regarding the placement of decoupling capacitors. reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionally, and/or using external buffers/latches. –21– Rev. C AD9225 U5 TP38 REF43 R34 50� 1 6 2 21 TP34 L2 VOUT VIN VCC J4 DUTAVDD FBEAD 1 GND 2 JP22 1 1 AVDDIN1 C18 12 C30 1 + 1 1 2 AVDD 1 P3 C39 10�F 1 4 0.1�F 1 R31 1 2 0.001�F 10V TP31 1 R25 2 TP30 JP23 C22 2 C47 820� + C52 2.49k� JP21 1 2 2 10�F 22�F 1 0.1�F 2 1 2 10V 20V 2 2 2 1 JP24 C36 JP19 1 1 AGND 1 1 2 12 0.1�F R3 C57 2 P3 + 2 C28 1 JP26 10k� 0.1�F 1 C2 0.1�F 2 JP25 1 2 + C29 2 2 1 2 AVDD 1 10�F 0.1�F 10V R26 2 2 1 7 3 4.99k� 15 14 R4 IN AVDD2 OTR OTR 2 8 R29 3 10k� 1 16 13 1 JP20 +V AVSS2 D11 D11 1k� 2 C21 12 N2 C35 17 12 6 U4 1 2 2 Q1 10�F SENSE D10 D10 0.1�F OUT 18 11 AD187 2N2222 10V 2 2 R28 VREF D9 D9 N1 1 19 10 C27 50� REFCOM D8 D8 2 –V 12 R27 0.1�F 1 20 9 1 IN CAPB D7 D7 4.99k� C34 12 21 8 4 2 C20 2 2 CAPT D6 D6 2 0.1�F C26 C33 22 7 U3 1 10�F CML D5 D5 2 1 0.1�F VEE 0.1�F R30 23 6 10V 1 1 2 1 VINA D4 D4 C19 316� C31 1 24 5 2 VINB D3 D3 10�F 0.1�F 2 25 4 2 10V 1 C32 AVSS1 D2 D2 26 3 0.1�F AVDD1 D1 D1 L3 TP37 TP29 1 27 2 TP37 DRVSS D0 D0 FBEAD R32 28 1 VCCIN 1 1 12 DRVDD CLK CLK 50� 1 VCC 1 1 P4 2 J3 1 1 C48 1 C24 + 2 AD9225 JP27 C53 22�F 0.1�F 2 TP27 1 0.1�F 2 20V DRVDD 2 2 AGND JP18 R21 1 TP33 DUTDRVDD 1 1 1 1 P4 1 2 C1 200� + C40 C37 10�F 1 2 1 0.001�F 0.1�F 10V 2 2 2 1 1 C42 TP28 R23 R22 TP32 15pF 200� 200� 2 DUTAUDD 1 T1 4 2 1 2 1 1 1 J1 1 1 C23 + C41 C38 2 5 1 1 1 1 1 10�F 0.001�F 0.1�F C46 C45 C44 C43 R24 10V 2 2 6 3 1 15pF 15pF 15pF 15pF 2 50� C25 2 2 2 2 2 0.1�F T4-6T 2 TP36 L6 L4 L1 TP5 TP40 FBEAD DUTAVDDIN FBEAD FBEAD 1 1 2 VEEIN 1 12 DVDDIN 1 2 1 DUTAVDD 2 P6 3 P4 VEE 1 DVDD P2 1 1 1 1 C58 + C49 1 1 C59 C54 C6 22�F + + C14 22�F 0.1�F 0.1�F 22�F 2 20V 0.1�F 20V 2 2 2 2 20V AGND 2 1 DGND P6 C12 P2 2 0.1�F TP6 U9 12 JP10 JP4 10 R17 22� 11 1 TP25 12 1 2 1 2 1 1 P1 P1 2 C4 TP7 L7404 U9 JP1 R5 22� JP11 10V 10�F TP24 1 2 9 8 1 12 1 1 2 2 1 + 3 P1 P1 4 R6 22� TP8 JP5 TP23 U9 1 2 JP12 L7404 1 2 1 5 6 12 5 6 1 P1 P1 R7 22� TP22 1 20 1 1 2 G1 VCC L5 L7404 7 P1 P1 8 19 10 U9 FBEAD G2 GND R8 22� TP21 JP16 DRVDDIN12 1 13 12 2 1 3 U6 1 1 DRVDD 9 10 P5 D11 A B 2 P1 P1 18 74541 A1 Y1 1 2 R9 22� TP20 1 3 17 C51 + L7404 1 C56 A2 Y2 1 2 22�F 4 11 P1 P1 12 16 0.1�F D10 A3 Y3 20V 2 R10 22� DGND DVDD TP19 2 5 15 1 1 D9 1 2 P5 2 A4 Y4 1 C7 13 P1 14 + 6 14 P1 C15 D8 Y5 10�F A5 R11 22� TP26 0.1�F 7 13 TP39 10V 1 D7 A6 Y6 1 2 2 2 R35 8 12 15 P1 P1 16 Y7 50� D6 A7 1 R12 22� 1 2 11 TP18 1 9 U1 U9 1 J5 D5 A8 Y8 1 2 REF43 17 18 DECOUPLING P1 P1 C11 2 R13 22� TP17 0.1�F 1 AVDD VIN VOUT 1 2 2 1 19 P1 P1 20 1 GND R14 22� C8 1 1 C9 1 TP16 + + C16 C17 1 1 2 10�F 10�F JP3 C5 0.1�F 21 22 0.1�F 1 2 P1 P1 10V 10V 10V 10�F 2 2 2 2 R15 22� TP15 1 20 1 + 2 1 1 2 G1 JP2 VCC 23 P1 P1 24 1 2 19 10 R19 R2 R18 G2 GND 4k� 5k� 1k� 2 3 1 1 2 1 25 26 2 18 P1 P1 D4 A1 Y1 CW CCV 3 17 JP17 2 D3 A2 Y2 3 1 4 U7 27 P1 P1 28 16 A B D2 A3 Y3 74541 5 15 C13 2 TP4 D1 A4 Y4 U8 0.1�F U8 6 14 29 30 JP9 P1 P1 D0 A5 Y5 1 2 1 3 4 98 1 2 1 7 13 J2 CLK OTR A6 Y6 1 8 12 31 P1 P1 32 2 R16 A7 Y7 L7404 L7404 R1 1 9 11 TP14 22� 2 JP15 A8 Y8 1 2 1 50� 3 1 B 33 34 JP14 A P1 P1 A B 2 3 1 TP13 JP32 2 2 1 TP9 U9 U9 35 P1 P1 36 TP10 U8 1 2 34 JP13 1 TP12 1 1 256 1 16 1 VCC CLR 37 P1 38 15 P1 JP28 R20 2 TP1 L7404 L7404 RCO 12 U8 CLK TP11 22� L7404 14 JP6 3 12 1 11 1 2 10 1 QA A JP29 13 39 P1 P1 40 4 U2 AVDD QB 12 B 1 TP2 74LS161 12 1 5 U8 C3 L7404 C10 + QC JP7 C JP30 DVDD 11 1 2 13 12 1 10�F 6 12 0.1�F 1 D QD 10V 10 2 2 7 1 C50 + C55 ENT TP3 ENP JP31 10�F U8 L7404 8 9 1 2 0.1�F JP8 U8 10V 1 2 1 GND 1 2 LOAD 2 2 DECOUPLING R33 1k� 2 L7404 1 DVDD Figure 35. Evaluation Board Schematic –22– Rev. C + + + + AD9225 Figure 39. Evaluation Board Solder Side Layout Figure 36. Evaluation Board Component Side (Not to Scale) Layout (Not to Scale) Figure 40. Evaluation Board Power Plane Layout Figure 37. Evaluation Board Ground Plane Layout (Not to Scale) Figure 41. Evaluation Board Solder Side Silkscreen Figure 38. Evaluation Board Component Side (Not to Scale) Silkscreen (Not to Scale) –23– Rev. C AD9225 OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 14 10.00 (0.3937) 45° 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.51 (0.0201) 0.10 1.27 (0.0500) 1.27 (0.0500) 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 1. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches) 10.50 10.20 9.90 28 15 5.60 5.30 8.20 5.00 7.80 7.40 1 14 0.25 1.85 0.09 2.00 MAX 1.75 1.65 8° 0.95 0.38 0.05 MIN SEATING 4° 0.75 0.22 COPLANARITY PLANE 0° 0.65 BSC 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 2. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9225AR −40°C to +85°C 28-Lead Standard Small Outline Package [SOIC_W] RW-28 AD9225ARS −40°C to +85°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD9225ARSRL −40°C to +85°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD9225ARZ −40°C to +85°C 28-Lead Standard Small Outline Package [SOIC_W] RW-28 AD9225ARZRL −40°C to +85°C 28-Lead Standard Small Outline Package [SOIC_W] RW-28 AD9225ARSZ −40°C to +85°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD9225ARSZRL −40°C to +85°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 1 Z = RoHS Compliant Part. Rev. C | Page 24 of 25 0.75 (0.0295) 0.25 (0.0098) 060106-A 06-07-2006-A AD9225 REVISION HISTORY 1/11—REV. B to REV. C Updated Outline Dimensions ....................................................... 24 Moved and Changes to Ordering Guide ..................................... 24 8/03—REV. A to REV. B Renumbered TPCs and Figures ........................................ Universal Changes to Ordering Guide ............................................................ 4 Updated Outline Dimensions ....................................................... 24 ©1998–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00577-0-1/11(C) Rev. C | Page 25 of 25