ANALOG DEVICES AD9222

Octal, 12-Bit, 40/50/65 MSPS Serial LVDS 1.8 V A/D Converter Data Sheet AD9222 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS AD9222 12 SNR = 70 dB (to Nyquist) VIN + A D + A SERIAL ADC D – A LVDS VIN – A ENOB = 11.3 bits 12 SFDR = 80 dBc VIN + B D + B SERIAL ADC D – B VIN – B LVDS Excellent linearity: DNL = ±0.3 LSB (typical), 12 INL = ±0.4 LSB (typical) VIN + C D + C SERIAL ADC LVDS D – C VIN – C Serial LVDS (ANSI-644, default) 12 Low power, reduced signal option (similar IEEE 1596.3) VIN + D SERIAL D + D ADC LVDS D – D VIN – D Data and frame clock outputs 12 325 MHz full-power analog bandwidth VIN + E SERIAL D + E ADC D – E VIN – E LVDS 2 V p-p input voltage range 12 1.8 V supply operation VIN + F D + F SERIAL ADC VIN – F LVDS D – F Serial port control 12 Full-chip and individual-channel power-down modes VIN + G D + G SERIAL ADC LVDS D – G Flexible bit orientation VIN – G Built-in and custom digital test pattern generation 12 VIN + H D + H SERIAL ADC Programmable clock and data alignment LVDS VIN – H D – H Programmable output resolution VREF Standby mode SENSE FCO + 0.5V FCO – DATA RATE REFT REF MULTIPLIER APPLICATIONS SERIAL PORT DCO + REFB SELECT INTERFACE DCO – Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK– ODM DTP Quadrature radio receivers Figure 1. Diversity radio receivers Tape drives The ADC contains several features designed to maximize Optical networking flexibility and minimize system cost, such as programmable Test equipment clock and data alignment and programmable digital test pattern GENERAL DESCRIPTION generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to- defined test patterns entered via the serial port interface (SPI). digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is use. The product operates at a conversion rate of up to 65 MSPS specified over the industrial temperature range of −40°C to +85°C. and is optimized for outstanding dynamic performance and low PRODUCT HIGHLIGHTS power in applications where a small package size is critical. 1. Small Footprint. Eight ADCs are contained in a small, The ADC requires a single 1.8 V power supply and LVPECL-/ space-saving package. CMOS-/LVDS-compatible sample rate clock for full performance 2. Low power of 114 mW/channel at 65 MSPS. operation. No external reference or driver components are 3. Ease of Use. A data clock output (DCO) is provided that required for many applications. operates at frequencies of up to 390 MHz and supports The ADC automatically multiplies the sample rate clock for double data rate (DDR) operation. the appropriate LVDS serial data rate. A data clock output (DCO) 4. User Flexibility. The SPI control offers a wide range of for capturing data on the output and a frame clock output (FCO) flexible features to meet specific system requirements. for signaling a new output byte are provided. Individual-channel 5. Pin-Compatible Family. This includes the AD9212 (10-bit) power-down is supported and typically consumes less than and AD9252 (14-bit). 2 mW when all channels are disabled. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. 05967-001 AD9222 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 21 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 24 General Description ......................................................................... 1 Serial Port Interface (SPI) .............................................................. 33 Functional Block Diagram .............................................................. 1 Hardware Interface ..................................................................... 34 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 36 Revision History ............................................................................... 2 Reading the Memory Map Table .............................................. 36 Specifications ..................................................................................... 3 Reserved Locations .................................................................... 36 AC Specifications .......................................................................... 4 Default Values ............................................................................. 36 Digital Specifications ................................................................... 5 Logic Levels ................................................................................. 36 Switching Specifications .............................................................. 6 Evaluation Board ............................................................................ 40 Timing Diagrams .............................................................................. 7 Power Supplies ............................................................................ 40 Absolute Maximum Ratings ............................................................ 9 Input Signals................................................................................ 40 Thermal Impedance ..................................................................... 9 Output Signals ............................................................................ 40 ESD Caution .................................................................................. 9 Default Operation and Jumper Selection Settings ................. 41 Pin Configuration and Function Descriptions ........................... 10 Alternative Analog Input Drive Configuration...................... 42 Equivalent Circuits ......................................................................... 12 Outline Dimensions ....................................................................... 59 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 59 Theory of Operation ...................................................................... 21 REVISION HISTORY 12/11—Rev E to Rev. F Changes to Figure 2 to Figure 4 ....................................................... 7 Changes to Figure 86 ...................................................................... 41 Added Figure 21 to Figure 24, Figure 27, Figure 28, Figure 30, Changes to Ordering Guide .......................................................... 59 Figure 32, Figure 37, Figure 38, Figure 40, Figure 42, Figure 44, Figure 46, Figure 48, and Figure 51 .............................................. 15 11/11—Rev. D to Rev. E Added Figure 56 and Figure 58 .................................................... 22 Changes to Output Signals Section .............................................. 41 Added Figure 70 ............................................................................. 25 Changes to Figure 86 ...................................................................... 41 Added Figure 72 ............................................................................. 26 Changes to Ordering Guide .......................................................... 60 Added Figure 74 ............................................................................. 27 4/10—Rev. C to Rev. D Added Figure 76 and Figure 78 .................................................... 28 Changes to Digital Outputs and Timing Section ....................... 28 Changes to Address 16 in Table 16 ............................................... 38 Changes to Table 9 Endnote .......................................................... 29 Updated Outline Dimensions ....................................................... 59 Added Table 10 ............................................................................... 30 Changes to Ordering Guide .......................................................... 59 Changes to RBIAS Pin Section ..................................................... 31 1/10—Rev. B to Rev. C Deleted Figure 56 and Figure 57................................................... 27 Updated Outline Dimensions ....................................................... 59 Changes to Table 15 ....................................................................... 35 Changes to Ordering Guide .......................................................... 60 Change to Input Signals Section ................................................... 40 Change to Output Signals Section................................................ 40 7/09—Rev. A to Rev. B Changes to Figure 86 ...................................................................... 40 Changes to Figure 5 ........................................................................ 10 Changes to Default Operation and Jumper Selection Changes to Figure 61 and Figure 62 ............................................. 23 Settings Section ............................................................................... 41 Changes to Figure 79 and Figure 80 ............................................. 31 Changes to Alternative Analog Input Configuration Section ......... 42 Updated Outline Dimensions ....................................................... 59 Added Figure 88 and Figure 89 .................................................... 42 Changes to Ordering Guide .......................................................... 59 Change to Figure 92 ....................................................................... 45 8/07—Rev. 0 to Rev. A Changes to Table 17 ....................................................................... 54 Added 65 MSPS Models .................................................... Universal Updated Outline Dimensions ....................................................... 59 Changes to Features .......................................................................... 1 Changes to Ordering Guide .......................................................... 60 Changes to Product Highlights ....................................................... 1 9/06—Revision 0: Initial Version Rev. F | Page 2 of 60 Data Sheet AD9222 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. AD9222-40 AD9222-50 AD9222-65 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±1 ±8 ±1 ±8 ±1 ±8 mV Offset Matching Full ±3 ±8 ±3 ±8 ±3 ±8 mV Gain Error Full ±0.4 ±1.2 ±1.5 ±2.5 ±3.5 ±5 % FS Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.4 ±0.8 % FS Differential Nonlinearity (DNL) Full ±0.25 ±0.5 ±0.3 ±0.65 ±0.25 ±0.6 LSB Integral Nonlinearity (INL) Full ±0.4 ±1 ±0.4 ±1 ±0.4 ±1 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C Gain Error Full ±17 ±17 ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ±21 ±21 ppm/°C REFERENCE Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 ±2 ±30 mV Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 3 mV Input Resistance Full 6 6 6 kΩ ANALOG INPUTS Differential Input Voltage Range Full 2 2 2 V p-p (VREF = 1 V) Common-Mode Voltage Full AVDD/2 AVDD/2 AVDD/2 V Differential Input Capacitance Full 7 7 7 pF Analog Bandwidth, Full Power Full 325 325 325 MHz POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD Full 338 348.5 357.5 367.5 450 470 mA IDRVDD Full 51 53.6 53.5 56.2 56.6 60.5 mA Total Power Dissipation Full 700 722 740 760 910 950.5 mW (Including Output Drivers) Power-Down Dissipation Full 2 11 2 11 2 11 mW 2 Standby Dissipation Full 83 89 100 mW CROSSTALK Full −90 −90 −90 dB 3 CROSSTALK (Overrange Condition) Full −90 −90 −90 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. Rev. F | Page 3 of 60 AD9222 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. AD9222-40 AD9222-50 AD9222-65 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 70.3 70.4 70.3 dB f = 19.7 MHz Full 69.5 70.3 69.5 70.3 68.5 70.0 dB IN f = 35 MHz Full 69.9 70.0 69.8 dB IN fIN = 70 MHz Full 68.8 69.0 69.5 dB SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) f = 2.4 MHz Full 70.0 70.0 69.5 dB IN fIN = 19.7 MHz Full 68.7 70.0 68.5 70.0 66.8 69.4 dB fIN = 35 MHz Full 69.5 69.8 69.3 dB fIN = 70 MHz Full 68.0 68.5 69 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 11.38 11.4 11.4 Bits fIN = 19.7 MHz Full 11.25 11.38 11.25 11.38 11.1 11.34 Bits f = 35 MHz Full 11.32 11.33 11.30 Bits IN f = 70 MHz Full 11.14 11.17 11.25 Bits IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz Full 85 85 83 dBc IN f = 19.7 MHz Full 73 85 73 84 70.5 80 dBc IN fIN = 35 MHz Full 80 83 80 dBc fIN = 70 MHz Full 76 77 75 dBc WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −85 −85 −83 dBc fIN = 19.7 MHz Full −85 −74 −84 −73 −80 −70.5 dBc fIN = 35 MHz Full −80 −83 −80 dBc f = 70 MHz Full −76 −77 −75 dBc IN WORST OTHER (Excluding Second or Third) f = 2.4 MHz Full −92 −92 −90 dBc IN f = 19.7 MHz Full −92 −80 −92 −80 −90 −80 dBc IN f = 35 MHz Full −92 −92 −90 dBc IN fIN = 70 MHz Full −90 −90 −85 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 80.0 80.0 dBc fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 77.0 77.0 75.0 dBc 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. F | Page 4 of 60 Data Sheet AD9222 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. AD9222-40 AD9222-50 AD9222-65 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL 2 Differential Input Voltage Full 250 250 250 mV p-p Input Common-Mode Voltage Full 1.2 1.2 1.2 V Input Resistance (Differential) 25°C 20 20 20 kΩ Input Capacitance 25°C 1.5 1.5 1.5 pF LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 0.3 V Input Resistance 25°C 30 30 30 kΩ Input Capacitance 25°C 0.5 0.5 0.5 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 0.3 V Input Resistance 25°C 70 70 70 kΩ Input Capacitance 25°C 0.5 0.5 0.5 pF LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 0 0.3 0 0.3 V Input Resistance 25°C 30 30 30 kΩ Input Capacitance 25°C 2 2 2 pF 3 LOGIC OUTPUT (SDIO/ODM) Logic 1 Voltage (I = 800 μA) Full 1.79 1.79 1.79 V OH Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 0.05 V DIGITAL OUTPUTS (D + x, D − x), 1 (ANSI-644) Logic Compliance LVDS LVDS LVDS Differential Output Voltage (V ) Full 247 454 247 454 247 454 mV OD Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 1.125 1.375 V Output Coding (Default) Offset binary Offset binary Offset binary DIGITAL OUTPUTS (D + x, D − x), (Low Power, Reduced Signal 1 Option) Logic Compliance LVDS LVDS LVDS Differential Output Voltage (V ) Full 150 250 150 250 150 250 mV OD Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 1.10 1.30 V Output Coding (Default) Offset binary Offset binary Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection. Rev. F | Page 5 of 60 AD9222 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. AD9222-40 AD9222-50 AD9222-65 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit 2 CLOCK Maximum Clock Rate Full 40 50 65 MSPS Minimum Clock Rate Full 10 10 10 MSPS Clock Pulse Width High (t ) Full 12.5 10.0 7.5 ns EH Clock Pulse Width Low (t ) Full 12.5 10.0 7.5 ns EL 2, 3 OUTPUT PARAMETERS Propagation Delay (tPD) Full 1.5 2.3 3.1 1.5 2.3 3.1 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 300 300 ps Fall Time (t ) (20% to 80%) Full 300 300 300 ps F FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 1.5 2.3 3.1 1.5 2.3 3.1 ns 4 DCO Propagation Delay (t ) Full t + t + t + ns CPD FCO FCO FCO (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) 4 DCO to Data Delay (t ) Full (t /24) (t /24) (t /24) (t /24) (t /24) (t /24) (t /24) (t /24) (t /24) ps DATA SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE − 300 + 300 − 300 + 300 − 300 + 300 4 DCO to FCO Delay (t ) Full (t /24) (t /24) (t /24) (t /24) (t /24) (t /24) (t /24) (t /24) (t /24) ps FRAME SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE − 300 + 300 − 300 + 300 − 300 + 300 Data to Data Skew Full ±50 ±200 ±50 ±200 ±50 ±200 ps (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) 25°C 600 600 600 ns Wake-Up Time (Power-Down) 25°C 375 375 375 μs Pipeline Latency Full 8 8 8 CLK cycles APERTURE Aperture Delay (t ) 25°C 750 750 750 ps A Aperture Uncertainty (Jitter) 25°C <1 <1 <1 ps rms Out-of-Range Recovery Time 25°C 1 1 1 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR4 material. 4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. Rev. F | Page 6 of 60 Data Sheet AD9222 TIMING DIAGRAMS N – 1 t A VIN ± x N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t PD t DATA D – x MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 D + x Figure 2. 12-Bit Data Serial Stream, MSB First (Default) N – 1 VIN ± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA D – x MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D8 D7 D6 D5 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 N – 8 N – 8 N – 8 D + x Figure 3. 10-Bit Data Serial Stream, MSB First Rev. F | Page 7 of 60 05967-002 05967-003 AD9222 Data Sheet N – 1 VIN ± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA D – x LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 LSB D0 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 D + x Figure 4. 12-Bit Data Serial Stream, LSB First Rev. F | Page 8 of 60 05967-004 Data Sheet AD9222 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings With may cause permanent damage to the device. This is a stress Parameter Respect To Rating rating only; functional operation of the device at these or any ELECTRICAL other conditions above those indicated in the operational AVDD AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD DRGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect AGND DRGND −0.3 V to +0.3 V device reliability. AVDD DRVDD −2.0 V to +2.0 V Digital Outputs DRGND −0.3 V to +2.0 V THERMAL IMPEDANCE (D + x, D − x, DCO+, DCO−, FCO+, FCO−) Table 6. CLK+, CLK− AGND −0.3 V to +3.9 V Air Flow 1 θ θ θ VIN + x, VIN − x AGND −0.3 V to +2.0 V Velocity (m/s) JA JB JC SDIO/ODM AGND −0.3 V to +2.0 V 0.0 17.7°C/W PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V 1.0 15.5°C/W 8.7°C/W 0.6°C/W 2.5 13.9°C/W REFT, REFB, RBIAS AGND −0.3 V to +2.0 V VREF, SENSE AGND −0.3 V to +2.0 V 1 θ for a 4-layer PCB with solid ground plane (simulated). Exposed pad JA ENVIRONMENTAL soldered to PCB. Operating Temperature −40°C to +85°C Range (Ambient) ESD CAUTION Maximum Junction 150°C Temperature Lead Temperature 300°C (Soldering, 10 sec) Storage Temperature −65°C to +150°C Range (Ambient) Rev. F | Page 9 of 60 AD9222 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AVDD 1 48 AVDD VIN + G 2 47 VIN + B VIN – G 3 46 VIN – B AVDD 4 45 AVDD EXPOSED PADDLE, PIN 0 VIN – H 5 (BOTTOM OF PACKAGE) 44 VIN – A VIN + H 6 43 VIN + A AVDD 7 42 AVDD AD9222 AVDD 8 41 PDWN TOP VIEW CLK– 9 40 CSB (Not to Scale) CLK+ 10 39 SDIO/ODM AVDD 11 38 SCLK/DTP AVDD 12 37 AVDD DRGND 13 36 DRGND DRVDD 14 35 DRVDD D – H 15 34 D + A D + H 16 33 D – A NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND Figure 5. 64-Lead LFCSP Pin Configuration, Top View Table 7. Pin Function Descriptions Pin No. Mnemonic Description 0 AGND Analog Ground (Exposed Paddle) 1, 4, 7, 8, 11, AVDD 1.8 V Analog Supply 12, 37, 42, 45, 48, 51, 59, 62 13, 36 DRGND Digital Output Driver Ground 14, 35 DRVDD 1.8 V Digital Output Driver Supply 2 VIN + G ADC G Analog Input True 3 VIN − G ADC G Analog Input Complement 5 VIN − H ADC H Analog Input Complement 6 VIN + H ADC H Analog Input True 9 CLK− Input Clock Complement 10 CLK+ Input Clock True 15 D − H ADC H Digital Output Complement 16 D + H ADC H Digital Output True 17 D − G ADC G Digital Output Complement 18 D + G ADC G Digital Output True 19 D − F ADC F Digital Output Complement 20 D + F ADC F Digital Output True 21 D − E ADC E Digital Output Complement 22 D + E ADC E Digital Output True 23 DCO− Data Clock Digital Output Complement 24 DCO+ Data Clock Digital Output True 25 FCO− Frame Clock Digital Output Complement 26 FCO+ Frame Clock Digital Output True 27 D − D ADC D Digital Output Complement 28 D + D ADC D Digital Output True 29 D − C ADC C Digital Output Complement 30 D + C ADC C Digital Output True 31 D − B ADC B Digital Output Complement 32 D + B ADC B Digital Output True Rev. F | Page 10 of 60 D – G 17 64 VIN + F D + G 18 63 VIN – F 62 D – F 19 AVDD D + F 20 61 VIN – E D – E 21 60 VIN + E D + E 22 59 AVDD DCO– 23 58 REFT DCO+ 24 57 REFB FCO– 25 56 VREF FCO+ 26 55 SENSE D – D 27 54 RBIAS D + D 28 53 VIN + D D – C 29 52 VIN – D D + C 30 51 AVDD D – B 31 50 VIN – C D + B 32 49 VIN + C 05967-005 Data Sheet AD9222 Pin No. Mnemonic Description 33 D − A ADC A Digital Output Complement 34 D + A ADC A Digital Output True 38 SCLK/DTP Serial Clock/Digital Test Pattern 39 SDIO/ODM Serial Data Input-Output/Output Driver Mode 40 CSB Chip Select Bar 41 PDWN Power Down 43 VIN + A ADC A Analog Input True 44 VIN − A ADC A Analog Input Complement 46 VIN − B ADC B Analog Input Complement 47 VIN + B ADC B Analog Input True 49 VIN + C ADC C Analog Input True 50 VIN − C ADC C Analog Input Complement 52 VIN − D ADC D Analog Input Complement 53 VIN + D ADC D Analog Input True 54 RBIAS External Resistor to Set the Internal ADC Core Bias Current 55 SENSE Reference Mode Selection 56 VREF Voltage Reference Input/Output 57 REFB Differential Reference (Negative) 58 REFT Differential Reference (Positive) 60 VIN + E ADC E Analog Input True 61 VIN − E ADC E Analog Input Complement 63 VIN − F ADC F Analog Input Complement 64 VIN + F ADC F Analog Input True Rev. F | Page 11 of 60 AD9222 Data Sheet EQUIVALENT CIRCUITS DRVDD V V D– D+ VIN ± x V V DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ 1kΩ SCLK/DTP AND PDWN 10Ω CLK– 30kΩ Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit 100Ω RBIAS 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit Figure 11. Equivalent RBIAS Circuit Rev. F | Page 12 of 60 05967-006 05967-007 05967-008 05967-009 05967-011 05967-010 Data Sheet AD9222 AVDD 70kΩ 1kΩ CSB VREF 6kΩ Figure 14. Equivalent VREF Circuit Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit Rev. F | Page 13 of 60 05967-013 05967-012 05967-014 AD9222 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 70.35dB SNR = 70.79dB ENOB = 11.40 BITS ENOB = 11.47 BITS –20 –20 SFDR = 83.86dBc SFDR = 84.71dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. Single-Tone 32k FFT with f = 35 MHz, AD9222-50 Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-40 IN 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 70.02dB SNR = 70.32dB ENOB = 11.45 BITS ENOB = 11.39 BITS –20 –20 SFDR = 86.3dBc SFDR = 84.28dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Single-Tone 32k FFT with f = 19.7 MHz, AD9222-40 IN Figure 19. Single-Tone 32k FFT with fIN = 70 MHz, AD9222-50 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 70.72dB SNR = 69.25dB ENOB = 11.45 BITS ENOB = 11.21 BITS –20 SFDR = 72.85dBc –20 SFDR = 85.79dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. Single-Tone 32k FFT with f = 120 MHz, AD9222-50 Figure 17. Single-Tone 32k FFT with f = 2.3 MHz, AD9222-50 IN IN Rev. F | Page 14 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05967-016 05967-015 05967-017 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05967-020 05967-019 05967-018 Data Sheet AD9222 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 68.67dB SNR = 70.21dB –20 –20 ENOB = 10.79 BITS ENOB = 11.31 BITS SFDR = 71.49dBc SFDR = 82.37dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 30 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-65 Figure 24. Single-Tone 32k FFT with fIN = 120 MHz, AD9222-65 0 100 AIN = –0.5dBFS SNR = 69.8dB 95 –20 ENOB = 11.22 BITS 2V p-p, SFDR SFDR = 80.61dBc 90 –40 85 –60 80 75 –80 2V p-p, SNR 70 –100 65 –120 60 0 5 10 15 20 25 30 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) ENCODE (MSPS) Figure 22. Single-Tone 32k FFT with fIN = 35 MHz, AD9222-65 Figure 25. SNR/SFDR vs. fSAMPLE, fIN = 2.61 MHz, AD9222-50 0 90 AIN = –0.5dBFS SNR = 69.65dB –20 ENOB = 11.07 BITS 85 SFDR = 74.79dBc 2V p-p, SFDR –40 80 –60 75 –80 70 2V p-p, SNR –100 65 –120 60 0 5 10 15 20 25 30 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) ENCODE (MSPS) Figure 23. Single-Tone 32k FFT with fIN = 70 MHz, AD9222-65 Figure 26. SNR/SFDR vs. fSAMPLE, fIN = 20.1 MHz, AD9222-50 Rev. F | Page 15 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05967-087 05967-086 05967-085 AMPLITUDE (dBFS) SNR/SFDR (dB) SNR/SFDR (dB) 05967-088 05967-022 05967-021 AD9222 Data Sheet 100 90 80 95 70 90 2V p-p, SFDR 2V p-p, SFDR 60 80dB 85 REFERENCE LINE 50 80 40 75 2V p-p, SNR 30 70 20 2V p-p, SNR 65 10 60 0 10 15 20 25 30 35 40 45 50 55 60 65 –60 –50 –40 –30 –20 –10 0 ENCODE (MSPS) INPUT AMPLITUDE (dBFS) Figure 27. SNR/SFDR vs. f , f = 2.3 MHz, AD9222-65 Figure 30. SNR/SFDR vs. Analog Input Level, f = 10.3 MHz, AD9222-65 SAMPLE IN IN 100 90 2V p-p, SFDR 90 85 80 2V p-p, SFDR 70 80 80dB 60 REFERENCE 75 50 40 2V p-p, SNR 70 30 2V p-p, SNR 20 65 10 0 60 10 15 20 25 30 35 40 45 50 55 60 65 –60 –50 –40 –30 –20 –10 0 ENCODE (MSPS) INPUT AMPLITUDE (dBFS) Figure 28. SNR/SFDR vs. f , f = 19.7 MHz, AD9222-65 Figure 31. SNR/SFDR vs. Analog Input Level, f = 35 MHz, AD9222-50 SAMPLE IN IN 100 90 90 80 80 70 2V p-p, SFDR 70 2V p-p, SFDR 60 80dB REFERENCE 60 LINE 80dB 50 REFERENCE 50 40 40 2V p-p, SNR 30 30 2V p-p, SNR 20 20 10 10 0 0 –60 –50 –40 –30 –20 –10 0 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 29. SNR/SFDR vs. Analog Input Level, f = 10.3 MHz, AD9222-50 Figure 32. SNR/SFDR vs. Analog Input Level, f = 35 MHz, AD9222-65 IN IN Rev. F | Page 16 of 60 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 05967-023 05967-090 05967-089 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 05967-024 05967-092 05967-091 Data Sheet AD9222 0 0 AIN1 AND AIN2 = –7dBFS AIN1 AND AIN2 = –7dBFS SFDR = 89.87dB SFDR = 80.42dB IMD2 = 96.07dBc IMD2 = 83.92dBc –20 –20 IMD3 = 90.16dBc IMD3 = 80.60dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, Figure 36. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, AD9222-50 AD9222-40 0 0 AIN1 AND AIN2 = –7dBFS AIN1 AND AIN2 = –7dBFS SFDR = 77.24dB SFDR = 79.5dB IMD2 = 91.66dBc –20 –20 IMD2 = 80.0dBc IMD3 = 77.72dBc IMD3 = 84.1dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, Figure 37. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, AD9222-65 AD9222-40 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 84.49dB AIN1 AND AIN2 = –7dBFS IMD2 = 85.83dBc SFDR = 75.2dB –20 IMD3 = 84.54dBc –20 IMD2 = 79.3dBc IMD3 = 75.1dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 30 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 38. Two-Tone 32k FFT with f = 70 MHz and f = 71 MHz, AD9222-65 Figure 35. Two-Tone 32k FFT with f = 15 MHz and f = 16 MHz, AD9222-50 IN1 IN2 IN1 IN2 Rev. F | Page 17 of 60 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05967-027 05967-026 05967-025 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05967-094 05967-093 05967-032 AD9222 Data Sheet 90 90 2V p-p, SFDR 85 85 SFDR 80 80 75 75 SNR 70 70 2V p-p, SINAD 65 65 60 60 1 10 100 1000 –40 –20 0 20 40 60 80 ANALOG INPUT FREQUENCY (MHz) TEMPERATURE (°C) Figure 39. SNR/SFDR vs. fIN, AD9222-50 Figure 42. SINAD/SFDR vs. Temperature, fIN = 2.3 MHz, AD9222-65 90 90 85 85 2V p-p, SFDR 80 2V p-p, SFDR 80 75 70 75 2V p-p, SNR 2V p-p, SINAD 65 70 60 65 55 50 60 1 10 100 1000 –40 –20 0 20 40 60 80 FREQUENCY (MHz) TEMPERATURE (°C) Figure 40. SNR/SFDR vs. f , AD9222-65 IN Figure 43. SINAD/SFDR vs. Temperature, fIN = 20.1 MHz, AD9222-50 100 90 95 2V p-p, SFDR 85 90 80 2V p-p, SFDR 85 80 75 75 70 2V p-p, SINAD 2V p-p, SINAD 70 65 65 60 60 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 41. SINAD/SFDR vs. Temperature, fIN = 2.61 MHz, AD9222-50 Figure 44. SINAD/SFDR vs. Temperature, fIN = 19.7 MHz, AD9222-65 Rev. F | Page 18 of 60 SNR/SFDR (dB) SNR/SFDR (dB) SINAD/SFDR (dB) 05967-030 05967-029 05967-095 SINAD/SFDR (dB) SINAD/SFDR (dB) SINAD/SFDR (dB) 05967-097 05967-031 05967-096 Data Sheet AD9222 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 48. DNL, fIN = 35 MHz, AD9222-65 Figure 45. INL, fIN = 2.3 MHz, AD9222-50 –30 1.0 0.8 –35 0.6 –40 0.4 –45 0.2 0 –50 –0.2 –55 –0.4 –60 –0.6 –65 –0.8 –70 –1.0 0 5 10 15 20 25 30 35 40 0 500 1000 1500 2000 2500 3000 3500 4000 CODE FREQUENCY (MHz) Figure 46. INL, fIN = 35 MHz, AD9222-65 Figure 49. CMRR vs. Frequency, AD9222-50 1.0 1.8 0.27 LSB rms 0.8 1.6 0.6 1.4 0.4 1.2 0.2 1.0 0 0.8 –0.2 0.6 –0.4 0.4 –0.6 0.2 –0.8 –1.0 0 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 47. DNL, fIN = 2.3 MHz, AD9222-50 Figure 50. Input-Referred Noise Histogram, AD9222-50 Rev. F | Page 19 of 60 DNL (LSB) INL (LSB) INL (LSB) 05967-099 05967-098 05967-036 DNL (LSB) NUMBER OF HITS (Millions) CMRR (dB) 05967-038 05967-056 05967-099 AD9222 Data Sheet 2.5 0 0.3 LSB rms –1 –3dB BANDWIDTH = 325MHz –2 2.0 –3 –4 1.5 –5 –6 1.0 –7 –8 0.5 –9 –10 0 –11 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 0 50 100 150 200 250 300 350 400 450 500 CODE FREQUENCY (MHz) Figure 51. Input-Referred Noise Histogram, AD9222-65 Figure 53. Full-Power Bandwidth vs. Frequency, AD9222-50 0 NPR = 60.3dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz –20 –40 –60 –80 –100 –120 0 5 10 15 20 25 FREQUENCY (MHz) Figure 52. Noise Power Ratio (NPR), AD9222-50 Rev. F | Page 20 of 60 AMPLITUDE (dBFS) NUMBER OF HITS (Millions) 05967-041 05967-100 AMPLITUDE (dBFS) 05967-040 Data Sheet AD9222 THEORY OF OPERATION The AD9222 architecture consists of a pipelined ADC divided The clock signal alternately switches the input circuit between into three sections: a 4-bit first stage followed by eight 1.5-bit sample mode and hold mode (see Figure 54). When the input stages and a final 3-bit flash. Each stage provides sufficient circuit is switched into sample mode, the signal source must be overlap to correct for flash errors in the preceding stage. The capable of charging the sample capacitors and settling within quantized outputs from each stage are combined into a final one-half of a clock cycle. A small resistor in series with each 12-bit result in the digital correction logic. The pipelined input can help reduce the peak transient current injected from architecture permits the first stage to operate with a new input the output stage of the driving source. In addition, low-Q inductors sample while the remaining stages operate with preceding samples. or ferrite beads can be placed on each leg of the input to reduce Sampling occurs on the rising edge of the clock. high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of low- Each stage of the pipeline, excluding the last, consists of a low Q inductors or ferrite beads is required when driving the converter resolution flash ADC connected to a switched-capacitor DAC front end at high IF frequencies. Either a shunt capacitor or two and an interstage residue amplifier (for example, a multiplying single-ended capacitors can be placed on the inputs to provide a digital-to-analog converter (MDAC)). The residue amplifier matching passive network. This ultimately creates a low-pass magnifies the difference between the reconstructed DAC output filter at the input to limit unwanted broadband noise. See the and the flash input for the next stage in the pipeline. One bit of AN-742 Application Note, the AN-827 Application Note, and the redundancy is used in each stage to facilitate digital correction Analog Dialogue article “Transformer-Coupled Front-End for of flash errors. The last stage simply consists of a flash ADC. Wideband A/D Converters” (Volume 39, April 2005) for more The output staging block aligns the data, corrects errors, and information. In general, the precise values depend on the passes the data to the output buffers. The data is then serialized application. and aligned to the frame and data clocks. The analog inputs of the AD9222 are not internally dc-biased. ANALOG INPUT CONSIDERATIONS Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that V = AVDD/2 is The analog input to the AD9222 is a differential switched-capacitor CM circuit designed for processing differential input signals. This recommended for optimum performance, but the device can circuit can support a wide common-mode range while maintaining function over a wider range with reasonable performance, as excellent performance. An input common-mode voltage of shown in Figure 55 and Figure 57. midsupply minimizes signal-dependent errors and provides optimum performance. H C PAR H VIN + x C SAMPLE S S S S C SAMPLE VIN – x H C PAR H Figure 54. Switched-Capacitor Input Circuit Rev. F | Page 21 of 60 05967-043 AD9222 Data Sheet 90 90 SFDR (dBc) 85 85 SFDR (dBc) 80 80 75 75 SNR (dB) SNR (dB) 70 70 65 65 60 60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 55. SNR/SFDR vs. Common-Mode Voltage, Figure 57. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, AD9222-50 fIN = 35 MHz, AD9222-50 90 90 SFDR (dBc) 85 85 SFDR (dBc) 80 80 75 75 SNR (dB) 70 70 SNR (dB) 65 65 60 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 56. SNR/SFDR vs. Common-Mode Voltage, Figure 58. SNR/SFDR vs. Common-Mode Voltage, f = 2.3 MHz, AD9222-65 f = 35 MHz, AD9222-65 IN IN Rev. F | Page 22 of 60 SNR/SFDR (dB) SNR/SFDR (dB) 05967-101 05967-044 SNR/SFDR (dB) SNR/SFDR (dB) 05967-102 05967-042 Data Sheet AD9222 ADT1–1WT For best dynamic performance, the source impedances driving 1:1 Z RATIO C R VIN + x and VIN − x should be matched such that common- VIN + x mode settling errors are symmetrical. These errors are reduced ADC 2Vp-p 49.9Ω 1 C DIFF AD9222 by the common-mode rejection of the ADC. An internal R AVDD VIN – x reference buffer creates the positive and negative reference AGND C 1kΩ voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer 1kΩ is set to midsupply, and the REFT and REFB voltages and span 0.1μF are defined as 1 C IS OPTIONAL. DIFF Figure 59. Differential Transformer-Coupled Configuration REFT = 1/2 (AVDD + VREF) for Baseband Applications REFB = 1/2 (AVDD − VREF) ADT1–1WT 2Vp-p Span = 2 × (REFT − REFB) = 2 × VREF 16nH 16nH 0.1μF 1:1 Z RATIO 33Ω VIN + x It can be seen from these equations that the REFT and REFB 65Ω ADC 499Ω 2.2pF 1kΩ AD9222 voltages are symmetrical about the midsupply voltage and, by 16nH 33Ω VIN – x definition, the input span is twice the value of the VREF voltage. AVDD Maximum SNR performance is achieved by setting the ADC to 1kΩ the largest span in a differential configuration. In the case of the 0.1μF 1kΩ AD9222, the largest input span available is 2 V p-p. Figure 60. Differential Transformer-Coupled Configuration for IF Applications Differential Input Configurations Single-Ended Input Configuration There are several ways to drive the AD9222 either actively or passively; however, optimum performance is achieved by A single-ended input may provide adequate performance in driving the analog input differentially. For example, using the cost-sensitive applications. In this configuration, SFDR and AD8334 differential driver to drive the AD9222 provides distortion performance degrade due to the large input common- excellent performance and a flexible interface to the ADC (see mode swing. If the application requires a single-ended input Figure 62) for baseband applications. This configuration is configuration, ensure that the source impedances on each input commonly used for medical ultrasound systems. are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can still be applied to the ADC’s For applications where SNR is a key parameter, differential VIN + x pin while the VIN − x pin is terminated. Figure 61 details transformer coupling is the recommended input configuration a typical single-ended input configuration. (see Figure 59 and Figure 60) because the noise performance of AVDD most amplifiers is not adequate to achieve the true performance C of the AD9222. 1kΩ R VIN + x Regardless of the configuration, the value of the shunt capacitor, 0.1µF 1kΩ 2V p-p 49.9Ω C, is dependent on the input frequency and may need to be ADC 1 C DIFF AVDD AD9222 reduced or removed. 1kΩ 25Ω R VIN – x C 0.1µF 1kΩ 1 C IS OPTIONAL. DIFF Figure 61. Single-Ended Input Configuration 0.1μF LOP VIP 0.1μF 187Ω R 0.1μF 120nH VOH INH VIN + x 1V p-p AD8334 1.0kΩ 22pF ADC LNA VGA 374Ω C AD9222 1.0kΩ R LMD VIN – x 0.1μF VOL 187Ω 0.1μF AVDD 0.1μF 10μF LON VIN 1kΩ 1kΩ 274Ω 18nF 0.1μF Figure 62. Differential Input Configuration Using the AD8334 Rev. F | Page 23 of 60 05967-049 05967-046 05967-048 05967-047 AD9222 Data Sheet In some applications, it is acceptable to drive the sample clock CLOCK INPUT CONSIDERATIONS inputs with a single-ended CMOS signal. In such applications, For optimum performance, the AD9222 sample clock inputs CLK+ should be directly driven from a CMOS gate, and the (CLK+ and CLK−) should be clocked with a differential signal. CLK− pin should be bypassed to ground with a 0.1 μF capacitor This signal is typically ac-coupled to the CLK+ and CLK− pins in parallel with a 39 kΩ resistor (see Figure 66). Although the via a transformer or capacitors. These pins are biased internally CLK+ input circuit supply is AVDD (1.8 V), this input is and require no additional biasing. designed to withstand input voltages of up to 3.3 V, making the Figure 63 shows a preferred method for clocking the AD9222. The selection of the drive logic voltage very flexible. low jitter clock source is converted from a single-ended signal AD9510/AD9511/ AD9512/AD9513/ to a differential signal using an RF transformer. The back-to- AD9514/AD9515 0.1µF back Schottky diodes across the secondary transformer limit CLK+ CLK OPTIONAL clock excursions into the AD9222 to approximately 0.8 V p-p 0.1µF 1 50Ω 100Ω CMOS DRIVER CLK+ differential. This helps prevent the large voltage swings of the ADC clock from feeding through to other portions of the AD9222, CLK AD9222 0.1µF and it preserves the fast rise and fall times of the signal, which CLK– are critical to low jitter performance. 0.1µF 39kΩ 1 50Ω RESISTOR IS OPTIONAL. ® MINI-CIRCUITS Figure 66. Single-Ended 1.8 V CMOS Sample Clock ADT1-1WT, 1:1Z 0.1µF 0.1µF XFMR AD9510/AD9511/ CLK+ CLK+ AD9512/AD9513/ 100Ω ADC 50Ω AD9514/AD9515 0.1µF AD9222 0.1µF CLK– CLK+ CLK OPTIONAL 0.1µF 1 SCHOTTKY 50Ω 100Ω 0.1µF CLK+ CMOS DRIVER DIODES: HSM2812 ADC CLK AD9222 Figure 63. Transformer-Coupled Differential Clock 0.1µF 0.1µF CLK– Another option is to ac-couple a differential PECL signal to the 1 50Ω RESISTOR IS OPTIONAL. sample clock input pins as shown in Figure 64. The AD9510/ Figure 67. Single-Ended 3.3 V CMOS Sample Clock AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance. Clock Duty Cycle Considerations AD9510/AD9511/ Typical high speed ADCs use both clock edges to generate a AD9512/AD9513/ AD9514/AD9515 variety of internal timing signals. As a result, these ADCs may 0.1µF 0.1µF be sensitive to clock duty cycle. Commonly, a 5% tolerance is CLK+ CLK CLK+ ADC required on the clock duty cycle to maintain dynamic performance 100Ω PECL DRIVER AD9222 0.1µF 0.1µF characteristics. The AD9222 contains a duty cycle stabilizer (DCS) CLK– CLK– CLK that retimes the nonsampling edge, providing an internal clock 1 1 240Ω 240Ω 50Ω 50Ω signal with a nominal 50% duty cycle. This allows a wide range 1 of clock input duty cycles without affecting the performance of 50Ω RESISTORS ARE OPTIONAL. Figure 64. Differential PECL Sample Clock the AD9222. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, AD9510/AD9511/ AD9512/AD9513/ some applications may require the DCS function to be off. If so, AD9514/AD9515 0.1µF 0.1µF keep in mind that the dynamic range performance can be affected CLK+ CLK CLK+ when operated in this mode. See the Memory Map section for ADC 100Ω LVDS DRIVER AD9222 more details on using this feature. 0.1µF 0.1µF CLK– CLK– CLK The duty cycle stabilizer uses a delay-locked loop (DLL) to 1 1 50Ω 50Ω create the nonsampling edge. As a result, any changes to the 1 sampling frequency require approximately eight clock cycles 50Ω RESISTORS ARE OPTIONAL. to allow the DLL to acquire and lock to the new rate. Figure 65. Differential LVDS Sample Clock Rev. F | Page 24 of 60 05967-050 05967-052 05967-051 05967-054 05967-053 Data Sheet AD9222 Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the As shown in Figure 69, the power dissipated by the AD9222 is clock input. The degradation in SNR at a given input frequency proportional to its sample rate. The digital power dissipation (fA) due only to aperture jitter (tJ) can be calculated by does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. SNR Degradation = 20 × log 10(1/2 × π × fA × tJ) 0.40 0.800 In this equation, the rms aperture jitter represents the root mean 0.35 square of all jitter sources, including the clock input, analog input 0.750 signal, and ADC aperture jitter specifications. IF undersampling 0.30 AVDD CURRENT applications are particularly sensitive to jitter (see Figure 68). 0.700 0.25 The clock input should be treated as an analog signal in cases 0.20 0.650 where aperture jitter may affect the dynamic range of the AD9222. TOTAL POWER Power supplies for clock drivers should be separated from the 0.15 0.600 ADC output driver supplies to avoid modulating the clock signal 0.10 with digital noise. Low jitter, crystal-controlled oscillators make 0.550 DRVDD CURRENT the best clock sources. If the clock is generated from another 0.05 type of source (by gating, dividing, or other methods), it should 0.500 0 be retimed by the original clock at the last step. 10 15 20 25 30 35 40 45 50 ENCODE (MSPS) Refer to the AN-501 Application Note and the AN-756 Figure 69. Supply Current vs. f for f = 10.3 MHz, AD9222- 50 Application Note for more in-depth information about jitter SAMPLE IN performance as it relates to ADCs. 500 950 130 450 RMS CLOCK JITTER REQUIREMENT 120 900 400 110 350 AVDD CURRENT 16 BITS 100 300 850 90 TOTAL POWER 250 14 BITS 80 200 800 12 BITS 70 150 10 BITS 60 100 750 0.125ps 8 BITS DRVDD CURRENT 50 0.25ps 50 0.5ps 1.0ps 700 40 0 10 20 30 40 50 60 2.0ps 30 ENCODE (MSPS) 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) Figure 70. Supply Current vs. f for f = 10.3 MHz, AD9222- 65 SAMPLE IN Figure 68. Ideal SNR vs. Input Frequency and Jitter Rev. F | Page 25 of 60 SNR (dB) 05967-055 CURRENT (mA) CURRENT (A) POWER (mW) POWER (W) 05967-057 05967-103 AD9222 Data Sheet By asserting the PDWN pin high, the AD9222 is placed into placed as close to the receiver as possible. If there is no far-end power-down mode. In this state, the ADC typically dissipates receiver termination or there is poor differential trace routing, 11 mW. During power-down, the LVDS output drivers are placed timing errors may result. To avoid such timing errors, it is in a high impedance state. The AD9222 returns to normal recommended that the trace length be no longer than 24 inches operating mode when the PDWN pin is pulled low. This pin is and that the differential output traces be kept close together and both 1.8 V and 3.3 V tolerant. at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 71. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 µF and 4.7 µF decoupling capacitors on REFT and REFB, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors, and approximately 375 µs is required to restore full operation. There are several other power-down options available when using the SPI. The user can individually power down each 5.0ns/DIV CH1 500mV/DIV = FCO channel or put the entire device into standby mode. The latter CH2 500mV/DIV = DCO CH3 500mV/DIV = DATA option allows the user to keep the internal PLL powered when Figure 71. LVDS Output Timing Example in ANSI-644 Mode (Default), fast wake-up times (~600 ns) are required. See the Memory AD9222-50 Map section for more details on using these features. Digital Outputs and Timing The AD9222 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SDIO/ODM pin or SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO/ODM Pin section or Table 16 in the Memory Map section for more information. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. 5.0ns/DIV CH1 500mV/DIV = FCO CH2 500mV/DIV = DCO The AD9222 LVDS outputs facilitate interfacing with LVDS CH3 500mV/DIV = DATA receivers in custom ASICs and FPGAs for superior switching Figure 72. LVDS Output Timing Example in ANSI-644 Mode (Default), performance in noisy environments. Single point-to-point net AD9222-65 topologies are recommended with a 100 Ω termination resistor Rev. F | Page 26 of 60 05967-084 05967-058 Data Sheet AD9222 600 An example of the LVDS output using the ANSI-644 standard EYE: ALL BITS ULS: 9596/15596 (default) data eye and a time interval error (TIE) jitter histogram 400 with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 73 and Figure 74. Figure 75 and Figure 76 show 200 examples of trace lengths exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease 0 of the data eye opening as the edge deviates from the ideal position. –200 It is the user’s responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed –400 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all eight outputs –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns in order to drive longer trace lengths (see Figure 77 and Figure 78). Even though this produces sharper rise and fall times on the data 140 edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. 120 In cases that require increased driver strength to the DCO± and 100 FCO± outputs because of load mismatch, Register 0x15 allows the user to increase the drive strength by 2×. To do this, set the 80 appropriate bit in Register 0x5. Note that this feature cannot be 60 used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and Bit 5 take precedence over this feature. See the Memory Map section for 40 more details. 20 500 EYE: ALL BITS ULS: 12071/12071 0 400 –150ps –100ps –50ps 0ps 50ps 100ps 150ps 300 Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths 200 Less than 24 Inches on Standard FR-4, AD9222-65 100 500 0 EYE: ALL BITS ULS: 12067/12067 400 –100 –200 300 –300 200 –400 100 –500 0 –100 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns –200 –300 90 –400 80 –500 70 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 60 100 50 90 40 80 30 70 20 60 10 50 0 40 –150ps –100ps –50ps 0ps 50ps 100ps 150ps 30 Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, AD9222-50 20 10 0 –200ps –100ps 0ps 100ps 200ps Figure 75. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-50 Rev. F | Page 27 of 60 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 05967-061 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 05967-059 05967-106 AD9222 Data Sheet 500 500 EYE: ALL BITS ULS: 7591/15591 EYE: ALL BITS ULS: 8000/15600 400 400 300 300 200 200 100 100 0 0 –100 –100 –200 –200 –300 –300 –400 –400 –500 –500 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 140 140 120 120 100 100 80 80 60 60 40 40 20 20 0 0 –300ps –200ps –100ps 0ps 100ps 200ps 300ps –200ps –100ps 0ps 100ps 200ps 300ps Figure 76. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Figure 78. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination Greater than 24 Inches on Standard FR-4, AD9222-65 on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-65 The format of the output data is offset binary by default. An 400 EYE: ALL BITS ULS: 12072/12072 example of the output coding format can be found in Table 8. 300 To change the output data format to twos complement, see the 200 Memory Map section. 100 Table 8. Digital Output Coding 0 (VIN + x) − (VIN − x), Digital Output Offset Binary –100 Input Span = 2 V p-p (V) (D11 ... D0) Code –200 4095 +1.00 1111 1111 1111 2048 0.00 1000 0000 0000 –300 2047 −0.000488 0111 1111 1111 –400 0 −1.00 0000 0000 0000 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns Data from each ADC is serialized and provided on a separate 80 channel. The data rate for each serial stream is equal to 12 bits 70 times the sample clock rate, with a maximum of 780 Mbps (12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion 60 rate is 10 MSPS. However, if lower sample rates are required for 50 a specific application, the PLL can be set up via the SPI to allow 40 encode rates as low as 5 MSPS. See the Memory Map section to enable this feature. 30 20 10 0 –150ps –100ps –50ps 0ps 50ps 100ps 150ps Figure 77. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-50 Rev. F | Page 28 of 60 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 05967-060 05967-105 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 05967-104 Data Sheet AD9222 Two output clocks are provided to assist in capturing data from falling edges of the DCO that supports double data rate (DDR) the AD9222. The DCO is used to clock the output data and is capturing. The FCO is used to signal the start of a new output equal to six times the sample clock (CLK) rate. Data is clocked byte and is equal to the sample clock rate. See the timing out of the AD9222 and must be captured on the rising and diagram shown in Figure 2 for more information. Table 9. Flexible Output Test Modes Output Test Mode Subject to Data Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select 0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 (8-bit) Same Yes 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 0010 +Full-scale short 1111 1111 (8-bit) Same Yes 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0011 −Full-scale short 0000 0000 (8-bit) Same Yes 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 0100 Checkerboard 1010 1010 (8-bit) 0101 0101 (8-bit) No 10 1010 1010 (10-bit) 01 0101 0101 (10-bit) 1010 1010 1010 (12-bit) 0101 0101 0101 (12-bit) 10 1010 1010 1010 (14-bit) 01 0101 0101 0101 (14-bit) 1 0101 PN sequence long N/A N/A Yes 1 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 (8-bit) 0000 0000 (8-bit) No 11 1111 1111 (10-bit) 00 0000 0000 (10-bit) 1111 1111 1111 (12-bit) 0000 0000 0000 (12-bit) 11 1111 1111 1111 (14-bit) 00 0000 0000 0000 (14-bit) 1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No 1001 1-/0-bit toggle 1010 1010 (8-bit) N/A No 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 1010 1× sync 0000 1111 (8-bit) N/A No 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1011 One bit high 1000 0000 (8-bit) N/A No 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1100 Mixed frequency 1010 0011 (8-bit) N/A No 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) 1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Rev. F | Page 29 of 60 AD9222 Data Sheet When the SPI is used, the DCO phase can be adjusted in 60° SDIO/ODM Pin increments relative to the data edge. This enables the user to The SDIO/ODM pin is for use in applications that do not require refine system timing margins if required. The default DCO+ SPI mode operation. This pin can enable a low power, reduced and DCO− timing, as shown in Figure 2, is 90° relative to the signal option (similar to the IEEE 1596.3 reduced range link output data edge. output standard) if it and the CSB pin are tied to AVDD during device power-up. This option should only be used when the An 8-, 10-, and 14-bit serial stream can also be initiated from digital output trace lengths are less than 2 inches from the LVDS the SPI. This allows the user to implement and test compatibility receiver. When this option is used, the FCO, DCO, and outputs with lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is function normally, but the LVDS signal swing of all channels is shortened. See Figure 3 for the 10-bit example. However, when reduced from 350 mV p-p to 200 mV p-p, allowing the user to using the 14-bit option, the data stream stuffs two 0s at the end further reduce the power on the DRVDD supply. of the 14-bit serial data. For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 kΩ When the SPI is used, all of the data outputs can also be internal pull-down resistor pulls this pin low. This pin is only inverted from their nominal state. This is not to be confused 1.8 V tolerant. If applications require this pin to be driven from a with inverting the serial stream to an LSB-first mode. In default 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to mode, as shown in Figure 2, the MSB is first in the data output serial stream. However, this can be inverted so that the LSB is limit the current. first in the data output serial stream (see Figure 4). Table 11. Output Driver Mode Pin Settings There are 12 digital output test pattern options available that Resulting Resulting can be initiated through the SPI. This is a useful feature when Selected ODM ODM Voltage Output Standard FCO and DCO Normal ANSI-644 ANSI-644 validating receiver capture and timing. Refer to Table 9 for the 10 kΩ to AGND Operation (default) (default) output bit sequencing options available. Some test patterns have Low power, Low power, ODM AVDD two serial sequential words and can be alternated in various reduced reduced signal ways, depending on the test pattern chosen. Note that some signal option option patterns may not adhere to the data format select option. In addition, user-defined test patterns can be assigned in the 0x19, SCLK/DTP Pin 0x1A, 0x1B, and 0x1C register addresses. All test mode options The SCLK/DTP pin is for use in applications that do not require except PN sequence short and PN sequence long can support SPI mode operation. This pin can enable a single digital test 8- to 14-bit word lengths in order to verify data capture to the pattern if it and the CSB pin are held high during device power- receiver. up. When the SCLK/DTP is tied to AVDD, the ADC channel The PN sequence short pattern produces a pseudorandom bit outputs shift out the following pattern: 1000 0000 0000. The 9 sequence that repeats itself every 2 − 1 or 511 bits. A FCO and DCO function normally while all channels shift out the description of the PN sequence and how it is generated can be repeatable test pattern. This pattern allows the user to perform found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The timing alignment adjustments among the FCO, DCO, and output only difference is that the starting value must be a specific value data. For normal operation, this pin should be tied to AGND instead of all 1s (see Table 10 for the initial values). through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant. The PN sequence long pattern produces a pseudorandom bit Table 12. Digital Test Pattern Pin Settings 23 sequence that repeats itself every 2 − 1 or 8,388,607 bits. A Resulting Resulting description of the PN sequence and how it is generated can be Selected DTP DTP Voltage D + x and D − x FCO and DCO found in section 5.6 of the ITU-T 0.150 (05/96) standard. The Normal Normal 10 kΩ to AGND Normal operation only differences are that the starting value must be a specific Operation operation DTP AVDD 1000 0000 0000 Normal operation value instead of all 1s (see Table 10 for the initial values) and the AD9222 inverts the bit stream with relation to the ITU standard. Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map Table 10. PN Sequence section for information about the options available. Initial First Three Output Samples Sequence Value (MSB First) PN Sequence Short 0x0df 0xdf9, 0x353, 0x301 PN Sequence Long 0x29b80a 0x591, 0xfd7, 0x0a3 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. Rev. F | Page 30 of 60 Data Sheet AD9222 CSB Pin The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input full- The CSB pin should be tied to AVDD for applications that do scale range of the ADC equals twice the voltage at the reference not require SPI mode operation. By tying CSB high, all SCLK pin for either an internal or an external reference configuration. and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. If the reference of the AD9222 is used to drive multiple converters to improve gain matching, the loading of the refer- RBIAS Pin ence by the other converters must be considered. Figure 81 To set the internal core bias current of the ADC, place a resistor depicts how the internal reference voltage is affected by loading. (nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the AVDD current of VIN + x the ADC to a nominal 450 mA at 65 MSPS. Therefore, it is VIN – x REFT imperative that at least a 1% tolerance on this resistor be used to 0.1µF achieve consistent performance + ADC 0.1µF 4.7µF CORE Voltage Reference REFB A stable, accurate 0.5 V voltage reference is built into the 0.1µF VREF AD9222. This is gained up internally by a factor of 2, setting 1µF 0.1µF 0.5V VREF to 1.0 V, which results in a full-scale differential input span SELECT LOGIC of 2 V p-p. The V is set internally by default; however, the REF SENSE VREF pin can be driven externally with a 1.0 V reference to improve accuracy. When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low-ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the Figure 79. Internal Reference Configuration PCB as the AD9222. The recommended capacitor values and configurations for the AD9222 reference pin are shown in VIN + x Figure 79. VIN – x REFT Table 13. Reference Settings 0.1µF + ADC 0.1µF 4.7µF Resulting CORE Differential REFB EXTERNAL REFERENCE Selected Mode SENSE Voltage Resulting VREF (V) Span (V p-p) 0.1µF VREF External AVDD N/A 2 × external Reference reference 1 1 1µF 0.1µF 0.5V Internal, AGND to 0.2 V 1.0 2.0 SELECT AVDD LOGIC 2 V p-p FSR SENSE Internal Reference Operation A comparator within the AD9222 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal 1 OPTIONAL. resistor divider (see Figure 79), setting VREF to 1 V. Figure 80. External Reference Operation Rev. F | Page 31 of 60 05967-064 05967-065 AD9222 Data Sheet 0.02 External Reference Operation 0 The use of an external reference may be necessary to enhance –0.02 the gain accuracy of the ADC or improve thermal drift charac- –0.04 teristics. Figure 82 shows the typical drift characteristics of the internal reference in 1 V mode. –0.06 When the SENSE pin is tied to AVDD, the internal reference is –0.08 disabled, allowing the use of an external reference. The external –0.10 reference is loaded with an equivalent 6 kΩ load. An internal –0.12 reference buffer generates the positive and negative full-scale –0.14 references, REFT and REFB, for the ADC core. Therefore, the –0.16 external reference must be limited to a nominal of 1.0 V. –0.18 5 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 0 Figure 82. Typical VREF Drift, AD9222-50 –5 –10 –15 –20 –25 –30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) Figure 81. VREF Accuracy vs. Load, AD9222-50 Rev. F | Page 32 of 60 V ERROR (%) REF 05727-083 V ERROR (%) REF 05967-028 Data Sheet AD9222 SERIAL PORT INTERFACE (SPI) CSB remains low until the communication cycle is complete. The AD9222 serial port interface allows the user to configure However, if connected to a slow device, CSB can be brought the converter for specific functions or operations through a high between bytes, allowing older microcontrollers enough structured register space provided inside the ADC. This gives time to transfer data into shift registers. CSB can be stalled the user added flexibility and customization, depending on the when transferring one, two, or three bytes of data. When W0 and application. Addresses are accessed via the serial port and can W1 are set to 11, the device enters streaming mode and continues be written to or read from via the port. Memory is organized to process data, either reading or writing, until CSB is taken into bytes that can be further divided down into fields, as doc- high to end the communication cycle. This allows complete umented in the Memory Map section. Detailed operational memory transfers without requiring additional instructions. information can be found in the AN-877 Application Note, Regardless of the mode, if CSB is taken high in the middle of a Interfacing to High Speed ADCs via SPI. byte transfer, the SPI state machine is reset and the device waits There are three pins that define the SPI: SCLK, SDIO, and CSB for a new instruction. (see Table 14). The SCLK pin is used to synchronize the read In addition to the operation modes, the SPI port configuration and write data presented to the ADC. The SDIO pin is a dual- influences how the AD9222 operates. For applications that do purpose pin that allows data to be sent to and read from the not require a control port, the CSB line can be tied and held high. internal ADC memory map registers. The CSB pin is an active This places the remainder of the SPI pins into their secondary low control that enables or disables the read and write cycles. modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin Table 14. Serial Port Pins sections. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for Pin Function communication. Although the device is synchronized during SCLK Serial Clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. power-up, the user should ensure that the serial port remains SDIO Serial Data Input/Output. A dual-purpose pin. The synchronized with the CSB line when using this mode. When typical role for this pin is an input or output, depending operating in 2-wire mode, it is recommended to use a 1-, 2-, or on the instruction sent and the relative position in the 3-byte transfer exclusively. Without an active CSB line, streaming timing frame. mode can be entered but not exited. CSB Chip Select Bar (Active Low). This control gates the read and write cycles. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents The falling edge of the CSB in conjunction with the rising edge of the on-chip memory. If the instruction is a readback operation, of the SCLK determines the start of the framing sequence. During performing a readback causes the SDIO pin to change from an an instruction phase, a 16-bit instruction is transmitted followed by input to an output at the appropriate point in the serial frame. one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions Data can be sent in MSB- or LSB-first mode. MSB-first mode can be found in Figure 84 and Table 15. During normal operation, is the default at power-up and can be changed by adjusting the CSB is used to signal to the device that SPI commands are to be configuration register. For more information about this and received and processed. When CSB is brought low, the device other features, see the AN-877 Application Note, Interfacing to processes SCLK and SDIO to process instructions. Normally, High Speed ADCs via SPI. Rev. F | Page 33 of 60 AD9222 Data Sheet This interface is flexible enough to be controlled by either serial HARDWARE INTERFACE PROMS or PIC mirocontrollers, providing the user with an The pins described in Table 14 compose the physical interface alternative method, other than a full SPI controller, to program between the user’s programming device and the serial port of the ADC (see the AN-812 Application Note). the AD9222. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an If the user chooses not to use the SPI, these dual-function pins input during write phases and as an output during readback. serve their secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation If multiple SDIO pins share a common connection, care should section for details on which pin-strappable functions are be taken to ensure that proper VOH levels are met. Assuming the supported on the SPI pins. same load for each AD9222, Figure 83 shows the number of SDIO pins that can be connected together and the resulting VOH level. 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 83. SDIO Pin Loading Rev. F | Page 34 of 60 V (V) OH 05967-037 Data Sheet AD9222 t t DS HI t t CLK H t t S t DH LO CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 84. Serial Timing Details Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns) Description t 5 Setup time between the data and the rising edge of SCLK DS t 2 Hold time between the data and the rising edge of SCLK DH t 40 Period of the clock CLK tS 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK t 16 Minimum period that SCLK should be in a logic high state HI t 16 Minimum period that SCLK should be in a logic low state LO t 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK EN_SDIO falling edge (not shown in Figure 84) tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 84) Rev. F | Page 35 of 60 05967-068 AD9222 Data Sheet MEMORY MAP RESERVED LOCATIONS READING THE MEMORY MAP TABLE Undefined memory locations should not be written to except Each row in the memory map register table (Table 16) has eight when writing the default values suggested in this data sheet. address locations. The memory map is divided into three sections: Addresses that have values marked as 0 should be considered the chip configuration register map (Address 0x00 to Address 0x02), reserved and have a 0 written into their registers during power-up. the device index and transfer register map (Address 0x05 and Address 0xFF), and the ADC functions register map (Address 0x08 DEFAULT VALUES to Address 0x22). When the AD9222 comes out of a reset, critical registers are The leftmost column of the memory map indicates the register preloaded with default values. These values are indicated in address number, and the default value is shown in the second right- Table 16, where an X refers to an undefined feature. most column. The (MSB) Bit 7 column is the start of the default LOGIC LEVELS hexadecimal value given. For example, Address 0x09, the clock An explanation of various registers follows: “Bit is set” is register, has a default value of 0x01, meaning Bit 7 = 0, Bit 6 = 0, synonymous with “bit is set to Logic 1” or “writing Logic 1 for Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or the bit.” Similarly, “clear a bit” is synonymous with “bit is set to 0000 0001 in binary. This setting is the default for the duty cycle Logic 0” or “writing Logic 0 for the bit.” stabilizer in the on condition. By writing a 0 to Bit 6 of this address, the duty cycle stabilizer turns off. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. F | Page 36 of 60 Data Sheet AD9222 Table 16. Memory Map Register Default Addr. (MSB) (LSB) Value Default Notes/ (Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments Chip Configuration Registers 00 chip_port_config 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles 1 = on reset reset 1 = on should be 0 = off 1 = on 1 = on 0 = off mirrored so that (default) 0 = off 0 = off (default) LSB- or MSB-first (default) (default) mode is set cor- rectly regardless of shift mode. 01 chip_id 8-bit Chip ID Bits 7:0 Read Default is unique (AD9222 = 0x07), (default) only chip ID, different for each device. This is a read- only register. 02 chip_grade X Child ID [6:4] X X X X Read Child ID used to (identify device variants of Chip ID) only differentiate graded devices. 000 = 65 MSPS 011 = 50 MSPS 001 = 40 MSPS Device Index and Transfer Registers 04 device_index_2 X X X X Data Data Data Data 0x0F Bits are set to Channel Channel Channel Channel determine which G F E on-chip device H 1 = on 1 = on 1 = on receives the next 1 = on (default) (default) (default) write command. (default) 0 = off 0 = off 0 = off 0 = off Clock Clock Data Data Data Data Bits are set to 05 device_index_1 X X 0x0F Channel Channel Channel Channel Channel Channel determine which DCO FCO D C B A on-chip device 1 = on 1 = on 1 = on 1 = on 1 = on 1 = on receives the next 0 = off 0 = off (default) (default) (default) (default) write command. (default) (default) 0 = off 0 = off 0 = off 0 = off FF device_update X X X X X X X SW 0x00 Synchronously transfer transfers data 1 = on from the master 0 = off shift register to (default) the slave. ADC Functions 08 modes X X X X X Internal power-down mode 0x00 Determines 000 = chip run (default) various generic 001 = full power-down modes of chip 010 = standby operation. 011 = reset Duty cycle Turns the 09 clock X X X X X X X 0x01 stabilizer internal duty 1 = on cycle stabilizer (default) on and off. 0 = off 0D test_io User test mode Reset PN Reset 0x00 When this reg- Output test mode—see Table 9 in the 00 = off (default) long gen PN short ister is set, the Digital Outputs and Timing section 01 = on, single alternate 1 = on gen test data is placed 0000 = off (default) 10 = on, single once 0 = off 1 = on on the output 0001 = midscale short 11 = on, alternate once (default) 0 = off pins in place of 0010 = +FS short (default) normal data. 0011 = −FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) Rev. F | Page 37 of 60 AD9222 Data Sheet Default Addr. (MSB) (LSB) Value Default Notes/ (Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 14 output_mode X 0 = LVDS X X X Output 00 = offset binary 0x00 Configures the ANSI-644 invert (default) outputs and the (default) 1 = on 01 = twos format of the data. 1 = LVDS 0 = off complement low power, (default) (IEEE 1596.3 similar) 15 output_adjust X X Output driver X X X DCO and 0x00 Determines termination FCO LVDS or other 00 = none (default) output properties. 2× Drive 01 = 200 Ω Primarily func- Strength 10 = 100 Ω tions to set the 1 = on 11 = 100 Ω LVDS span and 0 = off common-mode (default) levels in place of an external resistor. 16 output_phase X X X X 0011 = output clock phase adjust 0x03 On devices that (0000 through 1010) utilize global 0000 = 0° relative to data edge clock divide, 0001 = 60° relative to data edge determines 0010 = 120° relative to data edge which phase of 0011 = 180° relative to data edge (default) the divider 0101 = 300° relative to data edge output is used to 0110 = 360° relative to data edge supply the 1000 = 480° relative to data edge output clock. 1001 = 540° relative to data edge Internal latching 1010 = 600° relative to data edge is unaffected. 1011 to 1111 = 660° relative to data edge 19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB. 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB. 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB. 21 serial_control LSB first X X X <10 000 = 12 bits (default, normal bit 0x00 Serial stream 1 = on MSPS, stream) control. Default 0 = off low 001 = 8 bits causes MSB first (default) encode 010 = 10 bits and the native rate 011 = 12 bits bit stream mode 100 = 14 bits (global). 1 = on 0 = off (default) 22 serial_ch_stat X X X X X X Channel Channel 0x00 Used to power output power- down individual reset down sections of a 1 = on 1 = on converter (local). 0 = off 0 = off (default) (default) Rev. F | Page 38 of 60 Data Sheet AD9222 Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9222, it is recommended It is required that the exposed paddle on the underside of the that two separate 1.8 V supplies be used: one for analog (AVDD) ADC be connected to analog ground (AGND) to achieve the and one for digital (DRVDD). If only one supply is available, it best electrical and thermal performance of the AD9222. An should be routed to the AVDD first and then tapped off and exposed continuous copper plane on the PCB should mate to isolated with a ferrite bead or a filter choke preceded by the AD9222 exposed paddle, Pin 0. The copper plane should decoupling capacitors for the DRVDD. The user can employ have several vias to achieve the lowest possible resistive thermal several different decoupling capacitors to cover both high and path for heat dissipation to flow through the bottom of the PCB. low frequencies. These should be located close to the point of These vias should be solder-filled or plugged. entry at the PC board level and close to the parts, with minimal To maximize the coverage and adhesion between the ADC and trace lengths. PCB, partition the continuous copper plane by overlaying a A single PC board ground plane should be sufficient when silkscreen on the PCB into several uniform sections. This provides using the AD9222. With proper decoupling and smart parti- several tie points between the ADC and PCB during the reflow tioning of the PC board’s analog, digital, and clock sections, process, whereas using one continuous plane with no partitions optimum performance can be easily achieved. only guarantees one tie point. See Figure 85 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). SILKSCREEN PARTITION PIN 1 INDICATOR Figure 85. Typical PCB Layout Rev. F | Page 39 of 60 05967-069 AD9222 Data Sheet EVALUATION BOARD The AD9222 evaluation board provides all of the support cir- individually. Use P702 to connect a different supply for each cuitry required to operate the ADC in its various modes and section. At least one 1.8 V supply is needed for AVDD_DUT and configurations. The converter can be driven differentially using a DRVDD_DUT; however, it is recommended that separate supplies transformer (default) or an AD8334 driver. The ADC can also be be used for both analog and digital signals and that each supply driven in a single-ended fashion. Separate power pins are provided have a current capability of 1 A. To operate the evaluation board to isolate the DUT from the drive circuitry of the AD8334. Each using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) input configuration can be selected by changing the connection is needed. To operate the evaluation board using the SPI and alter- of various jumpers (see Figure 90 to Figure 94). Figure 86 shows nate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is the typical bench characterization setup used to evaluate the ac needed in addition to the other supplies. performance of the AD9222. It is critical that the signal sources INPUT SIGNALS used for the analog input and clock have very low phase noise When connecting the clock and analog sources to the evalu- (<1 ps rms jitter) to realize the optimum performance of the ation board, use clean signal generators with low phase noise, converter. Proper filtering of the analog input signal to remove such as Rohde & Schwarz SMA or HP8644 signal generators or the harmonics and lower the integrated or broadband noise at the equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable. input is also necessary to achieve the specified noise performance. Enter the desired frequency and amplitude from the ADC specifi- See Figure 90 to Figure 100 for the complete schematics and cations tables. Typically, most Analog Devices, Inc., evaluation layout diagrams demonstrating the routing and grounding boards can accept approximately 2.8 V p-p or 13 dBm sine wave techniques that should be applied at the system level. input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass POWER SUPPLIES filter with 50 Ω terminations. Good choices of such band-pass This evaluation board has a wall-mountable switching power filters are available from TTE, Allen Avionics, and K&L supply that provides a 6 V, 2 A maximum output. Connect the Microwave, Inc. The filter should be connected directly to the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to evaluation board if possible. 63 Hz. The other end of the supply is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, OUTPUT SIGNALS the 6 V supply is fused and conditioned before connecting to The default setup uses the Analog Devices HSC-ADC-FIFO5- three low dropout linear regulators that supply the proper bias INTZ to interface with the Analog Devices standard dual-channel to each of the various sections on the board. FIFO data capture board (HCS-ADC-EVALCZ). Two of the eight When operating the evaluation board in a nondefault condition, channels can be evaluated at the same time. For more L701 to L704 can be removed to disconnect the switching power information on the channel settings and optional settings of these supply. This enables the user to bias each section of the board boards, www.analog.com/FIFO. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz 6V DC 2A MAX 5.0V 1.8V 1.8V 3.3V 3.3V – + – + – + – + – + SWITCHING POWER SUPPLY PC ROHDE & SCHWARZ, RUNNING HSC-ADC-EVALCZ SMA, ADC BAND-PASS XFMR FIFO DATA 2V p-p SIGNAL INTERPOSER ANALYZER FILTER INPUT SYNTHESIZER CAPTURE AD9222 BOARD AND SPI CH A TO CH H BOARD EVALUATION BOARD USER 12-BIT USB ROHDE & SCHWARZ, SOFTWARE CLK SERIAL SMA, CONNECTION 2V p-p SIGNAL LVDS SYNTHESIZER SPI SPI SPI SPI Figure 86. Evaluation Board Connection Rev. F | Page 40 of 60 GND AVDD_5V GND AVDD_DUT GND DRVDD_DUT GND AVDD_3.3V GND VCC 05967-070 Data Sheet AD9222 A differential LVPECL clock can also be used to clock the DEFAULT OPERATION AND JUMPER SELECTION ADC input using the AD9515 (U401). Populate R406 and SETTINGS R407 with 0 Ω resistors and remove R215 and R216 to The following is a list of the default and optional settings or disconnect the default clock path inputs. In addition, populate modes allowed on the AD9222 Rev. A evaluation board. C205 and C206 with a 0.1 μF capacitor and remove C409 and • POWER: Connect the switching power supply that is C410 to disconnect the default clock path outputs. The provided with the evaluation kit between a rated 100 V ac AD9515 has many pin-strappable options that are set to a to 240 V ac wall outlet at 47 Hz to 63 Hz and P701. default mode of operation. Consult the AD9515 data sheet for more information about these and other options. • AIN: The evaluation board is set up for a transformer- coupled analog input with an optimum 50 Ω impedance In addition, an on-board oscillator is available on the OSC401 match of 150 MHz of bandwidth (see Figure 87). For more and can act as the primary clock source. The setup is quick bandwidth response, the differential capacitor across the and involves installing R403 with a 0 Ω resistor and setting analog inputs can be changed or removed. The common the enable jumper (J401) to the on position. If the user wishes mode of the analog inputs is developed from the center to employ a different oscillator, two oscillator footprint options tap of the transformer or AVDD_DUT/2. are available (OSC401) to check the ADC performance. 0 • PDWN: To enable the power-down feature, short J301 to –2 the on position (AVDD) on the PDWN pin. –3dB CUTOFF = 150MHz –4 • SCLK/DTP: To enable the digital test pattern on the digital outputs of the ADC, use J304. If J304 is tied to AVDD during –6 device power-up, Test Pattern 1000 0000 0000 is enabled. See –8 the SCLK/DTP Pin section for details. –10 • SDIO/ODM: To enable the low power, reduced signal option –12 (similar to the IEEE 1595.3 reduced range link LVDS output –14 standard), use J303. If J303 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, –16 reduced signal option from the default ANSI-644 standard. –18 0 50 100 150 200 250 300 350 400 450 500 This option changes the signal swing from 350 mV p-p to FREQUENCY (MHz) 200 mV p-p, reducing the power of the DRVDD supply. See Figure 87. Evaluation Board Full-Power Bandwidth, AD9222-50 the SDIO/ODM Pin section for more details. • VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, • CSB: To enable processing of the SPI information on the R317. This causes the ADC to operate in 2.0 V p-p full-scale SDIO and SCLK pins, tie J302 low in the always enable mode. range. A separate external reference option using the ADR510 To ignore the SDIO and SCLK information, tie J302 to AVDD. or ADR520 is also included on the evaluation board. Populate • Non-SPI Mode: For users who wish to operate the DUT R312 and R313 and remove C307. Proper use of the VREF without using SPI, remove Jumpers J302, J303, and J304. options is noted in the Voltage Reference section. This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins • RBIAS: RBIAS has a default setting of 10 kΩ (R301) to from the control bus, allowing the DUT to operate in its ground and is used to set the ADC core bias current. simplest mode. Each of these pins has internal termination and will float to its respective level. • CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth • D + x, D − x: If an alternative data capture method to the setup 1:1 impedance ratio transformer (T401) that adds a very shown in Figure 90 is used, optional receiver terminations, low amount of jitter to the clock path. The clock input is R318 and R320 to R328, can be installed next to the high 50 Ω terminated and ac-coupled to handle single-ended speed backplane connector. sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. Rev. F | Page 41 of 60 AMPLITUDE (dBFS) 05967-071 AD9222 Data Sheet In this example, a 16 MHz, two-pole low-pass filter was applied ALTERNATIVE ANALOG INPUT DRIVE to the AD8334 outputs. The following components need to be CONFIGURATION removed and/or changed: The following is a brief description of the alternative analog • Remove L507, L508, L511, L512, L515, L516, L519, L520, input drive configuration using the AD8334 dual VGA. If this L607, L608, L611, L612, L615, L616, L619, and L620 on the drive option is in use, some components may need to be populated, in which case all the necessary components are listed AD8334 analog outputs. in Table 17. For more details on the AD8334 dual VGA, • Populate L507, L508, L511, L512, L515, L516, L519, L520, including how it works and its optional pin settings, consult the L607, L608, L611, L612, L615, L616, L619, and L620 with AD8334 data sheet. 680 nH inductors. To configure the analog input to drive the VGA instead of the • Populate C543, C547, C551, C555, C643, C647, C651, and default transformer option, the following components need to C655 with a 68 pF capacitor. be removed and/or changed. 680nH 68pF • Remove R102, R115, R128, R141, R161, R162, R163, R164, 680nH R202, R208, R218, R225, R234, R241, R252, R259, T101, Figure 88. Example Filter Configured for16 MHz, Two-Pole Low-Pass Filter T102, T103, T104, T201, T202, T203, and T204 in the default analog input path. 0 f = 50MSPS SAMPLE • Populate R101, R114, R127, R140, R201, R217, R233, and AIN = 3.5MHz –20 AD8334 = MAX GAIN SETTING R251 with 0 Ω resistors in the analog input path. • Populate R152, R153, R154, R155, R156, R157, R158, R159, –40 R215, R216, R229, R230, R247, R248, R263, R264, C103, C105, C110, C112, C117, C119, C124, C126, C203, C205, –60 C210, C212, C217, C219, C224, and C226 with 10 kΩ resistors to provide an input common-mode level to the –80 ADC analog inputs. –100 • Populate R105, R113, R118, R124, R131, R137, R151, R160, R205, R213, R221, R222, R237, R238, R255, and R256 with –120 0 Ω resistors in the ADC analog input path to connect the 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 FREQUENCY (MHz) VGA outputs. Figure 89. AD9222 FFT Example Results Using 16 MHz, Two-Pole Low-Pass • Remove R515, R520, R527, R532, R615, R620, R627, and Filter Applied to the AD8334 Outputs (fSAMPLE = 50 MSPS, AIN = 3.5 MHz, R632 on the AD8334 analog outputs. AD8334 = Maximum Gain Setting, Analog Input Signal = −1.03 dBFS, SNR = 60.8 dBc, SFDR = 67.02 dBc) • Remove R512, R524, R612, and R624 to set the AD8334 mode and AD8334 HILO pin low. Some applications may require this to be different. Consult the AD8334 data sheet for more information on these functions. In this configuration, L505 to L520 and L605 to L620 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev. F | Page 42 of 60 AMPLITUDE (dBFS) 05967-107 05967-108 Data Sheet AD9222 Figure 90. Evaluation Board Schematic, DUT Analog Inputs Rev. F | Page 43 of 60 AVDD_DUT AVDD_DUT DNP P106 P102 DNP VGA Input R152 VGA Input Connection Ain Ain R105 Connection R131 DNP R154 INH1 0Ω−DNP 0Ω−DNP INH3 DNP R104 CH_A FB102 R108 C115 C101 R130 CH_C 0Ω FB108 R134 0.1µF 10Ω 33Ω 0.1µF T101 0Ω 1 6 T103 10Ω 33Ω VIN_A 1 6 R101 VIN_C R127 Channel A R106 0Ω−DNP R132 2 5 Channel C CM1 CM1 DNP 0Ω−DNP P101 R161 C104 R109 2 5 DNP C102 CM3 CM3 C117 P105 R163 C118 0.1µF 499Ω 2.2pF 1kΩ R135 3 4 R110 Ain 499Ω DNP 2.2pF R107 C103 3 4 33Ω Ain 1kΩ R133 FB101 R113 DNP DNP FB107 R137 DNP 10Ω CH_A VIN_A 10Ω C116 CH_C VIN_C R102 0Ω−DNP FB103 R103 FB109 CM1 0.1µF 64.9Ω 10Ω 0Ω−DNP R128 R129 10Ω R136 0Ω C105 CM3 64.9Ω 0Ω 33Ω C119 DNP R156 1 DNP R158 DNP 1 E101 E103 DNP C106 C120 DNP AVDD_DUT AVDD_DUT DNP R138 R111 AVDD_DUT 1kΩ R139 AVDD_DUT C121 1kΩ C107 1kΩ 0.1µF R112 0.1µF 1kΩ VGA Input AVDD_DUT VGA Input AVDD_DUT Connection Connection INH2 INH4 R153 R155 R118 DNP R151 DNP R114 0Ω−DNP R140 Channel B 0Ω−DNP 0Ω−DNP Channel D 0Ω−DNP C122 FB104 FB105 R121 C108 CH_B FB110 CH_D FB111 R146 P103 P107 0.1µF 10Ω 0.1µF 10Ω 33Ω 10Ω 33Ω T102 10Ω T104 1 6 1 6 Ain VIN_B Ain VIN_D DNP R119 DNP R144 2 5 2 5 CM2 CM2 R162 DNP R164 P104 DNP P108 CM4 CM4 C109 C111 R123 C124 C125 R148 R115 499Ω R141 499Ω 0.1µF 2.2pF 1kΩ 2.2pF 1kΩ 64.9Ω 3 4 64.9Ω 3 4 DNP R122 Ain Ain R145 R120 C110 33Ω R124 R160 R116 DNP DNP DNP R143 CH_B VIN_B C123 CH_D VIN_D 0Ω 0Ω 0Ω−DNP FB106 FB112 0.1µF 0Ω−DNP CM4 R147 10Ω R142 10Ω R117 CM2 33Ω 0Ω C112 C126 R159 0Ω R157 1 DNP DNP E104 DNP 1 DNP E102 C127 AVDD_DUT DNP C113 R149 AVDD_DUT DNP 1kΩ C128 R125 AVDD_DUT R150 AVDD_DUT 0.1µF 1KΩ 1kΩ C114 R126 0.1µF 1kΩ DNP: DO NOT POPULATE. 05967-072 AD9222 Data Sheet Figure 91. Evaluation Board Schematic, DUT Analog Inputs (Continued) Rev. F | Page 44 of 60 AVDD_DUT AVDD_DUT DNP P202 DNP VGA Input VGA Input P206 Connection Connection R248 Ain R205 R216 R237 INH5 0Ω−DNP Ain DNP DNP INH7 0Ω−DNP R204 CH_E FB202 R209 C215 C201 CH_G R236 FB208 R242 0Ω T201 10Ω 33Ω 0.1µF 0.1µF 0Ω T203 10Ω 33Ω Channel E 1 6 VIN_E 1 6 VIN_G R201 Channel G R233 R206 R239 2 5 0Ω−DNP 0Ω−DNP CM5 CM5 DNP R208 2 5 P201 C202 C204 R214 DNP R241 CM7 CM7 R246 499Ω P205 C217 C218 0.1µF 1kΩ 3 4 R210 2.2pF 499Ω 1kΩ DNP Ain R207 C203 3 4 2.2pF 33Ω Ain R240 FB201 R213 DNP DNP FB207 R238 DNP 10Ω CH_E VIN_E 10Ω C216 CH_G VIN_G 0Ω−DNP FB203 R202 R203 FB209 CM5 R234 0.1µF 0Ω−DNP 10Ω 0Ω R235 10Ω R245 64.9Ω C205 64.9kΩ CM7 0Ω 33Ω C219 DNP R215 1 DNP R247 1 E201 DNP E203 DNP C206 C220 DNP AVDD_DUT AVDD_DUT DNP R249 R211 AVDD_DUT 1kΩ R250 C221 AVDD_DUT 1kΩ C207 1kΩ 0.1µF R212 0.1µF 1kΩ VGA Input AVDD_DUT VGA Input AVDD_DUT Connection Connection INH6 INH8 R230 Channel H R264 Channel F R221 R255 R217 DNP R251 DNP 0Ω−DNP DNP 0Ω−DNP 0Ω−DNP 0Ω−DNP C222 FB204 CH_F FB205 R226 FB211 R260 P203 C208 P207 FB210 0.1µF CH_H 10Ω 10Ω 33Ω 33Ω 0.1µF T202 10Ω 10Ω 1 6 T204 Ain 1 6 VIN_F Ain VIN_H R257 DNP R223 DNP 2 5 2 5 DNP R259 C209 CM6 CM6 DNP R225 R228 CM8 CM8 P204 C211 R252 P208 C225 R262 R218 499Ω C224 0.1µF 499Ω 1kΩ 2.2pF 64.9Ω 2.2pF 1kΩ 64.9Ω 3 4 3 4 DNP R227 Ain Ain R224 C210 R258 33Ω R222 R220 DNP DNP R256 DNP R254 CH_F VIN_F C223 CH_H VIN_H 0Ω 0Ω 0Ω−DNP FB206 0Ω−DNP FB212 0.1µF CM8 10Ω R253 10Ω R261 R219 CM6 0Ω 33Ω C212 C226 0Ω R229 1 R263 DNP DNP DNP E204 1 DNP E202 C227 AVDD_DUT DNP C213 R265 AVDD_DUT DNP 1kΩ C228 R231 R266 AVDD_DUT 0.1µF AVDD_DUT 1kΩ 1kΩ C214 R232 0.1µF 1kΩ DNP: DO NOT POPULATE. 05967-073 Data Sheet AD9222 2 2 2 2 R307 10kΩ R306 AVDD_DUT 100kΩ R302 R305 DNP 100kΩ CW 49 VIN_C VIN+C 32 CHB D+B 50 VIN−C VIN_C 31 D−B CHB 51 AVDD_DUT AVDD 30 CHC D+C 52 VIN−D VIN_D 29 D−C CHC 53 GND R301 VIN_D VIN+D 10kΩ 28 D+D CHD 54 RBIAS 27 D−D CHD 55 VSENSE_DUT SENSE 26 FCO+ FCO 56 VREF_DUT VREF 25 FCO− FCO 57 REFB 24 DCO+ DCO 58 REFT 23 DCO− DCO 59 AVDD_DUT AVDD 22 D+E CHE 60 VIN_E VIN+E 21 CHE D−E 61 VIN−E VIN_E 20 D+F CHF 62 AVDD_DUT AVDD 19 D−F CHF 63 VIN−F VIN_F 18 D+G CHG 64 VIN_F VIN+F 17 D−G CHG 0 SLUG Figure 92. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface Rev. F | Page 45 of 60 C301 Reference 0.1µF Decoupling C303 C304 4.7µF 0.1µF C302 0.1µF Digital Outputs P301 GNDCD10 60 DCO DCO 40 C10 D10 50 GNDCD9 R318 59 DNP FCO D9 FCO 39 C9 49 GNDCD8 R320 58 DNP D8 CHA CHA 38 C8 48 GNDCD7 R321 57 DNP AVDD_DUT CHB CHB 1 48 37 C7 D7 47 R322 AVDD_DUT AVDD AVDD_DUT GNDCD6 AVDD 56 R318,R320−R328 DNP D6 CHC 2 47 CHC Optional Output 36 C6 46 VIN_G VIN+G VIN+B VIN_B GNDCD5 R323 Terminations 55 DNP 3 46 CHD D5 CHD 35 C5 VIN_G VIN−G VIN−B VIN_B 45 GNDCD4 R324 R303 R304 54 4 45 DNP 100kΩ DNP CHE CHE AVDD_DUT AVDD AVDD AVDD_DUT 34 C4 44 D4 GNDCD3 R325 53 5 44 DNP VIN_H VIN−H VIN−A VIN_A CHF CHF 33 C3 D3 43 R326 J301 GNDCD2 1 52 6 43 3 PWDN ENABLE VIN_H VIN+H VIN+A VIN_A DNP CHG CHG C2 42 32 D2 GNDCD1 R327 7 42 51 AVDD_DUT AVDD AVDD AVDD_DUT DNP CSB_DUT CHH CHH C1 41 J302 31 D1 GNDAB10 R328 1 8 41 3 AD9222BCPZ-65 AVDD_DUT AVDD PDWN ALWAYS ENABLE SPI 30 DNP B10 10 A10 20 9 40 GNDAB9 CLK CLK− CSB 29 SDIO_ODM R319 B9 U301 J303 9 A9 19 10 39 1 GNDAB8 CLK CLK+ SDIO/ODM 3 ODM Enable 28 B8 1kΩ 11 38 18 8 A8 GNDAB7 AVDD_DUT AVDD SCLK/DTP 27 SCLK_DTP J304 B7 12 37 7 A7 17 1 AVDD_DUT AVDD AVDD AVDD_DUT 3 GNDAB6 DTP Enable 26 13 36 B6 GND DRGND DRGND GND 6 A6 16 GNDAB5 25 14 35 B5 SCLK_CHB SCLK_CHA DRVDD_DUT DRVDD DRVDD DRVDD_DUT 5 A5 15 GNDAB4 24 15 34 CHH D−H D+A CHA B4 SDI_CHB SDI_CHA 14 4 A4 GNDAB3 16 33 23 CHH D+H D−A CHA B3 CSB3_CHB CSB1_CHA 3 A3 13 GNDAB2 22 B2 CSB4_CHB CSB2_CHA 2 A2 12 GNDAB1 21 B1 SDO_CHB SDO_CHA 1 A1 11 NC AVDD_DUT OPTIONAL Reference Circuitry EXT REF R309 VSENSE_DUT Vref Select VREF_DUT 4.99kΩ U302 R311 R314 DNP DNP ADR510ARTZ V = 0.5V REF TRIM/NC VOUT 1.0V R315 DNP R312 V = External REF DNP C306 C307 R31 C305 R310 0.1µF R308 1µF DNP 0.1µF V = 0.5V(1 + R219/R220) 10kΩ REF 470kΩ R313 R317 DNP 0Ω V = 1V REF Remove C214 when using external Vref DNP: DO NOT POPULATE. 05967-074 AD9222 Data Sheet 25 S0 16 S1 15 S2 14 S3 33 13 S4 12 S5 31 11 GND S6 10 S7 1 9 VS S8 8 S9 32 7 RSET S10 6 VREF Figure 93. Evaluation Board Schematic, Clock Circuitry Rev. F | Page 46 of 60 AVDD_3.3V OPTIONAL CLOCK DRIVE CIRCUIT R401 C401 10kΩ 0.1µF AVDD_3.3V 3 AVDD_3.3V ENABLE OSC401 R414 4.12kΩ AVDD_3.3V Optional Clock 2 J401 R408 R409 R410 Oscillator DNP DNP DNP 10kΩ 0.1µF OSC401 DISABLE OSC401 C405 14 1 VCC OE OPT_CLK 1 U401 CLK R425 12 3 R424 VCC OE DNP R406 GND_PAD R422 AVDD_3.3V 2 23 LVPECL OUTPUT 0Ω 0Ω 0.1µF AD9515 Pin−strap settings 10 5 R402 0Ω CLK OUT0 100Ω OUT GND R411 C406 DNP 10kΩ DNP 49.9Ω 3 22 8 7 DNP CLKB OUT0B CLK S0 AD9515BCPZ OUT GND R426 R427 R436 R437 OPT_CLK AVDD_3.3V AVDD_3.3V CRYSTAL_3 R420 R421 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 0Ω 0Ω 0Ω 0Ω Encode 240Ω 240Ω DNP DNP 5 19 R403 Input R407 SYNCB OUT1 0Ω SIGNAL=DNC;27,28 R412 R413 0Ω S1 S6 DNP OPT_CLK 18 DNP 10kΩ R429 DNP OUT1B R428 R438 R439 P401 AVDD_3.3V AVDD_3.3V 0Ω 0Ω 0Ω 0Ω DNP DNP Enc C407 R423 0.1µF C402 LVDS OUTPUT 100Ω S2 S7 0.1µF DNP R404 R431 R430 R440 R441 1 49.9Ω AVDD_3.3V AVDD_3.3V E401 0Ω 0Ω 0Ω 0Ω Clock Circuit S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 DNP DNP C408 R446 0.1µF R417 CLK DNP S3 S8 OPT_CLK DNP DNP 0Ω R433 R415 T401 R432 R442 R443 P402 0.1µF AVDD_3.3V AVDD_3.3V 3 4 0Ω 0Ω 0Ω 0Ω CR401 C409 Enc DNP DNP 0Ω HSMS-2812-TR1G C403 2 5 CLIP SINE OUT (DEFAULT) R416 0.1µF S4 S9 C410 R405 R434 R435 R444 R445 1 6 0Ω 0.1µF 0Ω C411 R418 AVDD_3.3V AVDD_3.3V 0Ω 0Ω 0Ω 0Ω 0.1µF 0Ω CLK DNP DNP S5 S10 AVDD_3.3V C412 C413 C414 C415 C416 C417 C418 0.1µF 0.1µF0.1µF 0.1µF 0.1µF 0.1µF 0.1µF DNP: DO NOT POPULATE. 2 3 1 05967-075 Data Sheet AD9222 R524 R523 10kΩ 10kΩ R513 187Ω C512 C511 10µF 0.1µF C533 C534 C535 C536 10µF 0.1µF 10µF 0.1µF C510 C509 10µF 0.1µF R512 R511 49 32 10kΩ 10kΩ VCM2 NC 50 31 VCM1 VCM3 R504 10kΩ 51 30 EN34 VCM4 R505 AVDD_5V 10kΩ 52 29 EN12 HILO 53 28 CLMP12 CLMP34 54 27 VG12 GAIN12 GAIN34 VG34 55 26 VPS1 VPS4 AVDD_5V AVDD_5V 56 25 VIN1 VIN4 57 24 VIP1 VIP4 58 23 LOP1 LOP4 59 22 LON1 LON4 60 21 COM1X COM4X 61 20 LMD1 LMD4 R509 274Ω 62 19 INH1 INH4 C505 63 0.1µF 18 COM1 COM4 64 17 COM2 COM3 C527 0.018µF C526 22pF L504 120nH 0.1µF C525 R503 274Ω R508 R507 274Ω 274Ω C502 0.018µF C521 C515 0.018µF 0.018µF C503 22pF L501 C520 120nH 22pF C514 22pF 0.1µF C501 L503 L502 120nH 120nH 0.1µF 0.1µF C519 C513 AVDD_5V AVDD_5V CW CW GND GND VG34 VG12 Variable Gain Circuit Variable Gain Circuit (0−1.0V DC) (0−1.0V DC) VG34 VG12 External Variable Gain Drive External Variable Gain Drive Figure 94. Evaluation Board Schematic, Optional DUT Analog Input Drive Rev. F | Page 47 of 60 Populate L505−L520 with 0Ω resistors or design your own filter. EXT VG Power Down Enable (0−1V=Disable Power) JP501 CH_D CH_D CH_C CH_C CH_B CH_B CH_A CH_A 1 2 DNP AVDD_5V 10kΩ R506 C507 C508 0.1µF 1000pF R517 R522 R529 R534 Rclamp Pin DNP DNP DNP DNP HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV R501 10kΩ C543 C551 C547 C555 DNP DNP DNP DNP L507 L508 L511 L512 L515 L516 L519 L520 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω R502 39kΩ C542 C546 C550 C554 DNP DNP DNP DNP L505 L506 L509 L510 L513 L514 L517 L518 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω C506 INH4 R516 R521 R528 R533 0.1µF DNP DNP DNP DNP C504 0.1µF U501 C540 C541 C544 C545 C548 C549 C552 C553 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF R515 R527 R532 R520 374Ω 374Ω 374Ω 374Ω 1 48 R518 R519 R525 R526 R530 R531 R514 INH3 INH2 COM12 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 2 47 LMD2 VOH1 C537 AVDD_5V 0.1µF 3 46 COM2X VOL1 4 45 LON2 VPS12 AVDD_5V C518 5 44 LOP2 VOL2 C538 0.1µF 0.1µF 6 43 VIP2 VOH2 7 42 VIN2 COM12 8 41 AVDD_5V VPS2 MODE AD8334ACPZ-REEL 9 40 MODE Pin AVDD_5V VPS3 NC Positive Gain Slope = 0−1.0V 10 39 Negitive Gain Slope = 2.25−5.0V VIN3 COM34 11 38 VIP3 VOH3 0.1µF C522 12 37 C523 LOP3 VOL3 0.1µF 13 36 LON3 VPS34 AVDD_5V 14 35 COM3X VOL4 15 34 LMD3 VOH4 C524 33 0.1µF 16 INH3 COM34 INH2 EXT VG JP502 1 2 C529 C528 0.1µF 0.1µF R535 10kΩ AVDD_5V INH1 C530 0.1µF R536 39kΩ Rclamp Pin HILO Pin=LO=+/− 50mV C531 HILO Pin=H=+/− 75mV 1000pF DNP C532 10kΩ 0.1µF R510 DNP: DO NOT POPULATE. 05967-076 AD9222 Data Sheet R613 187Ω C612 C611 10µF 0.1µF C633 C634 C635 C636 10µF 0.1µF 10µF 0.1µF C610 C609 10µF 0.1µF VCM2 NC 49 32 VCM1 VCM3 50 31 R604 10kΩ R605 AVDD_5V EN34 VCM4 R612 R611 10kΩ 51 30 10kΩ 10kΩ EN12 HILO 52 29 CLMP12 CLMP34 53 28 VG56 GAIN12 GAIN34 VG78 54 27 AVDD_5V VPS1 VPS4 AVDD_5V 55 26 VIN1 VIN4 56 25 VIP1 VIP4 57 24 LOP1 LOP4 58 23 LON1 LON4 59 22 COM1X COM4X 60 21 LMD1 LMD4 61 20 R609 274Ω INH1 INH4 C605 62 19 0.1µF COM1 COM4 63 18 COM2 COM3 64 17 C627 0.018µF C626 22pF L604 120nH 0.1µF C625 R603 274Ω R608 R607 274Ω 274Ω C602 0.018µF C621 C615 0.018µF 0.018µF C603 22pF L601 C620 120nH 22pF C614 22pF 0.1µF C601 L603 L602 120nH 120nH 0.1µF 0.1µF C619 C613 AVDD_5V AVDD_5V CW CW GND GND VG78 VG56 Variable Gain Circuit (0−1.0V DC) Variable Gain Circuit (0−1.0V DC) VG78 VG56 External Variable Gain Drive External Variable Gain Drive Figure 95. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued) Rev. F | Page 48 of 60 MODE Pin Populate L605−L620 with 0Ω Positive Gain Slope = 0−1.0V resistors or design your own filter. EXT VG Power Down Enable Negative Gain Slope = 2.25−5.0V (0−1V=Disable Power) JP601 CH_H CH_H CH_G CH_G CH_F CH_F CH_E CH_E 1 2 AVDD_5V C607 DNP 1000pF C608 10kΩ 0.1µF R606 R617 R622 R629 R636 DNP DNP DNP DNP Rclamp Pin HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV R601 10kΩ C643 C651 C647 C655 DNP DNP DNP DNP L607 L608 L611 L612 L615 L616 L619 L620 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω R602 39kΩ C642 C646 C650 C654 DNP DNP DNP DNP L605 L606 L609 L610 L613 L614 L617 L618 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω C606 INH8 R616 R621 R628 R633 0.1µF DNP DNP DNP DNP C604 0.1µF U601 C640 C641 C644 C645 C648 C649 C652 C653 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF R620 R627 R632 R615 374Ω 374Ω 374Ω 374Ω 1 48 R618 R619 R625 R626 R630 R631 INH7 R614 INH2 COM12 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 2 47 LMD2 VOH1 AVDD_5V C616 3 0.1µF 46 COM2X VOL1 4 45 LON2 VPS12 AVDD_5V R624 10kΩ C618 5 44 LOP2 VOL2 C617 0.1µF 0.1µF 6 43 VIP2 VOH2 7 42 VIN2 COM12 R623 8 41 10kΩ AVDD_5V VPS2 MODE AD8334ACPZ-REEL 9 40 AVDD_5V VPS3 NC 10 39 VIN3 COM34 11 38 VIP3 VOH3 0.1µF C622 C623 12 37 LOP3 VOL3 0.1µF 13 36 LON3 VPS34 AVDD_5V 14 35 COM3X VOL4 15 34 LMD3 VOH4 C624 16 33 0.1µF INH3 COM34 INH6 EXT VG JP602 1 2 C629 C628 0.1µF 0.1µF R634 10kΩ AVDD_5V INH5 C630 0.1µF R635 39kΩ Rclamp Pin HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV DNP C631 C632 10kΩ 1000pF 0.1µF R610 DNP: DO NOT POPULATE. 05967-077 Data Sheet AD9222 CR702 GREEN C702 C703 0.1µF 0.1µF GND 1 GND 1 R709 0Ω SDO_CHA R708 0Ω SDI_CHA R707 0Ω SCLK_CHA R706 0Ω CSB1_CHA PICVCC 1 2 PICVCC GP1 3 4 GP1 GP0 5 6 GP0 MCLR/GP3 7 8 MCLR/GP3 10 9 GND GND CR701 2 OPTIONAL GREEN Figure 96. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry Rev. F | Page 49 of 60 SPI CIRCUITRY FROM FIFO Power Supply Input +5V = PROGRAMMING = AVDD_5V 6V, 2A max +3.3V = NORMAL OPERATION = AVDD_3.3V REMOVE WHEN USING OR PROGRAMMING PIC (U402) D702 F701 AVDD_3.3V AVDD_5V FER701 PWR_IN 2 1 P701 NANOSMDC110F-2 SK33-TP J701 4 3 1 1 3 C704 D701 AVDD_3.3V 10µF C701 2 S2A-TP 3 7.5V POWER 0.1µF CON005 U701 2.5MM JACK R710 1 8 1kΩ VDD VSS R716 R703 R701 2 7 261Ω GP5 GP0 4.7kΩ R704 S701 0Ω−DNP 3 6 GP4 GP1 1 3 R705 0Ω−DNP 4 5 MCLR/GP3 GP2 2 4 0Ω−DNP PIC12F629-I/SNG Optional Power RESET/ REPROGRAM R702 Input 261Ω P702 L703 DNP 10µH SDIO_ODM 3.3V_AVDD 1 P1 AVDD_3.3V +3.3V 2 P2 C709 C710 10µF 0.1µF 5V_AVDD 3 P3 R712 AVDD_DUT 4 1kΩ P4 NC7W207P6X_NL R713 1kΩ DUT_AVDD 5 1 A1 Y1 6 P5 L701 10µH E701 6 2 5 P6 1 AVDD_5V +5.0V GND VCC AVDD_DUT R711 7 DUT_DRVDD 10kΩ 3 A2 Y2 4 P7 C706 C705 0.1µF 8 10µF P8 U702 PIC PROGRAMMING HEADER ISP J702 L702 10µH AVDD_DUT +1.8V C707 10µF NC7WZ16P6X_NL Decoupling Capacitors C708 0.1µF 1 Y1 A1 6 SCLK_DTP 2 AVDD_5V 5 GND VCC AVDD_DUT 3 A2 Y2 4 L704 C723 C724 C725 C726 C727 CSB_DUT 10µH 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF DRVDD_DUT +1.8V U703 C711 C712 R715 R714 10µF 0.1µF 10kΩ 10kΩ AVDD_DUT C731 C732 C733 C734 C735 C730 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF AVDD_5V U705 U707 C752 L705 L707 C749 C750 C751 C753 ADP3339ZAKC−1.8-RL ADP3339ZAKC−3.3-RL 10µH 10µH 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 3 2 3 2 PWR_IN IN DUT_AVDD PWR_IN IN 3.3V_AVDD OUT OUT 4 4 OUT OUT AVDD_DUT C714 C719 C720 C715 1µF 1µF 1µF C747 1µF C744 C745 C746 C748 0.1µF 1 0.1µF 0.1µF 0.1µF 0.1µF U704 U706 L706 L708 ADP3339ZAKC−1.8-RL ADP3339ZAKC−5-RL7 AVDD_3.3V 10µH 10µH 3 2 2 DRVDD_DUT 3 PWR_IN IN OUT DUT_DRVDD PWR_IN IN OUT 5V_AVDD 4 4 OUT OUT C742 C743 C740 C741 0.1µF 0.1µF 0.1µF 0.1µF C716 C717 C722 C721 1µF 1µF 1µF 1µF 1 DNP: DO NOT POPULATE. 05967-078 AD9222 Data Sheet Figure 97. Evaluation Board Layout, Primary Side Rev. F | Page 50 of 60 05967-079 Data Sheet AD9222 Figure 98. Evaluation Board Layout, Ground Plane Rev. F | Page 51 of 60 05967-080 AD9222 Data Sheet Figure 99. Evaluation Board Layout, Power Plane Rev. F | Page 52 of 60 05967-081 Data Sheet AD9222 Figure 100. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. F | Page 53 of 60 05967-082 AD9222 Data Sheet 1 Table 17. Evaluation Board Bill of Materials (BOM) Qnty. per Reference Item Board Designator Device Pkg. Value Mfg. Mfg. Part Number 1 1 AD9222-65EBZ PCB PCB PCB Capacitor 402 0.1 μF, ceramic, X5R, Murata GRM155R71C104KA88D 2 118 C101, C102, C107, C108, C109, C114, 10 V, 10% tol C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, C222, C223, C228, C301, C302, C304, C305, C306, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C501, C504, C505, C506, C508, C509, C511, C513, C518, C519, C522, C523, C524, C525, C528, C529, C530, C532, C534, C536, C537, C538, C601, C604, C605, C606, C608, C609, C611, C613, C616, C617, C618, C619, C622, C623, C624, C625, C628, C629, C630, C632, C634, C636, C701, C702, C703, C706, C708, C710, C712, C723, C724, C725, C726, C727, C730, C731, C732, C733, C734, C735, C740, C741, C742, C743, C744, C745, C746, C747, C748, C749, C750, C751, C752, C753 3 8 C104, C111, C118, Capacitor 402 2.2 pF, ceramic, COG, Murata GRM1555C1H2R20CZ01D C125, C204, C211, 0.25 pF tol, 50 V C218, C225 4 8 C510, C512, C533, Capacitor 805 10 μF, 6.3 V ±10% Murata GRM219R60J106KE19D C535, C610, C612, ceramic, X5R C633, C635 5 1 C303 Capacitor 603 4.7 μF, ceramic, X5R, Murata GRM188R60J475KE19D 6.3 V, 10% tol 6 4 C507, C531, C607, Capacitor 402 1000 pF, ceramic, X7R, Murata GRM155R71H102KA01D C631 25 V, 10% tol 7 8 C502, C515, C521, Capacitor 402 0.018 μF, ceramic, X7R, AVX 0402YC183KAT2A C527, C602, C615, 16 V, 10% tol C621, C627 Rev. F | Page 54 of 60 Data Sheet AD9222 Qnty. per Reference Item Board Designator Device Pkg. Value Mfg. Mfg. Part Number 8 8 C503, C514, C520, Capacitor 402 22 pF, ceramic, NPO, Murata GRM1555C1H220JZ01D C526, C603, C614, 5% tol, 50 V C620, C626 9 1 C704 Capacitor 1206 10 μF, tantalum, Rohm TCA1C106M8R 16 V, 20% tol 10 9 C307, C714, C715, Capacitor 603 1 μF, ceramic, X5R, Murata GRM188R61C105KA93D C716, C717, C719, 6.3 V, 10% tol C720, C721, C722 11 16 C540, C541, C544, Capacitor 805 0.1 μF, ceramic, X7R, Murata GRM21BR71H104KA01L C545, C548, C549, 50 V, 10% tol C552, C553, C640, C641, C644, C645, C648, C649, C652, C653 12 4 C705, C707, C709, Capacitor 603 10 μF, ceramic, X5R, Murata GRM188R60J106ME47D C711 6.3 V, 20% tol 13 1 CR401 Diode SOT-23 30 V, 20 mA, dual Avago HSMS-2812-TR1G Schottky Technologies 14 2 CR701, CR702 LED 603 Green, 4 V, 5 m candela Panasonic LNJ314G8TRA 15 1 D702 Diode DO-214AB 3 A, 30 V, SMC Micro SK33-TP Commercial Co. 16 1 D701 Diode DO-214AA 5 A, 50 V, SMC Micro S2A-TP Commercial Co. 17 1 F701 Fuse 1210 6.0 V, 2.2 A trip-current Tyco/Raychem NANOSMDC110F-2 resettable fuse 18 1 FER701 Choke coil 2020 10 μH, 5 A, 50 V, 190 Ω Murata DLW5BSN191SQ2L @ 100 MHz 19 24 FB101, FB102, Ferrite bead 603 10 Ω, test frequency Murata BLM18BA100SN1D FB103, FB104, 100 MHz, 25% tol, FB105, FB106, 500 mA FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212 20 4 JP501, JP502, Connector 2-pin 100 mil header jumper, Samtec TSW-102-07-G-S JP601, JP602 2-pin 21 6 J301, J302, J303, Connector 3-pin 100 mil header jumper, Samtec TSW-103-07-G-S J304, J401, J701 3-pin 23 1 J702 Connector 10-pin 100 mil header, male, Samtec TSW-105-08-G-D 2 × 5 double row straight 24 8 L701, L702, L703, Ferrite bead 1210 10 μH, bead core 3.2 × Murata BLM31PG500SN1L L704, L705, L706, 2.5 × 1.6 SMD, 2 A L707, L708 25 8 L501, L502, L503, Inductor 402 120 nH, test freq Murata LQG15HNR12J02D L504, L601, L602, 100 MHz, 5% tol, L603, L604 150 mA Rev. F | Page 55 of 60 AD9222 Data Sheet Qnty. per Reference Item Board Designator Device Pkg. Value Mfg. Mfg. Part Number 26 32 L505, L506, L507, Resistor 805 0 Ω, 1/8 W, 5% tol NIC NRC04Z0TRF L508, L509, L510, Components L511, L512, L513, Corp. L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 27 1 OSC401 Oscillator SMT Clock oscillator, Valphey Fisher VFAC3H-L-50MHz 50.00 MHz, 3.3 V, ±5% duty cycle 28 9 P101, P103, P105, Connector SMA Side-mount SMA for Johnson 142-0701-851 P107, P201, P203, 0.063" board thickness Components P205, P207, P401 29 1 P301 Connector HEADER 1469169-1, right angle Tyco 6469169-1 2-pair, 25 mm, header assembly 30 1 P701 Connector 0.1", PCMT RAPC722, power Switchcraft RAPC722X supply connector 31 21 R301, R307, R401, Resistor 402 10 kΩ, 1/16 W, NIC NRC04J103TRF R402, R410, R413, 5% tol Components R504, R505, R511, Corp. R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715 32 18 R103, R117, R129, Resistor 402 0 Ω, 1/16 W, NIC NRC04Z0TRF R142, R203, R219, 5% tol Components R235, R253, R317, Corp. R405, R415, R416, R417, R418, R706, R707, R708, R709 33 8 R102, R115, R128, Resistor 402 64.9 Ω, 1/16 W, NIC NRC04F64R9TRF R141, R202, R218, 1% tol Components R234, R252 Corp. 34 8 R104, R116, R130, Resistor 603 0 Ω, 1/10 W, NIC NRC06Z0TRF R143, R204, R220, 5% tol Components R236, R254 Corp. 35 28 R109, R111, R112, Resistor 402 1 kΩ, 1/16 W, NIC NRC04F1001TRF R123, R125, R126, 1% tol Components R135, R138, R139, Corp. R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713 36 16 R108, R110, R121, Resistor 402 33 Ω, 1/16 W, NIC NRC04J330TRF R122, R134, R136, 5% tol Components R146, R147, R209, Corp. R210, R226, R227, R242, R245, R260, R261 Rev. F | Page 56 of 60 Data Sheet AD9222 Qnty. per Reference Item Board Designator Device Pkg. Value Mfg. Mfg. Part Number 37 8 R161, R162, R163, Resistor 402 499 Ω, 1/16 W, NIC NRC04F4990TRF R164, R208, R225, 1% tol Components R241, R259 Corp. 38 3 R303, R305, R306 Resistor 402 100 kΩ, 1/16 W, NIC NRC04F1003TRF 1% tol Components Corp. 39 1 R414 Resistor 402 4.12 kΩ, 1/16W, NIC NRC04F4121TRF Components 1% tol Corp. 40 1 R404 Resistor 402 49.9 Ω, 1/16 W, Susumu RR0510R-49R9-D 0.5% tol 41 1 R309 Resistor 402 4.99 kΩ, 1/16 W, NIC NRC04F4991TRF 5% tol Components Corp. 42 5 R310, R501, R535, Potentiometer 3-lead 10 kΩ, Cermet trimmer COPAL CT94EW103 R601, R634 potentiometer, 18 turn ELECTRONICS top adjust, 10%, 1/2 W 43 1 R308 Resistor 402 470 kΩ, 1/16 W, NIC NRC04J474TRF Components 5% tol Corp. 44 4 R502, R536, R602, Resistor 402 39 kΩ, 1/16 W, NIC NRC04J393TRF R635 5% tol Components Corp. 45 16 R513, R514, R518, Resistor 402 187 Ω, 1/16 W, NIC NRC04F1870TRF R519, R525, R526, Components 1% tol R530, R531, R613, Corp. R614, R618, R619, R625, R626, R630, R631 46 8 R515, R520, R527, Resistor 402 374 Ω, 1/16 W, NIC NRC04F3740TRF R532, R615, R620, 1% tol Components R627, R632 Corp. 47 8 R503, R507, R508, Resistor 402 274 Ω, 1/16 W, NIC NRC04F2740TRF R509, R603, R607, 1% tol Components R608, R609 Corp. 48 11 R425,R427, R429, Resistor 201 0 Ω, 1/20 W, NIC NRC02Z0TRF R431, R433, R435, 5% tol Components R436, R439, R441, Corp. R443, R445 49 1 R701 Resistor 402 4.7 kΩ, 1/16 W, NIC NRC04J472TRF 1% tol Components Corp. 50 1 R702 Resistor 402 261 Ω, 1/16 W, NIC NRC04F2610TRF 1% tol Components Corp. 51 1 R716 Resistor 603 261 Ω, 1/16 W, NIC NRC06F261OTRF Components 1% tol Corp. 52 2 R420, R421 Resistor 402 240 Ω, 1/16 W, NIC NRC04J241TRF 5% tol Components Corp. 53 2 R422, R423 Resistor 402 100 Ω, 1/16 W, NIC NRC04F1000TRF 1% tol Components Corp. 54 1 S701 Switch SMD LIGHT TOUCH, Panasonic EVQ-PLDA15 100GE, 5 mm Rev. F | Page 57 of 60 AD9222 Data Sheet Qnty. per Reference Item Board Designator Device Pkg. Value Mfg. Mfg. Part Number 55 9 T101, T102, T103, Transformer CD542 ADT1-1WT+, Mini-Circuits ADT1-1WT+ T104, T201, T202, 1:1 impedance ratio T203, T204, T401 transformer 56 2 U704, U707 IC SOT-223 ADP33339AKC-1.8-RL, Analog Devices ADP3339AKCZ-1.8-RL 1.5 A, 1.8 V LDO regulator 57 2 U501, U601 IC CP-64-3 AD8334ACPZ-REEL, Analog Devices AD8334ACPZ-REEL ultralow noise precision dual VGA 58 1 U706 IC SOT-223 ADP3339AKC-5-RL7 Analog Devices ADP3339AKCZ-5-RL 59 1 U705 IC SOT-223 ADP3339AKC-3.3-RL Analog Devices ADP3339AKCZ-3.3-RL 60 1 U301 IC CP-64-3 AD9222BCPZ-65, octal, Analog Devices AD9222BCPZ-65 12-bit, 50 MSPS serial LVDS 1.8 V ADC 61 1 U302 IC SOT-23 ADR510ARTZ, 1.0 V, Analog Devices ADR510ARTZ precision low noise shunt voltage reference 62 1 U401 IC LFCSP AD9515BCPZ, 1.6 GHz Analog Devices AD9515BCPZ CP-32-2 clock distribution IC 63 1 U702 IC SC70, NC7WZ07P6X_NL, Fairchild NC7WZ07P6X_NL MAA06A UHS dual buffer 64 1 U703 IC SC70, NC7WZ16P6X_NL, Fairchild NC7WZ16P6X_NL MAA06A UHS dual buffer 65 1 U701 IC 8-SOIC Flash prog Microchip PIC12F629-I/SNG mem 1kx14, RAM size 64 × 8, 20 MHz speed, PIC12F controller series 1 This BOM is RoHS compliant. Rev. F | Page 58 of 60 Data Sheet AD9222 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 7.55 EXPOSED PAD 8.75 BSC (BOTTOM VIEW) 7.50 SQ BSC SQ 7.45 0.50 16 33 0.40 32 17 0.30 0.22 MIN TOP VIEW 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 101. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-6) Dimensions shown in millimeters ORDERING GUIDE 1, 2 Model Temperature Range Package Description Package Option AD9222ABCPZ-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9222ABCPZRL7-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7" Tape and Reel CP-64-6 AD9222ABCPZ-50 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9222ABCPZRL7-50 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7" Tape and Reel CP-64-6 AD9222ABCPZ-65 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9222ABCPZRL7-65 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7" Tape and Reel CP-64-6 AD9222-65EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to the HSC-ADC-EVALCZ data capture board. Rev. F | Page 59 of 60 02-23-2010-B AD9222 Data Sheet NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05967-0-12/11(F) Rev. F | Page 60 of 60