ANALOG DEVICES AD9221

Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters AD9221/AD9223/AD9220 FEATURES FUNCTIONAL BLOCK DIAGRAM Monolithic 12-Bit A/D Converter Product Family CLK AVDD DVDD Family Members Are: AD9221, AD9223, and AD9220 Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and SHA VINA MDAC1 MDAC2 MDAC3 10.0 MSPS GAIN = 16 GAIN = 8 GAIN = 4 VINB Low Power Dissipation: 59 mW, 100 mW, and 250 mW 5 4 3 A/D A/D A/D A/D Single 5 V Supply CAPT 5 4 3 3 Integral Nonlinearity Error: 0.5 LSB CAPB DIGITAL CORRECTION LOGIC Differential Nonlinearity Error: 0.3 LSB 12 VREF Input Referred Noise: 0.09 LSB OUTPUT BUFFERS OTR Complete On-Chip Sample-and-Hold Amplifier and SENSE BIT 1 (MSB) 1V MODE Voltage Reference SELECT BIT 12 AD9221/AD9223/AD9220 Signal-to-Noise and Distortion Ratio: 70 dB (LSB) Spurious-Free Dynamic Range: 86 dB REFCOM AVSS DVSS CML Out-of-Range Indicator amplifier (SHA) is equally suited for both multiplexed sys- Straight Binary Output Data tems that switch full-scale voltage levels in successive channels 28-Lead SOIC and 28-Lead SSOP as well as sampling single-channel inputs at frequencies up to GENERAL DESCRIPTION and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220 The AD9221, AD9223, and AD9220 are a generation of high is well suited for communication systems employing Direct- performance, single supply 12-bit analog-to-digital converters. IF down conversion since the SHA in the differential input Each device exhibits true 12-bit linearity and temperature drift mode can achieve excellent dynamic performance far beyond its 1 2 2 performance as well as 11.5-bit or better ac performance. The specified Nyquist frequency. AD9221/AD9223/AD9220 share the same interface options, A single clock input is used to control all internal conversion package, and pinout. Thus, the product family provides an upward cycles. The digital output data is presented in straight binary or downward component selection path based on performance, output format. An out-of-range (OTR) signal indicates an over- sample rate and power. The devices differ with respect to their flow condition that can be used with the most significant bit to specified sampling rate, and power consumption, which is reflected determine low or high overflow. in their dynamic performance over frequency. The AD9221/AD9223/AD9220 combine a low cost, high speed PRODUCT HIGHLIGHTS CMOS process and a novel architecture to achieve the resolution The AD9221/AD9223/AD9220 family offers a complete single- and speed of existing hybrid and monolithic implementations at chip sampling 12-bit, analog-to-digital conversion function in a fraction of the power consumption and cost. Each device is a pin compatible 28-lead SOIC and SSOP packages. complete, monolithic ADC with an on-chip, high performance, Flexible Sampling Rates—The AD9221, AD9223, and AD9220 low noise sample-and-hold amplifier and programmable voltage offer sampling rates of 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS, reference. An external reference can also be chosen to suit the respectively. dc accuracy and temperature drift requirements of the application. Low Power and Single Supply—The AD9221, AD9223, and The devices use a multistage differential pipelined architecture AD9220 consume only 59 mW, 100 mW, and 250 mW, respec- with digital output error correction logic to provide 12-bit accu- tively, on a single 5 V power supply. racy at the specified data rates and to guarantee no missing codes over the full operating temperature range. Excellent DC Performance Over Temperature—The AD9221/ AD9223/AD9220 provide 12-bit linearity and temperature drift The input of the AD9221/AD9223/AD9220 is highly flexible, 1 performance. allowing for easy interfacing to imaging, communications, medi- cal, and data-acquisition systems. A truly differential input Excellent AC Performance and Low Noise—The AD9221/ structure allows for both single-ended and differential input AD9223/AD9220 provide better than 11.3 ENOB performance 2 interfaces of varying input spans. The sample-and-hold and have an input referred noise of 0.09 LSB rms. Flexible Analog Input Range—The versatile on-board sample- NOTES 1 Excluding internal voltage reference. and-hold (SHA) can be configured for either single-ended or 2 Depends on the analog input configuration. differential inputs of varying input spans. REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. AD9221/AD9223/AD9220–SPECIFICATIONS (AVDD = 5 V, DVDD = 5 V, f = Max Conversion Rate, V = 2.5 V, VINB = 2.5 V, T to T , unless SAMPLE REF MIN MAX DC SPECIFICATIONS otherwise noted.) Parameter AD9221 AD9223 AD9220 Unit RESOLUTION 12 12 12 Bits min MAX CONVERSION RATE 1.5 3 10 MHz min INPUT REFERRED NOISE (TYP) V = 1 V 0.23 0.23 0.23 LSB rms typ REF V = 2.5 V 0.09 0.09 0.09 LSB rms typ REF ACCURACY Integral Nonlinearity (INL) ±0.4 ±0.5 ±0.5 LSB typ ±1.25 ±1.25 ±1.25 LSB max Differential Nonlinearity (DNL) ±0.3 ±0.3 ±0.3 LSB typ ±0.75 ±0.75 ±0.75 LSB max 1 INL ±0.6 ±0.6 ±0.7 LSB typ 1 DNL ±0.3 ±0.3 ±0.35 LSB typ No Missing Codes 12 12 12 Bits Guaranteed Zero Error (@ 25°C) ±0.3 ±0.3 ±0.3 % FSR max 2 Gain Error (@ 25°C) ±1.5 ±1.5 ±1.5 % FSR max 3 Gain Error (@ 25°C) ±0.75 ±0.75 ±0.75 % FSR max TEMPERATURE DRIFT Zero Error ±2 ±2 ±2 ppm/°C typ 2 Gain Error ±26 ±26 ±26 ppm/°C typ 3 Gain Error ±0.4 ±0.4 ±0.4 ppm/°C typ POWER SUPPLY REJECTION AVDD, DVDD (+5 V ± 0.25 V) ±0.06 ±0.06 ±0.06 % FSR max ANALOG INPUT Input Span (with V = 1.0 V) 222V p-p min REF Input Span (with V = 2.5 V) 555V p-p max REF Input (VINA or VINB) Range 000V min AVDD AVDD AVDD V max Input Capacitance 16 16 16 pF typ INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) 111V typ Output Voltage Tolerance (1 V Mode) ±14 ±14 ±14 mV max Output Voltage (2.5 V Mode) 2.5 2.5 2.5 V typ Output Voltage Tolerance (2.5 V Mode) ±35 ±35 ±35 mV max 4 Load Regulation 2.0 2.0 2.0 mV max REFERENCE INPUT RESISTANCE 555kΩ typ POWER SUPPLIES Supply Voltages AVDD 555V (±5% AVDD Operating) DVDD 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 V Supply Current IAVDD 14.0 26 58 mA max 11.8 20 51 mA typ IDVDD 0.5 0.5 4.0 mA max 0.02 0.02 <1.0 mA typ POWER CONSUMPTION 59.0 100 254 mW typ 70.0 130 310 mW max NOTES 1 V = 1 V. REF 2 Including internal reference. 3 Excluding internal reference. 4 Load regulation with 1 mA load current (in addition to that required by the AD9221/AD9223/AD9220). Specification subject to change without notice. –2– REV. E AD9221/AD9223/AD9220 (AVDD = 5 V, DVDD= 5 V, f = Max Conversion Rate, V = 1.0 V, VINB = 2.5 V, DC Coupled/Single- SAMPLE REF AC SPECIFICATIONS Ended Input T to T , unless otherwise noted.) MIN MAX Parameter AD9221 AD9223 AD9220 Unit MAX CONVERSION RATE 1.5 3.0 10.0 MHz min DYNAMIC PERFORMANCE Input Test Frequency 1 (VINA = –0.5 dBFS) 100 500 1000 kHz Signal-to-Noise and Distortion (SINAD) 70.0 70.0 70 dB typ 69.0 68.5 68.5 dB min Effective Number of Bits (ENOBs) 11.3 11.3 11.3 dB typ 11.2 11.1 11.1 dB min Signal-to-Noise Ratio (SNR) 70.2 70.0 70.2 dB typ 69.0 68.5 69.0 dB min Total Harmonic Distortion (THD) –83.4 –83.4 –83.7 dB typ –77.5 –76.0 –76.0 dB max Spurious Free Dynamic Range (SFDR) 86.0 87.5 88.0 dB typ 79.0 77.5 77.5 dB max Input Test Frequency 2 (VINA = –0.5 dBFS) 0.50 1.50 5.0 MHz Signal-to-Noise and Distortion (SINAD) 69.9 69.4 67.0 dB typ 69.0 68.0 65.0 dB min Effective Number of Bits (ENOBs) 11.3 11.2 10.8 dB typ 11.2 11.1 10.5 dB min Signal-to-Noise Ratio (SNR) 70.1 69.7 68.8 dB typ 69.0 68.5 67.5 dB min Total Harmonic Distortion (THD) –83.4 –82.9 –72.0 dB typ –77.5 –75.0 –68.0 dB max Spurious Free Dynamic Range (SFDR) 86.0 85.7 75.0 dB typ 79.0 76.0 69.0 dB max Full Power Bandwidth 25 40 60 MHz typ Small Signal Bandwidth 25 40 60 MHz typ Aperture Delay 111ns typ Aperture Jitter 444ps rms typ Acquisition to Full-Scale Step 125 43 30 ns typ Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVDD = 5 V, DVDD = 5 V, T to T , unless otherwise noted.) MIN MAX Parameter Symbol Unit CLOCK INPUT High Level Input Voltage V 3.5 V min IH Low Level Input Voltage V 1.0 V max IL High Level Input Current (V = DVDD) I ±10 µA max IN IH Low Level Input Current (V = 0 V) I ±10 µA max IN IL Input Capacitance C 5 pF typ IN LOGIC OUTPUTS DVDD = 5 V High Level Output Voltage (I = 50 µA) V 4.5 V min OH OH High Level Output Voltage (I = 0.5 mA) V 2.4 V min OH OH Low Level Output Voltage (I = 1.6 mA) V 0.4 V max OL OL Low Level Output Voltage (I = 50 µA) V 0.1 V max OL OL DVDD = 3 V High Level Output Voltage (I = 50 µA) V 2.95 V min OH OH High Level Output Voltage (I = 0.5 mA) V 2.80 V min OH OH Low Level Output Voltage (I = 1.6 mA) V 0.4 V max OL OL Low Level Output Voltage (I = 50 µA) V 0.05 V max OL OL Output Capacitance C 5 pF typ OUT Specifications subject to change without notice. REV. E –3– AD9221/AD9223/AD9220 SWITCHING SPECIFICATIONS (T to T with AVDD = 5 V, DVDD = 5 V, C = 20 pF) MIN MAX L Parameter Symbol AD9221 AD9223 AD9220 Unit Clock Period* t 667 333 100 ns min C CLOCK Pulsewidth High t 300 150 45 ns min CH CLOCK Pulsewidth Low t 300 150 45 ns min CL Output Delay t 888ns min OD 13 13 13 ns typ 19 19 19 ns max Pipeline Delay (Latency) 333Clock Cycles *The clock period may be extended to 1 ms without degradation in specified performance @ 25 °C. Specifications subject to change without notice. S1 S2 ANALOG S4 t C INPUT S3 t t CH CL INPUT CLOCK t OD DATA DATA 1 OUTPUT Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* THERMAL CHARACTERISTICS Thermal Resistance With 28-Lead SOIC Respect � = 71.4°C/W JA Parameter to Min Max Unit � = 23°C/W JC AVDD AVSS –0.3 +6.5 V 28-Lead SSOP DVDD DVSS –0.3 +6.5 V � = 63.3°C/W JA AVSS DVSS –0.3 +0.3 V � = 23°C/W JC AVDD DVDD –6.5 +6.5 V REFCOM AVSS –0.3 +0.3 V ORDERING GUIDE CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V Temperature Package Package VINA, VINB AVSS –0.3 AVDD + 0.3 V Model Range Description Option VREF AVSS –0.3 AVDD + 0.3 V SENSE AVSS –0.3 AVDD + 0.3 V AD9221AR –40°C to +85°C 28-Lead SOIC R-28 CAPB, CAPT AVSS –0.3 AVDD + 0.3 V AD9223AR –40°C to +85°C 28-Lead SOIC R-28 Junction Temperature 150 °C AD9220AR –40°C to +85°C 28-Lead SOIC R-28 Storage Temperature –65 +150 °C AD9221ARS –40°C to +85°C 28-Lead SSOP RS-28 Lead Temperature AD9223ARS –40°C to +85°C 28-Lead SSOP RS-28 (10 sec) 300 °C AD9220ARS –40°C to +85°C 28-Lead SSOP RS-28 AD9221-EB Evaluation Board *Stresses above those listed under Absolute Maximum Ratings may cause perma- AD9223-EB Evaluation Board nent damage to the device. This is a stress rating only; functional operation of the AD9220-EB Evaluation Board device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9221/AD9223/AD9220 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. E AD9221/AD9223/AD9220 PIN CONFIGURATION Zero Error The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the devia- 1 CLK 28 DVDD tion of the actual transition from that point. (LSB) BIT 12 2 27 DVSS BIT 11 3 26 AVDD Gain Error BIT 10 4 25 AVSS The first code transition should occur at an analog value 1/2 LSB AD9221/ BIT 9 5 24 VINB above negative full scale. The last transition should occur at an AD9223/ BIT 8 6 AD9220 23 VINA analog value 1 1/2 LSB below the nominal full scale. Gain error BIT 7 7 22 CML is the deviation of the actual difference between first and last TOP VIEW (Not to Scale) 8 BIT 6 21 CAPT code transitions and the ideal difference between first and last BIT 5 9 20 CAPB code transitions. BIT 4 10 19 REFCOM Temperature Drift 11 18 BIT 3 VREF The temperature drift for zero error and gain error specifies the BIT 2 12 17 SENSE maximum change from the initial (25°C) value to the value at (MSB) BIT 1 13 16 AVSS T or T . MIN MAX 15 OTR 14 AVDD Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with PIN FUNCTION DESCRIPTIONS the supply at its maximum limit. Aperture Jitter Pin Aperture jitter is the variation in aperture delay for successive Number Mnemonic Description samples and is manifested as noise on the input to the A/D. 1 CLK Clock Input Pin Aperture Delay 2BIT 12 Least Significant Data Bit (LSB) Aperture delay is a measure of the sample-and-hold amplifier 3–12 BITS 11–2 Data Output Bit (SHA) performance and is measured from the rising edge of the 13 BIT 1 Most Significant Data Bit (MSB) clock input to when the input signal is held for conversion. 14 OTR Out of Range 15, 26 AVDD 5 V Analog Supply Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio 16, 25 AVSS Analog Ground S/N+D is the ratio of the rms value of the measured input signal 17 SENSE Reference Select to the rms sum of all other spectral components below the Nyquist 18 VREF Reference I/O frequency, including harmonics but excluding dc. The value for 19 REFCOM Reference Common S/N+D is expressed in decibels. 20 CAPB Noise Reduction Pin Effective Number of Bits (ENOB) 21 CAPT Noise Reduction Pin For a sine wave, SINAD can be expressed in terms of the num- 22 CML Common-Mode Level (Midsupply) ber of bits. Using the following formula, 23 VINA Analog Input Pin (+) N = SINAD–. 176 /6.02 () 24 VINB Analog Input Pin (–) 27 DVSS Digital Ground it is possible to get a measure of performance expressed as N, 28 DVDD 3 V to 5 V Digital Supply the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its DEFINITIONS OF SPECIFICATIONS measured SINAD. Integral Nonlinearity (INL) Total Harmonic Distortion (THD) INL refers to the deviation of each individual code from a line THD is the ratio of the rms sum of the first six harmonic com- drawn from “negative full scale” through “positive full scale.” ponents to the rms value of the measured input signal and is The point used as negative full scale occurs 1/2 LSB before the expressed as a percentage or in decibels. first code transition. Positive full scale is defined as a level 1 1/2 Signal-to-Noise Ratio (SNR) LSB beyond the last code transition. The deviation is measured SNR is the ratio of the rms value of the measured input signal to from the middle of each particular code to the true straight line. the rms sum of all other spectral components below the Nyquist Differential Nonlinearity (DNL, No Missing Codes) frequency, excluding the first six harmonics and dc. The value An ideal ADC exhibits code transitions that are exactly 1 LSB for SNR is expressed in decibels. apart. DNL is the deviation from this ideal value. Guaranteed Spurious Free Dynamic Range (SFDR) no missing codes to 12-bit resolution indicates that all 4096 SFDR is the difference in dB between the rms amplitude of the codes, respectively, must be present over all operating ranges. input signal and the peak spurious signal. REV. E –5– AD9221/AD9223/AD9220 AD9221–Typical Performance Characteristics (AVDD = 5 V, DVDD = 5 V, f = 1.5 MSPS, T = 25�C) SAMPLE A 1.0 1.0 8,180,388 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 121,764 85,895 –0.8 –0.8 –1.0 –1.0 N–1 N N+1 0 4095 0 4095 CODE CODE CODE TPC 2. Typical INL TPC 3. “Grounded-Input” TPC 1. Typical DNL Histogram (Input Span = 2 V p-p) 80 –50 80 –55 75 75 –0.5dB –60 –20.0dB –0.5dB 70 70 –65 –6.0dB 65 65 –70 –6.0dB –6.0dB 60 –75 60 –80 55 55 –20.0dB –20.0dB –85 –0.5dB 50 50 –90 45 45 –95 –100 40 40 0.1 1.0 0.1 1.0 0.1 1.0 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz TPC 4. SINAD vs. Input Frequency TPC 5. THD vs. Input Frequency TPC 6. SINAD vs. Input Frequency (Input Span = 2.0 V p-p, V = 2.5 V) (Input Span = 2.0 V p-p, V = 2.5 V) (Input Span = 5.0 V p-p, V = 2.5 V) CM CM CM –50 –60 100 90 –55 –65 –20.0dB 80 –60 –70 70 –65 –75 SFDR 60 –70 –80 5V p-p –0.5dB 50 SNR –75 –85 40 2V p-p –6.0dB –80 –90 30 –85 –95 20 –90 –100 10 –60 –50 –40 –30 –20 –10 0 0.1 1.0 0.2 0.3 0.4 0.6 0.8 1 2 3 FREQUENCY – MHz A – dBFS IN SAMPLE RATE – MSPS TPC 8. THD vs. Sample Rate TPC 9. SNR/SFDR vs. A (Input TPC 7. THD vs. Input Frequency IN (A = –0.5 dB, f = 500 kHz, Amplitude) (f = 500 kHz, Input (Input Span = 5.0 V p-p, V = 2.5 V) IN IN IN CM V = 2.5 V) Span = 2 V p-p, V = 2.5 V) CM CM –6– REV. E THD– dB SINAD – dB DNL – LSBs THD – dB THD – dB INL – LSBs SNR/SFDR – dB SINAD – dB HITS AD9221/AD9223/AD9220 AD9223–Typical Performance Characteristics (AVDD = 5 V, DVDD = 5 V, f = 3.0 MSPS, T = 25�C) SAMPLE A 1.0 1.0 8,123,672 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 130,323 96,830 –0.8 –0.8 –1.0 –1.0 N–1 N N+1 0 0 4095 0 4095 CODE CODE CODE TPC 10. Typical DNL TPC 11. Typical INL TPC 12. “Grounded-Input” Histogram (Input Span = 2 V p-p) –50 80 80 –55 75 75 –0.5dB –60 –0.5dB –20.0dB 70 70 –65 –6.0dB 65 –70 65 –6.0dB –75 –0.5dB 60 60 –80 55 55 –6.0dB –20.0dB –85 –20.0dB 50 50 –90 45 –95 45 –100 40 40 0.1 1.0 10.0 0.1 1.0 10.0 0.1 1.0 10.0 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz TPC 13. SINAD vs. Input Frequency TPC 14. THD vs. Input Frequency TPC 15. SINAD vs. Input Frequency (Input Span = 2.0 V p-p, V = 2.5 V) (Input Span = 2.0 V p-p, V = 2.5 V) (Input Span = 5.0 V p-p, V = 2.5 V) CM CM CM –50 100 –60 –55 90 –65 –60 80 –70 –65 –20.0dB 70 –75 SFDR –70 60 5V p-p –75 –80 –6.0dB 50 –80 SNR –85 2V p-p –0.5dB 40 –85 –90 30 –90 –95 20 –95 –100 –100 10 –60 –50 –40 –30 –20 –10 0.1 1.0 10.0 0.4 0.6 0.8 1 2 3 4 5 6 0 A – dBFS FREQUENCY – MHz SAMPLE RATE – MSPS IN TPC 16. THD vs. Input Frequency TPC 18. SNR/SFDR vs. A (Input TPC 17. THD vs. Sample Rate IN (Input Span = 5.0 V p-p, V = 2.5 V) Amplitude) (f = 1.5 MHz, Input CM (A = –0.5 dB, f = 500 kHz, IN IN IN Span = 2 V p-p, V = 2.5 V) V = 2.5 V) CM CM REV. E –7– THD – dB SINAD – dB DNL – LSBs INL – LSBs THD – dB THD – dB SNR/SFDR – dB SINAD – dB HITS AD9221/AD9223/AD9220 AD9220–Typical Performance Characteristics (AVDD = 5 V, DVDD = 5 V, f = 10 MSPS, T = 25�C) SAMPLE A 1.0 1.0 8,123,672 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 –0.2 –0.2 –0.4 –0.4 –0.6 130,323 –0.6 134,613 –0.8 –0.8 –1.0 –1.0 N–1 N N+1 1 4095 1 4095 CODE CODE CODE TPC 19. Typical DNL TPC 20. Typical INL TPC 21. “Grounded-Input” Histogram (Input Span = 2 V p-p) 80 –50 80 –55 75 75 –0.5dB –0.5dB –60 70 70 –6.0dB –65 –6dB 65 –20dB 65 –70 60 –75 60 –6dB –80 –20.0dB 55 55 –20dB –85 –0.5dB 50 50 –90 45 45 –95 40 –100 40 0.1 1.0 10.0 0.1 1.0 10.0 0.5 1.0 10.0 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz TPC 22. SINAD vs. Input Frequency TPC 23. THD vs. Input Frequency TPC 24. SINAD vs. Input Frequency (Input Span = 2.0 V p-p, V = 2.5 V) (Input Span = 2.0 V p-p, V = 2.5 V) (Input Span = 5.0 V p-p, V = 2.5 V) CM CM CM –60 –50 90 –65 –55 80 SFDR 5V p-p –70 –60 70 –20.0dB –75 –65 60 2V p-p SNR –0.5dB –80 –70 50 –6.0dB –85 –75 40 –80 –90 30 –85 –95 20 –90 –100 10 0.1 1.0 10.0 110 15 0 –60 –50 –40 –30 –20 –10 FREQUENCY – MHz SAMPLE RATE – MSPS A – dBFS IN TPC 25. THD vs. Input Frequency TPC 26. THD vs. Clock Frequency TPC 27. SNR/SFDR vs. A (Input IN (Input Span = 5.0 V p-p, V = 2.5 V) (A = –0.5 dB, f = 1.0 MHz, Amplitude) (f = 5.0 MHz, Input CM IN IN IN V = 2.5 V) Span = 2 V p-p, V = 2.5 V) CM CM –8– REV. E THD – dB DNL – LSBs SINAD – dB THD – dB INL – LSBs THD – dB SINAD – dB SNR/SFDR – dB HITS AD9221/AD9223/AD9220 INTRODUCTION also similar. The data sheet is structured such that the designer The AD9221/AD9223/AD9220 are members of a high perfor- can make an informed decision in selecting the proper A/D and mance, complete single-supply 12-bit ADC product family based optimizing its performance to fit the specific application. on the same CMOS pipelined architecture. The product family 0 allows the system designer an upward or downward component AD9220 selection path based on dynamic performance, sample rate, and power. The analog input range of the AD9221/AD9223/AD9220 AD9223 –3 is highly flexible, allowing for both single-ended or differen- tial inputs of varying amplitudes that can be ac or dc coupled. Each device shares the same interface options, pinout, and –6 package offering. AD9221 The AD9221/AD9223/AD9220 utilize a four-stage pipeline architecture with a wideband input sample-and-hold amplifier –9 (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last stage, consists of a low resolution flash A/D connected to a switched capacitor DAC –12 and interstage residue amplifier (MDAC). The residue amplifier 1 10 100 FREQUENCY – MHz amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital Figure 2. Full-Power Bandwidth correction of flash errors. The last stage simply consists of a 4000 flash A/D. AD9220 The pipeline architecture allows a greater throughput rate at the AD9221 expense of pipeline delay or latency. This means that while the AD9223 3000 converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a 2000 concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers can be configured to 1000 interface with 5 V or 3.3 V logic families. The AD9221/AD9223/AD9220 use both edges of the clock in their internal timing circuitry (see Figure 1 and Specifications 0 0 for exact timing requirements). The A/D samples the analog 10 20 30 40 50 60 SETTLING TIME – ns input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the Figure 3. Settling Time input SHA is in the sample mode; during the clock high time, it is in hold. System disturbances just prior to the rising edge of ANALOG INPUT AND REFERENCE OVERVIEW the clock and/or excessive clock jitter may cause the input SHA Figure 4, a simplified model of the AD9221/AD9223/AD9220, to acquire the wrong value, and should be minimized. highlights the relationship between the analog inputs, VINA, The internal circuitry of both the input SHA and individual VINB, and the reference voltage, VREF. Like the voltage pipeline stages of each member of the product family are opti- applied to the top of the resistor ladder in a flash A/D converter, mized for both power dissipation and performance. An inherent the value VREF defines the maximum input voltage to the A/D trade-off exists between the input SHA’s dynamic performance core. The minimum input voltage to the A/D core is automati- and its power dissipation. Figures 2 and 3 show this trade-off by cally defined to be –VREF. comparing the full-power bandwidth and settling time of the AD9221/AD9223/AD9220. Both figures reveal that higher full- AD9221/AD9223/AD9220 power bandwidths and faster settling times are achieved at the +V VINA REF expense of an increase in power dissipation. Similarly, a trade- off exists between the sampling rate and the power dissipated 12 V CORE A/D in each stage. CORE As previously stated, the AD9221, AD9223, and AD9220 are –V VINB REF similar in most aspects except for the specified sampling rate, power consumption, and dynamic performance. The product Figure 4. AD9221/AD9223/AD9220 Equivalent family is highly flexible, providing several different input ranges Functional Input Circuit and interface options. As a result, many of the application issues and trade-offs associated with these resulting configurations are REV. E –9– CODE AMPLITUDE – dB AD9221/AD9223/AD9220 The addition of a differential input structure gives the user an The SHA’s optimum distortion performance for a differential or additional level of flexibility that is not possible with traditional single-ended input is achieved under the following two conditions: flash converters. The input stage allows the user to easily config- (1) the common-mode voltage is centered around midsupply ure the inputs for either single-ended operation or differential (i.e., AVDD/2 or approximately 2.5 V) and (2) the input signal operation. The A/D’s input structure allows the dc offset of the voltage span of the SHA is set at its lowest (i.e., 2 V input span). input signal to be varied independently of the input span of the This is due to the sampling switches, Q , being CMOS switches S1 converter. Specifically, the input to the A/D core is the differ- whose R resistance is very low but has some signal depen- ON ence of the voltages applied at the VINA and VINB input dency that causes frequency dependent ac distortion while the pins. Therefore, the equation, SHA is in the track mode. The R resistance of a CMOS ON switch is typically lowest at its midsupply but increases symmetri- (1) VV =INA –VINB CORE cally as the input signal approaches either AVDD or AVSS. A defines the output of the differential input stage and provides lower input signal voltage span centered at midsupply reduces the input to the A/D core. the degree of R modulation. ON The voltage, V , must satisfy the condition, CORE Figure 6 compares the AD9221/AD9223/AD9220’s THD vs. frequency performance for a 2 V input span with a common- (2) –VREF≤≤ V VREF CORE mode voltage of 1 V and 2.5 V. Note how each A/D with a where VREF is the voltage at the VREF pin. common-mode voltage of 1 V exhibits a similar degradation in THD performance at higher frequencies (i.e., beyond 750 kHz). While an infinite combination of VINA and VINB inputs exist Similarly, note how the THD performance at lower frequencies that satisfy Equation 2, there is an additional limitation placed becomes less sensitive to the common-mode voltage. As the on the inputs by the power supply voltages of the AD9221/ input frequency approaches dc, the distortion will be dominated AD9223/AD9220. The power supplies bound the valid operat- by static nonlinearities such as INL and DNL. It is important to ing range for VINA and VINB. The condition, note that these dc static nonlinearities are independent of any AVSS–. 03V<< VINA AVDD+03. V (3) R modulation. ON AVSS–. 03V<< VINB AVDD+03. V –50 where AVSS is nominally 0 V and AVDD is nominally 5 V, defines this requirement. Thus, the range of valid inputs for AD9220 VINA and VINB is any combination that satisfies both 1V CM Equations 2 and 3. –60 For additional information showing the relationship between AD9223 VINA, VINB, VREF and the digital output of the AD9221/ 1V AD9221 CM 1V CM –70 AD9223/AD9220, see Table IV. Refer to Table I and Table II at the end of this section for a AD9223 2.5V CM summary of both the various analog input and reference con- –80 figurations. AD9221 AD9220 2.5V 2.5V ANALOG INPUT OPERATION CM CM Figure 5 shows the equivalent analog input of the AD9221/ –90 0.1 1 10 AD9223/AD9220, which consists of a differential sample-and- FREQUENCY – MHz hold amplifier (SHA). The differential input structure of the SHA is highly flexible, allowing the devices to be easily config- Figure 6. AD9221/AD9223/AD9220 THD vs. Frequency for ured for either a differential or single-ended input. The dc V = 2.5 V and 1.0 V (A = –0.5 dB, Input Span = 2.0 V p-p) CM IN offset, or common-mode voltage, of the input(s) can be set to Due to the high degree of symmetry within the SHA topology, a accommodate either single-supply or dual-supply systems. Also, significant improvement in distortion performance for differen- note that the analog inputs, VINA and VINB, are interchange- tial input signals with frequencies up to and beyond Nyquist can able with the exception that reversing the inputs to the VINA be realized. This inherent symmetry provides excellent cancella- and VINB pins results in a polarity inversion. tion of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half, which C H further reduces the degree of R modulation and its effects ON Q on distortion. S2 + C PIN C Q S The optimum noise and dc linearity performance for either S1 C PAR VINA differential or single-ended inputs is achieved with the largest Q C Q H1 S1 S input signal voltage span (i.e., 5 V input span) and matched VINB – C input impedance for VINA and VINB. Note that only a slight PIN Q S2 C PAR degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9221/AD9223/ C H AD9220 DC Specifications. Figure 5. AD9221/AD9223/AD9220 Simplified Input Circuit –10– REV. E THD – dB AD9221/AD9223/AD9220 Referring to Figure 5, the differential SHA is implemented using a applications may require a larger resistor value to reduce the noise switched-capacitor topology. Therefore, its input impedance bandwidth or possibly limit the fault current in an overvoltage and its subsequent effects on the input drive source should be condition. Other applications may require a larger resistor value understood to maximize the converter’s performance. The com- as part of an antialiasing filter. In any case, since the THD bination of the pin capacitance, C , parasitic capacitance, C , performance is dependent on the series resistance and the above PIN PAR and sampling capacitance, C , is typically less than 16 pF. mentioned factors, optimizing this resistor value for a given S When the SHA goes into track mode, the input source must application is encouraged. charge or discharge the voltage stored on C to the new input S A slight improvement in SNR performance and dc offset voltage. This action of charging and discharging C , averaged S performance is achieved by matching the input resistance of VINA over a period of time and for a given sampling frequency, f , S and VINB. The degree of improvement is dependent on the makes the input impedance appear to have a benign resistive resistor value and the sampling rate. For series resistor values component. However, if this action is analyzed within a sampling greater than 100 Ω, the use of a matching resistor is encouraged. period (i.e., T = 1/f ), the input impedance is dynamic and there- S Figure 8 shows a plot for THD performance versus R for SERIES fore certain precautions on the input drive source should be the AD9221/AD9223/AD9220 at their respective sampling rate observed. and Nyquist frequency. The Nyquist frequency typically repre- The resistive component to the input impedance can be com- sents the worst case scenario for an ADC. In this case, a high puted by calculating the average charge that gets drawn by C H speed, high performance amplifier (AD8047) was used as the from the input drive source. It can be shown that if C is allowed S buffer op amp. Although not shown, the AD9221/AD9223/AD9220 to fully charge up to the input voltage before switches Q are S1 exhibits a slight increase in SNR (i.e. 1 dB to 1.5 dB) as the opened, then the average current into the input is the same as if resistance is increased from 0 kΩ to 2.56 kΩ due to its bandlimiting there were a resistor of 1/(C f ) ohms connected between the S S effect on wideband noise. Conversely, it exhibits slight decrease inputs. This means that the input impedance is inversely pro- in SNR (i.e., 0.5 dB to 2 dB) if VINA and VINB do not have a portional to the converter’s sample rate. Since C is only 4 pF, S matched input resistance. this resistive component is typically much larger than that of the drive source (i.e., 25 kΩ at f = 10 MSPS). S –45 If one considers the SHA’s input impedance over a sampling period, it appears as a dynamic input impedance to the input drive source. When the SHA goes into the track mode, the input –55 AD9223 source should ideally provide the charging current through R ON of switch Q in an exponential manner. The requirement of S1 exponential charging means that the most common input source, –65 an op amp, must exhibit a source impedance that is both low AD9220 and resistive up to and beyond the sampling frequency. The output impedance of an op amp can be modeled with a –75 series inductor and resistor. When a capacitive load is switched AD9221 onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output recov- –85 1 10 100 1k 10k ers, ringing may occur. To remedy the situation, a series resistor R – � SERIES can be inserted between the op amp and the SHA input as shown in Figure 7. The series resistance helps isolate the op amp from Figure 8. THD vs. R (f = f /2, A = –0.5 dB, Input SERIES IN S IN the switched-capacitor load. Span = 2 V p-p, V = 2.5 V) CM Figure 8 shows that a small R between 30 Ω and 50 Ω SERIES V provides the optimum THD performance for the AD9220. CC AD9221/AD9223/ Lower values of R are acceptable for the AD9223 and SERIES AD9220 R S AD9221 as their lower sampling rates provide a longer transient VINA R S recovery period for the AD8047. Note that op amps with lower VINB bandwidths will typically have a longer transient recovery period V EE VREF and therefore require a slightly higher value of R and/or SERIES 10�F 0.1�F lower sampling rate to achieve the optimum THD performance. SENSE REFCOM As the value of R increases, a corresponding increase in SERIES distortion is noted. This is due to its interaction with the SHA’s parasitic capacitor, C , which has a signal dependency. Thus, PAR Figure 7. Series Resistor Isolates Switched-Capacitor SHA the resulting R-C time constant is signal dependent and conse- Input from Op Amp. Matching Resistors Improve SNR quently a source of distortion. Performance The noise or small-signal bandwidth of the AD9221/AD9223/ The optimum size of this resistor is dependent on several factors, AD9220 is the same as their full-power bandwidth as shown in which include the AD9221/AD9223/AD9220 sampling rate, the Figure 2. For noise sensitive applications, the excessive bandwidth selected op amp, and the particular application. In most applica- may be detrimental and the addition of a series resistor and/or tions, a 30 Ω to 50 Ω resistor is sufficient. However, some REV. E –11– THD – dB AD9221/AD9223/AD9220 shunt capacitor can help limit the wideband noise at the A/D’s disable the reference amplifier if the SENSE pin is tied to AVDD. input by forming a low-pass filter. Note, however, that the Disabling the reference amplifier allows the VREF pin to be combination of this series resistance with the equivalent input driven by an external voltage reference. capacitance of the AD9221/AD9223/AD9220 should be evalu- ated for those time-domain applications that are sensitive to the AD9221/AD9223/AD9220 input signal’s absolute settling time. In applications where har- TO A/D monic distortion is not a primary concern, the series resistance 5k� CAPT may be selected in combination with the SHA’s nominal 16 pF of 5k� input capacitance to set the filter’s 3 dB cutoff frequency. A2 5k� A better method of reducing the noise bandwidth, while possi- CAPB 5k� bly establishing a real pole for an antialiasing filter, is to add DISABLE LOGIC some additional shunt capacitance between the input (i.e., VINA A2 and/or VINB) and analog ground. Since this additional shunt VREF capacitance combines with the equivalent input capacitance of A1 1V the AD9221/AD9223/AD9220, a lower series resistance can 7.5k� be selected to establish the filter’s cutoff frequency while not degrading the distortion performance of the device. The shunt SENSE DISABLE capacitance also acts like a charge reservoir, sinking or sourcing LOGIC 5k� A1 the additional charge required by the hold capacitor, C , further REFCOM H reducing current transients seen at the op amp’s output. The effect of this increased capacitive load on the op amp driv- Figure 9. Equivalent Reference Circuit ing the AD9221/AD9223/AD9220 should be evaluated. To The actual reference voltages used by the internal circuitry of optimize performance when noise is the primary consideration, the AD9221/AD9223/AD9220 appear on the CAPT and CAPB increase the shunt capacitance as much as the transient response pins. For proper operation when using the internal or an external of the input signal will allow. Increasing the capacitance too reference, it is necessary to add a capacitor network to decouple much may adversely affect the op amp’s settling time, frequency these pins. Figure 10 shows the recommended decoupling net- response, and distortion performance. work. This capacitive network performs the following three functions: (1) along with the reference amplifier, A2, it provides REFERENCE OPERATION a low source impedance over a large frequency range to drive The AD9221/AD9223/AD9220 contain an on-board band gap the A/D internal circuitry, (2) it provides the necessary compen- reference that provides a pin-strappable option to generate sation for A2, and (3) it band-limits the noise contribution from either a 1 V or 2.5 V output. With the addition of two external the reference. The turn-on time of the reference voltage appear- resistors, the user can generate reference voltages other than 1 V ing between CAPT and CAPB is approximately 15 ms and and 2.5 V. Another alternative is to use an external reference for should be evaluated in any power-down mode of operation. designs requiring enhanced accuracy and/or drift performance. See Table II for a summary of the pin-strapping options for the 0.1�F AD9221/AD9223/AD9220 reference configurations. CAPT Figure 9 shows a simplified model of the internal voltage reference AD9221/ 0.1�F 10�F AD9223/ of the AD9221/AD9223/AD9220. A pin-strappable reference AD9220 amplifier buffers a 1 V fixed reference. The output from the CAPB reference amplifier, A1, appears on the VREF pin. The voltage 0.1�F on the VREF pin determines the full-scale input span of the Figure 10. Recommended CAPT/CAPB Decoupling A/D. This input span equals, Network Full-Scale Input Span = 2 � VREF The A/D’s input span may be varied dynamically by changing The voltage appearing at the VREF pin as well as the state of the differential reference voltage appearing across CAPT and the internal reference amplifier, A1, are determined by the volt- CAPB symmetrically around 2.5 V (i.e., midsupply). To change age appearing at the SENSE pin. The logic circuitry contains the reference at speeds beyond the capabilities of A2, it will be two comparators that monitor the voltage at the SENSE pin. necessary to drive CAPT and CAPB with two high speed, low The comparator with the lowest set point (approximately 0.3 V) noise amplifiers. In this case, both internal amplifiers (i.e., A1 controls the position of the switch within the feedback path and A2) must be disabled by connecting SENSE to AVDD and of A1. If the SENSE pin is tied to REFCOM, the switch is VREF to REFCOM, and the capacitive decoupling network connected to the internal resistor network, thus providing a removed. The external voltages applied to CAPT and CAPB VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respec- short or resistor, the switch is connected to the SENSE pin. A tively, in which the input span can be varied between 2 V and short will provide a VREF of 1.0 V while an external resistor 5 V. Note that those samples within the pipeline A/D during network will provide an alternative VREF between 1.0 V and any reference transition will be corrupted and should be 2.5 V. The other comparator controls internal circuitry that will discarded. –12– REV. E AD9221/AD9223/AD9220 Table I. Analog Input Configuration Summary Input Range (V) Input Input Figure Connection Coupling Span (V) VINA* VINB* No. Comments Single-Ended DC 2 0 to 2 1 13, 14 Best for stepped input response applica- tions, suboptimum THD, and noise performance. Requires ±5 V op amp. 2 × VREF 0 to VREF 13, 14 Same as above but with improved noise 2 × VREF performance due to increase in dynamic range. Headroom/settling time require- ments of ±5 V op amp should be evaluated. 50 to 5 2.5 13, 14 Optimum noise performance, excellent THD performance. Requires op amp with VCC > 5 V due to headroom issue. 2 × VREF 2.5 – VREF 2.5 24 Optimum THD performance with VREF = to 1. Noise to performance improves while 2.5 + VREF THD performance degrades as VREF increases to 2.5 V. Single-supply operation (i.e., 5 V) for many op amps. Single-Ended AC 2 or 0 to 1 or 1 or VREF 15 Suboptimum ac performance due to input 2 × VREF 0 to 2 × VREF common-mode level not biased at optimum midsupply level (i.e., 2.5 V). 50 to 5 2.5 15 Optimum noise performance, excellent THD performance, ability to use ±5 V op amp. 2 × VREF 2.5 – VREF 2.5 16 Flexible input range, optimum THD to performance with VREF = 1. Noise 2.5 + VREF performance improves while THD perfor- mance degrades as VREF increases to 2.5 V. Ability to use +5 V or ±5 V op amp. Differential AC 2 2 to 3 3 to 2 19 Optimum full-scale THD and SFDR (via Transformer) performance well beyond the A/D’s Nyquist frequency. Preferred mode for under- sampling applications. 2 × VREF 2.5 – VREF/2 2.5 + VREF/2 19 Same as 2 V to 3 V input range with the to to exception that full-scale THD and SFDR 2.5 + VREF/2 2.5 – VREF/2 performance can be traded off for better noise performance. Refer to discussion in AC Coupling and Interface Issue section and Simple AC Interface section. 5 1.75 to 3.25 3.25 to 1.75 19 Optimum Noise performance. Also, the optimum THD and SFDR performance for “less than” full-scale signals (i.e., –6 dBFS). Refer to discussion in AC Coupling and Interface Issue section and Simple AC Interface section. *VINA and VINB can be interchanged if signal inversion is required. REV. E –13– AD9221/AD9223/AD9220 Table II. Reference Configuration Summary Reference Input Span (VINA–VINB) Operating Mode (V p-p) Required VREF (V) Connect To INTERNAL 2 1 SENSE VREF INTERNAL 5 2.5 SENSE REFCOM INTERNAL 2 ≤ SPAN ≤ 5 and 1 ≤ VREF ≤ 2.5 and R1 VREF and SENSE SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE and REFCOM EXTERNAL 2 ≤ SPAN ≤ 51 ≤ VREF ≤ 2.5 SENSE AVDD (Nondynamic) VREF EXT. REF. EXTERNAL 2 ≤ SPAN ≤ 5 CAPT and CAPB SENSE AVDD (Dynamic) Externally Driven VREF REFCOM EXT. REF. CAPT EXT. REF. CAPB DRIVING THE ANALOG INPUTS AD9221/AD9223/AD9220 offers the following benefits: (1) Introduction Signal swings are smaller and therefore linearity requirements The AD9221/AD9223/AD9220 has a highly flexible input placed on the input signal source may be easier to achieve, (2) structure, allowing it to interface with single-ended or differen- Signal swings are smaller and therefore may allow the use of op tial input interface circuitry. The applications shown in sections amps that may otherwise have been constrained by headroom Driving the Analog Inputs and Reference Configurations, along 20 with the information presented in Input and Reference Over- view of this data sheet, give examples of both single-ended and 30 differential operation. Refer to Tables I and II for a list of the different possible input and reference configurations and their 40 associated figures in the data sheet. AD9223 AD9221 50 The optimum mode of operation, analog input range, and asso- ciated interface circuitry will be determined by the particular 60 application’s performance requirements as well as power supply AD9220 options. For example, a dc coupled single-ended input would be 70 appropriate for most data acquisition and imaging applications. Also, many communication applications that require a dc coupled 80 input for proper demodulation can take advantage of the excel- 90 lent single-ended distortion performance of the AD9221/AD9223/ 0.1 1 10 100 AD9220. The input span should be configured such that the FREQUENCY– MHz system’s performance objectives and the headroom requirements of the driving op amp are simultaneously met. Figure 11. AD9221/AD9223/AD9220 Input CMR vs. Alternatively, the differential mode of operation with a transformer Input Frequency coupled input provides the best THD and SFDR performance limitations, (3) Differential operation minimizes even-order over a wide frequency range. This mode of operation should be harmonic products, and (4) Differential operation offers noise considered for the most demanding spectral based applications immunity based on the device’s common-mode rejection. that allow ac coupling (e.g., Direct IF to Digital Conversion). Figure 11 depicts the common-mode rejection of the three devices. Single-ended operation requires that VINA be ac- or dc-coupled As is typical of most CMOS devices, exceeding the supply limits to the input signal source while VINB of the AD9221/AD9223/ will turn on internal parasitic diodes, resulting in transient cur- AD9220 can be biased to the appropriate voltage corresponding rents within the device. Figure 12 shows a simple means of to a midscale code transition. Note that signal inversion may be clamping an ac- or dc-coupled single-ended input with the easily accomplished by transposing VINA and VINB. The rated addition of two series resistors and two diodes. An optional capaci- specifications for the AD9221/AD9223/AD9220 are character- tor is shown for ac-coupled applications. Note that a larger ized using single-ended circuitry with input spans of 5 V and series resistor could be used to limit the fault current through 2 V as well as VINB = 2.5 V. D1 and D2 but should be evaluated since it can cause a degrada- Differential operation requires that VINA and VINB be simulta- tion in overall performance. A similar clamping circuit could also neously driven with two equal signals that are in and out of be used for each input if a differential input signal is being applied. phase versions of the input signal. Differential operation of the –14– REV. E CMR – dB AD9221/AD9223/AD9220 OPTIONAL network can be inserted between the op amp’s output and the AC COUPLING AVDD AD9221/AD9223/AD9220 input to provide a real pole. V CC CAPACITOR D2 R R S1 S2 Simple Op Amp Buffer 1N4148 30� 20� AD9221/ AD9223/ In the simplest case, the input signal to the AD9221/AD9223/ D1 AD9220 AD9220 will already be biased at levels in accordance with the 1N4148 V selected input range. It is simply necessary to provide an EE adequately low source impedance for the VINA and VINB Figure 12. Simple Clamping Circuit analog input pins of the A/D. Figure 13 shows the recommended configuration for a single-ended drive using an op amp. In this SINGLE-ENDED MODE OF OPERATION case, the op amp is shown in a noninverting unity gain configu- The AD9221/AD9223/AD9220 can be configured for single- ration driving the VINA pin. The internal reference drives the ended operation using dc or ac coupling. In either case, the VINB pin. Note that the addition of a small series resistor of input of the A/D must be driven from an operational amplifier 30 Ω to 50 Ω connected to VINA and VINB will be beneficial that will not degrade the A/D’s performance. Because the A/D in nearly all cases. Refer to the Analog Input Operation section operates from a single-supply, it will be necessary to level-shift for a discussion on resistor selection. Figure 13 shows the ground-based bipolar signals to comply with its input require- proper connection for a 0 V to 5 V input range. Alternative ments. Both dc and ac coupling provide this necessary function, single-ended input ranges of 0 V to 2 × VREF can also be real- but each method results in different interface issues that may ized with the proper configuration of VREF (refer to the Using influence the system design and performance. the Internal Reference section). DC COUPLING AND INTERFACE ISSUES +V Many applications require the analog input signal to be dc- 5V AD9221/ R S AD9223/ coupled to the AD9221/AD9223/AD9220. An operational 0V U1 VINA AD9220 R S amplifier can be configured to rescale and level shift the input VINB signal so that it is compatible with the selected input range of –V 2.5V VREF the A/D. The input range to the A/D should be selected on the 10�F 0.1�F basis of system performance objectives as well as the analog SENSE power supply availability since this will place certain constraints on the op amp selection. Figure 13. Single-Ended AD9221/AD9223/AD9220 Many of the new high performance op amps are specified for Op Amp Drive Circuit only ±5 V operation and have limited input/output swing capa- Op Amp with DC Level Shifting bilities. Therefore, the selected input range of the AD9221/ Figure 14 shows a dc-coupled level shifting circuit employing an AD9223/AD9220 should be sensitive to the headroom require- op amp, A1, to sum the input signal with the desired dc offset. ments of the particular op amp to prevent clipping of the signal. Configuring the op amp in the inverting mode with the given Also, since the output of a dual supply amplifier can swing resistor values results in an ac signal gain of –1. If the signal below –0.3 V, clamping its output should be considered in some inversion is undesirable, interchange the VINA and VINB con- applications. nections to re-establish the original signal polarity. The dc voltage In some applications, it may be advantageous to use an op at VREF sets the common-mode voltage of the AD9221/AD9223/ amp specified for single-supply 5 V operation since it will AD9220. For example, when VREF = 2.5 V, the output level inherently limit its output swing to within the power supply from the op amp will also be centered around 2.5 V. The use of rails. An amplifier like the AD8041, AD8011, and AD817 are ratio matched, thin-film resistor networks will minimize gain useful for this purpose. Rail-to-rail output amplifiers such as and offset errors. Also, an optional pull-up resistor, R , may be P the AD8041 allow the AD9221/AD9223/AD9220 to be con- used to reduce the output load on VREF to ±1 mA. figured for larger input spans, which improves the noise performance. 1 500� If the application requires the largest input span (i.e., 0 V to +V CC 5 V) of the AD9221/AD9223/AD9220, the op amp will require 0.1�F larger supplies to drive it. Various high speed amplifiers in the NC +VREF Op Amp Selection Guide of this data sheet can be selected to 1 500� 7 0V DC 2 accommodate a wide range of supply options. Once again, 1 –VREF R S 6 A1 VINA clamping the output of the amplifier should be considered for 2 1 R 500� P 5 3 these applications. AVDD 4 AD9221/ 1 0.1�F AD9223/ 500� NC Two dc-coupled op amp circuits using a noninverting and AD9220 inverting topology are discussed below. Although not shown, R S VREF VINB the noninverting and inverting topologies can be easily config- NOTES ured as part of an antialiasing filter by using a Sallen-Key or 1 OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D Multiple-Feedback topology, respectively. An additional R-C 2 OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE Figure 14. Single-Ended Input with DC-Coupled Level Shift REV. E –15– AD9221/AD9223/AD9220 AC COUPLING AND INTERFACE ISSUES in parallel to achieve a low cutoff frequency while maintaining a For applications where ac coupling is appropriate, the op amp’s low impedance over a wide frequency range. R isolates the S output can be easily level shifted to the common-mode voltage, buffer amplifier from the A/D input. The optimum performance VCM, of the AD9221/AD9223/AD9220 via a coupling capacitor. is achieved when VINA and VINB are driven via «Immetrical This has the advantage of allowing the op amp’s common-mode networks. The f point can be approximated by the equation, –3 dB level to be symmetrically biased to its midsupply level (i.e., fR =× 12// π× 2×C1+C2 –3 dB() () (V + V )/2). Op amps that operate symmetrically with respect CC EE to their power supplies typically provide the best ac performance +5V as well as the greatest input/output span. Thus, various high +5V R speed/performance amplifiers that are restricted to +5 V/–5 V C1 V R IN S operation and/or specified for 5 V single-supply operation can be VINA easily configured for the 5 V or 2 V input span of the AD9221/ C2 R AD9221/ –5V AD9223/AD9220. The best ac distortion performance is achieved AD9223/ AD9220 when the A/D is configured for a 2 V input span and common- R R S +5V VINB mode voltage of 2.5 V. Note that differential transformer coupling, C1 R C2 which is another form of ac coupling, should be considered for optimum ac performance. Simple AC Interface Figure 16. AC-Coupled Input-Flexible Input Span, Figure 15 shows a typical example of an ac-coupled, single-ended V = 2 V configuration. The bias voltage shifts the bipolar, ground-refer- CM enced input signal to approximately VREF. The value for C1 Op Amp Selection Guide and C2 will depend on the size of the resistor, R. The capacitors, Op amp selection for the AD9221/AD9223/AD9220 is highly C1 and C2, are typically a 0.1 µF ceramic and 10 µF tanta- dependent on a particular application. In general, the performance lum capacitor in parallel to achieve a low cutoff frequency requirements of any given application can be characterized by while maintaining a low impedance over a wide frequency either time domain or frequency domain parameters. In either range. The combination of the capacitor and the resistor form a case, one should carefully select an op amp that preserves the high-pass filter with a high-pass –3 dB frequency determined performance of the A/D. This task becomes challenging when by the equation, one considers the AD9221/AD9223/AD9220’s high perfor- fR =× 12 / π××C1+C2 mance capabilities coupled with other extraneous system level () 3 dB() requirements such as power consumption and cost. The low impedance VREF voltage source both biases the VINB The ability to select the optimal op amp may be further compli- input and provides the bias voltage for the VINA input. Figure 15 cated by either limited power supply availability and/or limited shows the VREF configured for 2.5 V; thus the input range acceptable supplies for a desired op amp. Newer, high perfor- C1 mance op amps typically have input and output range limitations +5V in accordance with their lower supply voltages. As a result, some AD9221/ +VREF C2 op amps will be more appropriate in systems where ac-coupling R S V AD9223/ 0V IN VINA is allowable. When dc-coupling is required, op amps without –VREF AD9220 R headroom constraints, such as rail-to-rail op amps or ones R S –5V where larger supplies can be used, should be considered. The VINB following section describes some op amps currently available VREF from Analog Devices. The system designer is always encouraged C2 C1 SENSE to contact the factory or local sales office to be updated on Analog Devices’ latest amplifier product offerings. Highlights of the Figure 15. AC-Coupled Input areas where the op amps excel and where they may limit the performance of the AD9221/AD9223/AD9220 is also included. of the A/D is 0 V to 5 V. Other input ranges could be selected by changing VREF, but the A/D’s distortion performance will AD817: 50 MHz Unity GBW, 70 ns Settling to 0.01%, +5 V degrade slightly as the input common-mode voltage deviates to ±15 V Supplies from its optimum level of 2.5 V. Best Applications: Sample Rates < 7 MSPS, Low Noise, 5 V p-p Input Range Alternative AC Interface Limits: THD above 100 kHz Figure 16 shows a flexible ac-coupled circuit that can be config- ured for different input spans. Since the common-mode voltage AD826: Dual Version of AD817 of VINA and VINB are biased to midsupply independent of Best Applications: Differential and/or Low Imped- VREF, VREF can be pin-strapped or reconfigured to achieve ance Input input spans between 2 V and 5 V p-p. The AD9221/AD9223/ Drivers, Low Noise AD9220’s CMRR along with the symmetrical coupling R-C Limits: THD above 100 kHz networks will reject both power supply variations and noise. The AD818: 130 MHz @ G = +2 BW, 80 ns Settling to 0.01%, resistors, R, establish the common-mode voltage. They may +5 V to ±15 V Supplies have a high value (e.g., 5 kΩ) to minimize power consumption Best Applications: Sample Rates < 7 MSPS, Low and establish a low cutoff frequency. The capacitors, C1 and Noise, 5 V p-p Input Range, Gains ≥ +2 C2, are typically 0.1 µF ceramic and 10 µF tantalum capacitors Limits: THD above 100 kHz –16– REV. E AD9221/AD9223/AD9220 AD828: Dual Version of AD818 Note that although a single-ended-to-differential op amp topol- Best Applications: Differential and/or Low Imped- ogy would allow dc coupling of the input signal, no significant ance Input improvement in THD performance was realized when compared Drivers, Low Noise, Gains ≥ +2 to the dc single-ended mode of operation up to the AD9221/ Limits: THD above 100 kHz AD9223/AD9220’s Nyquist frequency (i.e., f < f /2). Also, IN S the additional op amp required in the topology tends to increase AD812: Dual, 145 MHz Unity GBW, Single-Supply Cur- the total system noise, power consumption, and cost. Thus, a rent Feedback, +5 V to ±15 V Supplies single-ended mode of operation is recommended for most appli- Best Applications: Differential and/or Low Imped- cations requiring dc coupling. ance Input Drivers, Sample Rates < 7 MSPS Limits: THD above 1 MHz A dramatic improvement in THD and SFDR performance can be realized by operating the AD9221/AD9223/AD9220 in the AD8011: f = 300 MHz, +5 V or ±5 V Supplies, Current –3 dB differential mode using a transformer. Figure 17 shows a plot of Feedback THD versus Input Frequency for the differential transformer Best Applications: Single-Supply, AC-DC-Coupled, coupled circuit for each A/D while Figure 18 shows a plot of Good AC Specs, Low Noise, Low Power (5 mW) SFDR versus Input Frequency. Both figures demonstrate the Limits: THD above 5 MHz, Usable Input/Output enhancement in spectral performance for the differential-mode Range of operation. The performance enhancement between the differen- AD8013: Triple, f = 230 MHz, +5 V or ±5 V Supplies, –3 dB tial and single-ended mode is most noteworthy as the input Current Feedback, Disable Function frequency approaches and goes beyond the Nyquist frequency Best Applications: 3:1 Multiplexer, Good AC Specs (i.e., f > f /2) corresponding to the particular A/D. IN S Limits: THD above 5 MHz, Input Range The figures are also helpful in determining the appropriate A/D AD9631: 220 MHz Unity GBW, 16 ns Settling to 0.01%, for Direct IF down conversion or undersampling applications. ±5 V Supplies Refer to Analog Devices application notes AN-301 and AN-302 Best Applications: Best AC Specs, Low Noise, for an informative discussion on undersampling. One should AC-Coupled select the A/D that meets or exceeds the distortion performance Limits: Usable Input/Output Range, Power requirements measured over the required frequency passband. Consumption For example, the AD9220 achieves the best distortion perfor- mance over an extended frequency range as a result of its greater AD8047: 130 MHz Unity GBW, 30 ns Settling to 0.01%, full-power bandwidth and thus would represent the best selec- ±5 V Supplies tion for an IF undersampling application at 21.4 MHz. Refer to Best Applications: Good AC Specs, Low Noise, the Applications section of this data sheet for more detailed AC-Coupled information and characterization of this particular application. Limits: THD > 5 MHz, Usable Input Range AD8041: Rail-to-Rail, 160 MHz Unity GBW, 55 ns Settling –50 to 0.01%, 5 V Supply, 26 mW Best Applications: Low Power, Single-Supply Systems, DC-Coupled, Large Input Range –60 Limits: Noise with 2 V Input Range AD8042: Dual AD8041 Best Applications: Differential and/or Low Imped- –70 AD9223 ance Input Drivers AD9221 Limits: Noise with 2 V Input Range –80 DIFFERENTIAL MODE OF OPERATION AD9220 Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a –90 1 10 100 single-ended-to-differential conversion. In systems that do not FREQUENCY – MHz need to be dc-coupled, an RF transformer with a center tap is the best method to generate differential inputs for the AD9221/ Figure 17. AD9221/AD9223/AD9220 THD vs. Input AD9223/AD9220. It provides all the benefits of operating the Frequency (V = 2.5 V, 2 V p-p Input Span, A/D in the differential mode without contributing additional CM A = –0.5 dB) noise or distortion. An RF transformer also has the added ben- IN efit of providing electrical isolation between the signal source and the A/D. REV. E –17– THD – dB AD9221/AD9223/AD9220 –55 Figure 23 of this data sheet. Figure 20 demonstrates how both spans of the AD9220 achieve the high degree of linearity and SFDR over a wide range of amplitudes required by the most –65 demanding communication applications. Similar performance is AD9221 achievable with the AD9221 and AD9223 at their correspond- AD9223 ing Nyquist frequency. –75 90 SFDR – 5.0V p-p 80 AD9220 –85 SFDR – 2.0V p-p 70 60 –95 1 10 100 FREQUENCY – MHz 50 SNR – 2.0V p-p 40 Figure 18. AD9221/AD9223/AD9220 SFDR vs. Input SNR – 5.0V p-p Frequency (V = 2.5 V, 2 V p-p Input Span, CM 30 A = –0.5 dB) IN Figure 19 shows the schematic of the suggested transformer 20 –50 –40 –30 –20 –10 0 circuit. The circuit uses a Mini-Circuits RF transformer, model INPUT AMPLITUDE – dBFS #T4-6T, which has an impedance ratio of 4 (turns ratio of 2). Figure 20. AD9220 SFDR, SNR vs. Input Amplitude The schematic assumes that the signal source has a 50 Ω source (f = 5 MHz, f = 10 MSPS, V = 2.5 V, Differential) IN CLK CM impedance. The 1:4 impedance ratio requires the 200 Ω sec- ondary termination for optimum power transfer and VSWR. Figure 20 also reveals a noteworthy difference in the SFDR and The center tap of the transformer provides a convenient means SNR performance of the AD9220 between the 2 V p-p and 5 V p-p of level shifting the input signal to a desired common-mode input span options. First, the SNR performance improves by 2 dB voltage. Optimum performance can be realized when the center with a 5.0 V p-p input span due to the increase in dynamic tap is tied to CML of the AD9221/AD9223/AD9220, which is range. Second, the SFDR performance of the AD9220 will the common-mode bias level of the internal SHA. improve for input signals below approximately –6.0 dBFS. A 3 dB to 5 dB improvement was typically realized for input signal levels between –6.0 dBFS and –36 dBFS. This improvement in SNR R C S S 33� 15pF and SFDR for a 5.0 V p-p span may be advantageous for com- VINA 49.9� munication systems that have additional margin or headroom CML to minimize clipping of the ADC. 0.1�F AD9221/ 200� AD9223/ AD9220 REFERENCE CONFIGURATIONS VINB R C MINI-CIRCUITS S S The figures associated with this section on internal and external T4-1 33� 15pF reference operation do not show recommended matching series resistors for VINA and VINB for the purpose of simplicity. Please refer to the Figure 19. Transformer Coupled Input Driving the Analog Inputs, Introduction section for a discussion of this topic. Also, the figures do not show the decoupling network asso- Transformers with other turns ratios may also be selected to ciated with the CAPT and CAPB pins. Please refer to the Reference optimize the performance of a given application. For example, a Operation section for a discussion of the internal reference circuitry given input signal source or amplifier may realize an improve- and the recommended decoupling network shown in Figure 10. ment in distortion performance at reduced output power levels and signal swings. Therefore, selecting a transformer with a USING THE INTERNAL REFERENCE higher impedance ratio (e.g., Mini-Circuits T16-6T with a 1:16 Single-Ended Input with 0 to 2 � VREF Range impedance ratio) effectively “steps up” the signal level, thus Figure 21 shows how to connect the AD9221/AD9223/AD9220 further reducing the driving requirements of the signal source. for a 0 V to 2 V or 0 V to 5 V input range via pin strapping the Referring to Figure 19, a series resistor, R , and shunt capacitor, S SENSE pin. An intermediate input range of 0 to 2 × VREF can C , were inserted between the AD9221/AD9223/AD9220 and S be established using the resistor programmable configuration in the secondary of the transformer. The values of 33 Ω and 15 pF Figure 23 and connecting VREF to VINB. were selected to specifically optimize both the THD and SNR In either case, both the common-mode voltage and input span performance of the A/D. R and C help provide some isola- S S are directly dependent on the value of VREF. More specifically, tion from transients at the A/D inputs reflected back through the the common-mode voltage is equal to VREF while the input primary of the transformer. span is equal to 2 × VREF. Thus, the valid input range extends The AD9221/AD9223/AD9220 can be easily configured for from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output either a 2 V p-p input span or 5.0 V p-p input span by setting will be 000 Hex; when VINA is ≥ 2 × VREF, the digital output the internal reference (see Table II). Other input spans can be will be FFF Hex. realized with two external gain setting resistors as shown in –18– REV. E SFDR – dB SNR/SFDR – dB AD9221/AD9223/AD9220 Shorting the VREF pin directly to the SENSE pin places the Resistor Programmable Reference internal reference amplifier in unity-gain mode and the resultant Figure 23 shows an example of how to generate a reference VREF output is 1 V. Therefore, the valid input range is 0 V to 2 V. voltage other than 1 V or 2.5 V with the addition of two external However, shorting the SENSE pin directly to the REFCOM pin resistors and a bypass capacitor. Use the equation, configures the internal reference amplifier for a gain of 2.5 and VREF=×11 V + R1/ R2 () the resultant VREF output is 2.5 V. Thus, the valid input range becomes 0 V to 5 V. The VREF pin should be bypassed to the to determine appropriate values for R1 and R2. These resistors REFCOM pin with a 10 µF tantalum capacitor in parallel with a should be in the 2 kΩ to 100 kΩ range. For the example shown, low inductance 0.1 µF ceramic capacitor. R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above, the resultant reference voltage on the VREF pin is 1.5 V. This 2�VREF sets the input span to be 3 V p-p. To assure stability, place a AD9221/ VINA AD9223/ 0V 0.1 µF ceramic capacitor in parallel with R1. AD9220 VINB 10�F 0.1�F The common-mode voltage can be set to VREF by connecting VREF VINB to VREF to provide an input span of 0 to 2 × VREF. SHORT FOR 0V TO 2V Alternatively, the common-mode voltage can be set to VREF by INPUT SPAN connecting VINB to a low impedance 2.5 V source. For the SENSE example shown, the valid input single range for VINA is 1 V to SHORT FOR 0V TO 5V 4 V since VINB is set to an external, low impedance 2.5 V source. INPUT SPAN The VREF pin should be bypassed to the REFCOM pin with a REFCOM 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor. Figure 21. Internal Reference—2 V p-p Input Span, V = 1 V, or 5 V p-p Input Span, V = 2.5 V CM CM 4V VINA Single-Ended or Differential Input, V = 2.5 V CM 1V Figure 22 shows the single-ended configuration that gives the best 2.5V VINB dynamic performance (SINAD, SFDR). To optimize dynamic AD9220 1.5V VREF specifications, center the common-mode voltage of the analog C1 R1 0.1�F 10�F 2.5k� 0.1�F input at approximately by 2.5 V by connecting VINB to a low SENSE impedance 2.5 V source. As described above, shorting the VREF R2 5k� pin directly to the SENSE pin results in a 1 V reference voltage and a 2 V p-p input span. The valid range for input signals is 1.5 V REFCOM to 3.5 V. The VREF pin should be bypassed to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low induc- Figure 23. Resistor Programmable Reference—3 V p-p tance 0.1 µF ceramic capacitor. Input Span, V = 2.5 V CM This reference configuration could also be used for a differential input in which VINA and VINB are driven via a transformer as USING AN EXTERNAL REFERENCE shown in Figure 19. In this case, the common-mode voltage, Using an external reference may enhance the dc performance of V , is set at midsupply by connecting the transformer’s center CM the AD9221/AD9223/AD9220 by improving drift and accuracy. tap to CML of the AD9221/AD9223/AD9220. VREF can be Figures 24 through 26 show examples of how to use an external configured for 1 V or 2.5 V by connecting SENSE to either VREF reference with the A/D. Table III is a list of suitable voltage or REFCOM respectively. Note that the valid input range for references from Analog Devices. To use an external reference, each of the differential inputs is one-half of single-ended input the user must disable the internal reference amplifier and drive and thus becomes V – VREF/2 to V + VREF/2. CM CM the VREF pin. Connecting the SENSE pin to AVDD disables the internal reference amplifier. 3.5V VINA AD9221/ 1.5V AD9223/ Table III. Suitable Voltage References AD9220 2.5V VINB 1V Initial Operating VREF Output Drift Accuracy Current SENSE 10�F 0.1�F Voltage (ppm/�C) % (max) (�A) REFCOM Internal 1.00 26 1.4 N/A AD589 1.235 10–100 1.2–2.8 50 Figure 22. Internal Reference—2 V p-p Input Span, AD1580 1.225 50–100 0.08–0.8 50 V = 2.5 V CM REF191 2.048 5–25 0.1–0.5 45 Internal 2.50 26 1.4 N/A REF192 2.50 5–25 0.08–0.4 45 REF43 2.50 10–25 0.06–0.1 600 AD780 2.50 3–7 0.04–0.2 1000 REV. E –19– AD9221/AD9223/AD9220 The AD9221/AD9223/AD9220 contains an internal reference conjunction with 1/2 of an OP282 to provide a very low imped- buffer, A2 (see Figure 9), that simplifies the drive requirements ance drive for VINB. The selected op amp need not be a high of an external reference. The external reference must be able to speed op amp and may be selected based on cost, power, and drive a ≈5 kΩ (±20%) load. Note that the bandwidth of the accuracy. reference buffer is deliberately left small to minimize the refer- ence noise contribution. As a result, it is not possible to change 3.75V VINA the reference voltage rapidly in this mode without the removal 1.25V of the CAPT/CAPB Decoupling Network. AD9221/ 820� AD9223/ 5V 1k� Variable Input Span with V = 2.5 V AD9220 CM 0.1�F Figure 24 shows an example of the AD9221/AD9223/AD9220 1k� VINB configured for an input span of 2 × VREF centered at 2.5 V. An 10�F 0.1�F 2N2222 external 2.5 V reference drives the VINB pin, thus setting the 1k� 316� 1/2 common-mode voltage at 2.5 V. The input span can be inde- OP282 7.5k� pendently set by a voltage divider consisting of R1 and R2, 1.225V 5V VREF which generates the VREF signal. A1 buffers this resistor net- 10�F 0.1�F AD1580 work and drives VREF. Choose this op amp based on accuracy 5V SENSE requirements. It is essential that a minimum of a 10 µF capaci- tor in parallel with a 0.1 µF low inductance ceramic capacitor Figure 26. External Reference Using the AD1580 decouple the reference output to ground. and Low Impedance Buffer 2.5V+VREF AD9221/ 2.5V VINA DIGITAL INPUTS AND OUTPUTS AD9223/ 2.5V–VREF AD9220 Digital Outputs 2.5V +5V VINB The AD9221/AD9223/AD9220 output data is presented in REF 22�F 0.1�F 0.1�F R1 positive true straight binary for all input ranges. Table IV indi- cates the output data formats for various input ranges regardless A1 VREF of the selected input range. A twos complement output data 0.1�F R2 format can be created by inverting the MSB. SENSE +5V Table IV. Output Data Format Figure 24. External Reference—V = 2.5 V (2.5 V CM Input (V) Condition (V) Digital Output OTR on VINB, Resistor Divider to Make VREF) VINA –VINB < – VREF 0000 0000 0000 1 Single-Ended Input with 0 to 2 � VREF Range VINA –VINB = – VREF 0000 0000 0000 0 Figure 25 shows an example of an external reference driving VINA –VINB = 0 1000 0000 0000 0 both VINB and VREF. In this case, both the common-mode VINA –VINB = + VREF – 1 LSB 1111 1111 1111 0 voltage and input span are directly dependent on the value of VINA –VINB ≥ + VREF 1111 1111 1111 1 VREF. More specifically, the common-mode voltage is equal to VREF while the input span is equal to 2 × VREF. Thus, the +FS –1 1/2 LSB OTR DATA OUTPUTS valid input range extends from 0 to 2 × VREF. For example, if 1111 1111 1111 OTR 1 the REF-191, a 2.048 external reference was selected, the valid 0 1111 1111 1111 input range extends from 0 to 4.096 V. In this case, 1 LSB of 0 1111 1111 1110 –FS+1/2 LSB the AD9221/AD9223/AD9220 corresponds to 1 mV. It is essen- tial that a minimum of a 10 µF capacitor in parallel with a 0.1 µF 0000 0000 0001 0 low inductance ceramic capacitor decouple the reference output 0 0000 0000 0000 to ground. 1 0000 0000 0000 –FS +FS –FS –1/2 LSB +FS –1/2 LSB 2�REF VINA AD9221/ 0V AD9223/ Figure 27. Output Data Format AD9220 +5V VINB VREF Out Of Range (OTR) 0.1�F 10�F 0.1�F An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital VREF output that is updated along with the data output corresponding 0.1�F to the particular sampled analog input voltage. Thus, OTR has +5V SENSE the same pipeline delay (latency) as the digital data. It is LOW when the analog input voltage is within the analog input range. Figure 25. Input Range = 0 V to 2 × VREF It is HIGH when the analog input voltage exceeds the input range as shown in Figure 27. OTR will remain HIGH until the Low Cost/Power Reference analog input returns within the input range and another conver- The external reference circuit shown in Figure 26 uses a low sion is completed. By logical ANDing OTR with the MSB and cost 1.225 V external reference (e.g., AD580 or AD1580) along its complement, overrange high or underrange low conditions with an op amp and transistor. The 2N2222 transistor acts in –20– REV. E AD9221/AD9223/AD9220 can be detected. Table V is a truth table for the over/underrange In the equation, the rms aperture jitter, t , represents the root- A circuit in Figure 28, which uses NAND gates. Systems requiring sum square of all the jitter sources, which include the clock programmable gain conditioning of the AD9221/AD9223/ input, analog input signal, and A/D aperture jitter specification. AD9220 input signal can immediately detect an out-of-range For example, if a 5 MHz full-scale sine wave is sampled by an condition, thus eliminating gain selection iterations. Also, OTR A/D with a total rms jitter of 15 ps, the SNR performance of the can be used for digital offset and gain calibration. A/D will be limited to 66.5 dB. Undersampling applications are particularly sensitive to jitter. Table V. Out-of-Range Truth Table The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9221/ OTR MSB Analog Input Is AD9223/AD9220. As such, supplies for clock drivers should be 00 In Range separated from the A/D output driver supplies to avoid modulating 01 In Range the clock signal with digital noise. Low jitter crystal controlled 10 Underrange oscillators make the best clock sources. If the clock is generated 11 Overrange from another type of source (by gating, dividing, or other method), it should be retimed by the original clock at the last step. MSB OVER = “1” Most of the power dissipated by the AD9221/AD9223/AD9220 is from the analog power supplies. However, lower clock speeds OTR will reduce digital current slightly. Figure 29 shows the relation- UNDER = “1” MSB ship between power and clock rate for each A/D. 66 Figure 28. Overrange or Underrange Logic 64 Digital Output Driver Considerations (DVDD) 62 The AD9221, AD9223 and AD9220 output drivers can be configured to interface with 5 V or 3.3 V logic families by setting 60 DVDD to 5 V or 3.3 V respectively. The AD9221/AD9223/ 5V p-p 58 AD9220 output drivers are sized to provide sufficient output 2V p-p current to drive a wide variety of logic families. However, large 56 drive currents tend to cause glitches on the supplies and may 54 affect SINAD performance. Applications requiring the AD9221/ 52 AD9223/AD9220 to drive large capacitive loads or large fanout may require additional decoupling capacitors on DVDD. In 50 extreme cases, external buffers or latches may be required. 48 0.5 1.0 1.5 2.0 2.5 3.0 Clock Input and Considerations CLOCK FREQUENCY – MHz The AD9221/AD9223/AD9220 internal timing uses the two Figure 29a. AD9221 Power Consumption vs. Clock edges of the clock input to generate a variety of internal timing Frequency signals. The clock input must meet or exceed the minimum specified pulsewidth high and low (t and t ) specifications CH CL 125 for the given A/D as defined in the Switching Specifications to meet the rated performance specifications. For example, the 120 clock input to the AD9220 operating at 10 MSPS may have a duty cycle between 45% to 55% to meet this timing requirement 115 since the minimum specified t and t is 45 ns. For clock CH CL rates below 10 MSPS, the duty cycle may deviate from this 110 range to the extent that both t and t are satisfied. CH CL 5V p-p 105 All high speed high resolution A/Ds are sensitive to the quality 2V p-p of the clock input. The degradation in SNR at a given full-scale 100 input frequency (f ) due to only aperture jitter (t ) can be IN A calculated with the following equation: 95 SNR = 20 log 1/ 2π f t [] 10 IN A 90 0 1 2 3 4 5 6 CLOCK FREQUENCY – MHz Figure 29b. AD9223 Power Consumption vs. Clock Frequency REV. E –21– POWER – mW POWER – mW AD9221/AD9223/AD9220 300 impedance over a wide frequency range. Note that the AVDD and AVSS pins are co-located on the AD9221/ AD9223/AD9220 to simplify the layout of the decoupling 280 capacitors and provide the shortest possible PCB trace INPUT = 5V p-p lengths. The AD9221/AD9223/AD9220/EB power plane 260 layout, shown in Figure 40 depicts a typical arrangement using a multilayer PCB. INPUT = 2V p-p 240 26 AVDD AD9221/ 0.1�F 220 AD9223/ 25 AD9220 AVSS 200 15 AVDD 01 2 4 6 8 10 124 0.1�F CLOCK FREQUENCY – MHz 16 AVSS Figure 29c. AD9220 Power Consumption vs. Clock Frequency Figure 30. Analog Supply Decoupling The CML is an internal analog bias point used internally by the GROUNDING AND DECOUPLING AD9221/AD9223/AD9220. This pin must be decoupled with at Analog and Digital Grounding least a 0.1 µF capacitor as shown in Figure 31. The dc level of Proper grounding is essential in any high speed, high resolution CML is approximately AVDD/2. This voltage should be buff- system. Multilayer printed circuit boards (PCBs) are recom- ered if it is to be used for any external biasing. mended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: AD9221/ 22 CML 1. The minimization of the loop area encompassed by a signal AD9223/ 0.1�F and its return path. AD9220 2. The minimization of the impedance associated with ground and power paths. Figure 31. CML Decoupling 3. The inherent distributed capacitor formed by the power The digital activity on the AD9221/AD9223/AD9220 chip falls plane, PCB insulation, and ground plane. into two general categories: correction logic and output drivers. These characteristics result in both a reduction of electro- The internal correction logic draws relatively small surges of magnetic interference (EMI) and an overall improvement in current, mainly during the clock transitions. The output drivers performance. draw large current impulses while the output bits are changing. It is important to design a layout that prevents noise from cou- The size and duration of these currents are a function of the pling onto the input signal. Digital signals should not be run in load on the output bits: large capacitive loads are to be avoided. parallel with input signal traces and should be routed away from Note, the internal correction logic of the AD9221, AD9223, the input circuitry. While the AD9221/AD9223/AD9220 features and AD9220 is referenced to AVDD while the output drivers separate analog and digital ground pins, it should be treated as are referenced to DVDD. an analog component. The AVSS and DVSS pins must be joined The decoupling shown in Figure 32, a 0.1 µF ceramic chip together directly under the AD9221/AD9223/AD9220. A solid capacitor, is appropriate for a reasonable capacitive load on ground plane under the A/D is acceptable if the power and the digital outputs (typically 20 pF on each pin). Applications ground return currents are managed carefully. Alternatively, involving greater digital loads should consider increasing the the ground plane under the A/D may contain serrations to steer digital decoupling proportionally, and/or using external buff- currents in predictable directions where cross-coupling between ers/latches. analog and digital would otherwise be unavoidable. The AD9221/ AD9223/AD9220/EB ground layout, shown in Figure 39, depicts the serrated type of arrangement. The analog and digital grounds 28 DVDD AD9221/ 0.1�F are connected by a jumper below the A/D. AD9223/ AD9220 DVSS 27 Analog and Digital Supply Decoupling The AD9221/AD9223/AD9220 features separate analog and digital supply and ground pins, helping to minimize digital Figure 32. Digital Supply Decoupling corruption of sensitive analog signals. In general, AVDD, the A complete decoupling scheme will also include large tantalum analog supply, should be decoupled to AVSS, the analog or electrolytic capacitors on the PCB to reduce low frequency common, as close to the chip as physically possible. Figure 30 ripple to negligible levels. Refer to the AD9221/AD9223/ shows the recommended decoupling for the analog supplies; AD9220/EB schematic and layouts in Figures 36 to 42 for more 0.1 µF ceramic chip capacitors should provide adequately low information regarding the placement of decoupling capacitors. –22– REV. E POWER – mW AD9221/AD9223/AD9220 90 APPLICATIONS Direct IF Down Conversion Using the AD9220 80 As previously noted, the AD9220’s performance in the differen- 70 tial mode of operation extends well beyond its baseband region SFDR and into several Nyquist zone regions. Thus, the AD9220 may 60 be well suited as a mix down converter in both narrow and 50 wideband applications. Various IF frequencies exist over the SNR 40 frequency range in which the AD9220 maintains excellent dynamic performance (e.g., refer to Figure 17 and 18). The IF 30 signal will be aliased to the ADC’s baseband region due to the 20 sampling process in a similar manner that a mixer will down- convert an IF signal. For signals in various Nyquist zones, the 10 following equation may be used to determine the final frequency 0 –50 –40 –30 –20 –10 0 after aliasing. A – dB IN f = f 1 NYQUIST SIGNAL Figure 34. AD9220 Differential Input SNR/SFDR f = f – f 2 NYQUIST SAMPLE SIGNAL vs. Input Amplitude (A ) @ 21.4 MHz f = abs (f – f ) IN 3 NYQUIST SAMPLE SIGNAL f = 2 × f – f 4 NYQUIST SAMPLE SIGNAL Multichannel Data Acquisition with Autocalibration f = abs (2 × f – f ) 5 NYQUIST SAMPLE SIGNAL The AD9221/AD9223/AD9220 is well suited for high perfor- mance, low power data acquisition systems. Aside from its There are several potential benefits in using the ADC to alias exceptional ac performance, it exhibits true 12-bit linearity and (i.e., or mix) down a narrow-band or wideband IF signal. First temperature drift performance (i.e., excluding internal refer- and foremost is the elimination of a complete mixer stage with ence). Furthermore, the A/D product family provides the system its associated amplifiers and filters, reducing cost and power designer with an upward or downward component selection dissipation. Second is the ability to apply various DSP tech- path based on power consumption and sampling rate. niques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, and detection. A typical multichannel data acquisition system is shown in Figure 35. Also shown is some additional inexpensive gain and One common example is the digitization of a 21.4 MHz IF offset autocalibration circuitry that is often required in high using a low jitter 10 MHz sample clock. Using the equation accuracy data acquisition systems. These additional peripheral above for the fifth Nyquist zone, the resultant frequency after components were selected based on their performance, power sampling is 1.4 MHz. Figure 33 shows the typical performance consumption, and cost. of the AD9220 operating under these conditions. Figure 34 demonstrates how the AD9220 is still able to maintain a high Referring to Figure 35, the AD9221/AD9223/AD9220 is config- degree of linearity and SFDR over a wide amplitude. ured for single-ended operation with a 2.5 V p-p input span and a 2.5 V common-mode voltage using an external, precision 2.5 1 0 voltage reference, U1. This configuration and input span allows the buffer amplifier, U4, to be single supply. Also, it simplifies ENCODE = 10MSPS –20 the design of the low temperature drift autocalibration circuitry A = 21.4MHz IN that uses thin-film resistors for temperature stability and ratio- –40 metric accuracy. The input of the AD9221/AD9223/AD9220 can be easily configured for a wider span but it should remain within the input/output swing capabilities of a high speed, rail- –60 to-rail, single-supply amplifier, U4 (e.g., AD8041). –80 8 2 The gain and offset calibration circuitry is based on two 8-bit, 4 7 5 3 6 current-output DAC08s, U3 and U5. The gain calibration 9 –100 circuitry consisting of U3, and an op amp, U2A, is configured to provide a low drift nominal 1.25 V reference to the AD9221/ –120 AD9223/AD9220. The resistor values that set the gain calibra- 15 FREQUENCY – MHz tion range were selected to provide a nominal adjustment span of ±128 LSBs with 1 LSB resolution with respect to the A/D. Note Figure 33. IF Sampling a 21.4 MHz Input Using that the bandwidth of the reference is low and, as a result, it is the AD9220 (V = 2.5 V, Input Span = 2 V p-p) CM not possible to change the reference voltage rapidly in this mode. REV. E –23– AMPLITUDE – dB SNR/SFDR – dB AD9221/AD9223/AD9220 The offset calibration circuitry consists of a DAC, U5 and input that corresponds to –FS of the A/D. Before the value is the buffer amplifier, U4. The DAC is configured for a bipolar read, U4 should be preloaded with a code of 00 (Hex). Several adjustment span of ±64 LSB with a 1/2 LSB resolution span readings can also be taken and averaged to determine the digital with respect to the AD9221/AD9223/AD9220. Note that both gain adjustment code to U2A. In this case, 1 LSB of the A/D current outputs of U5 were configured to provide a bipolar corresponds to 1 LSB of U4. adjustment span. Also, RC is used to decouple the output of Due to the AD9221/AD9223/AD9220’s excellent INL perfor- both DACs, U3 and U5, from their respective op amps. mance, a two-point calibration procedure (i.e., –FS to midscale) The calibration procedure consists of a two step process. First, instead of an endpoint calibration procedure was chosen. Also, the bipolar offset is calibrated by selecting CH2, the 2.5 V sys- since the bipolar offset is insensitive to any gain adjustment (due tem reference, of the analog multiplexer and preloading the DAC, to the differential SHA of the A/D), an iterative calibration U5, with a midscale code of 1000 0000. If possible, several process is not required. The temperature stability of the circuit readings of the A/D should be taken and averaged to determine is enhanced by selecting a dual precision op amp for U2 (e.g., the required digital offset adjustment code, U5. This averaged OP293) and low temperature drift, thin film resistors. Note that offset code requires an extra bit of resolution since 1 LSB of U5 this application circuit was not built at the release of this data equates to 1/2 LSB of the AD9221/AD9223/AD9220. The sheet. Please consult Analog Devices for application assistance required offset correction code to U5 can then be determined. or comments. Second, the system gain is calibrated by selecting CH2, a 1.25 V 0.1�F 1.25k� 1.25V 2.5k� 2.5k� 162� U2B 1.25V U2A 2.5k� 0.1�F 2.5k� 0.1�F �39mV 1.1k� U1 2 � 39� REF43 0.1�F 10�F CH1 +5V SENSE CH2 R 2.5k� C CH3 100� VREF(+) IOUT CH4 VREF OUT U6 U3 CH5 VREF(–) ADG608 DAC08 CH6 AD9221/ IOUT BIT 1 – BIT 12 2.5k� AD9223/ CH7 OTR AD9220 CH8 39� VINA U4 2.50V 39� VINB R R C C 2.5k� 100� 100� VREF(+) IOUT U5 VREF(–) DAC08 IOUT 2.5k� Figure 35. Typical Multichannel Data Acquisition System –24– REV. E AD9221/AD9223/AD9220 +5A +5A TPA JP19 D2 R15 TP16 1N5711 U8 JP20 22� MSB AD9221/ 12 VINA C18 C19 74HC541N 1 J8 0.1�F 0.1�F AD9223/ D3 C13 1 R16 AD9220 74HC04N G1 TP15 1N5711 15pF 19 13 Y0A 22� G2 Y5 Y5A 15 13 MSB A 9 Y1A A A BIT 7 14 3J8 AVDD BIT 1 Y4 A7 26 14 OTR BIT 6 Y2A 8 15 AVDD OTR NOT R17 C26 Y3 TP14 A6 23 BIT 2 12 BIT 5 7 16 Y3A 0.1�F INSTALLED 22� VINA BIT 2 Y4A A5 Y2 20 11 BIT 3 U6 Y4A 5J8 BIT 4 6 17 CAPB BIT 3 Y1 A4 21 10 BIT 4 C24 BIT 3 Y5A 5 18 R18 C23 CAPT BIT 4 TP13 Y0 A3 10�F 22 BIT 5 9 22� 0.1�F BIT 2 4 11 Y3A CML BIT 5 TP1 U5 16V A2 Y7 A 24 8 BIT 6 7J8 MSB 3 12 VINB BIT 6 Y6 A1 C28 18 7 BIT 7 R19 2 TP12 C25 VREF BIT 7 0.1�F A0 +5D2 17 BIT 8 22� 6 20 0.1�F +5A 10 Y2A SENSE BIT 8 GND +5VD 9J8 19 5 BIT 9 A TPB AGND REFCOM BIT 9 C21 D4 R20 27 4 BIT 10 TP11 DVSS BIT 10 0.1�F DGND 1N5711 22� 28 BIT 11 Y1A 3 DVDD BIT 11 11 J8 VINB 25 2 LSB +5D AVSS BIT 12 C15 C14 R21 TP10 D5 16 1 15pF AVSS CLK 0.1�F 22� 1N5711 Y0A 74HC541N 13 J8 JP10 A A A A 1 G1 R22 TP9 C20 11 NOT 19 22� CLK Y7 G2 Y7B 0.1�F REMOVE INSTALLED 9 12 15 J8 U8 U8 JP16 Y6 A7 FOR DIFF. 13 Y2B 4 3 5 6 8 MODE A6 Y5 R23 TP8 TPD TPC OTR 14 Y3B 7 22� Y4 Y6B A5 74HC04N 74HC04N Y4B CLK LSB U7 15 17 J8 6 JP21 Y3 A4 16 Y5B JP15 BIT 11 5 REFOUT R24 TP7 A3 Y2 TPE BIT 10 17 Y6B 22� 4 Y5B Y1 A2 19 J8 Y7B JP11 BIT 9 18 3 Y0 J7 A1 +5A BIT 8 2 R25 TP6 A0 20 +5D2 22� Y4B JP12 10 C33 CLK IN R12 GND +5VD 21 J8 0.1�F 10k� C22 C17 R26 TP5 JP13 R14 0.1�F 22� 0.1�F 50� Y3B 23 J8 C16 JP14 R13 10�F R27 TP4 10k� 16V 22� Y2B 39 J8 JP18 +5REFBUF A R28 TP3 JP17 22� R10 33 J8 820� REFOUT C10 +5REFBUF U3 C11 C9 10�F 0.1�F C12 16V 0.1�F REF43 0.1�F U4 2 6 +5REFBUF V V IN OUT 2J8 F.S./GAIN ADJ A C7 Q1 GND R11 7 A 0.1�F R7 3 4J8 JP9 2N2222 4 1k� 15k� R9 EXTERNAL REFERENCE A 6 AD817 6J8 50� AND REFERENCE BUFFER A U8 A 2 4 C34 8J8 9 8 C8 0.1�F U8 R29 10 J8 R8 10�F 316� DECOUPLING 74HC04N 10k� 16V 12 J8 +5D2 A A –SUPPLY A U8 14 J8 A 11 10 +SUPPLY C27 16 J8 0.1�F L1 74HC04N 18 J8 +5A L5 L6 U8 JP6 20 J8 VINB 13 12 +5REFBUF 22 J8 U2 C32 TPF 0.1�F 74HC04N 24 J8 J2 78L05P A R6 SPARE GATES 25 J8 +V 3 IN OUT 1 R5 CC 10k� C29 10k� GND 26 J8 22�F A 2 TPG 25V 27 J8 C3 J3 A A 0.1�F L2 28 J8 +SUPPLY –V –SUPPLY EE 29 J8 C30 C2 C4 A 22�F 0.1�F 0.1�F 30 J8 A JP5 U1 TPH 25V JP7 A J1 31 J8 J4 JP1 A L3 R4 7 A 3 AIN 32 J8 33� +5 DIG +5D C5 6 C31 AD8047 34 J8 TPI 0.1�F 22�F R1 A 2 4 C1 L4 25V J5 NC 35 J8 50� 0.1�F JP4 +5D2 DGND 36 J8 C6 A 0.1�F JP2 TPJ TPK TPL POWER NC 37 J8 A VINA GJ1 –SUPPLY SUPPLY J6 38 J8 JP3 AGND 40 J8 R2 R3 (GJ1-WIRE 261� 261� A A JUMPER CKT SIDE) Figure 36. Evaluation Board Schematic REV. E –25– AD9221/AD9223/AD9220 Figure 37. Evaluation Board Component Side Layout (Not to Scale) Figure 38. Evaluation Board Solder Side Layout (Not to Scale) –26– REV. E AD9221/AD9223/AD9220 Figure 39. Evaluation Board Ground Plane Layout (Not to Scale) Figure 40. Evaluation Board Power Plane Layout REV. E –27– AD9221/AD9223/AD9220 Figure 41. Evaluation Board Component Side Silkscreen (Not to Scale) Figure 42. Evaluation Board Component Side Silkscreen (Not to Scale) –28– REV. E AD9221/AD9223/AD9220 OUTLINE DIMENSIONS 28-Lead Standard SmWall Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 14 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) � 45� 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8� 1.27 (0.0500) SEATING 0� 0.51 (0.0201) 1.27 (0.0500) 0.32 (0.0126) COPLANARITY PLANE BSC 0.33 (0.0130) 0.40 (0.0157) 0.10 0.23 (0.0091) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 8.20 5.30 7.80 5.00 7.40 1 14 1.85 1.75 0.10 1.65 COPLANARITY 2.00 MAX 0.25 0.09 8� 0.95 0.65 0.38 0.05 BSC 4� 0.75 0.22 SEATING MIN 0� PLANE 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH REV. E –29– AD9221/AD9223/AD9220 Revision History Location Page 2/03—Data Sheet changed from REV. D to REV. E. Updated graphic captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Global Changes to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to Digital Output Driver Considerations (DVDD) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 –30– REV. E –31– –32– PRINTED IN U.S.A. C00576–0–2/03(E)