ANALOG DEVICES AD9212

Octal, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC Data Sheet AD9212 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND 8 analog-to-digital converters (ADCs) integrated into 1 package 100 mW ADC power per channel at 65 MSPS AD9212 10 SNR = 60.8 dB (to Nyquist) VIN + A D + A SERIAL ADC D – A LVDS VIN – A ENOB = 9.8 bits 10 SFDR = 80 dBc (to Nyquist) VIN + B D + B SERIAL ADC Excellent linearity D – B VIN – B LVDS DNL = ±0.3 LSB (typical); INL = ±0.4 LSB (typical) 10 VIN + C D + C SERIAL Serial LVDS (ANSI-644, default) ADC D – C VIN – C LVDS Low power, reduced signal option (similar to IEEE 1596.3) 10 VIN + D D + D SERIAL Data and frame clock outputs ADC LVDS D – D VIN – D 325 MHz, full-power analog bandwidth 10 2 V p-p input voltage range VIN + E SERIAL D + E ADC D – E VIN – E LVDS 1.8 V supply operation 10 Serial port control VIN + F D + F SERIAL ADC D – F Full-chip and individual-channel power-down modes VIN – F LVDS Flexible bit orientation 10 VIN + G D + G SERIAL ADC Built-in and custom digital test pattern generation D – G VIN – G LVDS Programmable clock and data alignment 10 VIN + H SERIAL D + H Programmable output resolution ADC LVDS D – H VIN – H Standby mode VREF SENSE FCO+ APPLICATIONS 0.5V FCO– DATA RATE Medical imaging and nondestructive ultrasound REFT REF MULTIPLIER SERIAL PORT DCO+ REFB SELECT Portable ultrasound and digital beam-forming systems INTERFACE DCO– Quadrature radio receivers Diversity radio receivers RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK– ODM DTP Tape drives Figure 1. Optical networking The ADC contains several features designed to maximize Test equipment flexibility and minimize system cost, such as programmable GENERAL DESCRIPTION clock and data alignment and programmable digital test pattern The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an generation. The available digital test patterns include built-in on-chip sample-and-hold circuit designed for low cost, low power, deterministic and pseudorandom patterns, along with custom user- small size, and ease of use. Operating at a conversion rate of up to defined test patterns entered via the serial port interface (SPI). 65 MSPS, it is optimized for outstanding dynamic performance The AD9212 is available in a RoHS-compliant, 64-lead LFCSP. It is and low power in applications where a small package size is critical. specified over the industrial temperature range of −40°C to +85°C. The ADC requires a single 1.8 V power supply and LVPECL-/ PRODUCT HIGHLIGHTS CMOS-/LVDS-compatible sample rate clock for full performance 1. Small Footprint. Eight ADCs are contained in a small package. operation. No external reference or driver components are 2. Low Power of 100 mW per Channel at 65 MSPS. required for many applications. 3. Ease of Use. A data clock output (DCO) operates up to The ADC automatically multiplies the sample rate clock for 300 MHz and supports double data rate (DDR) operation. the appropriate LVDS serial data rate. A data clock (DCO) 4. User Flexibility. SPI control offers a wide range of flexible for capturing data on the output and a frame clock (FCO) for features to meet specific system requirements. signaling a new output byte are provided. Individual channel 5. Pin-Compatible Family. This includes the AD9222 (12-bit) power-down is supported and typically consumes less than and AD9252 (14-bit). 2 mW when all channels are disabled. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05968-001 AD9212 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Clock Input Considerations ...................................................... 23  Applications ....................................................................................... 1  Serial Port Interface (SPI) .............................................................. 31  General Description ......................................................................... 1  Hardware Interface ..................................................................... 31  Functional Block Diagram .............................................................. 1  Memory Map .................................................................................. 33  Product Highlights ........................................................................... 1  Reading the Memory Map Table .............................................. 33  Revision History ............................................................................... 3  Reserved Locations .................................................................... 33  Specif ica t ions ..................................................................................... 4  Default Values ............................................................................. 33  AC Specifications .......................................................................... 5  Logic Levels ................................................................................. 33  Digital Specifications ................................................................... 6  Applications Information .............................................................. 36  Switching Specifications .............................................................. 7  Design Guidelines ...................................................................... 36  Timing Diagrams .......................................................................... 8  Evaluation Board ............................................................................ 37  Absolute Maximum Ratings .......................................................... 10  Power Supplies ............................................................................ 37  Thermal Impedance ................................................................... 10  Input Signals................................................................................ 37  ESD Caution ................................................................................ 10  Output Signals ............................................................................ 37  Pin Configuration and Function Descriptions ........................... 11  Default Operation and Jumper Selection Settings ................. 38  Equivalent Circuits ......................................................................... 13  Alternative Analog Input Drive Configuration...................... 39  Typical Performance Characteristics ........................................... 15  Outline Dimensions ....................................................................... 56  Theory of Operation ...................................................................... 20  Ordering Guide .......................................................................... 56  Analog Input Considerations .................................................... 20  Rev. E | Page 2 of 56 Data Sheet AD9212 REVISION HISTORY 12/11—Rev. D to Rev. E Changes to Table 9 Endnote .......................................................... 26 Changes to Output Signals Section and Figure 70 ...................... 37 Changes to Digital Outputs and Timing Section ........................ 27 Changed Default Operation and Jumper Selection Settings Added Table 10 ................................................................................ 27 Section .............................................................................................. 38 Changes to Table 11 and Table 12 ................................................. 27 Added Endnote 2 in Ordering Guide ........................................... 56 Changes to RBIAS Pin Section ...................................................... 28 Deleted Figure 63 to Figure 66 ...................................................... 28 5/10—Rev. C to Rev. D Moved Figure 65 .............................................................................. 28 Deleted LFCSP CP-64-3 Package ..................................... Universal Changes to Serial Port Interface (SPI) Section ............................ 30 Changes to output_phase Register, Table 16 ............................... 33 Changes to Hardware Interface Section ....................................... 30 Deleted Figure 85; Renumbered Sequentially ............................. 55 Changes to Table 15 ........................................................................ 31 Updated Outline Dimensions ........................................................ 55 Changes to Reading the Memory Map Table Section ................ 32 Changes to Ordering Guide ........................................................... 55 Added Applications Information and Design Guidelines Sections ............................................................................................. 35 12/09—Rev. B to Rev. C Changes to Input Signals Section .................................................. 36 Updated Outline Dimensions ........................................................ 55 Changes to Output Signals Section ............................................... 36 Changes to Ordering Guide ........................................................... 56 Changes to Figure 70 ...................................................................... 36 Changes to Default Operation and Jumper Selection Settings 7/09—Rev. A to Rev. B Section .............................................................................................. 37 Changes to Figure 5 ......................................................................... 10 Changes to Alternative Analog Input Drive Configuration Changes to Figure 49 and Figure 50 ............................................. 21 Section .............................................................................................. 38 Changes to Figure 63 and Figure 64 ............................................. 28 Changes to Figure 73 ...................................................................... 38 Updated Outline Dimensions ........................................................ 55 Change to Figure 75 ........................................................................ 40 Changes to Figure 76 ...................................................................... 41 12/07—Rev. 0 to Rev. A Changes to Figure 80 ...................................................................... 45 Changes to Features .......................................................................... 1 Changes to Table 17 ........................................................................ 52 Changes to Figure 1 ........................................................................... 1 Updated Outline Dimensions ........................................................ 55 Changes to Crosstalk Parameter ..................................................... 3 Changes to Ordering Guide ........................................................... 55 Changes to Logic Output (SDIO/ODM) ........................................ 5 10/06—Revision 0: Initial Version Changes to Figure 2 to Figure 4 ....................................................... 7 Changes to Figure 59 ...................................................................... 24 Rev. E | Page 3 of 56 AD9212 Data Sheet SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. AD9212-40 AD9212-65 1 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±1.5 ±8 ±1.5 ±8 mV Offset Matching Full ±3 ±8 ±3 ±8 mV Gain Error Full ±0.4 ±1.2 ±3.2 ±4.3 % FS Gain Matching Full ±0.3 ±0.7 ±0.4 ±0.9 % FS Differential Nonlinearity (DNL) Full ±0.1 ±0.4 ±0.3 ±0.65 LSB Integral Nonlinearity (INL) Full ±0.15 ±0.5 ±0.4 ±1 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±17 ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ±21 ppm/°C REFERENCE Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 mV Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 mV Input Resistance Full 6 6 kΩ ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Full 2 2 V p-p Common-Mode Voltage Full AVDD/2 AVDD/2 V Differential Input Capacitance Full 7 7 pF Analog Bandwidth, Full Power Full 325 325 MHz POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD Full 252 260 390 405 mA IDRVDD Full 49.5 53 54 58 mA Total Power Dissipation (Including Output Drivers) Full 542 560 800 833 mW Power-Down Dissipation Full 3 11 3 11 mW 2 Standby Dissipation Full 83 95 mW CROSSTALK AIN = −0.5 dBFS Full −90 −90 dB 3 Overrange Full −90 −90 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. Rev. E | Page 4 of 56 Data Sheet AD9212 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. AD9212-40 AD9212-65 1 Parameter Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 61.2 60.8 dB f = 19.7 MHz Full 60.2 61.2 60.8 dB IN f = 35 MHz Full 61.2 58.5 60.8 dB IN fIN = 70 MHz Full 61.0 60.7 dB SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) f = 2.4 MHz Full 61.2 60.7 dB IN fIN = 19.7 MHz Full 60.0 61.0 60.6 dB fIN = 35 MHz Full 61.0 57.0 60.5 dB fIN = 70 MHz Full 60.8 60.4 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 9.87 9.81 Bits fIN = 19.7 MHz Full 9.71 9.87 9.81 Bits f = 35 MHz Full 9.87 9.43 9.81 Bits IN f = 70 MHz Full 9.84 9.79 Bits IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz Full 87 81 dBc IN f = 19.7 MHz Full 72 85 79 dBc IN fIN = 35 MHz Full 79 62 77 dBc fIN = 35 MHz 25°C 69 77 dBc fIN = 70 MHz Full 74 72 dBc WORST HARMONIC (SECOND OR THIRD) fIN = 2.4 MHz Full −87 −81 dBc fIN = 19.7 MHz Full −85 −72 −79 dBc f = 35 MHz Full −79 −77 −62 dBc IN f = 35 MHz 25°C −77 −69 dBc IN f = 70 MHz Full −74 −72 dBc IN WORST OTHER (EXCLUDING SECOND OR THIRD) f = 2.4 MHz Full −90 −86 dBc IN f = 19.7 MHz Full −85 −72 −86 dBc IN fIN = 35 MHz Full −85 −85 −70 dBc fIN = 70 MHz Full −85 −85 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 77.0 dBc f = 70 MHz, f = 71 MHz 25°C 77.0 77.0 dBc IN1 IN2 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. E | Page 5 of 56 AD9212 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. AD9212-40 AD9212-65 1 Parameter Temperature Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL 2 Differential Input Voltage Full 250 250 mV p-p Input Common-Mode Voltage Full 1.2 1.2 V Input Resistance (Differential) 25°C 20 20 kΩ Input Capacitance 25°C 1.5 1.5 pF LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 0.5 0.5 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 V Input Resistance 25°C 70 70 kΩ Input Capacitance 25°C 0.5 0.5 pF LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 0 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 2 2 pF 3 LOGIC OUTPUT (SDIO/ODM) Logic 1 Voltage (IOH = 800 μA) Full 1.79 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 V DIGITAL OUTPUTS (D + x, D − x), (ANSI-644) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 247 454 247 454 mV Output Offset Voltage (V) Full 1.125 1.375 1.125 1.375 V OS Output Coding (Default) Offset binary Offset binary DIGITAL OUTPUTS (D + x, D − x), (LOW POWER, REDUCED SIGNAL OPTION) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 150 250 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 V Output Coding (Default) Offset binary Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection. Rev. E | Page 6 of 56 Data Sheet AD9212 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. AD9212-40 AD9212-65 1 Temp Parameter Min Typ Max Min Typ Max Unit 2 CLOCK Maximum Clock Rate Full 40 65 MSPS Minimum Clock Rate Full 10 10 MSPS Clock Pulse Width High (tEH) Full 12.5 7.7 ns Clock Pulse Width Low (tEL) Full 12.5 7.7 ns 2, 3 OUTPUT PARAMETERS Propagation Delay (tPD) Full 1.5 2.3 3.1 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 300 ps Fall Time (tF) (20% to 80%) Full 300 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 1.5 2.3 3.1 ns 4 DCO Propagation Delay (tCPD) Full tFCO + tFCO + ns (tSAMPLE/20) (tSAMPLE/20) 4 Full (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 ps DCO to Data Delay (tDATA) 4 Full (t /20) − 300 (t /20) (t /20) + 300 (t /20) − 300 (t /20) (t /20) + 300 ps DCO to FCO Delay (tFRAME) SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE Data-to-Data Skew Full ±50 ±200 ±50 ±200 ps (t − t ) DATA-MAX DATA-MIN Wake-Up Time (Standby) 25°C 600 600 ns Wake-Up Time (Power-Down) 25°C 375 375 μs Pipeline Latency Full 8 8 CLK cycles APERTURE Aperture Delay (t) 25°C 750 750 ps A Aperture Uncertainty (Jitter) 25°C <1 <1 ps rms Out-of-Range Recovery Time 25°C 1 1 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR-4 material. 4 t /20 is based on the number of bits divided by 2 because the delays are based on half duty cycles. SAMPLE Rev. E | Page 7 of 56 AD9212 Data Sheet TIMING DIAGRAMS N – 1 VIN ± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA D – x MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D8 D7 D6 D5 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 N – 8 N – 8 N – 8 D + x Figure 2. 10-Bit Data Serial Stream (Default), MSB First N – 1 VIN ± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FRAME FCO FCO– FCO+ t PD t DATA D – x MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 D + x Figure 3.12-Bit Data Serial Stream, MSB First Rev. E | Page 8 of 56 05968-003 05968-002 Data Sheet AD9212 N – 1 VIN ± x t A N t t EH EL CLK– CLK+ t CPD DCO– DCO+ t t FCO FRAME FCO– FCO+ t PD t DATA D – x LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 LSB D0 D1 D2 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 9 N – 8 N – 8 N – 8 N – 8 D + x Figure 4. 10-Bit Data Serial Stream, LSB First Rev. E | Page 9 of 56 05968-004 AD9212 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE Table 5. With Table 6. 1 Parameter Respect To Rating Air Flow Velocity (m/s) θ θ θ Unit JA JB JC ELECTRICAL 0.0 17.7 °C/W AVDD AGND −0.3 V to +2.0 V 1.0 15.5 8.7 0.6 °C/W DRVDD DRGND −0.3 V to +2.0 V 2.5 13.9 °C/W AGND DRGND −0.3 V to +0.3 V 1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad AVDD DRVDD −2.0 V to +2.0 V soldered to PCB. Digital Outputs DRGND −0.3 V to +2.0 V (D + x, D − x, DCO+, ESD CAUTION DCO−, FCO+, FCO−) CLK+, CLK− AGND −0.3 V to +3.9 V VIN + x, VIN − x AGND −0.3 V to +2.0 V SDIO/ODM AGND −0.3 V to +2.0 V PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V REFT, REFB, RBIAS AGND −0.3 V to +2.0 V VREF, SENSE AGND −0.3 V to +2.0 V ENVIRONMENTAL Operating Temperature −40°C to +85°C Range (Ambient) Storage Temperature −65°C to +150°C Range (Ambient) Maximum Junction 150°C Temperature Lead Temperature 300°C (Soldering, 10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. E | Page 10 of 56 Data Sheet AD9212 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AVDD 1 48 AVDD VIN + G 2 47 VIN + B VIN – G 3 46 VIN – B AVDD 4 45 AVDD EXPOSED PADDLE, PIN 0 VIN – H 5 (BOTTOM OF PACKAGE) 44 VIN – A VIN + H 6 43 VIN + A AVDD 7 42 AVDD AD9212 AVDD 8 41 PDWN TOP VIEW CLK– 9 40 CSB (Not to Scale) CLK+ 10 39 SDIO/ODM AVDD 11 38 SCLK/DTP AVDD 12 37 AVDD DRGND 13 36 DRGND DRVDD 14 35 DRVDD D – H 15 34 D + A D + H 16 33 D – A NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND Figure 5. 64-Lead LFCSP Pin Configuration, Top View Table 7. Pin Function Descriptions Pin No. Mnemonic Description 0 AGND Analog Ground (Exposed Paddle) 1, 4, 7, 8, 11, AVDD 1.8 V Analog Supply 12, 37, 42, 45, 48, 51, 59, 62 13, 36 DRGND Digital Output Driver Ground 14, 35 DRVDD 1.8 V Digital Output Driver Supply 2 VIN + G ADC G Analog Input True 3 VIN − G ADC G Analog Input Complement 5 VIN − H ADC H Analog Input Complement 6 VIN + H ADC H Analog Input True 9 CLK− Input Clock Complement 10 CLK+ Input Clock True 15 D − H ADC H Digital Output Complement 16 D + H ADC H Digital Output True 17 D − G ADC G Digital Output Complement 18 D + G ADC G Digital Output True 19 D − F ADC F Digital Output Complement 20 D + F ADC F Digital Output True 21 D − E ADC E Digital Output Complement 22 D + E ADC E Digital Output True 23 DCO− Data Clock Digital Output Complement 24 DCO+ Data Clock Digital Output True 25 FCO− Frame Clock Digital Output Complement 26 FCO+ Frame Clock Digital Output True 27 D − D ADC D Digital Output Complement 28 D + D ADC D Digital Output True 29 D − C ADC C Digital Output Complement 30 D + C ADC C Digital Output True 31 D − B ADC B Digital Output Complement Rev. E | Page 11 of 56 D – G 17 64 VIN + F D + G 18 63 VIN – F D – F 19 62 AVDD D + F 20 61 VIN – E D – E 21 60 VIN + E D + E 22 59 AVDD DCO– 23 58 REFT DCO+ 24 57 REFB FCO– 25 56 VREF FCO+ 26 55 SENSE D – D 54 RBIAS 27 VIN + D + D 28 53 D D – C 29 52 VIN – D D + C 30 51 AVDD D – B 31 50 VIN – C D + B 32 49 VIN + C 05968-005 AD9212 Data Sheet Pin No. Mnemonic Description 32 D + B ADC B Digital Output True 33 D − A ADC A Digital Output Complement 34 D + A ADC A Digital Output True 38 SCLK/DTP Serial Clock/Digital Test Pattern 39 SDIO/ODM Serial Data Input-Output/Output Driver Mode 40 CSB Chip Select Bar 41 PDWN Power-Down 43 VIN + A ADC A Analog Input True 44 VIN − A ADC A Analog Input Complement 46 VIN − B ADC B Analog Input Complement 47 VIN + B ADC B Analog Input True 49 VIN + C ADC C Analog Input True 50 VIN − C ADC C Analog Input Complement 52 VIN − D ADC D Analog Input Complement 53 VIN + D ADC D Analog Input True 54 RBIAS External Resistor to Set the Internal ADC Core Bias Current 55 SENSE Reference Mode Selection 56 VREF Voltage Reference Input/Output 57 REFB Negative Differential Reference 58 REFT Positive Differential Reference 60 VIN + E ADC E Analog Input True 61 VIN − E ADC E Analog Input Complement 63 VIN − F ADC F Analog Input Complement 64 VIN + F ADC F Analog Input True Rev. E | Page 12 of 56 Data Sheet AD9212 EQUIVALENT CIRCUITS DRVDD V V D – x D + x VIN ± x V V DRGND Figure 6. Equivalent Analog Input Circuit Figure 9. Equivalent Digital Output Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ 1kΩ SCLK/DTP OR PDWN 10Ω CLK– 30kΩ Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit 100Ω RBIAS 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit Figure 11. Equivalent RBIAS Circuit Rev. E | Page 13 of 56 05968-006 05968-007 05968-008 05968-009 05968-011 05968-010 AD9212 Data Sheet AVDD 70kΩ 1kΩ CSB VREF 6kΩ Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit Rev. E | Page 14 of 56 05968-013 05968-012 05968-014 Data Sheet AD9212 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 60.08dB SNR = 60.41dB ENOB = 9.61 ENOB = 9.7 SFDR = 71.68dBc SFDR = 76.11dBc –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 30 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with f = 2.3 MHz, AD9212-40 Figure 18. Single-Tone 32k FFT with f = 35 MHz, AD9212-65 IN IN 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 61.17dB SNR = 60.25dB ENOB = 9.85 ENOB = 9.66 SFDR = 81.27dBc –20 –20 SFDR = 72.45dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Single-Tone 32k FFT with fIN = 19.7 MHz, AD9212-40 Figure 19. Single-Tone 32k FFT with f = 70 MHz, AD9212-65 IN 0 0 AIN = –0.5dBFS AIN = –0.5dBFS SNR = 60.48dB SNR = 60.08dB ENOB = 9.72 ENOB = 9.61 –20 SFDR = 76.84dBc SFDR = 71.68dBc –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10 15 20 25 30 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. Single-Tone 32k FFT with f = 2.3 MHz, AD9212-65 IN Figure 20. Single-Tone 32k FFT with fIN = 120 MHz, AD9212-65 Rev. E | Page 15 of 56 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05968-039 05968-038 05968-037 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05968-042 05968-041 05968-040 AD9212 Data Sheet 90 90 SFDR SFDR 85 85 80 80 75 75 70 70 65 65 SNR SNR 60 60 55 55 50 50 10 15 20 25 30 35 40 10 20 30 40 50 60 ENCODE RATE (MSPS) ENCODE RATE (MSPS) Figure 24. SNR/SFDR vs. f , f = 35 MHz, AD9212-65 Figure 21. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, AD9212-40 SAMPLE IN 90 100 90 SFDR 85 80 80 70 75 60 70 50 SFDR 40 65 70dB REFERENCE SNR 30 60 SNR 20 55 10 50 0 10 15 20 25 30 35 40 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT LEVEL (dBFS) ENCODE RATE (MSPS) Figure 25. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9212-40 Figure 22. SNR/SFDR vs. fSAMPLE, fIN = 19.7 MHz, AD9212-40 90 100 SFDR 90 85 80 80 70 75 60 70 50 SFDR 40 65 SNR 30 70dB REFERENCE 60 SNR 20 55 10 50 0 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 ANALOG INPUT LEVEL (dBFS) ENCODE RATE (MSPS) Figure 23. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, AD9212-65 Figure 26. SNR/SFDR vs. Analog Input Level, f = 35 MHz, AD9212-40 IN Rev. E | Page 16 of 56 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 05968-045 05968-044 05968-043 SNR/SFDR (dB) SNR/SFDR (dB) SNR/SFDR (dB) 05968-047 05968-046 05968-048 Data Sheet AD9212 100 0 AIN1 AND AIN2 = –7dBFS SFDR = 76.7dB 90 IMD2 = 83.38dBc IMD3 = 77.21dBc –20 80 70 –40 60 50 –60 SFDR 40 –80 30 70dB REFERENCE SNR 20 –100 10 –120 0 –60 –50 –40 –30 –20 –10 0 0 24 68 10 12 14 16 18 20 ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9212-65 Figure 30. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, AD9212-40 100 0 AIN1 AND AIN2 = –7dBFS SFDR = 77.4dB 90 IMD2 = 77.92dBc IMD3 = 76.9dBc –20 80 70 –40 60 50 –60 SFDR 40 70dB REFERENCE –80 30 SNR 20 –100 10 –120 0 –60 –50 –40 –30 –20 –10 0 0 5 10 15 20 25 30 ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz) Figure 28. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, AD9212-65 Figure 31. Two-Tone 32k FFT with f = 15 MHz and IN1 f = 16 MHz, AD9212-65 IN2 0 0 AIN1 AND AIN2 = –7dBFS AIN1 AND AIN2 = –7dBFS SFDR = 84.8dB SFDR = 72.5dB IMD2 = 83.66dBc IMD2 = 77.14dBc IMD3 = 84.6dBc –20 –20 IMD3 = 72.55dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 24 68 10 12 14 16 18 20 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. Two-Tone 32k FFT with f = 15 MHz and f = 16 MHz, IN1 IN2 Figure 32. Two-Tone 32k FFT with f = 70 MHz and IN1 AD9212-40 f = 71 MHz, AD9212- 65 IN2 Rev. E | Page 17 of 56 SNR/SFDR (dB) SNR/SFDR (dB) AMPLITUDE (dBFS) 05968-051 05968-050 05968-049 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 05968-054 05968-053 05968-052 AD9212 Data Sheet 80 0.5 0.4 75 0.3 SFDR 0.2 70 0.1 65 0 –0.1 SNR 60 –0.2 –0.3 55 –0.4 –0.5 50 1 10 100 1000 0 200 400 600 800 1000 ANALOG INPUT FREQUENCY (MHz) CODE Figure 33. SNR/SFDR vs. f , AD9212-65 Figure 36. INL, f = 2.3 MHz, AD9212-65 IN IN 90 0.5 0.4 85 0.3 80 SFDR 0.2 75 0.1 70 0 –0.1 65 SINAD –0.2 60 –0.3 55 –0.4 50 –0.5 –40 –20 0 20 40 60 80 0 200 400 600 800 1000 TEMPERATURE (°C) CODE Figure 34. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, AD9212-40 Figure 37. DNL, f = 2.3 MHz, AD9212-65 IN –30 90 –35 85 SFDR –40 80 –45 75 –50 70 –55 65 SINAD 60 –60 55 –65 50 –70 –40 –20 0 20 40 60 80 0 5 10 15 20 25 30 35 40 TEMPERATURE (°C) FREQUENCY (MHz) Figure 38. CMRR vs. Frequency, AD9212-65 Figure 35. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, AD9212-65 Rev. E | Page 18 of 56 SINAD/SFDR (dB) SINAD/SFDR (dB) SNR/SFDR (dB) 05968-057 05968-056 05968-055 CMRR (dB) DNL (LSB) INL (LSB) 05968-061 05968-060 05968-058 Data Sheet AD9212 2.5 0 0.096 LSB rms –1 –3dB BANDWIDTH = 325MHz –2 2.0 –3 –4 1.5 –5 –6 1.0 –7 –8 0.5 –9 –10 0 –11 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 05 50 100 150 200 250 300 350 400 45000 CODE FREQUENCY (MHz) Figure 39. Input-Referred Noise Histogram, AD9212-65 Figure 41. Full Power Bandwidth vs. Frequency, AD9212-65 0 NPR = 51.13dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz –20 –40 –60 –80 –100 –120 510 15 20 25 0 FREQUENCY (MHz) Figure 40. Noise Power Ratio (NPR), AD9212- 65 Rev. E | Page 19 of 56 AMPLITUDE (dBFS) NUMBER OF HITS (Millions) 05968-062 05968-063 AMPLITUDE (dBFS) 05968-064 AD9212 Data Sheet THEORY OF OPERATION The AD9212 architecture consists of a pipelined ADC divided The clock signal alternately switches the input circuit between into three sections: a 4-bit first stage followed by eight 1.5-bit sample mode and hold mode (see Figure 42). When the input stages and a 3-bit flash. Each stage provides sufficient overlap circuit is switched into sample mode, the signal source must be to correct for flash errors in the preceding stage. The quantized capable of charging the sample capacitors and settling within outputs from each stage are combined into a final 10-bit result one-half of a clock cycle. A small resistor in series with each in the digital correction logic. The pipelined architecture permits input can help reduce the peak transient current injected from the first stage to operate with a new input sample while the the output stage of the driving source. In addition, low-Q inductors remaining stages operate with preceding samples. Sampling or ferrite beads can be placed on each leg of the input to reduce occurs on the rising edge of the clock. high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of low- Each stage of the pipeline, excluding the last, consists of a low Q inductors or ferrite beads is required when driving the converter resolution flash ADC connected to a switched-capacitor DAC front end at high IF frequencies. Either a shunt capacitor or two and an interstage residue amplifier (for example, a multiplying single-ended capacitors can be placed on the inputs to provide a digital-to-analog converter (MDAC)). The residue amplifier matching passive network. This ultimately creates a low-pass magnifies the difference between the reconstructed DAC output filter at the input to limit unwanted broadband noise. See the and the flash input for the next stage in the pipeline. One bit of AN-742 Application Note, Frequency Domain Response of redundancy is used in each stage to facilitate digital correction Switched-Capacitor ADCs; the AN-827 Application Note, A of flash errors. The last stage simply consists of a flash ADC. Resonant Approach to Interfacing Amplifiers to Switched-Capacitor The output staging block aligns the data, corrects errors, and ADCs; and the Analog Dialogue article “Transformer-Coupled passes the data to the output buffers. The data is then serialized Front-End for Wideband A/D Converters” (Volume 39, April 2005) and aligned to the frame and data clocks. for more information. In general, the precise values depend on the application. ANALOG INPUT CONSIDERATIONS The analog inputs of the AD9212 are not internally dc-biased. The analog input to the AD9212 is a differential switched- capacitor circuit designed for processing differential input signals. Therefore, in ac-coupled applications, the user must provide This circuit can support a wide common-mode range while this bias externally. Setting the device so that VCM = AVDD/2 is maintaining excellent performance. An input common-mode recommended for optimum performance, but the device can voltage of midsupply minimizes signal-dependent errors and function over a wider range with reasonable performance, as provides optimum performance. shown in Figure 45 and Figure 46. H C PAR H VIN + x C SAMPLE SS SS C SAMPLE VIN – x H C PAR H Figure 42. Switched-Capacitor Input Circuit Rev. E | Page 20 of 56 05968-017 Data Sheet AD9212 90 90 85 85 SFDR (dBc) SFDR 80 80 75 75 70 70 65 65 SNR (dB) SNR 60 60 55 55 50 50 0.3 0.6 0.9 1.2 1.5 0.3 0.6 0.9 1.2 1.5 ANALOG INPUT COMMON-MODE VOLTAGE (V) ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 43. SNR/SFDR vs. Common-Mode Voltage, Figure 45. SNR/SFDR vs. Common-Mode Voltage, f = 2.3 MHz, AD9212-40 f = 2.3 MHz, AD9212-65 IN IN 90 90 85 85 80 80 SFDR 75 75 SFDR (dBc) 70 70 65 65 SNR SNR (dB) 60 60 55 55 50 50 0.3 0.6 0.9 1.2 1.5 0.3 0.6 0.9 1.2 1.5 ANALOG INPUT COMMON-MODE VOLTAGE (V) ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 44. SNR/SFDR vs. Common-Mode Voltage, Figure 46. SNR/SFDR vs. Common-Mode Voltage, f = 19.7 MHz, AD9212-40 f = 35 MHz, AD9212-65 IN IN Rev. E | Page 21 of 56 SNR/SFDR (dB) SNR/SFDR (dB) 05968-066 05968-065 SNR/SFDR (dB) SNR/SFDR (dB) 05968-068 05968-067 AD9212 Data Sheet ADT1-1WT For best dynamic performance, the source impedances driving 1:1 Z RATIO C R VIN + x and VIN − x should be matched such that common-mode VIN + x settling errors are symmetrical. These errors are reduced by the ADC 1 2V p-p 49.9Ω C DIFF AD9212 common-mode rejection of the ADC. An internal reference buffer R AVDD VIN – x creates the positive and negative reference voltages, REFT and AGND C 1kΩ REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, 1kΩ and the REFT and REFB voltages and span are defined as 0.1μF 1 C IS OPTIONAL. DIFF REFT = 1/2 (AVDD + VREF) Figure 47. Differential Transformer-Coupled Configuration REFB = 1/2 (AVDD − VREF) for Baseband Applications Span = 2 × (REFT − REFB) = 2 × VREF ADT1-1WT 2V p-p 16nH 16nH 0.1μF 1:1 Z RATIO 33Ω It can be seen from these equations that the REFT and REFB VIN+x voltages are symmetrical about the midsupply voltage and, by 65Ω ADC 499Ω 2.2pF 1kΩ AD9212 definition, the input span is twice the value of the VREF voltage. 16nH 33Ω VIN–x Maximum SNR performance is achieved by setting the ADC to AVDD the largest span in a differential configuration. In the case of the 1kΩ AD9212, the largest input span available is 2 V p-p. 0.1μF 1kΩ Differential Input Configurations Figure 48. Differential Transformer-Coupled Configuration for IF Applications There are several ways to drive the AD9212 either actively or Single-Ended Input Configuration passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the AD8334 A single-ended input may provide adequate performance in differential driver to drive the AD9212 provides excellent perfor- cost-sensitive applications. In this configuration, SFDR and mance and a flexible interface to the ADC (see Figure 50) for distortion performance degrade due to the large input common- baseband applications. This configuration is commonly used mode swing. If the application requires a single-ended input for medical ultrasound systems. configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. For applications where SNR is a key parameter, differential A full-scale input of 2 V p-p can still be applied to the ADC’s transformer coupling is the recommended input configuration VIN + x pin while the VIN − x pin is terminated. Figure 49 (see Figure 47 and Figure 48), because the noise performance of details a typical single-ended input configuration. most amplifiers is not adequate to achieve the true performance AVDD of the AD9212. C Regardless of the configuration, the value of the shunt capacitor, 1kΩ R VIN + x C, is dependent on the input frequency and may need to be 0.1µF 2V p-p 49.9Ω 1kΩ reduced or removed. 1 ADC C DIFF AVDD AD9212 1kΩ 25Ω R VIN – x C 0.1µF 1kΩ 1 C IS OPTIONAL. DIFF Figure 49. Single-Ended Input Configuration 0.1μF LOP VIP 0.1μF 187Ω R VOH 0.1μF 120nH INH VIN + x 1V p-p AD8334 1.0kΩ 22pF ADC LNA VGA 374Ω C AD9212 1.0kΩ R LMD VIN – x 0.1μF VOL 187Ω 0.1μF AVDD 0.1μF10μF LON VIN 1kΩ 274Ω 18nF 0.1μF 1kΩ Figure 50. Differential Input Configuration Using the AD8334 Rev. E | Page 22 of 56 05968-021 05968-018 05968-020 05968-019 Data Sheet AD9212 In some applications, it is acceptable to drive the sample clock CLOCK INPUT CONSIDERATIONS inputs with a single-ended CMOS signal. In such applications, For optimum performance, the AD9212 sample clock inputs CLK+ should be driven directly from a CMOS gate, and the (CLK+ and CLK−) should be clocked with a differential signal. CLK− pin should be bypassed to ground with a 0.1 μF capacitor This signal is typically ac-coupled into the CLK+ and CLK− pins in parallel with a 39 kΩ resistor (see Figure 54). Although the via a transformer or capacitors. These pins are biased internally CLK+ input circuit supply is AVDD (1.8 V), this input is and require no additional biasing. designed to withstand input voltages of up to 3.3 V, making the Figure 51 shows the preferred method for clocking the AD9212. selection of the drive logic voltage very flexible. The low jitter clock source is converted from single-ended to AD9510/AD9511/ differential using an RF transformer. The back-to-back Schottky AD9512/AD9513/ AD9514/AD9515 0.1µF diodes across the secondary transformer limit clock excursions CLK+ CLK into the AD9212 to approximately 0.8 V p-p differential. This OPTIONAL 0.1µF 1 50Ω 100Ω CMOS DRIVER CLK+ helps prevent the large voltage swings of the clock from feeding ADC through to other portions of the AD9212, and it preserves the CLK AD9212 fast rise and fall times of the signal, which are critical to low 0.1µF CLK– jitter performance. 0.1µF 39kΩ 1 ® 50Ω RESISTOR IS OPTIONAL. Mini-Circuits ADT1–1WT, 1:1Z Figure 54. Single-Ended 1.8 V CMOS Sample Clock 0.1µF 0.1µF XFMR CLK+ CLK+ AD9510/AD9511/ 100Ω ADC AD9512/AD9513/ 50Ω AD9212 AD9514/AD9515 0.1µF 0.1µF CLK– CLK+ CLK SCHOTTKY OPTIONAL 0.1µF 0.1µF 1 50Ω 100Ω DIODES: CMOS DRIVER CLK+ HSM2812 ADC Figure 51. Transformer-Coupled Differential Clock CLK AD9212 0.1µF 0.1µF CLK– Another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 52. The AD9510/ 1 50Ω RESISTOR IS OPTIONAL. AD9511/AD9512/AD9513/AD9514/AD9515 family of clock Figure 55. Single-Ended 3.3 V CMOS Sample Clock drivers offers excellent jitter performance. Clock Duty Cycle Considerations AD9510/AD9511/ AD9512/AD9513/ Typical high speed ADCs use both clock edges to generate a AD9514/AD9515 0.1µF 0.1µF variety of internal timing signals. As a result, these ADCs may CLK+ CLK CLK+ be sensitive to the clock duty cycle. Commonly, a 5% tolerance is ADC 100Ω PECL DRIVER AD9212 required on the clock duty cycle to maintain dynamic performance 0.1µF 0.1µF CLK– CLK– characteristics. The AD9212 contains a duty cycle stabilizer (DCS) CLK 1 1 240Ω 240Ω 50Ω 50Ω that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range 1 50Ω RESISTORS ARE OPTIONAL. of clock input duty cycles without affecting the performance of Figure 52. Differential PECL Sample Clock the AD9212. When the DCS is on, noise and distortion perfor- AD9510/AD9511/ mance are nearly flat for a wide range of duty cycles. However, AD9512/AD9513/ AD9514/AD9515 some applications may require the DCS function to be off. If so, 0.1µF 0.1µF CLK+ CLK CLK+ keep in mind that the dynamic range performance can be affected ADC when operated in this mode. See the Memory Map section for 100Ω LVDS DRIVER AD9212 0.1µF 0.1µF more details on using this feature. CLK– CLK– CLK 1 1 50Ω 50Ω The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the 1 50Ω RESISTORS ARE OPTIONAL. sampling frequency require approximately eight clock cycles Figure 53. Differential LVDS Sample Clock to allow the DLL to acquire and lock to the new rate. Rev. E | Page 23 of 56 05968-022 05968-024 05968-023 05968-025 05968-026 AD9212 Data Sheet Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the As shown in Figure 57 and Figure 58, the power dissipated by clock input. The degradation in SNR at a given input frequency the AD9212 is proportional to its sample rate. The digital power (fA) due only to aperture jitter (tJ) can be calculated by dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. SNR Degradation = 20 × log 10(1/2 × π × fA × tJ) 0.30 0.60 In this equation, the rms aperture jitter represents the root mean 0.58 square of all jitter sources, including the clock input, analog input 0.25 0.56 signal, and ADC aperture jitter specifications. IF undersampling AVDD CURRENT applications are particularly sensitive to jitter (see Figure 56). 0.54 0.20 0.52 The clock input should be treated as an analog signal in cases 0.15 where aperture jitter may affect the dynamic range of the AD9212. 0.50 TOTAL POWER Power supplies for clock drivers should be separated from the 0.48 0.10 ADC output driver supplies to avoid modulating the clock signal 0.46 with digital noise. Low jitter crystal-controlled oscillators make 0.44 DRVDD CURRENT 0.05 the best clock sources. If the clock is generated from another 0.42 type of source (by gating, dividing, or other methods), it should 0 0.40 be retimed by the original clock at the last step. 10 15 20 25 30 35 40 ENCODE (MHz) Refer to the AN-501 Application Note and the AN-756 Figure 57. Supply Current vs. f for f = 10.3 MHz, AD9212-40 SAMPLE IN Application Note for more in-depth information about jitter 0.40 0.90 performance as it relates to ADCs. AVDD CURRENT 130 0.35 0.85 RMS CLOCK JITTER REQUIREMENT 120 0.30 0.80 110 0.25 0.75 100 16 BITS TOTAL POWER 0.20 0.70 90 14 BITS 80 0.15 0.65 12 BITS 70 0.10 0.60 10 BITS 60 DRVDD CURRENT 0.125ps 0.05 0.55 8 BITS 50 0.25ps 0.5ps 0 0.50 1.0ps 40 10 20 30 40 50 60 2.0ps ENCODE (MHz) 30 1 10 100 1000 Figure 58. Supply Current vs. f for f = 10.3 MHz, AD9212-65 SAMPLE IN ANALOG INPUT FREQUENCY (MHz) Figure 56. Ideal SNR vs. Input Frequency and Jitter Rev. E | Page 24 of 56 SNR (dB) 05968-015 CURRENT (A) CURRENT (A) POWER (W) POWER (W) 05968-090 05968-089 Data Sheet AD9212 By asserting the PDWN pin high, the AD9212 is placed into recommended that the trace length be no longer than 24 inches power-down mode. In this state, the ADC typically dissipates and that the differential output traces be kept close together and 11 mW. During power-down, the LVDS output drivers are placed at equal lengths. An example of the FCO and data stream when the AD9212 is used with traces of proper length and position is into a high impedance state. The AD9212 returns to normal operating mode when the PDWN pin is pulled low. This pin is shown in Figure 59. both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 4.7 μF decoupling capacitors on REFT and REFB, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors, and approximately 375 μs is required to restore full operation. CH1 500mV/DIV = FCO 5ns/DIV There are several other power-down options available when CH2 500mV/DIV = DCO CH3 500mV/DIV = DATA using the SPI. The user can individually power down each Figure 59. LVDS Output Timing Example in ANSI-644 Mode (Default), channel or put the entire device into standby mode. The latter AD9212-65 option allows the user to keep the internal PLL powered when An example of the LVDS output using the ANSI-644 standard fast wake-up times (~600 ns) are required. See the Memory (default) data eye and a time interval error (TIE) jitter histogram Map section for more details on using these features. with trace lengths less than 24 inches on standard FR-4 material Digital Outputs and Timing is shown in Figure 60. Figure 61 shows an example of the trace The AD9212 differential outputs conform to the ANSI-644 LVDS length exceeding 24 inches on standard FR-4 material. Notice standard by default upon power-up. This can be changed to a low that the TIE jitter histogram reflects the decrease of the data eye power, reduced signal option (similar to the IEEE 1596.3 standard) opening as the edge deviates from the ideal position. It is the user’s via the SDIO/ODM pin or the SPI. This LVDS standard can further responsibility to determine if the waveforms meet the timing reduce the overall power dissipation of the device by approximately budget of the design when the trace lengths exceed 24 inches. 36 mW. See the SDIO/ODM Pin section or Table 16 in the Additional SPI options allow the user to further increase the Memory Map section for more information. The LVDS driver internal termination (increasing the current) of all eight outputs current is derived on chip and sets the output current at each in order to drive longer trace lengths (see Figure 62). Even though output equal to a nominal 3.5 mA. A 100 Ω differential termination this produces sharper rise and fall times on the data edges and resistor placed at the LVDS receiver inputs results in a nominal is less prone to bit errors, the power dissipation of the DRVDD 350 mV swing at the receiver. supply increases when this option is used. The AD9212 LVDS outputs facilitate interfacing with LVDS In cases that require increased driver strength to the DCO± and receivers in custom ASICs and FPGAs for superior switching FCO± outputs because of load mismatch, Register 0x15 allows performance in noisy environments. Single point-to-point net the user to increase the drive strength by 2×. To do this, first set the topologies are recommended with a 100 Ω termination resistor appropriate bit in Register 0x05. Note that this feature cannot be placed as close to the receiver as possible. If there is no far-end used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and Bit 5 take receiver termination or there is poor differential trace routing, precedence over this feature. See the Memory Map section for timing errors may result. To avoid such timing errors, it is more details. Rev. E | Page 25 of 56 05968-027 AD9212 Data Sheet 500 400 EYE: ALL BITS ULS: 12071/12071 EYE: ALL BITS ULS: 12072/12072 400 300 300 200 200 100 100 0 0 –100 –100 –200 –200 –300 –300 –400 –500 –400 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 –150ps –100ps –50ps 0ps 50ps 100ps 150ps –150ps –100ps –50ps 0ps 50ps 100ps 150ps Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Termination On and Trace Lengths Greater Than 24 Inches on Standard FR-4 Less Than 24 Inches on Standard FR-4 The format of the output data is offset binary by default. An 500 EYE: ALL BITS ULS: 12067/12067 example of the output coding format can be found in Table 8. 400 To change the output data format to twos complement, see the 300 Memory Map section. 200 100 Table 8. Digital Output Coding 0 (VIN + x) − (VIN − x), Digital Output Offset Binary –100 Code Input Span = 2 V p-p (V) (D9 ... D0) –200 1023 +1.00 11 1111 1111 –300 512 0.00 10 0000 0000 –400 511 −0.001953 01 1111 1111 –500 0 −1.00 00 0000 0000 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns Data from each ADC is serialized and provided on a separate 100 channel. The data rate for each serial stream is equal to 10 bits 90 times the sample clock rate, with a maximum of 650 Mbps 80 (10 bits × 65 MSPS = 650 Mbps). The lowest typical conversion 70 rate is 10 MSPS. However, if lower sample rates are required for 60 a specific application, the PLL can be set up via the SPI to allow 50 encode rates as low as 5 MSPS. See the Memory Map section for 40 information about enabling this feature. 30 20 10 0 –200ps –100ps 0ps 100ps 200ps Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater Than 24 Inches on Standard FR-4 Rev. E | Page 26 of 56 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 05968-028 05968-030 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 05968-029 Data Sheet AD9212 Two output clocks are provided to assist in capturing data from falling edges of the DCO that supports double data rate (DDR) the AD9212. The DCO is used to clock the output data and is capturing. The FCO is used to signal the start of a new output equal to five times the sample clock (CLK) rate. Data is clocked byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information. out of the AD9212 and must be captured on the rising and Table 9. Flexible Output Test Modes Subject Output Test to Data Mode Bit Format Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Select 0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 (8-bit) Same Yes 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 0010 +Full-scale short 1111 1111 (8-bit) Same Yes 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0011 −Full-scale short 0000 0000 (8-bit) Same Yes 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 0100 Checkerboard 1010 1010 (8-bit) 0101 0101 (8-bit) No 10 1010 1010 (10-bit) 01 0101 0101 (10-bit) 1010 1010 1010 (12-bit) 0101 0101 0101 (12-bit) 10 1010 1010 1010 (14-bit) 01 0101 0101 0101 (14-bit) 1 0101 PN sequence long N/A N/A Yes 1 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 (8-bit) 0000 0000 (8-bit) No 11 1111 1111 (10-bit) 00 0000 0000 (10-bit) 1111 1111 1111 (12-bit) 0000 0000 0000 (12-bit) 11 1111 1111 1111 (14-bit) 00 0000 0000 0000 (14-bit) 1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No 1001 1-/0-bit toggle 1010 1010 (8-bit) N/A No 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 1010 1× sync 0000 1111 (8-bit) N/A No 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1011 One bit high 1000 0000 (8-bit) N/A No 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1100 Mixed frequency 1010 0011 (8-bit) N/A No 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) 1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Rev. E | Page 27 of 56 AD9212 Data Sheet When the SPI is used, the DCO phase can be adjusted in 60° SDIO/ODM Pin increments relative to the data edge. This enables the user to The SDIO/ODM pin is for use in applications that do not require refine system timing margins if required. The default DCO+ SPI mode operation. This pin can enable a low power, reduced and DCO− timing, as shown in Figure 2, is 90° relative to the signal option (similar to the IEEE 1596.3 reduced range link output data edge. output standard) if it and the CSB pin are tied to AVDD during An 8-, 12-, and 14-bit serial stream can also be initiated from the device power-up. This option should only be used when the SPI. This allows the user to implement different serial stream to digital output trace lengths are less than 2 inches from the LVDS test the device’s compatibility with lower and higher resolution receiver. When this option is used, the FCO, DCO, and outputs systems. When changing the resolution to a 12-bit serial stream, function normally, but the LVDS signal swing of all channels is the data stream is lengthened. See Figure 3 for the 12-bit example. reduced from 350 mV p-p to 200 mV p-p, allowing the user to However, when using the 12-bit option, the data stream stuffs further reduce the power on the DRVDD supply. two 0s at the end of the 10-bit serial data. For applications where this pin is not used, it should be tied low. When the SPI is used, all data outputs can be inverted from In this case, the device pin can be left open, and the 30 kΩ internal their nominal state. This is not to be confused with inverting pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. the serial stream to an LSB-first mode. In default mode, as If applications require this pin to be driven from a 3.3 V logic level, shown in Figure 2, the MSB is first in the data output serial insert a 1 kΩ resistor in series with this pin to limit the current. stream. However, this can be inverted so that the LSB is first in Table 11. Output Driver Mode Pin Settings the data output serial stream (see Figure 4). Resulting Resulting There are 12 digital output test pattern options available that Selected ODM ODM Voltage Output Standard FCO and DCO can be initiated through the SPI. This feature is useful when Normal AGND ANSI-644 ANSI-644 Operation (10 kΩ pull- (default) (default) validating receiver capture and timing. Refer to Table 9 for the down resistor) output bit sequencing options available. Some test patterns have ODM AVDD Low power, Low power, two serial sequential words and can be alternated in various reduced signal reduced signal ways, depending on the test pattern chosen. Note that some option option patterns do not adhere to the data format select option. In addition, customer user-defined test patterns can be assigned in SCLK/DTP Pin the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode The SCLK/DTP pin is for use in applications that do not require options except PN sequence short and PN sequence long can SPI mode operation. This pin can enable a single digital test pattern support 8- to 14-bit word lengths in order to verify data capture if it and the CSB pin are held high during device power-up. When to the receiver. the SCLK/DTP is tied to AVDD, the ADC channel outputs shift The PN sequence short pattern produces a pseudorandom bit out the following pattern: 10 0000 0000. The FCO and DCO 9 sequence that repeats itself every 2 − 1 or 511 bits. A description function normally while all channels shift out the repeatable of the PN sequence and how it is generated can be found in test pattern. This pattern allows the user to perform timing Section 5.1 of the ITU-T 0.150 (05/96) standard. The only alignment adjustments among the FCO, DCO, and output data. difference is that the starting value must be a specific value For normal operation, this pin should be tied to AGND through instead of all 1s (see Table 10 for the initial values). a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant. The PN sequence long pattern produces a pseudorandom bit Table 12. Digital Test Pattern Pin Settings 23 sequence that repeats itself every 2 − 1 or 8,388,607 bits. A Resulting Resulting description of the PN sequence and how it is generated can be Selected DTP DTP Voltage D + x and D − x FCO and DCO found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The Normal AGND Normal Normal operation only differences are that the starting value must be a specific Operation (10 kΩ pull- operation down resistor) value instead of all 1s (see Table 10 for the initial values) and the DTP AVDD 10 0000 0000 Normal operation AD9212 inverts the bit stream with relation to the ITU standard. Table 10. PN Sequence Additional and custom test patterns can also be observed when Initial First Three Output Samples commanded from the SPI port. Consult the Memory Map section Sequence Value (MSB First) for information about the options available. PN Sequence Short 0x0df 0xdf9, 0x353, 0x301 PN Sequence Long 0x29b80a 0x591, 0xfd7, 0xa3 Rev. E | Page 28 of 56 Data Sheet AD9212 CSB Pin VIN + x The CSB pin should be tied to AVDD for applications that do VIN – x REFT not require SPI mode operation. By tying CSB high, all SCLK 0.1µF and SDIO information is ignored. This pin is both 1.8 V and ADC + 0.1µF 4.7µF CORE 3.3 V tolerant. REFB RBIAS Pin 0.1µF VREF To set the internal core bias current of the ADC, place a resistor 1µF 0.1µF 0.5V that is nominally equal to 10.0 kΩ between the RBIAS pin and SELECT LOGIC ground. The resistor current is derived on chip and sets the SENSE AVDD current of the ADC to a nominal 390 mA at 65 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Voltage Reference A stable, accurate 0.5 V voltage reference is built into the Figure 63. Internal Reference Configuration AD9212. This is gained up internally by a factor of 2, setting VIN + x VREF to 1.0 V, which results in a full-scale differential input VIN – x span of 2 V p-p. VREF is set internally by default; however, the REFT VREF pin can be driven externally with a 1.0 V reference to 0.1µF + ADC improve accuracy. 0.1µF 4.7µF CORE REFB When applying the decoupling capacitors to the VREF, REFT, EXTERNAL REFERENCE and REFB pins, use ceramic low-ESR capacitors. These capacitors 0.1µF VREF should be close to the ADC pins and on the same layer of the 1 1 1µF 0.1µF 0.5V PCB as the AD9212. The recommended capacitor values and SELECT AVDD LOGIC configurations for the AD9212 reference pin are shown in SENSE Figure 63. Table 13. Reference Settings Resulting Selected SENSE Resulting Differential Mode Voltage VREF (V) Span (V p-p) 1 OPTIONAL. External AVDD N/A 2 × external Figure 64. External Reference Operation Reference reference 5 Internal, AGND to 0.2 V 1.0 2.0 2 V p-p FSR 0 –5 Internal Reference Operation A comparator within the AD9212 detects the potential at the –10 SENSE pin and configures the reference. If SENSE is grounded, –15 the reference amplifier switch is connected to the internal resistor divider (see Figure 63), setting VREF to 1 V. –20 The REFT and REFB pins establish their input span of the ADC –25 core from the reference configuration. The analog input full- scale range of the ADC equals twice the voltage at the reference –30 pin for either an internal or an external reference configuration. 01 0.5.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) If the reference of the AD9212 is used to drive multiple Figure 65. VREF Accuracy vs. Load converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. Figure 65 depicts how the internal reference voltage is affected by loading. Rev. E | Page 29 of 56 VREF ERROR (%) 05968-087 05968-032 05968-031 AD9212 Data Sheet 0.02 External Reference Operation 0 The use of an external reference may be necessary to enhance –0.02 the gain accuracy of the ADC or to improve thermal drift charac- teristics. Figure 66 shows the typical drift characteristics of the –0.04 internal reference in 1 V mode. –0.06 When the SENSE pin is tied to AVDD, the internal reference is –0.08 disabled, allowing the use of an external reference. The external –0.10 reference is loaded with an equivalent 6 kΩ load. An internal –0.12 reference buffer generates the positive and negative full-scale –0.14 references, REFT and REFB, for the ADC core. Therefore, the –0.16 external reference must be limited to a nominal voltage of 1.0 V. –0.18 –40 –20 0 2040 6080 TEMPERATURE (°C) Figure 66. Typical VREF Drift Rev. E | Page 30 of 56 VREF ERROR (%) 05968-088 Data Sheet AD9212 SERIAL PORT INTERFACE (SPI) Regardless of the mode, if CSB is taken high in the middle of a The AD9212 serial port interface allows the user to configure byte transfer, the SPI state machine is reset and the device waits the converter for specific functions or operations through a for a new instruction. structured register space provided inside the ADC. This may provide the user with additional flexibility and customization, In addition to the operation modes, the SPI port configuration depending on the application. Addresses are accessed via the influences how the AD9212 operates. For applications that do serial port and can be written to or read from via the port. Memory not require a control port, the CSB line can be tied and held high. is organized into bytes that can be further divided into fields, as This places the remainder of the SPI pins into their secondary documented in the Memory Map section. Detailed operational modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin information can be found in the AN-877 Application Note, sections. CSB can also be tied low to enable 2-wire mode. When Interfacing to High Speed ADCs via SPI. CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during Three pins define the SPI: the SCLK, SDIO, and CSB pins (see power-up, the user should ensure that the serial port remains Table 14). The SCLK pin is used to synchronize the read and write synchronized with the CSB line when using this mode. When data presented to the ADC. The SDIO pin is a dual-purpose pin operating in 2-wire mode, it is recommended that a 1-, 2-, or 3- that allows data to be sent to and read from the internal ADC byte transfer be used exclusively. Without an active CSB line, memory map registers. The CSB pin is an active low control streaming mode can be entered but not exited. that enables or disables the read and write cycles. In addition to word length, the instruction phase determines if Table 14. Serial Port Pins the serial frame is a read or write operation, allowing the serial Pin Function port to be used to both program the chip and read the contents SCLK Serial Clock. The serial shift clock input, which is used to of the on-chip memory. If the instruction is a readback operation, synchronize serial interface reads and writes. performing a readback causes the SDIO pin to change from an SDIO Serial Data Input/Output. A dual-purpose pin that typically input to an output at the appropriate point in the serial frame. serves as an input or output, depending on the instruction sent and the relative position in the timing frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode CSB Chip Select Bar (Active Low). This control gates the read is the default at power-up and can be changed by adjusting the and write cycles. configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to The falling edge of the CSB in conjunction with the rising edge High Speed ADCs via SPI. of the SCLK determines the start of the framing sequence. During HARDWARE INTERFACE an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 The pins described in Table 14 constitute the physical interface between the user’s programming device and the serial port of and Bit Field W1. An example of the serial timing and its the AD9212. The SCLK and CSB pins function as inputs when definitions can be found in Figure 68 and Table 15. using the SPI. The SDIO pin is bidirectional, functioning as an During normal operation, CSB is used to signal to the device input during write phases and as an output during readback. that SPI commands are to be received and processed. When If multiple SDIO pins share a common connection, care should be CSB is brought low, the device processes SCLK and SDIO to execute instructions. Normally, CSB remains low until the taken to ensure that proper VOH levels are met. Assuming the same communication cycle is complete. However, if connected to a load for each AD9212, Figure 67 shows the number of SDIO pins slow device, CSB can be brought high between bytes, allowing that can be connected together and the resulting VOH level. older microcontrollers enough time to transfer data into shift This interface is flexible enough to be controlled by either serial registers. CSB can be stalled when transferring one, two, or PROMs or PIC microcontrollers, providing the user with an three bytes of data. alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note). When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, If the user chooses not to use the SPI, these dual-function pins until CSB is taken high to end the communication cycle. This serve their secondary functions when the CSB is strapped to allows complete memory transfers without requiring additional AVDD during device power-up. See the Theory of Operation instructions. section for details on which pin-strappable functions are supported on the SPI pins. Rev. E | Page 31 of 56 AD9212 Data Sheet 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 03 10 200 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 67. SDIO Pin Loading t t t t DS HI CLK H t t S DH t LO CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 68. Serial Timing Details Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns) Description t 5 Setup time between the data and the rising edge of SCLK DS tDH 2 Hold time between the data and the rising edge of SCLK tCLK 40 Period of the clock tS 5 Setup time between CSB and SCLK t 2 Hold time between CSB and SCLK H t 16 Minimum period that SCLK should be in a logic high state HI tLO 16 Minimum period that SCLK should be in a logic low state tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 68) t 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK DIS_SDIO rising edge (not shown in Figure 68) Rev. E | Page 32 of 56 V (V) OH 05968-059 05968-033 Data Sheet AD9212 MEMORY MAP RESERVED LOCATIONS READING THE MEMORY MAP TABLE Undefined memory locations should not be written to except Each row in the memory map register table (Table 16) has eight when writing the default values suggested in this data sheet. address locations. The memory map is divided into three sections: Addresses that have values marked as 0 should be considered the chip configuration register map (Address 0x00 to Address 0x02), reserved and have 0 written to their registers during power-up. the device index and transfer register map (Address 0x04, Address 0x05, and Address 0xFF), and the ADC functions register DEFAULT VALUES map (Address 0x08 to Address 0x22). When the AD9212 comes out of a reset, critical registers are The leftmost column of the memory map indicates the register preloaded with default values. These values are indicated in address number; the default value is shown in the second right- Table 16, where an X refers to an undefined feature. most column. The Bit 7 column is the start of the default LOGIC LEVELS hexadecimal value given. For example, Address 0x09, the clock An explanation of various registers follows: “bit is set” is register, has a default value of 0x01, meaning Bit 7 = 0, Bit 6 = 0, synonymous with “bit is set to Logic 1” or “writing Logic 1 for Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or the bit.” Similarly, “clear a bit” is synonymous with “bit is set to 0000 0001 in binary. This setting is the default for the duty cycle Logic 0” or “writing Logic 0 for the bit.” stabilizer in the on condition. By writing 0 to Bit 0 of this address followed by writing 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. All registers, except Register 0x00, Register 0x04, Register 0x05, and Register 0xFF, are buffered with a master-slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. E | Page 33 of 56 AD9212 Data Sheet 1 Table 16. Memory Map Register Default Addr. (MSB) (LSB) Value Notes/ (Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments Chip Configuration Registers 00 chip_port_config 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles 1 = on reset reset 1 = on should be 0 = off 1 = on 1 = on 0 = off mirrored so (default) 0 = off 0 = off (default) that LSB- or (default) (default) MSB-first mode is set correctly regardless of shift mode. 01 chip_id 10-bit Chip ID Bits [7:0] Read Default is unique (AD9212 = 0x08), (default) only chip ID, different for each device. This is a read- only register. 02 chip_grade X Child ID [6:4] X X X X Read Child ID used to (identify device variants of Chip ID) only differentiate 000 = 65 MSPS graded devices. 001 = 40 MSPS Device Index and Transfer Registers 04 device_index_2 X X X X Data Data Data Data 0x0F Bits are set to Channel Channel Channel Channel determine which G F E on-chip device H 1 = on 1 = on 1 = on receives the next 1 = on (default) (default) (default) write command. (default) 0 = off 0 = off 0 = off 0 = off 05 device_index_1 X X Clock Clock Data Data Data Data 0x0F Bits are set to Channel Channel Channel Channel Channel Channel determine which DCO FCO D C B A on-chip device 1 = on 1 = on 1 = on 1 = on 1 = on 1 = on receives the next 0 = off 0 = off (default) (default) (default) (default) write command. (default) (default) 0 = off 0 = off 0 = off 0 = off FF device_update X X X X X X X SW 0x00 Synchronously transfer transfers data 1 = on from the master 0 = off shift register to (default) the slave. ADC Functions Registers 08 modes X X X X X Internal power-down mode 0x00 Determines 000 = chip run (default) various generic 001 = full power-down modes of chip 010 = standby operation. 011 = reset 09 clock X X X X X X X Duty 0x01 Turns the cycle internal duty stabilizer cycle stabilizer 1 = on on and off. (default) 0 = off 0D test_io User test mode Reset PN Reset 0x00 When this register Output test mode—see Table 9 in the 00 = off (default) long gen PN short is set, the test Digital Outputs and Timing section 01 = on, single alternate 1 = on gen data is placed on 0000 = off (default) 10 = on, single once 0 = off 1 = on the output pins 0001 = midscale short 11 = on, alternate once (default) 0 = off in place of 0010 = +FS short (default) normal data. 0011 = −FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) Rev. E | Page 34 of 56 Data Sheet AD9212 Default Addr. (MSB) (LSB) Value Notes/ (Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 14 output_mode X 0 = LVDS X X X Output 00 = offset binary 0x00 Configures the ANSI-644 invert (default) outputs and the (default) 1 = on 01 = twos complement format of the data. 1 = LVDS 0 = off low power, (default) (IEEE 1596.3 similar) 15 output_adjust X X Output driver X X X DCO and 0x00 Determines termination FCO LVDS or other 00 = none (default) output properties. 2× drive 01 = 200 Ω Primarily func- strength 10 = 100 Ω tions to set the 1 = on 11 = 100 Ω LVDS span and 0 = off common-mode (default) levels in place of an external resistor. 16 output_phase X X X X 0011 = output clock phase adjust 0x03 On devices that (0000 through 1010) utilize global 0000 = 0° relative to data edge clock divide, 0001 = 60° relative to data edge this register 0010 = 120° relative to data edge determines 0011 = 180° relative to data edge (default) which phase 0101 = 300° relative to data edge of the divider 0110 = 360° relative to data edge output is used 1000 = 480° relative to data edge to supply the 1001 = 540° relative to data edge output clock. 1010 = 600° relative to data edge Internal latching 1011 to 1111 = 660° relative to data edge is unaffected. 19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB. 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB. 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB. 21 serial_control LSB first X X X <10 000 = 10 bits (default, normal bit 0x00 Serial stream 1 = on MSPS, stream) control. Default 0 = off low 001 = 8 bits causes MSB first (default) encode 010 = 10 bits and the native rate 011 = 12 bits bit stream (global). mode 100 = 14 bits 1 = on 0 = off (default) 22 serial_ch_stat X X X X X X Channel Channel 0x00 Used to power output power- down individual reset down sections of a 1 = on 1 = on converter (local). 0 = off 0 = off (default) (default) 1 X = an undefined feature Rev. E | Page 35 of 56 AD9212 Data Sheet APPLICATIONS INFORMATION Exposed Paddle Thermal Heat Slug Recommendations DESIGN GUIDELINES It is required that the exposed paddle on the underside of the Before starting design and layout of the AD9212 as a system, it ADC be connected to analog ground (AGND) to achieve the is recommended that the designer become familiar with these best electrical and thermal performance of the AD9212. An guidelines, which discuss the special circuit connections and exposed continuous copper plane on the PCB should mate to layout requirements needed for certain pins. the AD9212 exposed paddle, Pin 0. The copper plane should Power and Ground Recommendations have several vias to achieve the lowest possible resistive thermal When connecting power to the AD9212, it is recommended path for heat dissipation to flow through the bottom of the PCB. that two separate 1.8 V supplies be used: one for analog (AVDD) These vias should be solder-filled or plugged. and one for digital (DRVDD). If only one supply is available, it To maximize the coverage and adhesion between the ADC and should be routed to the AVDD first and then tapped off and PCB, partition the continuous copper plane by overlaying a isolated with a ferrite bead or a filter choke preceded by silkscreen on the PCB into several uniform sections. This provides decoupling capacitors for the DRVDD. The user can employ multiple tie points between the ADC and PCB during the several different decoupling capacitors to cover both high and reflow process, whereas using one continuous plane with no low frequencies. These capacitors should be located close to the partitions guarantees only one tie point. See Figure 69 for a PCB point of entry at the PC board level and close to the parts, with layout example. For detailed information on packaging and the minimal trace lengths. PCB layout of chip scale packages, see the AN-772 Application A single PC board ground plane should be sufficient when Note, A Design and Manufacturing Guide for the Lead Frame using the AD9212. With proper decoupling and smart parti- Chip Scale Package (LFCSP). tioning of the PC board’s analog, digital, and clock sections, SILKSCREEN PARTITION PIN 1 INDICATOR optimum performance can be easily achieved. Figure 69. Typical PCB Layout Rev. E | Page 36 of 56 05968-034 Data Sheet AD9212 EVALUATION BOARD The AD9212 evaluation board provides all the support cir- board individually. Use P702 to connect a different supply for cuitry required to operate the ADC in its various modes and each section. At least one 1.8 V supply is needed for AVDD_DUT configurations. The converter can be driven differentially by using and DRVDD_DUT; however, it is recommended that separate a transformer (default) or an AD8334 driver. The ADC can also be supplies be used for both analog and digital signals and that each driven in a single-ended fashion. Separate power pins are provided supply have a current capability of 1 A. To operate the evaluation to isolate the DUT from the drive circuitry of the AD8334. Each board using the VGA option, a separate 5.0 V analog supply input configuration can be selected by changing the connections (AVDD_5 V) is needed. To operate the evaluation board using of various jumpers (see Figure 74 to Figure 78). Figure 70 shows the SPI and alternate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is needed in addition to the other supplies. the typical bench characterization setup used to evaluate the ac performance of the AD9212. It is critical that the signal sources INPUT SIGNALS used for the analog input and clock have very low phase noise When connecting the clock and analog sources to the (<1 ps rms jitter) to realize the optimum performance of the evaluation board, use clean signal generators with low phase converter. Proper filtering of the analog input signal to remove noise, such as Rohde & Schwarz SMA or HP8644 signal generators harmonics and lower the integrated or broadband noise at the or the equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial input is also necessary to achieve the specified noise performance. cable. Enter the desired frequency and amplitude from the ADC See Figure 74 to Figure 84 for the complete schematics and specifications tables. Typically, most Analog Devices, Inc., evalu- layout diagrams demonstrating the routing and grounding ation boards can accept approximately 2.8 V p-p or 13 dBm techniques that should be applied at the system level. sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, POWER SUPPLIES band-pass filter with 50 Ω terminations. Good choices of such This evaluation board has a wall-mountable switching power band-pass filters are available from TTE, Allen Avionics, and supply that provides a 6 V, 2 A maximum output. Connect the K&L Microwave, Inc. The filter should be connected directly to supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to the evaluation board if possible. 63 Hz. The other end of the supply is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, OUTPUT SIGNALS the 6 V supply is fused and conditioned before connecting to The default setup uses the Analog Devices HSC-ADC-FIFO5- three low dropout linear regulators that supply the proper bias INTZ to interface with the Analog Devices standard dual-channel to each of the various sections on the board. FIFO data capture board (HCS-ADC-EVALCZ). Two of the When operating the evaluation board in a nondefault condition, eight channels can be evaluated at the same time. For more L701 to L704 can be removed to disconnect the switching information on the channel settings and optional settings of power supply. This enables the user to bias each section of the these boards, visit www.analog.com/FIFO. WALL OUTLET 100V AC TO 240V AC 47Hz TO 63Hz 6V DC 2A MAX 5.0V 1.8V 1.8V 3.3V 3.3V –+ –+ –+ –+ –+ SWITCHING POWER SUPPLY PC RUNNING ADC ROHDE & SCHWARZ, INTERPOSER HSC-ADC-EVALCZ ANALYZER SMA, BAND-PASS XFMR BOARD FIFO DATA AND SPI 2V p-p SIGNAL FILTER INPUT CAPTURE SYNTHESIZER USER BOARD CH A TO CH H AD9212 SOFTWARE 10-BIT ROHDE & SCHWARZ, EVALUATION BOARD USB CLK SERIAL SMA, CONNECTION LVDS 2V p-p SIGNAL SYNTHESIZER SPI SPI SPI SPI Figure 70. Evaluation Board Connection Rev. E | Page 37 of 56 GND AVDD_5V GND AVDD_DUT GND DRVDD_DUT GND AVDD_3.3V GND VCC 05968-035 AD9212 Data Sheet A differential LVPECL clock can also be used to clock the DEFAULT OPERATION AND JUMPER SELECTION ADC input using the AD9515 (U401). Populate R406 and SETTINGS R407 with 0 Ω resistors, and remove R215 and R216 to The following is a list of the default and optional settings or disconnect the default clock path inputs. In addition, populate modes allowed on the AD9212 Rev. A evaluation board. C205 and C206 with a 0.1 μF capacitor, and remove C409 and  Power: Connect the switching power supply that is C410 to disconnect the default clock path outputs. The provided with the evaluation kit between a rated 100 V ac AD9515 has many pin-strappable options that are set to a to 240 V ac wall outlet at 47 Hz to 63 Hz and P701. default mode of operation. Consult the AD9515 data sheet for more information about these and other options.  AIN: The evaluation board is set up for a transformer- coupled analog input with an optimum 50 Ω impedance In addition, an on-board oscillator is available on the OSC401 match of 150 MHz of bandwidth (see Figure 71). For more and can act as the primary clock source. The setup is quick bandwidth response, the differential capacitor across the and involves installing R403 with a 0 Ω resistor and setting analog inputs can be changed or removed. The common the enable jumper (J401) to the on position. If the user wishes mode of the analog inputs is developed from the center to employ a different oscillator, two oscillator footprint options tap of the transformer or AVDD_DUT/2. are available (OSC401) to check the ADC performance. 0  PDWN: To enable the power-down feature, short J301 to –1 the on position (AVDD) for the PDWN pin. –2 –3dB CUTOFF = 186MHz –3  SCLK/DTP: To enable the digital test pattern on the digital –4 outputs of the ADC, use J304. If J304 is tied to AVDD during –5 device power-up, Test Pattern 10 0000 0000 is enabled. See the –6 –7 SCLK/DTP Pin section for details. –8  SDIO/ODM: To enable the low power, reduced signal option –9 (similar to the IEEE 1595.3 reduced range link LVDS output –10 –11 standard), use J303. If J303 is tied to AVDD during device –12 power-up, it enables the LVDS outputs in a low power, –13 reduced signal option from the default ANSI-644 standard. –14 0 50 100 150 200 250 300 350 400 450 500 This option changes the signal swing from 350 mV p-p to FREQUENCY (MHz) 200 mV p-p, reducing the power of the DRVDD supply. See Figure 71. Evaluation Board Full-Power Bandwidth the SDIO/ODM Pin section for more details.  VREF: VREF is set to 1.0 V by tying the SENSE pin to  CSB: To enable processing of the SPI information on the ground, R317. This causes the ADC to operate in 2.0 V p-p SDIO and SCLK pins, tie J302 low in the always enable full-scale range. A separate external reference option using mode. To ignore the SDIO and SCLK information, tie J302 the ADR510 is also included on the evaluation board. to AVDD. Populate R312 and R313, and remove C307. Proper use of  Non-SPI Mode: For users who wish to operate the DUT the VREF options is noted in the Voltage Reference without using the SPI, simply remove Jumpers J302, J303, section. and J304. This disconnects the CSB, SCLK/DTP, and  RBIAS: RBIAS has a default setting of 10 kΩ (R301) to SDIO/ODM pins from the control bus, allowing the DUT ground and is used to set the ADC core bias current. to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level.  Clock: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth  D + x, D − x: If an alternative data capture method to the 1:1 impedance ratio transformer (T401) that adds a very setup shown in Figure 74 is used, optional receiver low amount of jitter to the clock path. The clock input is terminations, R318 and R320 to R328, can be installed next 50 Ω terminated and ac-coupled to handle single-ended to the high speed backplane connector. sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. Rev. E | Page 38 of 56 AMPLITUDE (dBFS) 05968-086 Data Sheet AD9212 In this example, a 16 MHz, two-pole low-pass filter was applied ALTERNATIVE ANALOG INPUT DRIVE to the AD8334 outputs. The following components need to be CONFIGURATION removed and/or changed: The following is a brief description of the alternative analog  Remove L507, L508, L511, L512, L515, L516, L519, L520, input drive configuration using the AD8334 dual VGA. If this L607, L608, L611, L612, L615, L616, L619, and L620 on the drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 17. AD8334 analog outputs. For more details on the AD8334 dual VGA, including how it works  Populate L507, L508, L511, L512, L515, L516, L519, L520, and its optional pin settings, consult the AD8334 data sheet. L607, L608, L611, L612, L615, L616, L619, and L620 with To configure the analog input to drive the VGA instead of the 680 nH inductors. default transformer option, the following components need to  Populate C543, C547, C551, C555, C643, C647, C651, and be removed and/or changed. C655 with a 68 pF capacitor.  Remove R102, R115, R128, R141, R161, R162, R163, R164, 680nH 68pF R202, R208, R218, R225, R234, R241, R252, R259, T101, 680nH T102, T103, T104, T201, T202, T203, and T204 in the Figure 72. Example Filter Configured for 16 MHz, Two-Pole Low-Pass Filter default analog input path. 0  Populate R101, R114, R127, R140, R201, R217, R233, and f =65MSPS SAMPLE R251 with 0 Ω resistors in the analog input path. AIN = 3.5MHz –20 AD8334 = MAX GAIN SETTING  Populate R152, R153, R154, R155, R156, R157, R158, R159, R215, R216, R229, R230, R247, R248, R263, R264, C103, –40 C105, C110, C112, C117, C119, C124, C126, C203, C205, C210, C212, C217, C219, C224, and C226 with 10 kΩ –60 resistors to provide an input common-mode level to the ADC analog inputs. –80  Populate R105, R113, R118, R124, R131, R137, R151, R160, –100 R205, R213, R221, R222, R237, R238, R255, and R256 with 0 Ω resistors in the ADC analog input path to connect the –120 VGA outputs. 05 2.5.07.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz)  Remove R515, R520, R527, R532, R615, R620, R627, and Figure 73. AD9212 FFT Example Results Using R632 on the AD8334 analog outputs. 16 MHz, Two-Pole Low-Pass Filter Applied to the AD8334 Outputs (Analog Input Signal = −1.03 dBFS, SNR = 56.75 dBc, SFDR = 64.4 dBc)  Remove R512, R524, R612, and R624 to set the AD8334 mode and AD8334 HILO pin low. Some applications may require this to be different. Consult the AD8334 data sheet for more information on these functions. In this configuration, L505 to L520 and L605 to L620 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev. E | Page 39 of 56 AMPLITUDE (dBFS) 05968-091 05968-092 AD9212 Data Sheet Figure 74. Evaluation Board Schematic, DUT Analog Inputs Rev. E | Page 40 of 56 AVDD_DUT AVDD_DUT DNP P106 P102 DNP VGA Input R152 VGA Input Connection Ain Ain R105 Connection R131 DNP R154 INH1 0Ω−DNP 0Ω−DNP INH3 DNP R104 CH_A FB102 C101 R108 C115 R130 CH_C 0Ω FB108 R134 10Ω 33Ω 0.1µF 0.1µF T101 1 6 0Ω T103 10Ω 33Ω VIN_A 1 6 R101 VIN_C R127 Channel A R106 0Ω−DNP R132 2 5 Channel C DNP 0Ω−DNP CM1 CM1 R161 C104 R109 2 5 DNP P101 C102 CM3 CM3 C117 P105 R163 C118 0.1µF 499Ω 2.2pF 1kΩ R135 3 4 R110 499Ω DNP Ain R107 C103 34 2.2pF 1kΩ 33Ω Ain R133 FB101 R113 DNP DNP FB107 R137 DNP 10Ω CH_A VIN_A 10Ω C116 CH_C VIN_C R102 0Ω−DNP FB103 R103 FB109 CM1 64.9Ω 10Ω 0.1µF 0Ω−DNP R128 R129 R136 0Ω C105 10Ω CM3 64.9Ω 0Ω 33Ω C119 DNP R156 1 DNP R158 DNP E101 1 DNP E103 C106 C120 DNP AVDD_DUT AVDD_DUT DNP R138 R111 AVDD_DUT 1kΩ R139 C121 AVDD_DUT 1kΩ C107 1kΩ 0.1µF R112 0.1µF 1kΩ VGA Input AVDD_DUT VGA Input AVDD_DUT Connection Connection INH2 INH4 R153 R155 R118 DNP R151 R114 DNP R140 Channel B 0Ω−DNP 0Ω−DNP 0Ω−DNP Channel D C122 0Ω−DNP FB104 C108 CH_B FB105 R121 FB111 R146 P103 P107 FB110 CH_D 0.1µF 10Ω 10Ω 33Ω 0.1µF T102 10Ω T104 10Ω 33Ω 1 6 1 6 Ain VIN_B Ain VIN_D DNP R144 R119 DNP 2 5 25 R162 P104 CM2 CM2 DNP CM4 CM4 DNP R164 C109 R123 P108 C125 R148 R115 C111 R141 C124 499Ω 499Ω 1kΩ 1kΩ 0.1µF 34 2.2pF 34 DNP 2.2pF 64.9Ω R122 64.9Ω Ain Ain R120 C110 R145 33Ω R116 R124 DNP DNP R160 DNP R143 CH_B VIN_B C123 CH_D VIN_D 0Ω FB106 0Ω FB112 0Ω−DNP 0.1µF 0Ω−DNP CM4 R142 R147 10Ω 10Ω R117 CM2 33Ω C112 0Ω C126 R159 0Ω R157 1 DNP DNP E104 DNP 1 DNP E102 C127 AVDD_DUT DNP C113 R149 AVDD_DUT DNP 1kΩ C128 R125 AVDD_DUT R150 0.1µF AVDD_DUT 1KΩ 1kΩ C114 R126 0.1µF 1kΩ DNP: DO NOT POPULATE. 05968-072 Data Sheet AD9212 Figure 75. Evaluation Board Schematic, DUT Analog Inputs (Continued) Rev. E | Page 41 of 56 AVDD_DUT AVDD_DUT DNP DNP P202 VGA Input VGA Input P206 R205 Connection Connection Ain R216 R237 R248 0Ω−DNP INH5 C201 INH7 Ain FB202 DNP C215 0Ω−DNP DNP R204 R209 0.1µF CH_E R236 R242 CH_G FB208 0Ω 10Ω 33Ω 0.1µF T201 0Ω 33Ω 1 6 T203 10Ω Channel E VIN_E 1 6 VIN_G Channel G R233 R201 25 R206 R239 CM5 0Ω−DNP 25 P201 0Ω−DNP CM5 C203 C204 R214 DNP R208 CM7 CM7 P205 DNP C217 R246 R210 R241 C218 34 1kΩ 499Ω DNP 2.2pF Ain DNP 1kΩ R207 33Ω 34 499Ω 2.2pF Ain FB201 R240 DNP CH_E FB207 DNP C202 VIN_E 10Ω FB203 C216 CH_G VIN_G R202 R203 R213 R234 0.1µF R238 FB209 R235 10Ω 0.1µF R245 64.9Ω 0Ω 0Ω−DNP C205 CM5 64.9kΩ CM7 10Ω 0Ω 0Ω−DNP 33Ω C219 DNP R215 1 DNP R247 E201 1 DNP E203 DNP R211 C206 C220 AVDD_DUT DNP AVDD_DUT DNP R249 C221 1kΩ AVDD_DUT C207 AVDD_DUT 1kΩ R212 0.1µF R250 1kΩ 0.1µF 1kΩ VGA Input VGA Input AVDD_DUT AVDD_DUT Connection Connection INH6 INH8 R230 Channel F R221 R255 R264 R251 R217 DNP Channel H C208 0Ω−DNP C222 DNP 0Ω−DNP FB204 FB205 R226 R260 0Ω−DNP 0Ω−DNP FB210 FB211 0.1µF 0.1µF P203 CH_F P207 CH_H 33Ω 10Ω 10Ω 10Ω 10Ω 33Ω 1 T202 6 T204 Ain 1 6 Ain VIN_F VIN_H DNP DNP R257 R220 R223 25 R254 25 CM6 R259 P204 CM6 R225 P208 CM8 CM8 DNP 0Ω DNP C210 C211 R228 R252 C224 C225 R262 R218 0Ω 499Ω 499Ω 34 2.2pF 1kΩ 64.9Ω 34 2.2pF 1kΩ DNP DNP 64.9Ω R258 Ain R224 Ain DNP DNP CH_F VIN_F CH_H VIN_H C209 C223 FB206 R222 R256 FB212 0.1µF 0.1µF CM8 R261 R219 R227 R253 10Ω 0Ω−DNP 0Ω−DNP 10Ω 0Ω 33Ω C212 0Ω 33Ω C226 R229 CM6 1 R263 DNP E204 DNP DNP 1 DNP E202 C227 AVDD_DUT DNP C213 R265 C228 AVDD_DUT DNP 1kΩ R231 AVDD_DUT C214 AVDD_DUT 0.1µF 1kΩ R266 1kΩ 0.1µF R232 1kΩ DNP: DO NOT POPULATE. 10Ω 05968-073 AD9212 Data Sheet 2 2 2 2 R307 10kΩ R306 AVDD_DUT 100kΩ R302 R305 DNP 100kΩ CW 49 VIN_C VIN+C 32 D+B CHB 50 VIN_C VIN−C 31 D−B CHB 51 AVDD AVDD_DUT 30 D+C CHC 52 VIN_D VIN−D 29 D−C CHC R301 53 GND VIN_D VIN+D 10kΩ 28 D+D CHD 54 RBIAS 27 D−D CHD 55 SENSE VSENSE_DUT 26 FCO+ FCO 56 VREF_DUT VREF 25 FCO− FCO 57 REFB 24 DCO DCO+ 58 REFT 23 DCO− DCO 59 AVDD_DUT AVDD 22 D+E CHE 60 VIN_E VIN+E 21 CHE D−E 61 VIN_E VIN−E 20 D+F CHF 62 AVDD_DUT AVDD 19 D−F CHF 63 VIN−F VIN_F 18 D+G CHG 64 VIN_F VIN+F 17 D−G CHG 0 SLUG Figure 76. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface Rev. E | Page 42 of 56 C301 Reference 0.1µF Decoupling C303 C304 4.7µF 0.1µF C302 0.1µF Digital Outputs P301 GNDCD10 60 DCO DCO 40 C10 D10 50 GNDCD9 R318 59 DNP FCO D9 FCO 39 C9 49 GNDCD8 R320 58 DNP D8 CHA CHA 38 C8 48 GNDCD7 R321 57 DNP AVDD_DUT CHB CHB 1 48 37 C7 D7 47 GNDCD6 R322 AVDD_DUT AVDD AVDD_DUT AVDD 56 R318,R320−R328 DNP D6 CHC 2 47 CHC Optional Output 36 C6 46 VIN_G VIN+G VIN+B VIN_B GNDCD5 R323 Terminations 55 DNP 3 46 CHD D5 CHD 35 C5 VIN_G VIN−G VIN−B VIN_B 45 GNDCD4 R324 R303 R304 54 DNP 4 45 100kΩ DNP AVDD_DUT AVDD AVDD AVDD_DUT CHE CHE 34 C4 44 D4 GNDCD3 R325 53 5 44 DNP VIN_H VIN−H VIN−A VIN_A CHF CHF 33 C3 43 D3 GNDCD2 R326 J301 1 52 6 43 3 VIN_H VIN+H VIN+A VIN_A PDWN ENABLE DNP CHG CHG 42 32 C2 D2 GNDCD1 R327 7 42 51 AVDD_DUT AVDD AVDD AVDD_DUT DNP CSB_DUT CHH CHH C1 41 J302 31 D1 GNDAB10 R328 1 8 41 3 AD9212BCPZ-65 ALWAYS ENABLE SPI AVDD_DUT AVDD PDWN 30 DNP B10 A10 20 10 9 40 GNDAB9 CLK CLK− CSB 29 SDIO_ODM R319 B9 9 A9 19 10 U301 39 J303 GNDAB8 1 CLK CLK+ SDIO/ODM 3 ODM Enable 28 B8 1kΩ 11 38 8 A8 18 AVDD_DUT AVDD SCLK/DTP GNDAB7 27 SCLK_DTP B7 12 37 J304 17 1 7 A7 AVDD_DUT AVDD AVDD AVDD_DUT 3 GNDAB6 DTP Enable 26 13 36 B6 GND DRGND DRGND GND 6 A6 16 GNDAB5 25 14 35 B5 SCLK_CHB SCLK_CHA DRVDD_DUT DRVDD DRVDD DRVDD_DUT 5 A5 15 GNDAB4 24 15 34 B4 CHH D−H D+A CHA SDI_CHB SDI_CHA 4 A4 14 GNDAB3 16 33 23 CHH D+H D−A CHA B3 CSB3_CHB CSB1_CHA 13 3 A3 GNDAB2 22 B2 CSB4_CHB CSB2_CHA 2 A2 12 GNDAB1 21 SDO_CHB B1 SDO_CHA 1 A1 11 NC AVDD_DUT OPTIONAL Reference Circuitry EXT REF R309 Vref Select VSENSE_DUT 4.99kΩ VREF_DUT U302 R311 R314 DNP DNP V = 0.5V ADR510ARTZ REF TRIM/NC VOUT 1.0V R315 R312 DNP V = External REF DNP C306 C307 R31 C305 R310 0.1µF R308 1µF DNP 0.1µF V = 0.5V(1 + R219/R220) REF 10kΩ 470kΩ R313 R317 DNP 0Ω V = 1V REF Remove C214 when DNP: DO NOT POPULATE. using external Vref 05968-074 Data Sheet AD9212 25 S0 16 S1 15 S2 14 S3 33 13 S4 12 S5 31 11 GND S6 10 S7 1 9 VS S8 8 S9 32 7 RSET S10 6 VREF Figure 77. Evaluation Board Schematic, Clock Circuitry Rev. E | Page 43 of 56 AVDD_3.3V OPTIONAL CLOCK DRIVE CIRCUIT R401 C401 10kΩ 0.1µF AVDD_3.3V 3 AVDD_3.3V ENABLE OSC401 R414 4.12kΩ AVDD_3.3V 2 Optional Clock J401 R408 R409 R410 DNP Oscillator DNP DNP 10kΩ 0.1µF OSC401 DISABLE OSC401 C405 14 1 VCC OE OPT_CLK 1 U401 CLK R425 12 3 R424 VCC OE DNP GND_PAD AVDD_3.3V R406 2 23 R422 LVPECL OUTPUT 0Ω 0Ω 0.1µF AD9515 Pin−strap settings 10 5 R402 0Ω CLK OUT0 100Ω OUT GND R411 C406 DNP 10kΩ DNP 49.9Ω 3 22 8 7 CLKB OUT0B CLK S0 DNP AD9515BCPZ OUT GND R427 R426 R436 R437 OPT_CLK AVDD_3.3V AVDD_3.3V CRYSTAL_3 R420 R421 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 0Ω 0Ω 0Ω 0Ω Encode 240Ω 240Ω DNP DNP 5 19 R403 R407 SYNCB OUT1 Input 0Ω SIGNAL=DNC;27,28 0Ω R412 R413 S1 S6 DNP 18 OPT_CLK R429 DNP 10kΩ R428 R438 R439 DNP OUT1B P401 AVDD_3.3V AVDD_3.3V 0Ω 0Ω 0Ω 0Ω DNP DNP Enc C407 R423 0.1µF C402 100Ω LVDS OUTPUT 0.1µF S2 S7 DNP R404 R430 R431 R440 R441 1 49.9Ω AVDD_3.3V E401 AVDD_3.3V 0Ω 0Ω 0Ω 0Ω Clock Circuit S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 DNP DNP C408 R446 0.1µF R417 CLK DNP S3 S8 OPT_CLK DNP DNP 0Ω R415 R432 R433 R442 R443 T401 P402 0.1µF AVDD_3.3V AVDD_3.3V 3 4 CR401 C409 0Ω 0Ω 0Ω 0Ω Enc DNP DNP 0Ω HSMS-2812-TR1G 2 5 CLIP SINE OUT (DEFAULT) C403 R416 S4 S9 0.1µF C410 R405 R435 R434 R444 R445 1 6 0.1µF 0Ω 0Ω R418 AVDD_3.3V AVDD_3.3V C411 0Ω 0Ω 0Ω 0Ω 0Ω CLK DNP DNP 0.1µF S5 S10 AVDD_3.3V C412 C413 C414 C415 C416 C417 C418 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF DNP: DO NOT POPULATE. 2 3 1 05968-075 AD9212 Data Sheet R524 R523 10kΩ 10kΩ R513 187Ω C512 C511 10µF 0.1µF C533 C534 C535 C536 10µF 0.1µF 10µF 0.1µF C510 C509 10µF 0.1µF R512 R511 49 32 10kΩ 10kΩ VCM2 NC 50 31 VCM1 VCM3 R504 10kΩ 51 30 R505 AVDD_5V EN34 VCM4 10kΩ 52 29 EN12 HILO 53 28 CLMP12 CLMP34 54 27 VG12 GAIN12 GAIN34 VG34 55 26 AVDD_5V VPS1 VPS4 AVDD_5V 56 25 VIN1 VIN4 57 24 VIP1 VIP4 58 23 LOP1 LOP4 59 22 LON1 LON4 60 21 COM1X COM4X 61 20 LMD1 LMD4 R509 274Ω 62 19 INH1 INH4 C505 0.1µF 63 18 COM1 COM4 64 17 COM2 COM3 C527 0.018µF C526 22pF L504 120nH 0.1µF C525 R503 274Ω R508 R507 274Ω 274Ω C502 0.018µF C521 C515 0.018µF 0.018µF C503 22pF L501 C520 120nH 22pF C514 22pF 0.1µF L503 C501 L502 120nH 120nH 0.1µF 0.1µF C519 C513 AVDD_5V AVDD_5V CW CW GND GND VG34 VG12 Variable Gain Circuit Variable Gain Circuit (0−1.0V DC) (0−1.0V DC) VG34 VG12 External External Variable Gain Drive Variable Gain Drive Figure 78. Evaluation Board Schematic, Optional DUT Analog Input Drive Rev. E | Page 44 of 56 Populate L505−L520 with 0Ω resistors or design your own filter. EXT VG Power Down Enable (0−1V=Disable Power) JP501 CH_D CH_D CH_C CH_C CH_B CH_B CH_A CH_A 12 DNP AVDD_5V 10kΩ R506 C507 C508 0.1µF 1000pF R517 R522 R529 R534 Rclamp Pin DNP DNP DNP DNP HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV R501 10kΩ C543 C551 C547 C555 DNP DNP DNP DNP L507 L508 L511 L512 L515 L516 L519 L520 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω R502 39kΩ C542 C546 C550 C554 DNP DNP DNP DNP L505 L506 L509 L510 L513 L514 L517 L518 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω C506 INH4 R516 R521 R528 R533 0.1µF DNP DNP DNP DNP C504 0.1µF U501 C540 C541 C544 C545 C548 C549 C552 C553 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF R515 R527 R532 R520 374Ω 374Ω 374Ω 374Ω 1 48 R514 R518 R519 R525 R526 R530 R531 INH3 INH2 COM12 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 2 47 LMD2 VOH1 AVDD_5V C537 0.1µF 3 46 COM2X VOL1 4 45 LON2 VPS12 AVDD_5V C518 5 44 LOP2 VOL2 C538 0.1µF 0.1µF 6 43 VIP2 VOH2 7 42 VIN2 COM12 8 41 AVDD_5V VPS2 MODE AD8334ACPZ-REEL 9 40 MODE Pin AVDD_5V VPS3 NC Positive Gain Slope = 0−1.0V 10 39 Negitive Gain Slope = 2.25−5.0V VIN3 COM34 11 38 VIP3 VOH3 0.1µF C522 C523 12 37 LOP3 VOL3 0.1µF 36 13 LON3 VPS34 AVDD_5V 14 35 COM3X VOL4 15 34 LMD3 VOH4 C524 16 33 0.1µF INH3 COM34 INH2 EXT VG JP502 1 2 C529 C528 0.1µF 0.1µF R535 10kΩ AVDD_5V INH1 C530 0.1µF R536 39kΩ Rclamp Pin HILO Pin=LO=+/− 50mV C531 HILO Pin=H=+/− 75mV DNP 1000pF C532 10kΩ 0.1µF R510 DNP: DO NOT POPULATE. 05968-076 Data Sheet AD9212 R613 187Ω C612 C611 10µF 0.1µF C633 C634 C635 C636 10µF 0.1µF 10µF 0.1µF C610 C609 10µF 0.1µF VCM2 NC 49 32 VCM1 VCM3 50 31 R604 10kΩ R605 AVDD_5V EN34 VCM4 R612 R611 10kΩ 10kΩ 10kΩ 51 30 EN12 HILO 52 29 CLMP12 CLMP34 53 28 VG56 GAIN12 GAIN34 VG78 54 27 AVDD_5V VPS1 VPS4 AVDD_5V 55 26 VIN1 VIN4 56 25 VIP1 VIP4 57 24 LOP1 LOP4 58 23 LON1 LON4 59 22 COM1X COM4X 60 21 LMD1 LMD4 61 20 R609 274Ω INH1 INH4 C605 62 19 0.1µF COM1 COM4 63 18 COM2 COM3 64 17 C627 0.018µF C626 22pF L604 120nH 0.1µF C625 R603 274Ω R608 R607 274Ω 274Ω C602 0.018µF C621 C615 0.018µF 0.018µF C603 22pF L601 C620 120nH 22pF C614 22pF 0.1µF C601 L603 L602 120nH 120nH 0.1µF 0.1µF C619 C613 AVDD_5V AVDD_5V CW CW GND GND VG78 VG56 Variable Gain Circuit (0−1.0V DC) Variable Gain Circuit (0−1.0V DC) VG78 VG56 External Variable Gain Drive External Variable Gain Drive Figure 79. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued) Rev. E | Page 45 of 56 MODE Pin Populate L605−L620 with 0Ω Positive Gain Slope = 0−1.0V resistors or design your own filter. EXT VG Power Down Enable Negative Gain Slope = 2.25−5.0V (0−1V=Disable Power) JP601 CH_H CH_H CH_G CH_G CH_F CH_F CH_E CH_E 12 AVDD_5V C607 DNP 1000pF C608 10kΩ 0.1µF R606 R617 R622 R629 R636 DNP DNP DNP DNP Rclamp Pin HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV R601 10kΩ C643 C651 C647 C655 DNP DNP DNP DNP L607 L608 L611 L612 L615 L616 L619 L620 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω R602 39kΩ C642 C646 C650 C654 DNP DNP DNP DNP L605 L606 L609 L610 L613 L614 L617 L618 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω C606 INH8 R616 R621 R628 R633 0.1µF DNP DNP DNP DNP C604 0.1µF U601 C648 C653 C640 C641 C644 C645 C649 C652 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF R620 R627 R632 R615 374Ω 374Ω 374Ω 374Ω 1 48 R618 R619 R625 R626 R630 R631 R614 INH7 INH2 COM12 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 2 47 LMD2 VOH1 AVDD_5V C616 3 46 0.1µF COM2X VOL1 4 45 LON2 VPS12 AVDD_5V R624 5 44 10kΩ C618 LOP2 VOL2 C617 0.1µF 6 43 0.1µF VIP2 VOH2 7 42 VIN2 COM12 R623 8 41 AVDD_5V VPS2 MODE 10kΩ AD8334ACPZ-REEL 9 40 AVDD_5V VPS3 NC 10 39 VIN3 COM34 11 38 VIP3 VOH3 0.1µF C622 C623 12 37 LOP3 VOL3 0.1µF 13 36 LON3 VPS34 AVDD_5V 14 35 COM3X VOL4 15 34 LMD3 VOH4 C624 0.1µF 16 33 INH3 COM34 INH6 EXT VG JP602 12 C629 0.1µF C628 0.1µF R634 10kΩ AVDD_5V INH5 C630 0.1µF R635 39kΩ Rclamp Pin HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV DNP C631 C632 10kΩ 1000pF 0.1µF R610 DNP: DO NOT POPULATE. 05968-077 AD9212 Data Sheet CR702 GREEN C702 C703 0.1µF 0.1µF GND GND 1 1 R709 0Ω SDO_CHA R708 0Ω SDI_CHA R707 0Ω SCLK_CHA R706 0Ω CSB1_CHA PICVCC 1 2 PICVCC GP1 3 4 GP1 GP0 5 6 GP0 MCLR/GP3 7 8 MCLR/GP3 9 10 GND GND CR701 2 OPTIONAL GREEN Figure 80. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry Rev. E | Page 46 of 56 SPI CIRCUITRY FROM FIFO Power Supply Input +5V = PROGRAMMING = AVDD_5V 6V, 2A max +3.3V = NORMAL OPERATION = AVDD_3.3V REMOVE WHEN USING OR PROGRAMMING PIC (U402) F701 D702 AVDD_3.3V AVDD_5V FER701 PWR_IN 2 1 P701 NANOSMDC110F-2 SK33-TP J701 43 1 1 3 C704 D701 AVDD_3.3V 10µF C701 2 S2A-TP 3 7.5V POWER 0.1µF CON005 U701 2.5MM JACK R710 1 8 1kΩ VDD VSS R716 R703 R701 2 7 261Ω GP5 GP0 4.7kΩ R704 S701 0Ω−DNP 3 6 GP4 GP1 1 3 R705 0Ω−DNP 4 5 MCLR/GP3 GP2 2 4 0Ω−DNP PIC12F629-I/SNG Optional Power RESET/ REPROGRAM R702 Input 261Ω P702 L703 DNP 10µH SDIO_ODM 3.3V_AVDD 1 AVDD_3.3V +3.3V P1 2 P2 C709 C710 10µF 0.1µF 3 5V_AVDD P3 R712 AVDD_DUT 4 1kΩ P4 NC7WZ07P6X_NL R713 DUT_AVDD 1kΩ 5 A1 Y1 1 6 P5 L701 10µH E701 6 2 5 P6 1 AVDD_5V +5.0V GND VCC AVDD_DUT R711 7 DUT_DRVDD 10kΩ 34 A2 Y2 P7 C705 C706 8 10µF 0.1µF P8 U702 PIC PROGRAMMING HEADER ISP J702 L702 10µH AVDD_DUT +1.8V C707 Decoupling Capacitors 10µF C708 NC7WZ16P6X_NL 0.1µF 1 A1 Y1 6 SCLK_DTP 2 5 AVDD_5V GND VCC AVDD_DUT 3 A2 Y2 L704 4 C723 C724 C725 C726 C727 CSB_DUT 0.1µF 0.1µF 0.1µF 0.1µF 10µH 0.1µF DRVDD_DUT +1.8V U703 C711 C712 R715 R714 0.1µF 10kΩ 10µF 10kΩ AVDD_DUT C733 C731 C732 C734 C735 C730 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF AVDD_5V U707 U705 L707 C749 C750 C751 C752 C753 L705 ADP3339AKCZ−1.8-RL ADP3339AKCZ−3.3-RL 10µH 0.1µF 0.1µF 0.1µF 10µH 0.1µF 0.1µF 2 3 3 2 PWR_IN IN OUT DUT_AVDD PWR_IN IN OUT 3.3V_AVDD 4 4 OUT OUT AVDD_DUT C714 C715 C719 C720 1µF 1µF 1µF 1µF C745 C746 C747 C748 C744 0.1µF 0.1µF 0.1µF 0.1µF 1 0.1µF U704 U706 L706 L708 ADP3339AKCZ−1.8-RL ADP3339AKCZ−5-RL7 10µH 10µH AVDD_3.3V 3 2 3 2 DRVDD_DUT PWR_IN OUT DUT_DRVDD PWR_IN OUT 5V_AVDD IN IN 4 4 OUT OUT C742 C743 C740 C741 0.1µF 0.1µF 0.1µF 0.1µF C716 C717 C721 C722 1µF 1µF 1µF 1µF 1 DNP: DO NOT POPULATE. 05968-078 Data Sheet AD9212 Figure 81. Evaluation Board Layout, Primary Side Rev. E | Page 47 of 56 05968-079 AD9212 Data Sheet Figure 82. Evaluation Board Layout, Ground Plane Rev. E | Page 48 of 56 05968-045 Data Sheet AD9212 Figure 83. Evaluation Board Layout, Power Plane Rev. E | Page 49 of 56 05968-046 AD9212 Data Sheet Figure 84. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. E | Page 50 of 56 05968-082 Data Sheet AD9212 1 Table 17. Evaluation Board Bill of Materials (BOM) Qty per Reference Manufacturer Item Board Designator Device Package Value Manufacturer Part Number 1 1 AD9212LFCSP_REVA PCB PCB PCB Capacitor 402 Murata GRM155R71C104KA88D 2 118 C101, C102, C107, 0.1 μF, ceramic, X5R, C108, C109, C114, 10 V, 10% tol C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, C222, C223, C228, C301, C302, C304, C305, C306, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C501, C504, C505, C506, C508, C509, C511, C513, C518, C519, C522, C523, C524, C525, C528, C529, C530, C532, C534, C536, C537, C538, C601, C604, C605, C606, C608, C609, C611, C613, C616, C617, C618, C619, C622, C623, C624, C625, C628, C629, C630, C632, C634, C636, C701, C702, C703, C706, C708, C710, C712, C723, C724, C725, C726, C727, C730, C731, C732, C733, C734, C735, C740, C741, C742, C743, C744, C745, C746, C747, C748, C749, C750, C751, C752, C753 3 8 C104, C111, C118, Capacitor 402 2.2 pF, ceramic, COG, Murata GRM1555C1H2R20CZ01D C125, C204, C211, 0.25 pF tol, 50 V C218, C225 4 8 C510, C512, C533, Capacitor 805 10 μF, 6.3 V ±10%, Murata GRM219R60J106KE19D C535, C610, C612, ceramic, X5R C633, C635 5 1 C303 Capacitor 603 4.7 μF, ceramic, X5R, Murata GRM188R60J475KE19D 6.3 V, 10% tol 6 4 C507, C531, C607, Capacitor 402 1000 pF, ceramic, X7R, Murata GRM155R71H102KA01D C631 25 V, 10% tol 7 8 C502, C515, C521, Capacitor 402 0.018 μF, ceramic, X7R, AVX 0402YC183KAT2A C527, C602, C615, 16 V, 10% tol C621, C627 Rev. E | Page 51 of 56 AD9212 Data Sheet Qty per Reference Manufacturer Item Board Designator Device Package Value Manufacturer Part Number 8 8 C503, C514, C520, Capacitor 402 22 pF, ceramic, NPO, Murata GRM1555C1H220JZ01D C526, C603, C614, 5% tol, 50 V C620, C626 9 1 C704 Capacitor 1206 10 μF, tantalum, ROHM Co., Ltd. TCA1C106M8R 16 V, 20% tol 10 9 C307, C714, C715, Capacitor 603 1 μF, ceramic, X5R, Murata GRM188R61C105KA93D C716, C717, C719, 6.3 V, 10% tol C720, C721, C722 11 16 C540, C541, C544, Capacitor 805 0.1 μF, ceramic, X7R, Murata GRM21BR71H104KA01L C545, C548, C549, 50 V, 10% tol C552, C553, C640, C641, C644, C645, C648, C649, C652, C653 12 4 C705, C707, C709, Capacitor 603 10 μF, ceramic, X5R, Murata GRM188R60J106ME47D C711 6.3 V, 20% tol 13 1 CR401 Diode SOT-23 30 V, 20 mA, dual Avago HSMS-2812-TR1G Schottky Technologies 14 2 CR701, CR702 LED 603 Green, 4 V, 5 m candela Panasonic LNJ314G8TRA 15 1 D702 Diode DO- 3 A, 30 V, SMC Micro SK33-TP 214AB Commercial Co. 16 1 D701 Diode DO- 5 A, 50 V, SMC Micro S2A-TP 214AA Commercial Co. 17 1 F701 Fuse 1210 6.0 V, 2.2 A trip-current Tyco/Raychem NANOSMDC110F-2 resettable fuse 18 1 FER701 Choke coil 2020 10 μH, 5 A, 50 V, 190 Ω Murata DLW5BSN191SQ2L @ 100 MHz 19 24 FB101, FB102, Ferrite bead 603 10 Ω, test frequency Murata BLM18BA100SN1D FB103, FB104, 100 MHz, 25% tol, FB105, FB106, 500 mA FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212 20 4 JP501, JP502, Connector 2-pin 100 mil header jumper, Samtec TSW-102-07-G-S JP601, JP602 2-pin 21 6 J301, J302, J303, Connector 3-pin 100 mil header jumper, Samtec TSW-103-07-G-S J304, J401, J701 3-pin 23 1 J702 Connector 10-pin 100 mil header, male, Samtec TSW-105-08-G-D 2 × 5 double row straight 24 8 L701, L702, L703, Ferrite bead 1210 10 μH, bead core 3.2 × Murata BLM31PG500SN1L L704, L705, L706, 2.5 × 1.6 SMD, 2 A L707, L708 25 8 L501, L502, L503, Inductor 402 120 nH, test freq Murata LQG15HNR12J02D L504, L601, L602, 100 MHz, 5% tol, L603, L604 150 mA Rev. E | Page 52 of 56 Data Sheet AD9212 Qty per Reference Manufacturer Item Board Designator Device Package Value Manufacturer Part Number 26 32 L505, L506, L507, Resistor 805 0 Ω, 1/8 W, 5% tol NIC NRC04Z0TRF L508, L509, L510, Components L511, L512, L513, Corp. L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 27 1 OSC401 Oscillator SMT Clock oscillator, Valpey Fisher VFAC3-BHL-65MHz 65.00 MHz, 3.3 V, ±5% duty cycle 28 9 P101, P103, P105, Connector SMA Side-mount SMA for Johnson 142-0701-851 P107, P201, P203, 0.063" board thickness Components P205, P207, P401 29 1 P301 Connector HEADER 1469169-1, right angle Tyco 6469169-1 2-pair, 25 mm, header assembly 30 1 P701 Connector 0.1", RAPC722, power Switchcraft RAPC722X PCMT supply connector 31 21 R301, R307, R401, Resistor 402 10 kΩ, 1/16 W, 5% tol NIC NRC04J103TRF R402, R410, R413, Components R504, R505, R511, Corp. R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715 32 18 Resistor 402 0 Ω, 1/16 W, 5% tol NRC04Z0TRF R103, R117, R129, NIC R142, R203, R219, Components R235, R253, R317, Corp. R405, R415, R416, R417, R418, R706, R707, R708, R709 33 8 Resistor 402 64.9 Ω, 1/16 W, 1% tol NRC04F64R9TRF R102, R115, R128, NIC R141, R202, R218, Components R234, R252 Corp. 34 8 R104, R116, R130, Resistor 603 0 Ω, 1/10 W, 5% tol NIC NRC06Z0TRF R143, R204, R220, Components R236, R254 Corp. 35 28 R109, R111, R112, Resistor 402 1 kΩ, 1/16 W, 1% tol NIC NRC04F1001TRF R123, R125, R126, Components R135, R138, R139, Corp. R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713 36 16 R108, R110, R121, Resistor 402 33 Ω, 1/16 W, 5% tol NIC NRC04J330TRF R122, R134, R136, Components R146, R147, R209, Corp. R210, R226, R227, R242, R245, R260, R261 Rev. E | Page 53 of 56 AD9212 Data Sheet Qty per Reference Manufacturer Item Board Designator Device Package Value Manufacturer Part Number 37 8 R161, R162, R163, Resistor 402 499 Ω, 1/16 W, 1% tol NIC NRC04F4990TRF R164, R208, R225, Components R241, R259 Corp. 38 3 R303, R305, R306 Resistor 402 100 kΩ, 1/16 W, 1% tol NIC NRC04F1003TRF Components Corp. 39 1 R414 Resistor 402 4.12 kΩ, 1/16W, 1% tol NIC NRC04F4121TRF Components Corp. 40 1 R404 Resistor 402 49.9 Ω, 1/16 W, 0.5% tol Susumu RR0510R-49R9-D 41 1 R309 Resistor 402 4.99 kΩ, 1/16 W, 5% tol NIC NRC04F4991TRF Components Corp. 42 5 R310, R501, R535, Potentiometer 3-lead 10 kΩ, Cermet trimmer Copal CT94EW103 R601, R634 potentiometer, 18-turn Electronics top adjust, 10%, 1/2 W Corp. 43 1 R308 Resistor 402 470 kΩ, 1/16 W, 5% tol NIC NRC04J474TRF Components Corp. 44 4 R502, R536, R602, Resistor 402 39 kΩ, 1/16 W, 5% tol NIC NRC04J393TRF R635 Components Corp. 45 16 R513, R514, R518, Resistor 402 187 Ω, 1/16 W, 1% tol NIC NRC04F1870TRF R519, R525, R526, Components R530, R531, R613, Corp. R614, R618, R619, R625, R626, R630, R631 46 8 R515, R520, R527, Resistor 402 374 Ω, 1/16 W, 1% tol NIC NRC04F3740TRF R532, R615, R620, Components R627, R632 Corp. 47 8 R503, R507, R508, Resistor 402 274 Ω, 1/16 W, 1% tol NIC NRC04F2740TRF R509, R603, R607, Components R608, R609 Corp. 48 11 R425, R427, R429, Resistor 201 0 Ω, 1/20 W, 5% tol NIC NRC02Z0TRF R431, R433, R435, Components R436, R439, R441, Corp. R443, R445 49 1 R701 Resistor 402 4.7 kΩ, 1/16 W, 1% tol NIC NRC04J472TRF Components Corp. 50 1 R702 Resistor 402 261 Ω, 1/16 W, 1% tol NIC NRC04F2610TRF Components Corp. 51 1 R716 Resistor 603 261 Ω, 1/16 W, 1% tol NIC NRC06F261OTRF Components Corp. 52 2 R420, R421 Resistor 402 240 Ω, 1/16 W, 5% tol NIC NRC04J241TRF Components Corp. 53 2 R422, R423 Resistor 402 100 Ω, 1/16 W, 1% tol NIC NRC04F1000TRF Components Corp. 54 1 S701 Switch SMD Light Touch, Panasonic EVQPLDA15 100 GE, 5 mm Rev. E | Page 54 of 56 Data Sheet AD9212 Qty per Reference Manufacturer Item Board Designator Device Package Value Manufacturer Part Number 55 9 T101, T102, T103, Transformer CD542 ADT1-1WT+, Mini-Circuits ADT1-1WT+ T104, T201, T202, 1:1 impedance ratio T203, T204, T401 transformer 56 2 U704, U707 IC SOT-223 ADP3339AKC-1.8-RL, Analog Devices ADP3339AKCZ-1.8-RL 1.5 A, 1.8 V LDO regulator 57 2 U501, U601 IC CP-64-3 AD8334ACPZ-REEL, Analog Devices AD8334ACPZ-REEL ultralow noise precision dual VGA 58 1 U706 IC SOT-223 ADP3339AKC-5-RL7 Analog Devices ADP3339AKCZ-5-RL7 59 1 U705 IC SOT-223 ADP3339AKC-3.3-RL Analog Devices ADP3339AKCZ-3.3-RL 60 1 U301 IC CP-64-3 AD9212BCPZ-65, octal, Analog Devices AD9212BCPZ-65 10-bit, 65 MSPS serial LVDS 1.8 V ADC 61 1 U302 IC SOT-23 ADR510ARTZ, 1.0 V, Analog Devices ADR510ARTZ precision low noise shunt voltage reference 62 1 U401 IC Analog Devices AD9515BCPZ LFCSP AD9515BCPZ, 1.6 GHz CP-32-2 clock distribution IC 63 1 U702 IC SC70, NC7WZ07P6X_NL, Fairchild NC7WZ07P6X_NL MAA06A UHS dual buffer 64 1 U703 IC SC70, NC7WZ16P6X_NL, Fairchild NC7WZ16P6X_NL MAA06A UHS dual buffer 65 1 U701 IC 8-SOIC Flash prog Microchip PIC12F629-I/SNG mem 1k × 14, RAM size 64 × 8, 20 MHz speed, PIC12F controller series 1 This BOM is RoHS compliant. Rev. E | Page 55 of 56 AD9212 Data Sheet OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 64 49 1 48 PIN 1 INDICATOR 0.50 7.55 EXPOSED PAD 8.75 BSC (BOTTOM VIEW) 7.50 SQ BSC SQ 7.45 0.50 16 33 0.40 32 17 0.30 0.22 MIN TOP VIEW 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 85. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-6) Dimensions shown in millimeters ORDERING GUIDE Temperature Package 1 Model Notes Range Package Description Option AD9212ABCPZ-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9212ABCPZRL7-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7” Tape and Reel CP-64-6 AD9212ABCPZ-65 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9212ABCPZRL7-65 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7” Tape and Reel CP-64-6 2 AD9212-65EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board. ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05968-0-12/11(E) Rev. E | Page 56 of 56 02-23-2010-B