ANALOG DEVICES AD9204

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9204 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB 1.8 V analog supply operation 1.8 V to 3.3 V output supply SPI SNR ORA 61.3 dBFS at 9.7 MHz input PROGRAMMING DATA D9A 61.0 dBFS at 200 MHz input VIN+A ADC SFDR VIN–A D0A 75 dBc at 9.7 MHz input DCOA 73 dBc at 200 MHz input VREF Low power SENSE DRVDD AD9204 30 mW per channel at 20 MSPS REF VCM SELECT 63 mW per channel at 80 MSPS ORB RBIAS Differential input with 700 MHz bandwidth D9B VIN–B On-chip voltage reference and sample-and-hold circuit ADC VIN+B D0B DNL = ±0.11 LSB Serial port control options DCOB Scalable analog input: 1 V p-p to 2 V p-p differential DIVIDE DUTY CYCLE MODE Offset binary, gray code, or twos complement data format 1TO 8 STABILIZER CONTROLS Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider CLK+ CLK– SYNC DCS PDWN DFS OEB Built-in selectable digital test pattern generation Figure 1. Energy-saving power-down modes PRODUCT HIGHLIGHTS Data clock out with programmable clock and data 1. The AD9204 operates from a single 1.8 V analog power alignment supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. APPLICATIONS 2. The patented sample-and-hold circuit maintains excellent Communications performance for input frequencies up to 200 MHz and is Diversity radio systems designed for low cost, low power, and ease of use. Multimode digital receivers 3. A standard serial port interface supports various product GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA features and functions, such as data output formatting, I/Q demodulation systems internal clock divider, power-down, DCO/DATA timing Smart antenna systems and offset adjustments, and voltage reference modes. Battery-powered instruments 4. The AD9204 is packaged in a 64-lead RoHS compliant Handheld scope meters LFCSP that is pin compatible with the AD9268 16-bit Ultrasound ADC, the AD9251 and AD9258 14-bit ADCs, and the Radar/LIDAR AD9231 12-bit ADC, enabling a simple migration path PET/SPECT imaging between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. MUX OPTION CMOS CMOS OUTPUT BUFFER OUTPUT BUFFER 08122-001 AD9204 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 22 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 23 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 25 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 26 Revision History ............................................................................... 2 Timing ......................................................................................... 26 General Description ......................................................................... 3 Built-In Self-Test (BIST) and Output Test .................................. 27 Specif ica t ions ..................................................................................... 4 Built-In Self-Test (BIST) ............................................................ 27 DC Specifications ......................................................................... 4 Output Test Modes ..................................................................... 27 AC Specifications .......................................................................... 5 Channel/Chip Synchronization .................................................... 28 Digital Specifications ................................................................... 6 Serial Port Interface (SPI) .............................................................. 29 Switching Specifications .............................................................. 7 Configuration Using the SPI ..................................................... 29 Timing Specifications .................................................................. 8 Hardware Interface ..................................................................... 30 Absolute Maximum Ratings ............................................................ 9 Configuration Without the SPI ................................................ 30 Thermal Characteristics .............................................................. 9 SPI Accessible Features .............................................................. 30 ESD Caution .................................................................................. 9 Memory Map .................................................................................. 31 Pin Configuration and Function Descriptions ........................... 10 Reading the Memory Map Register Table ............................... 31 Typical Performance Characteristics ........................................... 12 Open Locations .......................................................................... 31 AD9204-80 .................................................................................. 12 Default Values ............................................................................. 31 AD9204-65 .................................................................................. 14 Memory Map Register Table ..................................................... 32 AD9204-40 .................................................................................. 15 Memory Map Register Descriptions ........................................ 34 AD9204-20 .................................................................................. 16 Applications Information .............................................................. 35 Equivalent Circuits ......................................................................... 17 Design Guidelines ...................................................................... 35 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 36 ADC Architecture ...................................................................... 19 Ordering Guide .......................................................................... 36 Analog Input Considerations .................................................... 19 REVISION HISTORY 7/09—Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD9204 GENERAL DESCRIPTION A differential clock input controls all internal conversion cycles. The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, An optional duty cycle stabilizer (DCS) compensates for wide 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter variations in the clock duty cycle while maintaining excellent (ADC). It features a high performance sample-and-hold circuit overall ADC performance. and on-chip voltage reference. The digital output data is presented in offset binary, gray code, or The product uses multistage differential pipeline architecture twos complement format. A data output clock (DCO) is provided with output error correction logic to provide 10-bit accuracy at for each ADC channel to ensure proper latch timing with receiving 80 MSPS data rates and to guarantee no missing codes over the logic. Both 1.8 V and 3.3 V CMOS levels are supported and output full operating temperature range. data can be multiplexed onto a single output bus. The ADC contains several features designed to maximize The AD9204 is available in a 64-lead RoHS compliant LFCSP flexibility and minimize system cost, such as programmable and is specified over the industrial temperature range (−40°C clock and data alignment and programmable digital test pattern to +85°C). generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. 0 | Page 3 of 36 AD9204 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. AD9204-20/AD9204-40 AD9204-65 AD9204-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.1 ±0.70 ±0.1 ±0.50 ±0.1 ±0.70 % FSR 1 Gain Error Full +1.8 +1.8 +1.8 % FSR 2 Differential Nonlinearity (DNL) Full ±0.30 ±0.30 ±0.30 LSB 25°C ±0.075 ±0.15 ±0.11 LSB 2 Integral Nonlinearity (INL) Full ±0.60 ±0.60 ±0.60 LSB 25°C ±0.15 ±0.25 ±0.25 LSB MATCHING CHARACTERISTICS Offset Error 25°C ±0.0 ±0.75 ±0.0 ±0.75 ±0.0 ±0.75 % FSR 1 Gain Error 25°C ±0.3 ±0.3 ±0.3 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.06 0.08 0.08 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p 3 Input Capacitance Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current 2 IAVDD Full 33.5/46.4 35.8/49.6 61.1 64.8 70.3 75.2 mA 2 IDRVDD (1.8 V) Full 2.6/4.4 6.5 8.0 mA 2 IDRVDD (3.3 V) Full 5.0/8.3 12.4 15.3 mA POWER CONSUMPTION DC Input Full 59.5/82.1 108 125 mW 2 Sine Wave Input (DRVDD = 1.8 V) Full 64.9/91.4 69.5/97.7 121.7 128.5 141 150 mW 2 Sine Wave Input (DRVDD = 3.3 V) Full 76.7/111 150.8 177 mW 4 Standby Power Full 37/37 37 37 mW Power-Down Power Full 2.2 2.2 2.2 mW 1 Measured with a 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input, the CLK active. Rev. 0 | Page 4 of 36 AD9204 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. AD9204-20/AD9204-40 AD9204-65 AD9204-80 1 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 61.7 61.5 61.3 dBFS IN f = 30.5 MHz 25°C 61.6 61.4 61.3 dBFS IN Full 61.0 60.5 dBFS fIN = 70 MHz 25°C 61.6 61.4 61.3 dBFS Full 60.4 dBFS fIN = 200 MHz 25°C 61.0 61.0 dBFS SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 9.7 MHz 25°C 61.5 61.2 61.1 dBFS fIN = 30.5 MHz 25°C 61.5 61.2 61.1 dBFS Full 60.1 59.7 dBFS f = 70 MHz 25°C 61.5 61.2 61.1 dBFS IN Full 59.5 dBFS fIN = 200 MHz 25°C 60 60 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 9.9 9.8 9.8 Bits fIN = 30.5 MHz 25°C 9.9 9.8 9.8 Bits fIN = 70 MHz 25°C 9.9 9.8 9.8 Bits f = 200 MHz 25°C 9.6 9.6 Bits IN WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −81 −78 −78 dBc f = 30.5 MHz 25°C −81 −78 −78 dBc IN Full −65 −64 dBc fIN = 70 MHz 25°C −82 −78 −78 dBc Full −64 dBc fIN = 200 MHz 25°C −73 −73 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 78 75 75 dBc fIN = 30.5 MHz 25°C 78 75 75 dBc Full 65 64 dBc f = 70 MHz 25°C 78 75 75 dBc IN Full 64 dBc fIN = 200 MHz 25°C 73 73 dBc WORST OTHER (HARMONIC OR SPUR) f = 9.7 MHz 25°C −82 −80 −80 dBc IN fIN = 30.5 MHz 25°C −82 −80 −80 dBc Full −71 −70 dBc f = 70 MHz 25°C −82 −80 −80 dBc IN Full −70 dBc f = 200 MHz 25°C −80 −80 dBc IN TWO-TONE SFDR f = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 78 78 dBc IN 2 CROSSTALK Full −100 −100 −100 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. 0 | Page 5 of 36 AD9204 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. AD9204-20/AD9204-40/AD9204-65/AD9204-80 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p- p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF 1 LOGIC INPUTS (SCLK/DFS, SYNC, PDWN) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (CSB) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full +40 +135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUTS (SDIO/DCS) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full +40 +130 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, I = 50 μA Full 3.29 V OH High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, I = 50 μA Full 1.79 V OH High Level Output Voltage, I = 0.5 mA Full 1.75 V OH Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. 0 | Page 6 of 36 AD9204 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. AD9204-20/AD9204-40 AD9204-65 AD9204-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz 1 Conversion Rate Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (t) Full 50/25 15.38 12.5 ns CLK CLK Pulse Width High (tCH) 25.0/12.5 7.69 6.25 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (t) Full 3 3 3 ns DCO DCO to Data Skew (t) Full 0.1 0.1 0.1 ns SKEW Pipeline Delay (Latency) Full 9 9 9 Cycles 2 Wake-Up Time Full 350 350 350 μs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A/CH B DATA N – 9 N – 8N – 7N – 6N – 5 t PD Figure 2. CMOS Output Data Timing N – 1 N + 4 t A N + 5 N N + 3 VIN N + 1 N + 2 t CH t CLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A CH B CH A CH B CH A CH B CH A CH B CH A CH A/CH B DATA N – 9 N – 9 N – 8 N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 t PD Figure 3. CMOS Interleaved Output Timing Rev. 0 | Page 7 of 36 08122-003 08122-002 AD9204 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.24 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns t Time required for the SDIO pin to switch from an input to an 10 ns EN_SDIO output relative to the SCLK falling edge t 10 ns DIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge CLK+ t t SSYNC HSYNC SYNC Figure 4. SYNC Input Timing Requirements Rev. 0 | Page 8 of 36 08122-004 AD9204 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating The exposed paddle is the only ground connection for the chip. AVDD to AGND −0.3 V to +2.0 V The exposed paddle must be soldered to the AGND plane of the DRVDD to AGND −0.3 V to +3.9 V user’s circuit board. Soldering the exposed paddle to the user’s VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V board also increases the reliability of the solder joints and CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V maximizes the thermal capability of the package. SYNC to AGND −0.3 V to DRVDD + 0.3 V Table 7. Thermal Resistance VREF to AGND −0.3 V to AVDD + 0.2 V Airflow SENSE to AGND −0.3 V to AVDD + 0.2 V Velocity VCM to AGND −0.3 V to AVDD + 0.2 V 1, 2 1, 3 1, 4 (m/sec) Package Type θJA θJC θJB Unit RBIAS to AGND −0.3 V to AVDD + 0.2 V 64-Lead LFCSP 0 23 2.0 °C/W CSB to AGND −0.3 V to DRVDD + 0.3 V 9 mm × 9 mm 1.0 20 12 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V (CP-64-4) 2.5 18 °C/W SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V 1 OEB to AGND −0.3 V to DRVDD + 0.3 V Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). PDWN to AGND −0.3 V to DRVDD + 0.3 V 3 Per MIL-Std 883, Method 1012.1. D0A/D0B Through D13A/D13B to AGND −0.3 V to DRVDD + 0.3 V 4 Per JEDEC JESD51-8 (still air). DCOA/DCOB to AGND −0.3 V to DRVDD + 0.3 V Typical θJA is specified for a 4-layer PCB with a solid ground Operating Temperature Range (Ambient) −40°C to +85°C plane. As shown in Table 7, airflow improves heat dissipation, Maximum Junction Temperature 150°C Under Bias which reduces θ . In addition, metal in direct contact with the JA Storage Temperature Range (Ambient) −65°C to +150°C package leads from metal traces, through holes, ground, and power planes reduces the θJA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ESD CAUTION rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 36 AD9204 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK+ 1 PIN 1 48 PDWN INDICATOR CLK– 2 47 OEB SYNC 3 46 CSB NC 4 45 SCLK/DFS NC 5 44 SDIO/DCS NC 6 43 ORA NC 7 42 D9A (MSB) NC 8 41 D8A AD9204 NC 9 40 D7A TOP VIEW DRVDD 10 39 D6A (Not to Scale) 38 D0B (LSB) 11 D5A D1B 12 37 DRVDD D2B 13 36 D4A D3B 14 35 D3A D4B 15 34 D2A D5B 16 33 D1A NOTES 1. NC = NO CONNECT 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 5. Pin Configuration Table 8. Pin Function Description Pin No. Mnemonic Description 0 GND Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 4, 5, 6, 7, 8, 9, 25, 26, 27, NC Do Not Connect. 29, 30, 31 10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 11 to 18, 20, 21 D0B to D9B Channel B Digital Outputs. D9B = MSB. 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. 32 to 36, 38 to 42 D0A to D9A Channel A Digital Outputs. D9A = MSB. 43 ORA Channel A Out-of-Range Digital Output. 44 SDIO/DCS SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull- down in SPI mode. Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal pull-up in non-SPI (DCS) mode. 45 SCLK/DFS SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down. Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down. DFS high = twos complement output. DFS low = offset binary output. 46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up. 47 OEB Digital Input. Enable Channel A and Channel B digital outputs if low, three-state outputs if high. 30 kΩ internal pull-down. 48 PDWN Digital Input. 30 kΩ internal pull-down. PDWN high = power-down device. PDWN low = run device, normal operation. Rev. 0 | Page 10 of 36 D6B 17 64 AVDD D7B 18 63 AVDD DRVDD 19 62 VIN+B D8B 20 61 VIN–B D9B (MSB) 21 60 AVDD AVDD ORB 22 59 DCOB 23 58 RBIAS DCOA 24 57 VCM NC 25 56 SENSE NC 26 55 VREF NC 27 54 AVDD DRVDD 28 53 AVDD NC 29 52 VIN–A NC 30 51 VIN+A NC 31 50 AVDD D0A (LSB) 32 49 AVDD 08122-005 AD9204 Pin No. Mnemonic Description 49, 50, 53, 54, 59, 60, 63, 64 AVDD 1.8 V Analog Supply Pins. 51, 52 VIN+A, VIN−A Channel A Analog Inputs. 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog output voltage at midsupply to set common mode of the analog inputs. 58 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 61, 62 VIN−B, VIN+B Channel B Analog Inputs. Rev. 0 | Page 11 of 36 AD9204 TYPICAL PERFORMANCE CHARACTERISTICS AD9204-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 0 80MSPS 80MSPS 30.5MHz @ –1dBFS 9.7MHz @ –1dBFS SNR = 60.5dB (61.5dBFS) SNR = 60.5dB (61.5dBFS) –20 –20 SFDR = 80.3dBc SFDR = 83.5dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 5 10152025303540 0 5 10152025303540 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD9204-80 Single-Tone FFT with f = 9.7 MHz Figure 9. AD9204-80 Single-Tone FFT with f = 30.5 MHz IN IN 0 0 80MSPS 80MSPS 70.3MHz @ –1dBFS 200MHz @ –1dBFS SNR = 60.4dB (61.4dBFS) SNR = 60.1dB (60.1dBFS) –20 –20 SFDR = 82.2dBc SFDR = 74.176dBc –40 –40 –60 –60 2 –80 –80 3 + 6 5 4 –100 –100 –120 –120 0 5 10152025303540 0 5 10152025303540 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. AD9204-80 Single-Tone FFT with fIN = 70.3 MHz Figure 10. AD9204-80 Single-Tone FFT with fIN =200 MHz 0 80MSPS 30.5MHz @ –7dBFS –15 –10 32.5MHz @ –7dBFS SFDR = 78dBc –30 SFDR (dBc) –30 –45 IMD3 (dBc) –50 –60 F1 + F2 SFDR (dBFS) –75 –70 2F1 – F2 F2 – F1 2F1 – F2 2F2 + F1 –90 –90 IMD3 (dBFS) –105 –110 –120 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 4 8 12 16 20 24 28 32 36 40 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 8. AD9204-80 Two-Tone FFT with f = 30.5 MHz and f = 32.5 MHz IN1 IN2 Figure 11. AD9204-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f = 30.5 MHz and f = 32.5 MHz IN1 IN2 Rev. 0 | Page 12 of 36 AMPLITUDE (dB) AMPLITUDE (dBFS) AMPLITUDE (dB) 08122-062 08122-033 08122-036 SFDR/IMD3 (dBFS/dBc) AMPLITUDE (dBFS) AMPLITUDE (dB) 08122-134 08122-034 08122-054 AD9204 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 85 90 80 80 SFDRFS SFDR (dBc) 70 75 SNRFS 60 70 50 65 40 SNR (dBFS) SFDR 30 60 SNR 20 55 10 50 0 50 100 150 200 0 –60 –50 –40 –30 –20 –10 0 AIN FREQUENCY (MHz) INPUT AMPLITUDE (dBc) Figure 12. AD9204-80 SNR/SFDR vs. Input Frequency (AIN) with Figure 15. AD9204-80 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7MHz IN 2 V p-p Full Scale 85 120,000 SFDR (dBc) 100,000 80 80,000 75 60,000 70 40,000 65 20,000 SNR (dBFS) 60 0 0 102030405060 70 80 N – 3N – 2N – 1 N N + 1 N + 2 N + 3 SAMPLE RATE (MHz) OUTPUT CODE Figure 13. AD9204-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz Figure 16. AD9204-80 Grounded Input Histogram 0.20 1.0 0.8 0.16 0.12 0.6 0.08 0.4 0.04 0.2 0 0 –0.2 –0.04 –0.08 –0.4 –0.12 –0.6 –0.8 –0.16 –0.20 –1.0 24 224 424 624 824 1024 24 224 424 624 824 1024 OUTPUT CODE OUTPUT CODE Figure 14. AD9204-80 DNL with fIN = 9.7 MHz Figure 17. AD9204-80 INL with fIN = 9.7 MHz Rev. 0 | Page 13 of 36 DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08122-057 08122-055 08122-038 INL ERROR (LSB) NUMBER OF HITS SNR/SFDR (dBc/dBFS) 08122-061 08122-037 08122-048 AD9204 AD9204-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 0 65MSPS 9.7MHz @ –1dBFS –10 SNR = 60.6dB (61.6dBFS) –20 SFDR = 83.1dBc –30 SFDR (dBc) –40 –50 IMD3 (dBc) –60 –70 –80 SFDR (dBFS) –90 –100 IMD3 (dBFS) –110 –120 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 5 1015202530 INPUT AMPLITUDE (dBFS) FREQUENCY (MHz) Figure 18. AD9204-65 Single-Tone FFT with fIN = 9.7 MHz Figure 21. AD9204-65 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz IN 0 85 65MSPS 70.3MHz @ –1dBFS 80 –20 SNR = 60.6dB (61.6dBFS) SFDR (dBc) SFDR = 83.4dBc 75 –40 70 –60 65 SNR (dBFS) –80 60 –100 55 –120 50 0 5 1015202530 0 50 100 150 200 FREQUENCY (MHz) AIN FREQUENCY (MHz) Figure 19. AD9204-65 Single-Tone FFT with f = 70.3 MHz Figure 22. AD9204-65 SNR/SFDR vs. Input Frequency (AIN) with IN 2 V p-p Full Scale 0 65MSPS 30.5MHz @ –1dBFS –20 SNR = 60.6dB (61.6dBFS) SFDR = 83.9dBc –40 –60 –80 –100 –120 0 5 1015202530 FREQUENCY (MHz) Figure 20. AD9204-65 Single-Tone FFT with fIN = 30.5 MHz Rev. 0 | Page 14 of 36 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 08122-031 08122-032 08122-030 SFDR/IMD3 (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08122-056 08122-060 AD9204 AD9204-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 90 0 40MSPS 80 SFDRFS 9.7MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) –20 SFDR = 82.0dBc 70 SNRFS 60 –40 50 –60 40 SFDR 30 –80 SNR 20 –100 10 0 –120 0 5 10 15 20 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBc) FREQUENCY (MHz) Figure 23. AD9204-40 Single-Tone FFT with fIN = 9.7 MHz Figure 25. AD9204-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 40MSPS 30.5MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) –20 SFDR = 83.8dBc –40 –60 –80 –100 –120 0 246 8 1012 141618 20 FREQUENCY (MHz) Figure 24. AD9204-40 Single-Tone FFT with f = 30.5 MHz IN Rev. 0 | Page 15 of 36 AMPLITUDE (dB) AMPLITUDE (dB) 08122-029 08122-028 SNR/SFDR (dBc/dBFS) 08122-059 AD9204 AD9204-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 90 20MSPS SFDR (dBFS) 80 9.7MHz @ –1dBFS –20 SNR = 60.6dBFS (61.6dBFS) SFDR = 81.3dBc 70 SNR (dBFS) –40 60 50 –60 SFDR (dBc) 40 SNR (dBc) 30 –80 20 –100 10 0 –120 04 2 6810 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBc) FREQUENCY (MHz) Figure 26. AD9204-20 Single-Tone FFT with fIN = 9.7 MHz Figure 28. AD9204-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7MHz 0 20MSPS 30.5MHz @ –1dBFS –20 SNR = 60.6dBFS (61.6dBFS) SFDR = 84.0dBc –40 –60 –80 –100 –120 04 2 6810 FREQUENCY (MHz) Figure 27. AD9204-20 Single-Tone FFT with f = 30.5 MHz IN Rev. 0 | Page 16 of 36 AMPLITUDE (dB) AMPLITUDE (dB) 08122-026 08122-024 SNR/SFDR (dBc/dBFS) 08122-058 AD9204 EQUIVALENT CIRCUITS DRVDD AVDD VIN±x Figure 29. Equivalent Analog Input Circuit Figure 32. Equivalent Digital Output Circuit 5Ω CLK+ 15kΩ 0.9V 15kΩ DRVDD 5Ω CLK– 350Ω SCLK/DFS, SYNC, OEB, AND PDWN 30kΩ Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Figure 30. Equivalent Clock Input Circuit AVDD AVDD DRVDD 30kΩ 350Ω SDIO/DCS 375Ω RBIAS 30kΩ AND VCM Figure 34. Equivalent RBIAS, VCM Circuit Figure 31. Equivalent SDIO/DCS Input Circuit Rev. 0 | Page 17 of 36 08122-039 08122-040 08122-041 08122-042 08122-044 08122-043 AD9204 DRVDD AVDD AVDD 30kΩ 350Ω CSB 375Ω VREF 7.5kΩ Figure 35. Equivalent CSB Input Circuit Figure 37. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 36. Equivalent SENSE Circuit Rev. 0 | Page 18 of 36 08122-046 08122-045 08122-047 AD9204 THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS The AD9204 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically The analog input to the AD9204 is a differential switched- on the same carrier but from two separate antennae. The ADCs capacitor circuit designed for processing differential input can also be operated with independent analog inputs. The user signals. This circuit can support a wide common-mode range can sample any f /2 frequency segment from dc to 200 MHz, S while maintaining excellent performance. By using an input using appropriate low-pass or band-pass filtering at the ADC common-mode voltage of midsupply, users can minimize inputs with little loss in ADC performance. Operation to signal-dependent errors and achieve optimum performance. 300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. H In nondiversity applications, the AD9204 can be used as a base- C band or direct downconversion receiver, where one ADC is PAR H VIN+x used for I input data and the other is used for Q input data. C SAMPLE SS Synchronization capability is provided to allow synchronized SS timing among multiple channels or multiple devices. C SAMPLE VIN–x Programming and control of the AD9204 are accomplished H C PAR using a 3-bit SPI-compatible serial interface. H ADC ARCHITECTURE The AD9204 architecture consists of a multistage, pipelined ADC. Figure 38. Switched-Capacitor Input Circuit Each stage provides sufficient overlap to correct for flash errors The clock signal alternately switches the input circuit between in the preceding stage. The quantized outputs from each stage are sample-and-hold mode (see Figure 38). When the input circuit combined into a final 10-bit result in the digital correction logic. is switched to sample mode, the signal source must be capable The pipelined architecture permits the first stage to operate with of charging the sample capacitors and settling within one-half a new input sample, while the remaining stages operate with of a clock cycle. A small resistor in series with each input can preceding samples. Sampling occurs on the rising edge of help reduce the peak transient current injected from the output the clock. stage of the driving source. In addition, low Q inductors or ferrite Each stage of the pipeline, excluding the last, consists of a low beads can be placed on each leg of the input to reduce high resolution flash ADC connected to a switched-capacitor DAC differential capacitance at the analog inputs and, therefore, and an interstage residue amplifier (for example, a multiplying achieve the maximum bandwidth of the ADC. Such use of low digital-to-analog converter (MDAC)). The residue amplifier Q inductors or ferrite beads is required when driving the converter magnifies the difference between the reconstructed DAC output front end at high IF frequencies. Either a shunt capacitor or two and the flash input for the next stage in the pipeline. One bit of single-ended capacitors can be placed on the inputs to provide a redundancy is used in each stage to facilitate digital correction matching passive network. This ultimately creates a low-pass of flash errors. The last stage simply consists of a flash ADC. filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the The output staging block aligns the data, corrects errors, and Analog Dialogue article “Transformer-Coupled Front-End for passes the data to the CMOS output buffers. The output buffers Wideband A/D Converters” (Volume 39, April 2005) for more are powered from a separate (DRVDD) supply, allowing adjust- information. In general, the precise values depend on the ment of the output voltage swing. During power-down, the application. output buffers go into a high impedance state. Rev. 0 | Page 19 of 36 08122-006 AD9204 Input Common Mode The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9204 (see Figure 41), and the The analog inputs of the AD9204 are not internally dc-biased. driver can be configured in a Sallen-Key filter topology to Therefore, in ac-coupled applications, the user must provide a provide band limiting of the input signal. dc bias externally. Setting the device so that VCM = AVDD/2 is 200Ω recommended for optimum performance, but the device can 33Ω VIN–x function over a wider range with reasonable performance, as VIN 76.8Ω AVDD 90Ω shown in Figure 39 and Figure 40. 10pF ADA4938-2 ADC An on-board, common-mode voltage reference is included in 0.1µF 120Ω 33Ω VCM the design and is available from the VCM pin. The VCM pin VIN+x 200Ω must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Figure 41. Differential Input Configuration Using the ADA4938-2 100 For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer-coupling is the recommended input configuration. An example is shown in Figure 42. To bias 90 the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. 80 SFDR (dBc) VIN–x R 2V p-p 49.9Ω 70 C ADC R SNR (dBFS) VCM VIN+x 60 0.1µF Figure 42. Differential Transformer-Coupled Configuration 50 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 The signal characteristics must be considered when selecting INPUT COMMON-MODE VOLTAGE (V) a transformer. Most RF transformers saturate at frequencies Figure 39. SNR/SFDR vs. Input Common-Mode Voltage, below a few megahertz (MHz). Excessive signal power can f = 32.1 MHz, f = 80 MSPS IN S also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the 100 noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9204. For applications above 90 ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 44). 80 SFDR (dBc) An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. 70 An example is shown in Figure 45. See the AD8352 data sheet SNR (dBFS) for more information. 60 In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 9 displays the suggested values to 50 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 set the RC network. However, these values are dependent on INPUT COMMON-MODE VOLTAGE (V) the input signal and should be used only as a starting guide. Figure 40. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 10.3 MHz, fS = 20 MSPS Table 9. Example RC Network Differential Input Configurations R Series Frequency Range (MHz) (Ω Each) C Differential (pF) Optimum performance is achieved while driving the AD9204 in a 0 to 70 33 22 differential input configuration. For baseband applications, the 70 to 200 125 Open AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. Rev. 0 | Page 20 of 36 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 08122-140 08122-139 08122-007 08122-008 AD9204 10µF AVDD Single-Ended Input Configuration 1kΩ R VIN+x A single-ended input can provide adequate performance in 1V p-p 0.1µF 49.9Ω 1kΩ cost-sensitive applications. In this configuration, SFDR and AVDD ADC C distortion performance degrade due to the large input common- 1kΩ R mode swing. If the source impedances on each input are matched, VIN–x 10µF 0.1µF 1kΩ there should be little effect on SNR performance. Figure 43 shows a typical single-ended input configuration. Figure 43. Single-Ended Input Configuration 0.1µF R 0.1µF VIN+x 2V p-p 25Ω P S S P C ADC A 0.1µF 25Ω 0.1µF R VCM VIN–x Figure 44. Differential Double Balun Input Configuration V CC 0.1µF 0Ω 0.1µF 16 8, 13 0.1µF ANALOG INPUT R 11 1 VIN+x 2 200Ω C ADC R R AD8352 C D G D 3 200Ω 0.1µF 10 R 4 VCM VIN–x 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 45. Differential Input Configuration Using the AD8352 Rev. 0 | Page 21 of 36 08122-010 08122-011 08122-009 AD9204 In either internal or external reference mode, the maximum VOLTAGE REFERENCE input range of the ADC can be varied by configuring SPI A stable and accurate 1.0 V voltage reference is built into the Address 0x18 as shown in Table 11, resulting in a selectable AD9204. The VREF can be configured using either the internal differential span from 1 V p-p to 2 V p-p. 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that If the internal reference of the AD9204 is used to drive multiple follow. The Reference Decoupling section describes the best converters to improve gain matching, the loading of the reference practices PCB layout of the reference. by the other converters must be considered. Figure 47 shows how the internal reference voltage is affected by loading. Internal Reference Connection A comparator within the AD9204 detects the potential at the 0 SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, –0.5 the reference amplifier switch is connected to the internal resistor divider (see Figure 46), setting VREF to 1.0 V. –1.0 INTERNAL V = 0.993V REF –1.5 VIN+A/VIN+B VIN–A/VIN–B –2.0 ADC –2.5 CORE –3.0 VREF 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 LOAD CURRENT (mA) 1.0µF 0.1µF SELECT Figure 47. VREF Accuracy vs. Load Current LOGIC SENSE 0.5V ADC Figure 46. Internal Reference Configuration Table 10. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Table 11. Scaled Differential Span Summary Selected Mode Resulting VREF (V) SPI Register 0x18 (Hex) Resulting Differential Span (V p-p) Fixed Internal or External Reference 1.0 (internal or external) 0xC0 1.0 Fixed Internal or External Reference 1.0 (internal or external) 0xC8 1.14 Fixed Internal or External Reference 1.0 (internal or external) 0xD0 1.33 Fixed Internal or External Reference 1.0 (internal or external) 0xD8 1.6 Fixed Internal or External Reference 1.0 (internal or external) 0xE0 2.0 Rev. 0 | Page 22 of 36 08122-012 REFERENCE VOLTAGE ERROR (%) 08122-014 AD9204 Clock Input Options External Reference Operation The AD9204 has a very flexible clock input structure. The clock The use of an external reference may be necessary to enhance input can be a CMOS, LVDS, LVPECL, or sine wave signal. the gain accuracy of the ADC or improve thermal drift charac- Regardless of the type of signal being used, clock source jitter teristics. Figure 48 shows the typical drift characteristics of the is of the most concern, as described in the Jitter Considerations internal reference in 1.0 V mode. section. 4 Figure 50 and Figure 51 show two preferred methods for clocking 3 the AD9204 (at clock rates up to 625 MHz). A low jitter clock 2 V ERROR (mV) source is converted from a single-ended signal to a differential REF 1 signal using either an RF transformer or an RF balun. 0 The RF balun configuration is recommended for clock frequencies –1 between 125 MHz and 625 MHz, and the RF transformer is recom- –2 mended for clock frequencies from 10 MHz to 200 MHz. The –3 back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9204 to approx- –4 imately 0.8 V p-p differential. –5 This limit helps prevent the large voltage swings of the clock –6 –40 –20 0 20 40 60 80 from feeding through to other portions of the AD9204 while TEMPERATURE (°C) preserving the fast rise and fall times of the signal that are critical Figure 48. Typical VREF Drift to a low jitter performance. When the SENSE pin is tied to AVDD, the internal reference is ® disabled, allowing the use of an external reference. An internal Mini-Circuits ADT1-1WT, 1:1 Z reference buffer loads the external reference with an equivalent 0.1µF 0.1µF XFMR CLOCK 7.5 kΩ load (see Figure 37). The internal buffer generates the CLK+ INPUT 100Ω 50Ω positive and negative full-scale references for the ADC core. ADC 0.1µF Therefore, the external reference must be limited to a maximum CLK– SCHOTTKY of 1.0 V. 0.1µF DIODES: HSMS2822 CLOCK INPUT CONSIDERATIONS Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz) For optimum performance, clock the AD9204 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a 1nF 0.1µF CLOCK transformer or capacitors. These pins are biased internally CLK+ INPUT 50Ω (see Figure 49) and require no external bias. ADC 0.1µF 1nF AVDD CLK– SCHOTTKY DIODES: HSMS2822 0.9V Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz) CLK+ CLK– 2pF 2pF Figure 49. Equivalent Clock Input Circuit Rev. 0 | Page 23 of 36 V ERROR (mV) REF 08122-016 08122-052 08122-018 08122-017 AD9204 If a low jitter clock source is not available, another option is to Input Clock Divider ac couple a differential PECL signal to the sample clock input The AD9204 contains an input clock divider with the ability pins, as shown in Figure 52. The AD9510/AD9511/AD9512/ to divide the input clock by integer values between 1 and 8. AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer Optimum performance can be obtained by enabling the excellent jitter performance. internal duty cycle stabilizer (DCS) when using divide ratios other than 1, 2, or 4. 0.1µF 0.1µF The AD9204 clock divider can be synchronized using the CLOCK CLK+ INPUT external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow AD951x 100Ω ADC the clock divider to be resynchronized on every SYNC signal PECL DRIVER 0.1µF 0.1µF CLOCK or only on the first SYNC signal after the register is written. A CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their Figure 52. Differential PECL Sample Clock (Up to 625 MHz) clock dividers aligned to guarantee simultaneous input sampling. A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 53. The AD9510/ Clock Duty Cycle AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 Typical high speed ADCs use both clock edges to generate clock drivers offer excellent jitter performance. a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic 0.1µF 0.1µF CLOCK CLK+ performance characteristics. INPUT AD951x 100Ω ADC The AD9204 contains a duty cycle stabilizer (DCS) that retimes LVDS DRIVER 0.1µF 0.1µF CLOCK the nonsampling (falling) edge, providing an internal clock CLK– INPUT 50kΩ 50kΩ signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting Figure 53. Differential LVDS Sample Clock (Up to 625 MHz) the performance of the AD9204. Noise and distortion perform- ance are nearly flat for a wide range of duty cycles with the DCS In some applications, it may be acceptable to drive the sample on, as shown in Figure 55. clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and Jitter in the rising edge of the input is still of concern and is not bypass the CLK− pin to ground with a 0.1 μF capacitor (see easily reduced by the internal stabilization circuit. The duty Figure 54). cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated V CC with it that must be considered in applications in which the OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω clock rate can change dynamically. A wait time of 1.5 μs to 5 μs CLOCK CLK+ CMOS DRIVER INPUT 1 1kΩ is required after a dynamic clock frequency increase or decrease 50Ω ADC before the DCS loop is relocked to the input signal. CLK– 80 0.1µF 75 1 50Ω RESISTOR IS OPTIONAL. 70 Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) DCS ON 65 60 55 DCS OFF 50 45 40 10 20 30 40 50 60 70 80 POSITIVE DUTY CYCLE (%) Figure 55. SNR vs. DCS On/Off Rev. 0 | Page 24 of 36 08122-021 08122-020 08122-019 SNR (dBFS) 08122-053 AD9204 Jitter Considerations POWER DISSIPATION AND STANDBY MODE High speed, high resolution ADCs are sensitive to the quality As shown in Figure 57, the analog core power dissipated by of the clock input. The degradation in SNR from the low fre- the AD9204 is proportional to its sample rate. The digital quency SNR (SNRLF) at a given input frequency (fINPUT) due to power dissipation of the CMOS outputs is determined primarily jitter (tJRMS) can be calculated by by the strength of the digital drivers and the load on each output bit. (−SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF INPUT JRMS The maximum DRVDD current (IDRVDD) can be calculated as In the previous equation, the rms aperture jitter represents IDRVDD = VDRVDD × CLOAD × fCLK × N the clock input jitter specification. Input frequency (IF) undersampling applications are particularly sensitive to jitter, where N is the number of output bits (30, in the case of the as illustrated in Figure 56. AD9204). 80 This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist 75 0.05ps frequency of f /2. In practice, the DRVDD current is estab- CLK 70 lished by the average number of output bits switching, which 0.2ps is determined by the sample rate and the characteristics of the 65 analog input signal. 60 0.5ps Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 57 was 55 1.0ps taken using the same operating conditions as those used in the Typical Performance Characteristics, with a 5 pF load on each 1.5ps 50 2.0ps output driver. 3.0ps 2.5ps 45 140 1 10 100 1k FREQUENCY (MHz) 130 Figure 56. SNR vs. Input Frequency and Jitter AD9204-80 120 The clock input should be treated as an analog signal in cases in 110 which aperture jitter may affect the dynamic range of the AD9204. 100 To avoid modulating the clock signal with digital noise, keep 90 AD9204-65 power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make 80 the best clock sources. If the clock is generated from another type AD9204-40 70 of source (by gating, dividing, or another method), it should be 60 retimed by the original clock at the last step. AD9204-20 50 See the AN-501 Application Note and the AN-756 Application 0 10 20 30 40 50 60 70 80 CLOCK RATE (MSPS) Note available on www.analog.com for more information. Figure 57. AD9204 Analog Core Power vs. Clock Rate Rev. 0 | Page 25 of 36 SNR (dBFS) 08122-022 ANALOG CORE POWER (mW) 08122-051 AD9204 The AD9204 is placed in power-down mode either by the SPI As detailed in the AN-877 Application Note, Interfacing to High port or by asserting the PDWN pin high. In this state, the ADC Speed ADCs via SPI, the data format can be selected for offset typically dissipates 2.2 mW. During power-down, the output binary, twos complement, or gray code when using the SPI control. drivers are placed in a high impedance state. Asserting the Table 12. SCLK/DFS Mode Selection (External Pin Mode) PDWN pin low returns the AD9204 to its normal operating Voltage at Pin SCLK/DFS SDIO/DCS mode. Note that PDWN is referenced to the digital output AGND Offset binary (default) DCS disabled driver supply (DRVDD) and should not exceed that supply DRVDD Twos complement DCS enabled (default) voltage. Low power dissipation in power-down mode is achieved by Digital Output Enable Function (OEB) shutting down the reference, reference buffer, biasing networks, The AD9204 has a flexible three-state ability for the digital and clock. Internal capacitors are discharged when entering power- output pins. The three-state mode is enabled using the OEB down mode and then must be recharged when returning to normal pin or through the SPI interface. If the OEB pin is low, the operation. As a result, wake-up time is related to the time spent output data drivers and DCOs are enabled. If the OEB pin is in power-down mode, and shorter power-down cycles result in high, the output data drivers and DCOs are placed in a high proportionally shorter wake-up times. impedance state. This OEB function is not intended for rapid When using the SPI port interface, the user can place the ADC access to the data bus. Note that OEB is referenced to the digital in power-down mode or standby mode. Standby mode allows output driver supply (DRVDD) and should not exceed that the user to keep the internal reference circuitry powered when supply voltage. faster wake-up times are required. See the Memory Map section When using the SPI interface, the data outputs and DCO of for more details. each channel can be independently three-stated by using the DIGITAL OUTPUTS output disable (OEB) bit (Bit 4) in Register 0x14. The AD9204 output drivers can be configured to interface with TIMING 1.8 V to 3.3 V CMOS logic families. Output data can also be The AD9204 provides latched data with a pipeline delay of multiplexed onto a single output bus to reduce the total number of nine clock cycles. Data outputs are available one propagation traces required. delay (tPD) after the rising edge of the clock signal. The CMOS output drivers are sized to provide sufficient output Minimize the length of the output data lines and loads placed current to drive a wide variety of logic families. However, large on them to reduce transients within the AD9204. These drive currents tend to cause current glitches on the supplies that transients can degrade converter dynamic performance. may affect converter performance. The lowest typical conversion rate of the AD9204 is 3 MSPS. At Applications requiring the ADC to drive large capacitive loads clock rates below 3 MSPS, dynamic performance can degrade. or large fanouts may require external buffers or latches. Data Clock Output (DCO) The output data format can be selected to be either offset binary The AD9204 provides two data clock output (DCO) signals or twos complement by setting the SCLK/DFS pin when operating intended for capturing the data in an external register. The CMOS in the external pin mode (see Table 12). data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description. Table 13. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 0000 10 0000 0000 0000 1 VIN+ − VIN− = −VREF 00 0000 0000 0000 10 0000 0000 0000 0 VIN+ − VIN− = 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 1111 01 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 1111 01 1111 1111 1111 1 Rev. 0 | Page 26 of 36 AD9204 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion The AD9204 includes a built-in test feature designed to enable of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN verification of the integrity of each channel, as well as facilitate sequence can be continued from its last value by writing a 0 in board level debugging. A built-in self-test (BIST) feature that Bit 2 of Register 0x0E. However, if the PN sequence is not reset, verifies the integrity of the digital datapath of the AD9204 is the signature calculation will not equal the predetermined value included. Various output test options are also provided to place at the end of the test. At that point, the user must rely on predictable values on the outputs of the AD9204. verifying the output data. BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES The BIST is a thorough test of the digital portion of the selected The output test options are described in Table 17 at Address AD9204 signal path. Perform the BIST test after a reset to ensure 0x0D. When an output test mode is enabled, the analog section that the part is in a known state. During BIST, data from an internal of the ADC is disconnected from the digital back-end blocks, pseudorandom noise (PN) source is driven through the digital and the test pattern is run through the output formatting block. datapath of both channels, starting at the ADC block output. Some of the test patterns are subject to output formatting, and At the datapath output, CRC logic calculates a signature from some are not. The PN generators from the PN sequence tests the data. The BIST sequence runs for 512 cycles and then stops. can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These Once completed, the BIST compares the signature results with a tests can be performed with or without an analog signal (if predetermined value. If the signatures match, the BIST sets Bit 0 present, the analog signal is ignored), but they do require an of Register 0x24, signifying that the test passed. If the BIST test encode clock. For more information, see the AN-877 Appli- failed, Bit 0 of Register 0x24 is cleared. The outputs are connected cation Note, Interfacing to High Speed ADCs via SPI. during this test so that the PN sequence can be observed as it runs. Writing 0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence Rev. 0 | Page 27 of 36 AD9204 CHANNEL/CHIP SYNCHRONIZATION The AD9204 has a SYNC input that offers the user flexible to the sample clock; however, to ensure that there is no timing synchronization options for synchronizing sample clocks uncertainty between multiple parts, the SYNC input signal should across multiple ADCs. The input clock divider can be enabled be externally synchronized to the input clock signal, meeting the to synchronize on a single occurrence of the SYNC signal or on setup and hold times shown in Table 5. Drive the SYNC input every occurrence. The SYNC input is internally synchronized using a single-ended CMOS-type signal. Rev. 0 | Page 28 of 36 AD9204 SERIAL PORT INTERFACE (SPI) The AD9204 serial port interface (SPI) allows the user to configure The falling edge of CSB, in conjunction with the rising edge of the converter for specific functions or operations through a SCLK, determines the start of the framing. An example of the structured register space provided inside the ADC. The SPI serial timing and its definitions can be found in Figure 58 and gives the user added flexibility and customization, depending Table 5. on the application. Addresses are accessed via the serial port Other modes involving the CSB are available. The CSB can be and can be written to or read from via the port. Memory is held low indefinitely, which permanently enables the device; organized into bytes that can be further divided into fields, this is called streaming. The CSB can stall high between bytes to which are documented in the Memory Map section. For allow for additional external timing. When CSB is tied high, SPI detailed operational information, see the AN-877 Applica- functions are placed in high impedance mode. This mode turns tion Note, Interfacing to High Speed ADCs via SPI. on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: the SCLK, the SDIO, Data follows the instruction phase, and its length is determined by the W0 and W1 bits, as shown in Figure 58. and the CSB (see Table 14). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to All data is composed of 8-bit words. The first bit of the first byte the ADC. The SDIO (serial data input/output) is a dual-purpose in a multibyte serial data transfer frame indicates whether a read pin that allows data to be sent and read from the internal ADC command or a write command is issued. This allows the serial memory map registers. The CSB (chip select bar) is an active- data input/output (SDIO) pin to change direction from an input low control that enables or disables the read and write cycles. to an output at the appropriate point in the serial frame. Table 14. Serial Port Interface Pins In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing Pin Function the serial port to be used both to program the chip and to read SCLK Serial Clock. The serial shift clock input is used to synchronize serial interface reads and writes. the contents of the on-chip memory. If the instruction is a readback SDIO Serial Data Input/Output. A dual-purpose pin that operation, performing a readback causes the serial data input/ typically serves as an input or an output, depending output (SDIO) pin to change direction from an input to an output on the instruction being sent and the relative position at the appropriate point in the serial frame. in the timing frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB CSB Chip Select Bar. An active-low control that gates the read and write cycles. first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t t t DS CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 SDIO DON’T CARE D5 D4 D3 D2 D1 D0 DON’T CARE Figure 58. Serial Port Interface Timing Diagram Rev. 0 | Page 29 of 36 08122-023 AD9204 Table 15. Mode Selection HARDWARE INTERFACE External The pins described in Table 14 constitute the physical interface Pin Voltage Configuration between the programming device of the user and the serial port SDIO/DCS AVDD (default) Duty cycle stabilizer enabled of the AD9204. The SCLK and CSB pins function as inputs AGND Duty cycle stabilizer disabled when using the SPI interface. The SDIO pin is bidirectional, SCLK/DFS AVDD Twos complement enabled functioning as an input during write phases and as an output AGND (default) Offset binary enabled during readback. OEB AVDD Outputs in high impedance The SPI interface is flexible enough to be controlled by AGND (default) Outputs enabled either FPGAs or microcontrollers. One method for SPI PDWN AVDD Chip in power-down or standby configuration is described in detail in the AN-812 Appli- AGND (default) Normal operation cation Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. SPI ACCESSIBLE FEATURES The SPI port should not be active during periods when the full Table 16 provides a brief description of the general features that dynamic performance of the converter is required. Because the are accessible via the SPI. These features are described in detail SCLK signal, the CSB signal, and the SDIO signal are typically in the AN-877 Application Note, Interfacing to High Speed ADCs asynchronous to the ADC clock, noise from these signals can via SPI. The AD9204 part-specific features are described in degrade converter performance. If the on-board SPI bus is used detail in Table 17. for other devices, it may be necessary to provide buffers between Table 16. Features Accessible Using the SPI this bus and the AD9204 to prevent these signals from transi- Feature Description tioning at the converter inputs during critical sampling periods. Mode Allows the user to set either power-down mode SDIO/DCS and SCLK/DFS serve a dual function when the or standby mode SPI interface is not being used. When the pins are strapped to Clock Allows the user to access the DCS via the SPI AVDD or ground during device power-on, they are associated Offset Allows the user to digitally adjust the with a specific function. The Digital Outputs section describes converter offset the strappable functions supported on the AD9204. Test I/O Allows the user to set test modes to have known data on output bits CONFIGURATION WITHOUT THE SPI Output Mode Allows the user to set up outputs In applications that do not interface to the SPI control registers, Output Phase Allows the user to set the output clock polarity the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the Output Delay Allows the user to vary the DCO delay PDWN pin serve as standalone CMOS-compatible control VREF Allows the user to set the reference voltage pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power- down feature control. In this mode, connect the CSB chip select to AVDD, which disables the serial port interface. Rev. 0 | Page 30 of 36 AD9204 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 17) has After the AD9204 is reset, critical registers are loaded with eight bit locations. The memory map is roughly divided into default values. The default values for the registers are given four sections: the chip configuration registers (Address 0x00 in the memory map register table (see Table 17). to Address 0x02); the device index and transfer registers Logic Levels (Address 0x05 and Address 0xFF); the program registers An explanation of logic level terminology follows: (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 and Address 0x101). • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Table 17 documents the default hexadecimal value for each • “Clear a bit” is synonymous with “bit is set to Logic 0” or hexadecimal address shown. The column with the heading Bit 7 “writing Logic 0 for the bit.” (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the VREF register, has a hexadecimal Transfer Register Map default value of 0xE0. This means that Bits[7:5] = 1, and the Address 0x08 to Address 0x18 are shadowed. Writes to these remaining Bits[4:0] = 0. This setting is the default reference addresses do not affect part operation until a transfer command selection setting. The default value uses a 2.0 V p-p reference. is issued by writing 0x01 to Address 0xFF, setting the transfer bit. For more information on this function and others, see the AN-877 This allows these registers to be updated internally and simulta- Application Note, Interfacing to High Speed ADCs via SPI. This neously when the transfer bit is set. The internal update takes document details the functions controlled by Register 0x00 to place when the transfer bit is set, and then the bit autoclears. register 0xFF. The remaining registers, Register 0x100 and Channel-Specific Registers Register 0x101, are documented in the Memory Map Register Descriptions section following Table 17. Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are OPEN LOCATIONS internally duplicated for each channel. These registers and bits All address and bit locations that are not included in the SPI are designated in the memory map register table as local. These map are not currently supported for this device. Unused bits of local registers and bits can be accessed by setting the appropriate a valid address location should be written with 0s. Writing to these Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. locations is required only when part of an address location is If both bits are set, the subsequent write affects the registers of open (for example, Address 0x18). If the entire address location both channels. In a read cycle, set only Channel A or Channel B is open, it is omitted from the SPI map (for example, Address 0x13) to read one of the two registers. If both bits are set during an and should not be written. SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. 0 | Page 31 of 36 AD9204 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB Soft reset 1 1 Soft LSB first 0 0x18 The nibbles are configuration first reset mirrored so that (global) LSB- or MSB-first mode registers correctly, regard- less of shift mode 0x01 Chip ID (global) 8-bit chip ID bits [7:0] Unique chip ID AD9204 = 0x25 used to diffe- rentiate devices; read only 0x02 Chip grade Open Speed grade ID 6:4 Open Unique speed (global) 20 MSPS = 000 grade ID used to 40 MSPS = 001 differentiate 65 MSPS = 010 devices; read only 80 MSPS = 011 Device Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open ADC B ADC A 0xFF Bits are set to default default determine which device on-chip receives the next write command; the default is all devices on-chip 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave Program Registers (May or May Not Be Indexed by Device Index) 0x08 Modes External External pin function Open Open 00 = chip run 0x80 Determines power- 0x00 full power-down 01 = full power- various generic down 0x01 standby down modes of chip enable (local) 10 = standby operation (local) 11 = chip wide digital reset (local) 0x09 Clock (global) Open Open Open Open Open Duty 0x00 cycle stabilize 0x0B Clock divide Open Clock divider [2:0] 0x00 The divide ratio is (global) the value plus 1 Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Rev. 0 | Page 32 of 36 AD9204 Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0D Test mode (local) User test mode Reset PN Reset PN Output test mode [3:0] (local) 0x00 When set, the test (local) long gen short gen 0000 = off (default) data is placed on 00 = single 0001 = midscale short the output pins in 01 = alternate 0010 = positive FS place of normal 10 = single once 0011 = negative FS data 11 = alternate 0100 = alternating checkerboard once 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 0x0E BIST enable Open Open BIST INIT Open BIST 0x00 When Bit 0 is set, enable the BIST function is initiated 0x10 Offset adjust 8-bit device offset adjustment [7:0] (local) 0x00 Device offset trim (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 0x14 Output mode 00 = 3.3 V CMOS Output mux Output Open Output 00 = offset binary 0x00 Configures the 10 = 1.8 V CMOS enable disable invert 01 = twos outputs and the (interleaved) (local) (local) complement format of the data 10 = gray code 11 = offset binary (local) 0x15 OUTPUT_ADJUST 3.3 V DCO 1.8 V DCO 3.3 V data 1.8 V data 0x22 Determines drive strength drive strength drive strength drive strength CMOS output 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe drive strength (default) 01 = 2 stripes (default) 01 = 2 stripes properties 01 = 2 stripes 10 = 3 stripes (default) 01 = 2 stripes 10 = 3 stripes 10 = 3 stripes 11 = 4 stripes 10 = 3 stripes (default) 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 0x16 OUTPUT_PHASE DCO Input clock phase adjust [2:0] 0x00 On devices that output (Value is number of input clock utilize global polarity cycles of phase delay) clock divide, 0 = 000 = no delay determines which normal 001 = 1 input clock cycle phase of the 1 = 010 = 2 input clock cycles divider output is inverted 011 = 3 input clock cycles used to supply (local) 100 = 4 input clock cycles the output clock; 101 = 5 input clock cycles internal latching 110 = 6 input clock cycles is unaffected 111 = 7 input clock cycles 0x17 OUTPUT_DELAY Enable Enable 0x00 This sets the fine DCO/Data delay[2:0] DCO data output delay of 000 = 0.56 ns delay delay the output clock 001 = 1.12 ns but does not 010 = 1.68 ns change internal 011 = 2.24 ns timing 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x18 VREF Reserved =11 Internal VREF adjustment [2:0] 0xE0 Selects and/or 000 = 1.0 V p-p adjusts the VREF 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.60 V p-p 100 = 2.0 V p-p 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB Rev. 0 | Page 33 of 36 AD9204 Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB 0x24 MISR_LSB Open Open Open Open Open Open Open B0 0x00 Least significant byte of MISR; read only 0x2A Features Open Open Open Open Open Open Open OR 0x01 Disables the OR output pin for the enable indexed channel (local) 0 = ADC A 0x2E Output assign Open Open Open Open Open Open Open Ch A = Assign an ADC to 1 = ADC B 0x00 an output (local) Ch B = channel 0x01 Digital Feature Control 0x10 Sync control Open Open Open Open Open Clock Clock Master 0x01 0 (global) divider divider sync next sync sync enable only enable 0x10USR2 Enable Open Open Open Enable Run Open Disable 0x88 Enables internal 1 OEB GCLK GCLK SDIO oscillator for clock Pin 47 detect pull- rates < 5 MHz (local) down USR2 (Register 0x101) MEMORY MAP REGISTER DESCRIPTIONS Bit 7—Enable OEB Pin 47 For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Normally set high, this bit allows Pin 47 to function as the Note, Interfacing to High Speed ADCs via SPI. output enable. If it is set low, it disables Pin 47. Sync Control (Register 0x100) Bit 3—Enable GCLK Detect Bits[7:3]—Reserved Normally set high, this bit enables a circuit that detects encode rates below about 5 MSPS. When a low encode rate is detected, Bit 2—Clock Divider Next Sync Only an internal oscillator, GCLK, is enabled, ensuring the proper If the master sync enable bit (Address 0x100, Bit 0) and the operation of several circuits. If set low, the detector is disabled. clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2—Run GCLK Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable This bit enables the GCLK oscillator. For some applications bit (Address 0x100, Bit 1) resets after it syncs. with encode rates below 10 MSPS, it may be preferable to set this bit high to supersede the GCLK detector. Bit 1—Clock Divider Sync Enable Bit 0—Disable SDIO Pull-Down Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 and Bit 0 are high and the device is This bit can be set high to disable the internal 30 kΩ pull-down operating in continuous sync mode as long as Bit 2 of the on the SDIO pin, which can be used to limit the loading when sync control is low. many devices are connected to the SPI bus. Bit 0—Master Sync Enable Bit 0 must be high to enable any of the sync functions. Rev. 0 | Page 34 of 36 AD9204 APPLICATIONS INFORMATION The copper plane should have several vias to achieve the DESIGN GUIDELINES lowest possible resistive thermal path for heat dissipation to Before starting design and layout of the AD9204 as a system, flow through the bottom of the PCB. Fill or plug these vias it is recommended that the designer become familiar with these with nonconductive epoxy. guidelines, which discuss the special circuit connections and To maximize the coverage and adhesion between the ADC and layout requirements needed for certain pins. the PCB, a silkscreen should be overlaid to partition the continuous Power and Ground Recommendations plane on the PCB into several uniform sections. This provides When connecting power to the AD9204, it is strongly several tie points between the ADC and the PCB during the reflow recommended that two separate supplies be used. Use one 1.8 V process. Using one continuous plane with no partitions guarantees supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for only one tie point between the ADC and the PCB. For detailed the digital output supply (DRVDD). If a common 1.8 V AVDD information about packaging and PCB layout of chip scale and DRVDD supply must be used, the AVDD and DRVDD packages, see the AN-772 Application Note, A Design and domains must be isolated with a ferrite bead or filter choke Manufacturing Guide for the Lead Frame Chip Scale Package and separate decoupling capacitors. Several different decoupling (LFCSP), at www.analog.com. capacitors can be used to cover both high and low frequencies. VCM Locate these capacitors close to the point of entry at the PCB The VCM pin should be decoupled to ground with a 0.1 μF level and close to the pins of the part, with minimal trace length. capacitor, as shown in Figure 42. A single PCB ground plane should be sufficient when using the RBIAS AD9204. With proper decoupling and smart partitioning of the The AD9204 requires that a 10 kΩ resistor be placed between PCB analog, digital, and clock sections, optimum performance is easily achieved. the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. Exposed Paddle Thermal Heat Sink Recommendations Reference Decoupling The exposed paddle (Pin 0) is the only ground connection for the AD9204 and, therefore, it must be connected to analog Externally decouple the VREF pin to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic ground (AGND) on the customer’s PCB. To achieve the best capacitor. electrical and thermal performance, mate an exposed (no solder mask) continuous copper plane on the PCB to the SPI Port AD9204 exposed paddle, Pin 0. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9204 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. 0 | Page 35 of 36 AD9204 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 TOP VIEW BSC EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1, 2 AD9204BCPZ-80 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9204BCPZRL7-80 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9204BCPZ-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9204BCPZRL7-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9204BCPZ-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9204BCPZRL7-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9204BCPZ-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1, 2 AD9204BCPZRL7-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 1 AD9204-80EBZ Evaluation Board 1 AD9204-65EBZ Evaluation Board 1 AD9204-40EBZ Evaluation Board 1 AD9204-20EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08122-0-7/09(0) Rev. 0 | Page 36 of 36 091707-C