ANALOG DEVICES AD9203

10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter AD9203 FEATURES FUNCTIONAL BLOCK DIAGRAM CLK AVDD DRVDD CMOS 10-Bit, 40 MSPS sampling A/D converter CLAMP Power dissipation: 74 mW (3 V supply, 40 MSPS) AD9203 STBY CLAMPIN 17 mW (3 V supply, 5 MSPS) AINP A/D AINN Operation between 2.7 V and 3.6 V supply SHA GAIN SHA GAIN 3-STATE Differential nonlinearity: −0.25 LSB A/D D/A A/D D/A Power-down (standby) mode, 0.65 mW REFTF CORRECTION LOGIC REFBF ENOB: 9.55 @ fIN = 20 MHz Out-of-range indicator BANDGAP OUTPUT BUFFERS OTR REFERENCE VREF Adjustable on-chip voltage reference 10 D9 (MSB) + REFSENSE – IF undersampling up to fIN = 130 MHz D0 (LSB) 0.5V Input range: 1 V to 2 V p-p differential or single-ended AVSS PWRCON DFS DRVSS Adjustable power consumption Internal clamp circuit Figure 1. APPLICATIONS CCD imaging Video Portable instrumentation IF and baseband communications Cable modems Medical ultrasound out-of-range signal (OTR) indicates an overflow condition that can be used with the most significant bit to determine over- or GENERAL DESCRIPTION underrange. The AD9203 is a monolithic low power, single supply, 10-bit, The AD9203 can operate with a supply range from 2.7 V to 3.6 40 MSPS analog-to-digital converter, with an on-chip voltage V, an attractive option for low power operation in high-speed reference. The AD9203 uses a multistage differential pipeline portable applications. architecture and guarantees no missing codes over the full operating temperature range. Its input range may be adjusted The AD9203 is specified over industrial (−40°C to +85°C) between 1 V and 2 V p-p. temperature ranges and is available in a 28-lead TSSOP package. The AD9203 has an onboard programmable reference. An PRODUCT HIGHLIGHTS external reference can also be chosen to suit the dc accuracy Low Power—The AD9203 consumes 74 mW on a 3 V supply and temperature drift requirements of an application. operating at 40 MSPS. In standby mode, power is reduced to An external resistor can be used to reduce power consumption 0.65 mW. when operating at lower sampling rates. This yields power High Performance—Maintains better than 9.55 ENOB at 40 savings for users who do not require the maximum sample rate. MSPS input signal from dc to Nyquist. This feature is especially useful at sample rates far below 40 Very Small Package—The AD9203 is available in a 28-lead MSPS. Excellent performance is still achieved at reduced power. TSSOP. For example, 9.7 ENOB performance may be realized with only Programmable Power—The AD9203 power can be further 17 mW of power, using a 5 MHz clock. reduced by using an external resistor at lower sample rates. Built-In Clamp Function—Allows dc restoration of video A single clock input is used to control all internal conversion signals. cycles. The digital output data is presented in straight binary or twos complementary output format by using the DFS pin. An Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 00573-001 AD9203 TABLE OF CONTENTS Specifications..................................................................................... 3 Driving the Analog Input.......................................................... 13 Absolute Maximum Ratings............................................................ 5 Op Amp Selection Guide .......................................................... 14 Thermal Characteristics .............................................................. 5 Differential Mode of Operation ............................................... 15 ESD Caution.................................................................................. 5 Power Control............................................................................. 16 Pin Configuration and Function Descriptions............................. 6 Interfacing to 5 V Systems ........................................................ 16 Terminology ...................................................................................... 7 Clock Input and Considerations .............................................. 16 Typical Performance Characteristics ............................................. 8 Digital Inputs and Outputs ....................................................... 16 Operations ....................................................................................... 11 Applications..................................................................................... 18 Theory of Operation .................................................................. 11 Direct IF Down Conversion ..................................................... 18 Operational Modes..................................................................... 11 Ultrasound Applications ........................................................... 19 Input and Reference Overview ................................................. 12 Evaluation Board ............................................................................ 20 Internal Reference Connection ................................................ 12 Outline Dimensions ....................................................................... 25 External Reference Operation .................................................. 13 Ordering Guide .......................................................................... 25 Clamp Operation........................................................................ 13 REVISION HISTORY 8/04—Data sheet changed from Rev. A to Rev. B Changes to Table 5.......................................................................... 16 4/01—Data sheet changed from Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to TPC 2 ............................................................................. 8 Added Figures 41 to 46 .................................................................. 23 7/99—Revision 0: Initial Version Rev. B | Page 2 of 28 AD9203 SPECIFICATIONS AVDD = 3 V, DRVDD = 3 V, FS = 40 MSPS, input span from 0.5 V to 2.5 V, internal 1 V reference, PWRCON = AVDD, 50% clock duty cycle, TMIN to TMAX unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Conditions RESOLUTION 10 Bits MAX CONVERSION RATE F 40 MSPS S Clock PIPELINE DELAY 5.5 Cycles DC ACCURACY Differential Nonlinearity DNL ± 0.25 ± 0.7 LSB Integral Nonlinearity INL ± 0.65 ± 1.4 LSB Offset Error E ± 0.6 ± 2.8 % FSR ZS Gain Error E ± 0.7 ± 4.0 % FSR FS ANALOG INPUT Input Voltage Range AIN 1 2 V p-p Input Capacitance C 1.4 pF IN Aperture Delay TAP 2.0 ns Aperture Uncertainty (Jitter) TAJ 1.2 ps rms Input Bandwidth (–3 dB) BW 390 MHz Input Referred Noise 0.3 mV Switched, Single-Ended INTERNAL REFERENCE Output Voltage (0.5 V Mode) VREF 0.5 V REFSENSE = VREF Output Voltage (1 V Mode) VREF 1 V REFSENSE = GND Output Voltage Tolerance (1 V Mode) ± 5 ± 30 mV Load Regulation 0.65 1.2 mV 1.0 mA Load POWER SUPPLY Operating Voltage AVDD 2.7 3.0 3.6 V DRVDD 2.7 3.0 3.6 V Analog Supply Current IAVDD 20.1 22.0 mA Digital Supply Current IDRVDD 4.4 6.0 mA f = 4.8 MHz, Output Bus Load = 10pF IN 9.5 14.0 mA fIN= 20 MHz, Output Bus Load = 20 pF Power Consumption 74 84.0 mW fIN= 4.8 MHz, Output Bus Load = 10pF 88.8 108.0 mW fIN= 20 MHz, Output Bus Load = 20 pF Power-Down P 0.65 1.2 mW D Power Supply Rejection Ratio PSRR 0.04 ± 0.25 % F S DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion1 SINAD f = 4.8 MHz 59.7 dB f = 20 MHz 57.2 59.3 dB Effective Bits ENOB 1 f = 4.8 MHz 9.6 Bits f = 20 MHz 9.2 9.55 Bits Signal-to-Noise Ratio SNR f = 4.8 MHz1 60.0 dB f = 20 MHz 57.5 59.5 dB Total Harmonic Distortion THD f = 4.8MHz −76.0 dB f = 20 MHz −74.0 −65.0 dB Spurious-Free Dynamic Range SFDR 1 f = 4.8 MHz 80 dB f = 20 MHz 67.8 78 dB Rev. B | Page 3 of 28 AD9203 Parameter Symbol Min Typ Max Unit Conditions Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.2 Degree NTSC 40 IRE Ramp Differential Gain DG 0.3 % DIGITAL INPUTS High Input Voltage VIH 2.0 V Low Input Voltage VIL 0.4 V Clock Pulse Width High 11.25 ns Clock Pulse Width Low 11.25 ns 2 Clock Period 25 ns DIGITAL OUTPUTS High-Z Leakage I ± 5.0 µA Output = 0 to DRVDD OZ Data Valid Delay tOD 5 ns CL= 20 pF Data Enable Delay tDEN 6 ns CL= 20 pF Data High-Z Delay tDHZ 6 ns CL= 20 pF LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) VOH 2.95 V High Level Output Voltage (IOH = 0.5 mA) VOH 2.80 V Low Level Output Voltage (I = 1.6 mA) V 0.3 V OL OL Low Level Output Voltage (I = 50 µA) V 0.05 V OL OL 1 Differential Input (2 V p-p). 2 The AD9203 will convert at clock rates as low as 20 kHz. N+1 N N+2 N–1 N+3 ANALOG N+6 INPUT N+4 N+5 CLOCK DATA N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 OUT T = 3ns MIN OD 7ns MAX (C = 20pF) LOAD Figure 2. Timing Diagram Rev. B | Page 4 of 28 00573-002 AD9203 ABSOLUTE MAXIMUM RATINGS Table 2. With Parameter Respect to Min Max Unit AVDD AVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V AVSS DRVSS –0.3 +0.3 V AVDD DRVDD –3.9 +3.9 V REFCOM AVSS –0.3 +0.3 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V AINP AINN AVSS AVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings –0.3 may cause permanent damage to the device. This is a stress VREF AVSS –0.3 AVDD + 0.3 V rating only; functional operation of the device at these or any REFSENSE AVSS –0.3 AVDD + 0.3 V other conditions above those indicated in the operational REFTF, REFBF AVSS –0.3 AVDD + 0.3 V sections of this specification is not implied. Exposure to STBY AVSS –0.3 AVDD + 0.3 V absolute maximum ratings for extended periods may affect CLAMP AVSS –0.3 AVDD + 0.3 V device reliability. CLAMPIN AVSS –0.3 AVDD + 0.3 V PWRCON AVSS –0.3 AVDD + 0.3 V DFS AVSS –0.3 AVDD + 0.3 V 3-STATE AVSS –0.3 AVDD + 0.3 V Junction 150 °C Temperature Storage –65 +150 °C THERMAL CHARACTERISTICS Temperature 28-Lead TSSOP Lead 300 °C J = 97.9°C/W A Temperature J = 14.0°C/W (10 s) C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 5 of 28 AD9203 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DRVSS 1 28 AVDD DRVDD 2 AVSS 27 (LSB) D0 3 26 AINN D1 4 25 AINP D2 5 24 REFBF D3 6 23 VREF AD9203 TOP VIEW D4 7 22 REFTF (Not to Scale) D5 8 21 PWRCON D6 9 20 CLAMPIN D7 10 19 CLAMP D8 11 18 REFSENSE (MSB) D9 12 17 STBY OTR 13 16 3-STATE DFS 14 15 CLK Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin Name Description 1 DRVSS Digital Ground. 2 DRVDD Digital Supply. 3 D0 Bit 0, Least Significant Bit. 4 D1 Bit 1. 5 D2 Bit 2. 6 D3 Bit 3. 7 D4 Bit 4. 8 D5 Bit 5. 9 D6 Bit 6. 10 D7 Bit 7. 11 D8 Bit 8. 12 D9 Bit 9, Most Significant Bit. 13 OTR Out-of-Range Indicator. 14 DFS Data Format Select HI: Twos Complement; LO: Straight Binary. 15 CLK Clock Input. 16 3-STATE HI: High Impedance State Output; LO: Active Digital Output Drives. 17 STBY HI: Power-Down Mode; LO: Normal Operation. 18 REFSENSE Reference Select. 19 CLAMP HI: Enable Clamp; LO: Open Clamp. 20 CLAMPIN Clamp Signal Input. 21 PWRCON Power Control Input. 22 REFTF Top Reference Decoupling. 23 VREF Reference In/Out. 24 REFBF Bottom Reference Decoupling. 25 AINP Noninverting Analog Input. 26 AINN Inverting Analog Input. 27 AVSS Analog Ground. 28 AVDD Analog Supply. Rev. B | Page 6 of 28 00573-003 AD9203 TERMINOLOGY Integral Nonlinearity Error (INL) Signal-To-Noise Ratio (SNR) Linearity error refers to the deviation of each individual code SNR is the ratio of the rms value of the measured input signal to from a line drawn from negative full scale through positive full the rms sum of all other spectral components below the Nyquist scale. The point used as negative full scale occurs 1/2 LSB frequency, excluding harmonics and dc. The value for SNR is before the first code transition. Positive full scale is defined as a expressed in decibels. level 1 1/2 LSB beyond the last code transition. The deviation is Spurious-Free Dynamic Range (SFDR) measured from the middle of each particular code to the true The difference in dB between the rms amplitude of the input straight line. signal and the peak spurious signal. Differential Nonlinearity Error (DNL, No Missing Codes) Offset Error An ideal ADC exhibits code transitions that are exactly 1 LSB First transition should occur for an analog value 1/2 LSB above apart. DNL is the deviation from this ideal value. Guaranteed negative full scale. Offset error is defined as the deviation of the no missing codes to 10-bit resolution indicates that all 1024 actual transition from that point. codes respectively, must be present over all operating ranges. Gain Error Signal-To-Noise and Distortion (S/N+D, SINAD) Ratio The first code transition should occur at an analog value 1/2 S/N+D is the ratio of the rms value of the measured input signal LSB above negative full scale. The last transition should occur to the rms sum of all other spectral components below the for an analog value 1 1/2 LSB below the positive full scale. Gain Nyquist frequency, including harmonics but excluding dc. The error is the deviation of the actual difference between first and value for S/N+D is expressed in decibels. last code transitions and the ideal difference between first and Effective Number of Bits (ENOB) last code transitions. For a sine wave, SINAD can be expressed in terms of the Power Supply Rejection number of bits. Using the following formula, The specification shows the maximum change in full scale from N = (SINAD – 1.76)/6.02 the value with the supply at the minimum limit to the value with the supply at its maximum limit. it is possible to get a measure of performance expressed as N, the effective number of bits. Aperture Jitter Aperture jitter is the variation in aperture delay for successive Thus, effective number of bits for a device for sine wave inputs samples and is manifested as noise on the input to the A/D. at a given input frequency can be calculated directly from its measured SINAD. Aperture Delay Aperture delay is a measure of the sample-and-hold amplifier Total Harmonic Distortion (THD) (SHA) performance and is measured from the rising edge of the THD is the ratio of the rms sum of the first six harmonic clock input to when the input signal is held for conversion. components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Pipeline Delay (Latency) The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided on every rising edge. Rev. B | Page 7 of 28 AD9203 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3 V, DRVDD = 3 V, FS = 40 MSPS, 1 V Internal Reference, PWRCON = AVDD, 50% Duty Cycle, unless otherwise noted. 61 85 2V SINGLE-ENDED INPUT 80 59 2V DIFFERENTIAL INPUT 75 57 70 1V DIFFERENTIAL INPUT 65 55 1V SINGLE- 60 ENDED INPUT 53 55 1V DIFFERENTIAL INPUT 2V DIFFERENTIAL 50 51 INPUT 2V SINGLE- 45 ENDED INPUT 49 40 1V SINGLE-ENDED INPUT 47 35 0 20 40 60 80 100 120 0 20406080 100 120 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 4. SNR vs. Input Frequency and Configuration Figure 7. SFDR vs. Input Frequency and Configuration –80 60 9.6 2V DIFFERENTIAL –75 INPUT –70 55 8.8 1V DIFFERENTIAL 1V DIFFERENTIAL INPUT INPUT –65 2V DIFFERENTIAL 50 8.0 –60 INPUT 1V DIFFERENTIAL INPUT –55 1V SINGLE- 1V SINGLE- 45 7.1 ENDED INPUT ENDED INPUT –50 1V SINGLE- ENDED INPUT –45 40 6.3 –40 2V SINGLE- 2V SINGLE- 2V SINGLE- –35 ENDED INPUT ENDED INPUT ENDED INPUT 35 5.5 –30 0 20 40 60 80 100 120 0 20406080 100 120 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 5. SINAD vs. Input Frequency and Configuration Figure 8. THD vs. Input Frequency and Configuration –75 –75 –70 –0.5dB –0.5dB –65 –65 –6.0dB –60 –6.0dB –55 –55 –20dB –50 –20dB –45 –45 –40 –35 0 20406080 100 120 0 20406080 100 120 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 6. THD vs. Input Frequency and Amplitude Figure 9. THD vs. Input Frequency and Amplitude (Differential Input VREF = 0.5 V) (Differential Input VREF = 1 V) Rev. B | Page 8 of 28 SINAD (dB) THD (dB) SNR (dB) 00573-006 00573-004 ENOB 00573-005 THD (dB) THD (dB) SFDR (dB) 00573-009 00573-008 00573-007 AD9203 1.2E+07 1.0 0.8 10000000 1.0E+07 0.6 0.4 8.0E+06 0.2 6.0E+06 0 –0.2 4.0E+06 –0.4 –0.6 2.0E+06 –0.8 4560 10310 0.0E+00 –1.0 N–1 N N+1 0 100 200 300 400 500 600 700 800 900 1024 CODE Figure 13. Typical DNL Performance Figure 10. Grounded Input Histogram 80 10 SNR = 59.9dB 0 THD = –75dB 85 SFDR = 82dB –10 –THD 70 –20 –30 65 –40 –50 60 SNR –60 55 –70 –80 50 –90 –100 45 –110 40 –120 0 102030405060 0E+0 2.5E+6 5.0E+6 7.5E+6 10.0E+6 12.5E+6 15.0E+6 17.5E+6 20.0E+6 SAMPLE RATE (MSPS) Figure 14. Single Tone Frequency Domain Performance (Input Frequency = Figure 11. SNR and THD vs. Sample Rate (f = 20 MHz) IN 10 MHz, Sample Rate = 40 MSPS 2 V Differential Input, 8192 Point FFT) 80 1.0 0.8 75 0.6 –THD 0.4 70 0.2 65 0 –0.2 60 –0.4 SNR –0.6 55 –0.8 50 –1.0 2.5 3.0 3.5 4.0 0 100 200 300 400 500 600 700 800 900 1024 SUPPLY VOLTAGE (V) Figure 12. Typical INL Performance Figure 15. SNR and THD vs. Power Supply (f = 20 MHz, Sample Rate = 40 MSPS) IN Rev. B | Page 9 of 28 HITS +SNR/–THD (dB) LSB 00573-011 00573-012 00573-010 +SNR/–THD (dB) dB LSB 00573-015 00573-014 00573-013 AD9203 0 0.2 –1 0.1 –2 –3 0 0.5V –4 –0.1 –5 1V –6 –0.2 –7 –0.3 –8 –9 –0.4 10 100 1000 –40 –20 0 20 40 60 80 100 INPUT FREQUENCY (MHz) TEMPERATURE (°C) Figure 16. Full Power Bandwidth Figure 18. Reference Voltage vs. Temperature 3500 3000 1V REFERENCE 2500 2000 0.5V REFERENCE 1500 1000 500 0 0 200 400 600 800 1000 OFF-TIME (ms) Figure 17. Wake-Up Time vs. Off Time (VREF Decoupling = 10 µF) Rev. B | Page 10 of 28 WAKE-UP TIME (µs) AMPLITUDE (dB) 00573-017 00573-016 V ERROR (%) REF 00573-018 AD9203 OPERATIONS THEORY OF OPERATION OPERATIONAL MODES The AD9203 implements a pipelined multistage architecture to The AD9203 may be connected in several input configurations, achieve high sample rates while consuming low power. It as shown in Table 4. distributes the conversion over several smaller A/D subblocks, The AD9203 may be driven differentially from a source that refining the conversion with progressively higher accuracy as it keeps the signal peaks within the power supply rails. passes the results from stage to stage. As a consequence of the distributed conversion, the AD9203 requires a small fraction of Alternatively, the input may be driven into AINP or AINN from the 1023 comparators used in a traditional 10-bit flash-type a single-ended source. The input span will be 2 the A/D. A sample-and-hold function within each of the stages programmed reference voltage. One input will accept the signal, permits the first stage to operate on a new input sample while while the opposite input will be set to midscale by connecting it the remaining stages operate on preceding samples. to the internal or an external reference. For example, a 2 V p-p signal may be applied to AINP while a 1 V reference is applied Each stage of the pipeline, excluding the last, consists of a low to AINN. The AD9203 will then accept a signal varying resolution flash A/D connected to a switched capacitor DAC between 2 V and 0 V. See Figure 19, Figure 20, and Figure 21 for and interstage residue amplifier (MDAC). The residue amplifier more details. magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of The single-ended (ac-coupled) input of the AD9203 may also be redundancy is used in each one of the stages to facilitate digital clamped to ground by the internal clamp switch. This is correction of flash errors. The last stage simply consists of a accomplished by connecting the CLAMP pin to AINN or AINP. flash A/D. Digital output formats may be configured in binary and twos complement. This is determined by the potential on the DFS The input of the AD9203 incorporates a novel structure that pin. If the pin is set to Logic 0, the data will be in straight binary merges the input sample-and-hold amplifier (SHA) and the first format. If the pin is asserted to Logic 1, the data will be in twos pipeline residue amplifier into a single, compact switched complement format. capacitor circuit. This structure achieves considerable noise and power savings over a conventional implementation that uses Power consumption may be reduced by placing a resistor separate amplifiers by eliminating one amplifier in the pipeline. between PWRCON and AVSS. This may be done to conserve By matching the sampling network of the input SHA with the power when not encoding high-speed analog input frequencies first stage flash A/D, the AD9203 can sample inputs well or sampling at the maximum conversion rate. See the beyond the Nyquist frequency with no degradation in performance. Sampling occurs on the falling edge of the clock. Power Control section for more information. Table 4. Modes Name Figure Number Advantages 1 V Differential Figure 28 with VREF Connected to Differential Modes Yield the Best Dynamic Performance REFSENSE 2 V Differential Figure 28 with REFSENSE Connected to Differential Modes Yield the Best Dynamic Performance AGND 1 V Single-Ended Figure 20 Video and Applications Requiring Clamping Require Single-Ended Inputs 2 V Single-Ended Figure 19 Video and Applications Requiring Clamping Require Single-Ended Inputs Rev. B | Page 11 of 28 AD9203 Figure 19 illustrates the input configured with a 1 V reference. INPUT AND REFERENCE OVERVIEW This will set the single-ended input of the AD9203 in the 2 V Like the voltage applied to the top of the resistor ladder in a span (2 × VREF). This example shows the AINN input is tied to flash A/D converter, the value VREF defines the maximum the 1 V VREF. This will configure the AD9203 to accept a 2 V input voltage to the A/D core. The minimum input voltage to input centered around 1 V. the A/D core is automatically defined to be −VREF. 2V AINP 0V The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional AINN REFTF 2V flash converters. The input stage allows the user to easily 0.1µF configure the inputs for either single-ended operation or ADC 10µF differential operation. The A/D’s input structure allows the dc CORE 0.1µF offset of the input signal to be varied independently of the input REFBF span of the converter. Specifically, the input to the A/D core is 1V 0.1µF the difference of the voltages applied at the AINP and AINN VREF + input pins. Therefore, the equation, 0.5V 10µF 0.1µF – V = AINP − AINN (1) CORE LOGIC defines the output of the differential input stage and provides REFSENSE AD9203 the input to the A/D core. Figure 19. Internal Reference Set for a 2 V Span The voltage, VCORE, must satisfy the condition, Figure 20 illustrates the input configured with a 0.5 V reference. −VREF ≤ V ≤ VREF (2) CORE This will set the single-ended input of the ADC in a 1 V span (2 × VREF). The AINN input is tied to the 0.5 VREF. This will where VREF is the voltage at the VREF pin. configure the AD9203 to accept a 1 V input centered around The actual span (AINP − AINN) of the ADC is ±VREF. 0.5 V. 1V While an infinite combination of AINP and AINN inputs exist AINP 0V that satisfy Equation 2, an additional limitation is placed on the AINN inputs by the power supply voltages of the AD9203. The power REFTF 1.75V supplies bound the valid operating range for AINP and AINN. 0.1µF The condition, ADC 10µF CORE 0.1µF AVSS − 0.3 V < AINP < AVDD + 0.3 V REFBF AVSS − 0.3 V < AINN < AVDD + 0.3 V (3) 1.25V 0.1µF VREF + where AVSS is nominally 0 V and AVDD is nominally 3 V, 0.5V 10µF 0.1µF defines this requirement. The range of valid inputs for AINP – and AINN is any combination that satisfies both Equations 2 and 3. LOGIC AD9203 REFSENSE INTERNAL REFERENCE CONNECTION Figure 20. Internal Reference Set for a 1 V Span A comparator within the AD9203 will detect the potential of the VREF pin. If REFSENSE is grounded, the reference Figure 21 shows the reference programmed by external resistors amplifier switch will connect to the resistor divider (see Figure for 0.75 V. This will set the ADC to receive a 1.5 V span 19). That will make VREF equal to 1 V. If resistors are placed centered about 0.75 V. The reference is programmed according between VREF, REFSENSE and ground, the switch will be to the algorithm: connected to the REFSENSE position and the reference VREF = 0.5 V × [1 + (RA/RB)] amplitude will depend on the external programming resistors (Figure 21). If REFSENSE is tied to VREF, the switch will also connect to REFSENSE and the reference voltage will be 0.5 V (Figure 20). REFTF and REFBF will drive the ADC conversion core and establish its maximum and minimum span. The range of the ADC will equal twice the voltage at the reference pin for either an internal or external reference. Rev. B | Page 12 of 28 00573-020 00573-019 AD9203 1.5V AINP CLAMP OPERATION 0V The AD9203 contains an internal clamp. It may be used when REFTF 1.875V AINN operating the input in a single-ended mode. This clamp is very 0.1µF useful for clamping NTSC and PAL video signals to ground. ADC 10µF The clamp cannot be used in the differential input mode. CORE 0.1µF REFBF 1.125V REFSENSE AD9203 0.1µF VREF + VREF 0.5V AINN 10µF 0.1µF – ADC C CORE IN R A AINP 1V p-p LOGIC AD9203 0V DC REFSENSE 50Ω TYP R B CLAMPIN CLAMP Figure 21. Programmable Reference Configuration SW1 EXTERNAL REFERENCE OPERATION Figure 22 illustrates the use of an external reference. An Figure 23. Clamp Configuration (VREF = 0.5 V) external reference may be necessary for several reasons. Tighter Figure 23 shows the internal clamp circuitry and the external reference tolerance will enhance the accuracy of the ADC and control signals needed for clamp operation. To enable the will allow lower temperature drift performance. When several clamp, apply a logic high 1 to the CLAMP pin. This will close ADCs track one another, a single reference (internal or SW1, the internal switch. SW1 is opened by asserting the external) will be necessary. The AD9203 will draw less power CLAMP pin low 0. The capacitor holds the voltage across C IN when an external reference is used. constant until the next interval. The charge on the capacitor will When the REFSENSE pin is tied to AVDD, the internal leak off as a function of input bias current (see Figure 24). reference will be disabled, allowing the use of an external 250 reference. 200 The AD9203 contains an internal reference buffer. It will load the external reference with an equivalent 10 kΩ load. The 150 internal buffer will generate positive and negative full-scale references for the ADC core. 100 In Figure 22, an external reference is used to set the midscale set point for single-ended use. At the same time, it sets the input 50 voltage span through a resistor divider. If the ADC is being driven differentially through a transformer, the external 0 reference can set the center tap (common-mode voltage). –50 3.0V 0 0.5 1.0 1.5 2.0 2.5 3.0 2.0V AINP INPUT VOLTAGE (V) 5V 1.0V AD9203 Figure 24. Input Bias Current vs. Input Voltage (F = 40 MSPS) S EXTERNAL AINN REF (2V) 0.1µF 10µF 0.1µF 1.5kΩ DRIVING THE ANALOG INPUT Figure 25 illustrates the equivalent analog input of the AD9203, A3 VREF 1V (a switched capacitor input). Bringing CLK to a logic high, opens S3 and closes S1 and S2. The input source connected to 1.5kΩ 0.1µF AVDD REFSENSE AIN and must charge Capacitor CH during this time. Bringing CLK to a logic low opens S2, and then S1 opens followed by closing S3. This puts the input in the hold mode. Figure 22. External Reference Configuration Rev. B | Page 13 of 28 00573-021 00573-022 INPUT BIAS (µA) 00573-024 00573-023 AD9203 C1 R1 AD9203 V AIN IN S1 R2 C H AD9203 C2 + V C BIAS P AVDD/2 – S3 S2 C C P H Figure 27. AC-Coupled Input The f–3 dB point can be approximated by the equation: Figure 25. Input Architecture f = 1/(2π × [R2] C ) The structure of the input SHA places certain requirements on −3dB EQ the input drive source. The combination of the pin capacitance, where C is the parallel combination of C1 and C2. Note that EQ CP, and the hold capacitance, CH, is typically less than 5 pF. The C1 is typically a large electrolytic or tantalum capacitor that input source must be able to charge or discharge this becomes inductive at high frequencies. Add a small ceramic or capacitance to 10-bit accuracy in one half of a clock cycle. polystyrene capacitor (on the order of 0.01 µF) that is negligibly When the SHA goes into track mode, the input source must inductive at higher frequencies while maintaining a low charge or discharge capacitor CH from the voltage already stored impedance over a wide frequency range. on C to the new voltage. In the worst case, a full-scale voltage H step on the input source must provide the charging current There are additional considerations when choosing the resistor through the R (100 Ω) of Switch 1 and quickly (within 1/2 ON values for an ac-coupled input. The ac-coupling capacitors CLK period) settle. This situation corresponds to driving a low integrate the switching transients present at the input of the input impedance. Adding series resistance between the output AD9203 and cause a net dc bias current, IB, to flow into the of the signal source and the AIN pin reduces the drive input. The magnitude of the bias current increases as the signal requirements placed on the signal source. Figure 26 shows this changes and as the clock frequency increases. This bias current configuration. The bandwidth of the particular application will result in an offset error of (R1 + R2) IB. If it is necessary to limits the size of this resistor. To maintain the performance compensate for this error, consider modifying VBIAS to outlined in the data sheet specifications, the resistor should be account for the resultant offset. In systems that must use dc limited to 50 Ω or less. The series input resistor can be used to coupling, use an op amp to level shift ground-referenced signals isolate the driver from the AD9203’s switched capacitor input. to comply with the input requirements of the AD9203. The external capacitor may be selected to limit the bandwidth OP AMP SELECTION GUIDE into the AD9203. Two input RC networks should be used to balance differential input drive schemes (Figure 26). Op amp selection for the AD9203 is highly application dependent. In general, the performance requirements of any The input span of the AD9203 is a function of the reference given application can be characterized by either time domain or voltage. For more information regarding the input range, see frequency domain constraints. In either case, one should the Internal Reference Connection and External Reference carefully select an op amp that preserves the performance of the Operation sections of the data sheet. A/D. This task becomes challenging when one considers the AD9203’s high performance capabilities coupled with other <50Ω AIN system level requirements such as power consumption and cost. V S AD9203 The ability to select the optimal op amp may be further complicated by either limited power supply availability and/or Figure 26. Simple AD9203 Drive Configuration limited acceptable supplies for a desired op amp. Newer, high performance op amps typically have input and output range In many cases, particularly in single-supply operation, ac limitations in accordance with their lower supply voltages. As a coupling offers a convenient way of biasing the analog input result, some op amps will be more appropriate in systems where signal to the proper signal range. Figure 27 shows a typical ac coupling is allowed. When dc coupling is required, the configuration for ac-coupling the analog input signal to the headroom constraints of op amps (such as rail-to-rail op amps) AD9203. Maintaining the specifications outlined in the data or ones where larger supplies can be used, should be sheet requires careful selection of the component values. The considered. most important is the f high-pass corner frequency. It is a –3 dB function of R2 and the parallel combination of C1 and C2. The following section describes some op amps currently available from Analog Devices. Please contact the factory or local sales office for updates on Analog Devices latest amplifier product offerings. Rev. B | Page 14 of 28 00573-026 00573-025 00573-027 AD9203 2V AD8051: f = 110 MHz. Low cost. Best used for driving –3 dB AINP 1V single-ended ac-coupled configuration. Operates on a 3 V power rail. AINN AD9203 AD8052: Dual Version of above amp. VREF 10µF 0.1µF AD8138 is a higher performance version of AD8131. Its gain is REFSENSE programmable and provides 14-bit performance. Figure 29. Transformer Coupled Input DIFFERENTIAL MODE OF OPERATION Since not all applications have a signal preconditioned for The center tap of the transformer provides a convenient means differential operation, there is often a need to perform a single- of level-shifting the input signal to a desired common-mode ended-to-differential conversion. In systems that do not need a voltage. Figure 30 illustrates the performance of the AD9203 dc input, an RF transformer with a center tap is one method to over a wide range of common-mode levels. generate differential inputs beyond 20 MHz for the AD9203. Transformers with other turns ratios may also be selected to This provides all the benefits of operating the A/D in the optimize the performance of a given application. For example, differential mode without contributing additional noise or selecting a transformer with a higher impedance ratio, such as distortion. An RF transformer also has the benefit of providing minicircuits T16–6T with an impedance ratio of 16, effectively electrical isolation between the signal source and the A/D. steps up the signal amplitude, thus further reducing the driving An improvement in THD and SFDR performance can be requirements of the signal source. realized by operating the AD9203 in differential mode. The The AD9203 can be easily configured for either a 1 V p-p or 2 V performance enhancement between the differential and single- p-p input span by setting the internal reference. Other input ended mode is greatest as the input frequency approaches and spans can be realized with two external gain setting resistors as goes beyond the Nyquist frequency (i.e., f > F /2). IN S shown in Figure 21 of this data sheet. Figure 34 and Figure 35 The AD8138 provides a convenient method of converting a demonstrate the SNR and SFDR performance over a wide range single-ended signal to a differential signal. This is an ideal of amplitudes required by most communication applications. method for generating a direct coupled signal to the AD9203. –80 The AD8138 will accept a signal and shift it to an externally 1.0V REF provided common-mode level. The AD8138 configuration is 0.5V REF –70 shown in Figure 28. 3V 3V 10µF 10µF –60 0.1µF 0.1µF 0.1µF 499Ω 10kΩ –50 28 2 6 499Ω 49.9Ω AVDD DRVDD 8 5 25 AINP 20pF DIGITAL 49.9Ω AD9203 –40 2 AD8138 OUTPUTS AINN 523Ω 49.9Ω 4 1 26 AVSS DRVSS 0.1µF 3 20pF 27 1 –30 10kΩ 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 499Ω COMMON-MODE VOLTAGE (V) Figure 28. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter Figure 30. THD vs. Common-Mode Voltage vs. THD (AIN = 2 V Differential) (fIN = 5 MHz, fS = 40 MSPS) Figure 29 shows the schematic of a suggested transformer circuit. The circuit uses a Minicircuits RF transformer, model number T4–1T, which has an impedance ratio of four (turns ratio of 2). Rev. B | Page 15 of 28 00573-028 THD (dB) 00573-029 00573-030 AD9203 –90 CLOCK INPUT AND CONSIDERATIONS The AD9203 internal timing uses the two edges of the clock –80 input to generate a variety of internal timing signals. Sampling THD occurs on the falling edge. The clock input to the AD9203 operating at 40 MSPS may have a duty cycle between 45% to –70 55% to meet this timing requirement since the minimum specified t and t is 11.25 ns. For clock rates below 40 MSPS, SNR CH CL –60 the duty cycle may deviate from this range to the extent that both tCH and tCL are satisfied. See Figure 31 for dynamics vs. –50 duty cycle. High-speed, high-resolution A/Ds are sensitive to the quality of –40 the clock input. The degradation in SNR at a given full-scale 40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 DUTY CYCLE (%) input frequency (f ) due only to aperture jitter (t ) can be IN A calculated with the following equation: Figure 31. THD and SNR vs. Clock Duty Cycle = 5 MHz Differential, Clock = 40 MSPS) (fIN SNR degradation = 20 log10 [1/2π fIN tA] In the equation, the rms aperture jitter, tA, represents the Table 5. Power Programming Resistance rootsum square of all the jitter sources, which include the clock Clock MSPS Resistor Value (k) input, analog input signal, and A/D aperture jitter specification. Undersampling applications are particularly sensitive to jitter. 1 50 Clock input should be treated as an analog signal in cases where 5 to 10 100 aperture jitter may affect the dynamic range of the AD9203. 15 to 20 200 Power supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the clock signal >20 500 with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing or another method), it POWER CONTROL should be retimed by the original clock at the last step. Power consumed by the AD9203 may be reduced by placing a The clock input is referred to the analog supply. Its logic resistor between the PWRCON pin and ground. This function threshold is AVDD/2. will be valuable to users who do not need the AD9203’s high conversion rate, but do need even lower power consumption. DIGITAL INPUTS AND OUTPUTS The external resistor sets the programming of the analog Each of the AD9203 digital control inputs, 3-STATE, DFS, and current mirrors. Table 5 illustrates the relationship between STBY are referenced to analog ground. CLK is also referenced programmed power and performance. to analog ground. A low power mode feature is provided such that for STBY = HIGH and the static power of the AD9203 At lower clock rates, less power is required within the analog drops to 0.65 mW. sections of the AD9203. Placing an external resistor on the PWRCON pin will shunt control current away from some of the Asserting the DFS pin high will invert the MSB pin, changing current mirrors. This enables the ADC to convert low data rates the data to a twos complement format. with extremely low power consumption. The AD9203 has an OTR (out of range) function. If the input INTERFACING TO 5 V SYSTEMS voltage is above or below full scale by 1 LSB, the OTR flag will The AD9203 can be integrated into 5 V systems. This is go high. See Figure 32. accomplished by deriving a 3 V power supply from the existing 5 V analog power line through an AD3307-3 linear regulator. Care must be maintained so that logic inputs do not exceed the maximum rated values listed on the Specifications page. Rev. B | Page 16 of 28 THD (dB) 00573-031 AD9203 OTR OTR DATA OUTPUTS 1 11111 11111 0 11111 11111 0 11111 11110 0 00000 00001 0 00000 00000 1 00000 00000 –FS +FS –FS + 1 LSB +FS – 1 LSB Figure 32. Output Data Format G1 = 20dB AD9203 G2 = 20dB BANDPASS SAW FILTER MINI CIRCUITS 50Ω FILTER OUTPUT T4-6T 50Ω 50Ω 1:4 AINP 200Ω 200Ω AINN 22.1Ω 93.1Ω AVDD/2 Figure 33. Simplified IF Sampling Circuit Rev. B | Page 17 of 28 00573-033 00573-032 AD9203 APPLICATIONS DIRECT IF DOWN CONVERSION The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC Sampling IF signals above an ADC’s baseband region (i.e., dc to for a narrowband IF sampling application. Both single tone and FS/2) is becoming increasingly popular in communication dual tone SFDR vs. amplitude are very useful in assessing an applications. This process is often referred to as direct IF down ADC’s dynamic and static nonlinearities. SNR vs. amplitude conversion or undersampling. There are several potential performance at the given IF is useful in assessing the ADC’s benefits in using the ADC to alias (or mix) down a narrow band noise performance and noise contribution due to aperture jitter. or wide band IF signal. First and foremost is the elimination of a In any application, one is advised to test several units of the complete mixer stage with its associated amplifiers and filters, same device under the same conditions to evaluate the given reducing cost and power dissipation. Second is the ability to applications sensitivity to that particular device. Figure 34 and apply various DSP techniques to perform such functions as Figure 35 combine the dual tone SFDR as well as single tone filtering, channel selection, quadrature demodulation, data SFDR and SNR performances at IF frequencies of 70 MHz, and reduction, detection, etc. A detailed discussion on using this 130 MHz. Note, the SFDR vs. amplitude data is referenced to technique in digital receivers can be found in Analog Devices dBFS while the single tone SNR data is referenced to dBc. The Application Notes AN-301 and AN-302. performance characteristics in these figures are representative In direct IF down conversion applications, one exploits the of the AD9203 without any preceding gain stage. The AD9203 inherent sampling process of an ADC in which an IF signal was operated in the differential mode (via transformer) with a lying outside the baseband region can be aliased back into the 2 V span and a sample rate of 40 MSPS. The analog supply baseband region in a manner similar to a mixer downconverting (AVDD) and the digital supply (DRVDD) were set to 3.0 V. an IF signal. Similar to the mixer topology, an image rejection 90 filter is required to limit other potential interfering signals from SFDR 2 TONE 80 also aliasing back into the ADC’s baseband region. 70 SFDR 1 TONE A trade-off exists between the complexity of this image 60 rejection filter and the ADC’s sample rate and dynamic range. 50 SNR The AD9203 is well suited for various IF sampling applications. 40 Its low distortion input SHA has a full-power bandwidth extending to 130 MHz, thus encompassing many popular IF 30 frequencies. Only the 2 V span should be used for 20 undersampling beyond 20 MHz. A DNL of ±0.25 LSB 10 combined with low thermal input referred noise allows the 0 AD9203 in the 2 V span to provide >59 dB of SNR for a 03 5 10 15 20 250 baseband input sine wave. Also, its low aperture jitter of 1.2 ps INPUT POWER LEVEL (dB FULL SCALE) rms ensures minimum SNR degradation at higher IF Figure 34. SNR/SFDR for IF @ 70 MHz (Clock = 40 MSPS) frequencies. In fact, the AD9203 is capable of still maintaining 80 58 dB of SNR at an IF of 70 MHz with a 2 V input span. SFDR 2 TONE 70 To maximize its distortion performance, the AD9203 should be 60 configured in the differential mode with a 2 V span using a SFDR 1 TONE transformer. The center-tap of the transformer is biased to the 50 reference output of the AD9203. Preceding the AD9203 and 40 transformer is an optional bandpass filter as well as a gain stage. SNR A low Q passive bandpass filter can be inserted to reduce out of 30 band distortion and noise that lies within the AD9203’s 390 20 MHz bandwidth. A large gain stage(s) is often required to compensate for the high insertion losses of a SAW filter used for 10 channel selection and image rejection. The gain stage will also 0 provide adequate isolation for the SAW filter from the charge 03 5 10 15 20 25 305 INPUT POWER LEVEL (dB FULL SCALE) kick back currents associated with the AD9203’s switched capacitor input stage. Figure 35. SNR/SFDR for IF @ 130 MHz (Clock = 40 MSPS) Rev. B | Page 18 of 28 SNR/SFDR (dB) SNR/SFDR (dB) 00573-035 00573-034 AD9203 AD9203 is powered from a 3 V supply rail while the high ULTRASOUND APPLICATIONS performance AD604 is powered from 5 V supply rails. An The AD9203 provides excellent performance in 10-bit AD8138 is used to drive the AD9203. This is implemented due ultrasound applications. This is demonstrated by its high SNR to the ability of differential drive techniques to cancel common- with analog input frequencies up to and including Nyquist. The mode noise and input anomalies. presence of spurs near the base of a fundamental frequency bin is demonstrated by Figure 37. Note that the spurs near the noise The 74 mW power consumption gives the 40 MSPS AD9203 an floor are more than 80 dB below f . This is especially valuable IN order of magnitude improvement over older generation in Doppler ultrasound applications where low frequency shifts components. from the fundamental are important. 10 FUND CONDITIONED SNR = 59.9dB 0 TRANSDUCER THD = –75dB SIGNAL SFDR = 82dB –10 SINGLE- 3V ANALOG ENDED AD9203 –20 INPUT ANALOG AINP –30 AD604 AD8138 TGC –40 AMPLIFIER AINN –50 GAIN –60 CONTROL –70 1.5V –80 3V –90 –100 Figure 36. Ultrasound Connection for the AD9203 –110 4.5E+6 4.7E+6 4.9E+6 5.1E+6 5.3E+6 5.5E+6 f IN Figure 36 illustrates the AD604 variable gain amplifier configured for time gain compensation (TGC). The low power Figure 37. SFDR Performance Near the Fundamental Signal (8192 Point FFT, fIN = 5 MHz, FS = 40 MSPS) Rev. B | Page 19 of 28 00573-036 dB 00573-037 AD9203 EVALUATION BOARD for single-ended and differential operation as well as 1 V and The AD9203 evaluation board is shipped wired for 2 V 2 V spans. Refer to Figure 39. differential operation. The board should be connected to power and test equipment as shown in Figure 38. It is easily configured 3V 3V 3V 3V +– –+ +– +– DRVDD GND +3-5D AVDD GND AVEE J1 SYNTHESIZER ANTI- ANALOG 1MHz 1.9V p-p ALIASING INPUT HP8644 FILTER OUTPUT DSP AD9203 WORD EQUIPMENT EVALUATION BOARD J5 SYNTHESIZER EXTERNAL 40MHz 1V p-p CLOCK HP8644 Figure 38. Evaluation Board Connection Rev. B | Page 20 of 28 00573-038 AD9203 Figure 39. Evaluation Board (Rev. C) Rev. B | Page 21 of 28 U6 98 R35 TP12 74LVX14 U6 U6 4.99Ω 1 U6 1 2 56 ASW6 R51 AVDD AVDD 11 10 49.9Ω JP50 2 JP51 74LVX14 74LVX14 12 CLK 74LVX14 12 AVDD 3 R34 DRVDD 1 C102 A B SW7 U6 2kΩ C16 U6 0.1µF 13 12 2 3 4 0.1µF TP1 3 U6 BYPASS R52 74LVX14 B C19 C30 74LVX14 49.9Ω 0.1µF 0.1µF 1 + 2 1 J5 1 + R36 2 2 C17 4.99kΩ C18 10µF 10µF R4 10V TP2 10V 49.9Ω C10 28 2 0.1µF AVDD DRVDD 13 OTR OTR 1 J4 15 3 CLK D0 D0 2 16 4 R53 3-STATE D1 D1 49.9Ω 17 5 STBY D2 D2 19 6 C3 CLAMP D3 D3 0.1µF 21 7 C5 C6 PWRCON D4 D4 10µF 0.1µF 22 8 REFTF D5 D5 10V R104 23 9 VREF D6 D6 10Ω U1 24 10 REFBF D7 D7 25 11 C4 R103 AINP D8 D8 0.1µF 10Ω 26 12 AINN D9 D9 JP64 20 1 2 CLAMP IN R102 AVDD JP2 14 1 2 TBD BY USER DFS R54 JP65 C100 C101 200kΩ 2 1 JP61 JP1 20pF 20pF 1 2 AD9203 2 1 R101 AVDD C9 18 TBD BY USER 1µF TP3 REFSENSE JP60 + 2 1 1 2 AVSS DRVSS JP63 JP53 10V 1 2 3 2 T1 1 A 27 1 4 JP54 1 2 R56 C11 B C34 C33 0.1µF 2 0.1µF 10µF TBD SW8 B 2 TPB 10V 2 BY USER 1 3 C12 J1 6 R55 JP8 JP58 JP59 2 2 1 0.1µF TBD P 2 1 1 A 1 BY USER C1 S 1 0.1µF R1 AVDD 49.9Ω JP26 2 1 C2 4.7µF R2 10V JP52 1 2 100Ω JP3 1 2 00573-039 + AD9203 Figure 40. Evaluation Board (Rev. C) Rev. B | Page 22 of 28 TP20 TP21 TP29 B2 B3 B1 RN1 L1 FBEAD L2 FBEAD L3 FBEAD 22Ω 2 2 2 1 1 1 1 14 1 1 1 DRVDD AVDD +3-5D 1 P1 P1 2 RN1 22Ω 2 13 C23 C25 C31 + + + 3 P1 P1 4 C22 C24 C32 10µF 33µF 10µF RN1 0.1µF 0.1µF 0.1µF 10V 16V 10V 22Ω 3 12 5 P1 P1 6 RN1 22Ω 11 4 7 P1 P1 8 RN1 22Ω 5 10 TP4 9 P1 P1 10 RN1 14 10 B4 D9 A1 L4 FBEAD B1 22Ω 6 9 15 9 2 11 P1 1 1 P1 12 D8 B2 A2 AVEE 16 8 RN1 D7 B3 A3 22Ω 8 17 7 7 D6 B4 U4 A4 13 P1 P1 14 C7 18 6 RN2 C8 D5 A5 B5 33µF 19 5 22Ω 0.1µF 14 1 16V D4 B6 A6 15 P1 P1 16 20 4 RN2 D3 B7 A7 21 3 22Ω 13 2 B8 A8 17 P1 P1 18 24 1 RN2 +3-5D DRVDD VCCB VCCA AVDD 23 2 22Ω 3 12 T/R C40 NC1 C20 19 P1 P1 20 C44 22 + 11 C45 RN2 0.1µF 0.1µF OE GD2 10µF 0.1µF 13 12 22Ω 4 11 10V GD1 GD3 21 P1 P1 22 RN2 R106 TBD 74LVXC4245WM 22Ω 5 10 B 23 P1 P1 24 4 R111 25 P1 P1 26 AGND3,4,5 R107 1Ω 3 8 1 B 1kΩ J12 V+ U3 14 10 27 P1 P1 28 2 2 D2 A1 B1 R112 OUT AD8131 15 9 R113 25Ω V– D1 B2 A2 1 50Ω 16 8 29 P1 P1 30 A D0 B3 A3 6 + C15 C13 R108 17 7 10µF LSB11 B4 U5 A4 5 0.1µF 1kΩ 18 6 10V 31 P1 LSB12 A5 P1 32 B5 19 5 RN2 OTR B6 A6 22Ω A 6 9 20 4 R105 CLK B7 A7 33 P1 P1 34 21 3 TBD B8 A8 24 1 AVSS DRVDD VCCB VCCA +3-5D 35 P1 P1 36 23 2 NC1 T/R C41 C21 C26 22 11 C14 0.1µF 0.1µF OE GD2 + 10µF 37 P1 P1 38 0.1µF 13 12 10V RN2 GD3 GD1 22Ω 7 8 39 P1 P1 40 74LVXC4245WM TP23 TP24 TP25 TP26 TP27 TP28 1 B6 1 B5 00573-040 AD9203 Figure 41. Evaluation Board Component Side Assembly (Not to Scale) Figure 42. Evaluation Board Component Side (Not to Scale) Figure 43. Evaluation Board Solder Side Assembly (Not to Scale) Rev. B | Page 23 of 28 00573-041 00573-043 00573-042 AD9203 Figure 44. Evaluation Board Solder Side (Not to Scale) Figure 45. Evaluation Board Ground Plane (Not to Scale) Figure 46. Evaluation Board Power Plane (Not to Scale) Rev. B | Page 24 of 28 00573-045 00573-046 00573-044 AD9203 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 SEATING COPLANARITY 0.19 0.09 0.45 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 47. 28-Lead Thin Shrink Small Outline Package (RU-28) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model Temperature Range Package Description Package Option AD9203ARU −40°C to +85°C 28-Lead Thin Shrink Small Outline RU-28 AD9203ARURL7 −40°C to +85°C 28-Lead Thin Shrink Small Outline RU-28 1 AD9203ARUZ −40°C to +85°C 28-Lead Thin Shrink Small Outline RU-28 1 AD9203ARUZRL7 −40°C to +85°C 28-Lead Thin Shrink Small Outline RU-28 AD9203-EB Evaluation Board 1 Z = Pb-free part. Rev. B | Page 25 of 28 AD9203 NOTES Rev. B | Page 26 of 28 AD9203 NOTES Rev. B | Page 27 of 28 AD9203 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00573–0–8/04(B) Rev. B | Page 28 of 28