ANALOG DEVICES AD9201

Dual Channel, 20 MHz 10-Bit a Resolution CMOS ADC AD9201 FUNCTIONAL BLOCK DIAGRAM FEATURES Complete Dual Matching ADCs AVDD AVSS DVDD DVSS CLOCK Low Power Dissipation: 215 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V IINA I AD9201 SLEEP "I" ADC REGISTER Differential Nonlinearity Error: 0.4 LSB IINB SELECT On-Chip Analog Input Buffers REFERENCE IREFB BUFFER On-Chip Reference IREFT THREE- Signal-to-Noise Ratio: 57.8 dB QREFB ASYNCHRONOUS STATE DATA QREFT MULTIPLEXER OUTPUT 10 BITS Over Nine Effective Bits BUFFER VREF Spurious-Free Dynamic Range: –73 dB 1V REFSENSE No Missing Codes Guaranteed CHIP SELECT 28-Lead SSOP QINB Q "Q" ADC REGISTER QINA PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD9201 is a complete dual channel, 20 MSPS, 10-bit 1. Dual 10-Bit, 20 MSPS ADCs CMOS ADC. The AD9201 is optimized specifically for applica- A pair of high performance 20 MSPS ADCs that are opti- tions where close matching between two ADCs is required (e.g., mized for spurious free dynamic performance are provided for I/Q channels in communications applications). The 20 MHz encoding of I and Q or diversity channel information. sampling rate and wide input bandwidth will cover both narrow- 2. Low Power band and spread-spectrum channels. The AD9201 integrates two Complete CMOS Dual ADC function consumes a low 10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal 215 mW on a single supply (on 3 V supply). The AD9201 voltage reference and multiplexed digital output buffers. operates on supply voltages from 2.7 V to 5.5 V. Each ADC incorporates a simultaneous sampling sample-and- 3. On-Chip Voltage Reference hold amplifier at its input. The analog inputs are buffered; no The AD9201 includes an on-chip compensated bandgap external input buffer op amp will be required in most applica- voltage reference pin programmable for 1 V or 2 V. tions. The ADCs are implemented using a multistage pipeline 4. On-chip analog input buffers eliminate the need for external architecture that offers accurate performance and guarantees no op amps in most applications. missing codes. The outputs of the ADCs are ported to a multi- plexed digital output buffer. 5. Single 10-Bit Digital Output Bus The AD9201 ADC outputs are interleaved onto a single The AD9201 is manufactured on an advanced low cost CMOS output bus saving board space and digital pin count. process, operates from a single supply from 2.7 V to 5.5 V, and consumes 215 mW of power (on 3 V supply). The AD9201 input 6. Small Package structure accepts either single-ended or differential signals, The AD9201 offers the complete integrated function in a providing excellent dynamic performance up to and beyond compact 28-lead SSOP package. its 10 MHz Nyquist input frequencies. 7. Product Family The AD9201 dual ADC is pin compatible with a dual 8-bit ADC (AD9281) and has a companion dual DAC product, the AD9761 dual DAC. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or Fax: 781/326-8703 © Analog Devices, Inc., 1999 otherwise under any patent or patent rights of Analog Devices. (AVDD = +3 V, DVDD = +3 V, F = 20 MSPS, VREF = 2 V, INB = 0.5 V, T to T SAMPLE MIN MAX, AD9201–SPECIFICATIONS internal ref, differential input signal, unless otherwise noted) Parameter Symbol Min Typ Max Units Condition RESOLUTION 10 Bits CONVERSION RATE F 20 MHz S DC ACCURACY Differential Nonlinearity DNL–0.4 LSB REFT = 1 V, REFB = 0 V Integral Nonlinearity INL 1.2 LSB Differential Nonlinearity (SE) DNL–0.5–1 LSB REFT = 1 V, REFB = 0 V Integral Nonlinearity (SE) INL–1.5–2.5 LSB Zero-Scale Error, Offset Error E–1.5–3.8 % FS ZS –3.5–5.4 % FS Full-Scale Error, Gain Error E FS Gain Match–0.5 LSB Offset Match–5 LSB ANALOG INPUT Input Voltage Range AIN –0.5 AVDD/2 V Input Capacitance C 2pF IN Aperture Delay t 4ns AP Aperture Uncertainty (Jitter) t 2ps AJ Aperture Delay Match 2 ps Input Bandwidth (–3 dB) BW Small Signal (–20 dB) 240 MHz Full Power (0 dB) 245 MHz INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode)–10 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Output Voltage Tolerance (2 V Mode)–15 mV Load Regulation (1 V Mode)–28 mV 1 mA Load Current Load Regulation (2 V Mode)–15 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V AVDD – DVDD £ 2.3 V DRVDD 2.7 3 5.5 V 71.6 mA AVDD = 3 V Supply Current I AVDD 0.1 mA I DRVDD 215 245 mW AVDD = DVDD = 3 V Power Consumption P D Power-Down 15.5 mW STBY = AVDD, Clock = AVSS Power Supply Rejection PSR 0.8 1.3 % FS 1 DYNAMIC PERFORMANCE Signal-to-Noise and Distortion SINAD f = 3.58 MHz 55.6 57.3 dB f = 10 MHz 55.8 dB Signal-to-Noise SNR f = 3.58 MHz 55.9 57.8 dB f = 10 MHz 56.2 dB Total Harmonic Distortion THD f = 3.58 MHz –69 –63.3 dB f = 10 MHz –66.3 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz –66 –73 dB f = 10 MHz –70.5 dB 2 Two-Tone Intermodulation Distortion IMD –62 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.1 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.05 % F = 14.3 MHz S Crosstalk Rejection 68 dB REV. D –2– AD9201 Parameter Symbol Min Typ Max Units Condition 3 DYNAMIC PERFORMANCE (SE) Signal-to-Noise and Distortion SINAD f = 3.58 MHz 52.3 dB Signal-to-Noise SNR f = 3.58 MHz 55.5 dB Total Harmonic Distortion THD f = 3.58 MHz –55 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz –58 dB DIGITAL INPUTS High Input Voltage V 2.4 V IH 0.3 V Low Input Voltage V IL –6mA DC Leakage Current I IN Input Capacitance C 2pF IN LOGIC OUTPUT (with DVDD = 3 V) High Level Output Voltage (I = 50 mA) V 2.88 V OH OH Low Level Output Voltage (I = 1.5 mA) V 0.095 V OL OL LOGIC OUTPUT (with DVDD = 5 V) High Level Output Voltage (I = 50 mA) V 4.5 V OH OH Low Level Output Voltage (I = 1.5 mA) V 0.4 V OL OL Data Valid Delay t 11 ns OD MUX Select Delay t 7ns MD Data Enable Delay t 13 ns C = 20 pF. Output Level to ED L 90% of Final Value Data High-Z Delay t 13 ns DHZ CLOCKING Clock Pulsewidth High t 22.5 ns CH 22.5 ns Clock Pulsewidth Low t CL Pipeline Latency 3.0 Cycles NOTES 1 AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V. 2 IMD referred to larger of two input signals. 3 SE is single ended input, REFT = 1.5 V, REFB = –0.5 V. Specifications subject to change without notice. t OD CLOCK INPUT ADC SAMPLE ADC SAMPLE ADC SAMPLE ADC SAMPLE ADC SAMPLE #1 #2 #3 #4 #5 SELECT t I CHANNEL Q CHANNEL MD INPUT OUTPUT ENABLED OUTPUT ENABLED SAMPLE #1-1 SAMPLE #1 SAMPLE #2 Q CHANNEL Q CHANNEL Q CHANNEL OUTPUT OUTPUT OUTPUT SAMPLE #1-3 SAMPLE #1-2 DATA Q CHANNEL Q CHANNEL OUTPUT OUTPUT OUTPUT SAMPLE #1-1 SAMPLE #1 I CHANNEL I CHANNEL OUTPUT OUTPUT Figure 1. ADC Timing REV. D –3– AD9201 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS With Pin Respect No. Name Description Parameter to Min Max Units 1 DVSS Digital Ground AVDD AVSS –0.3 +6.5 V 2 DVDD Digital Supply DVDD DVSS –0.3 +6.5 V 3 D0 Bit 0 (LSB) AVSS DVSS –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V 4 D1 Bit 1 CLK AVSS –0.3 AVDD + 0.3 V 5 D2 Bit 2 Digital Outputs DVSS –0.3 DVDD + 0.3 V 6 D3 Bit 3 AINA, AINB AVSS –1.0 AVDD + 0.3 V 7 D4 Bit 4 VREF AVSS –0.3 AVDD + 0.3 V 8 D5 Bit 5 REFSENSE AVSS –0.3 AVDD + 0.3 V 9 D6 Bit 6 REFT, REFB AVSS –0.3 AVDD + 0.3 V Junction Temperature +150 °C 10 D7 Bit 7 Storage Temperature –65 +150 °C 11 D8 Bit 8 Lead Temperature 12 D9 Bit 9 (MSB) 10 sec +300 °C 13 SELECT Hi I Channel Out, Lo Q Channel Out *Stresses above those listed under Absolute Maximum Ratings may cause perma- 14 CLOCK Clock nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational 15 SLEEP Hi Power Down, Lo Normal Operation sections of this specification is not implied. Exposure to absolute maximum ratings 16 INA-I I Channel, A Input for extended periods may effect device reliability. 17 INB-I I Channel, B Input 18 REFT-I Top Reference Decoupling, I Channel ORDERING GUIDE 19 REFB-I Bottom Reference Decoupling, I Channel Temperature Package Package 20 AVSS Analog Ground Model Range Description Options* 21 REFSENSE Reference Select AD9201ARS –40°C to +85°C 28-Lead SSOP RS-28 22 VREF Internal Reference Output AD9201-EVAL Evaluation Board 23 AVDD Analog Supply *RS = Shrink Small Outline. 24 REFB-Q Bottom Reference Decoupling, Q Channel 25 REFT-Q Top Reference Decoupling, Q Channel PIN CONFIGURATION 26 INB-Q Q Channel, B Input 27 INA-Q Q Channel, A Input DVSS CHIP-SELECT 28 CHIP-SELECT Hi-High Impedance, Lo-Normal Operation DVDD INA-Q INB-Q (LSB) D0 REFT-Q D1 DEFINITIONS OF SPECIFICATIONS REFB-Q D2 AD9201 AVDD INTEGRAL NONLINEARITY (INL) D3 TOP VIEW (Not to Scale) VREF Integral nonlinearity refers to the deviation of each individual D4 code from a line drawn from “zero” through “full scale.” The D5 REFSENSE AVSS point used as “zero” occurs 1/2 LSB before the first code tran- D6 REFB-I sition. “Full scale” is defined as a level 1 1/2 LSBs beyond the D7 last code transition. The deviation is measured from the center D8 REFT-I (MSB) D9 INB-I of each particular code to the true straight line. SELECT INA-I CLOCK DIFFERENTIAL NONLINEARITY (DNL, NO MISSING SLEEP CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. D –4– AD9201 AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS AVSS AVSS DRVSS AVSS AVSS AVSS a. D0–D9, OTR b. Three-State, Standby c. CLK AVDD AVDD AVDD AVDD AVDD IN REFBS AVSS AVDD AVSS REFBF AVSS AVSS AVSS AVSS d. INA, INB e. Reference f. REFSENSE g. VREF Figure 2. Equivalent Circuits scale. Gain error is the deviation of the actual difference be- OFFSET ERROR tween first and last code transitions and the ideal difference The first transition should occur at a level 1 LSB above “zero.” between the first and last code transitions. Offset is defined as the deviation of the actual first code transi- tion from that point. GAIN MATCH The change in gain error between I and Q channels. OFFSET MATCH The change in offset error between I and Q channels. PIPELINE DELAY (LATENCY) The number of clock cycles between conversion initiation and EFFECTIVE NUMBER OF BITS (ENOB) the associated output data being made available. New output For a sine wave, SINAD can be expressed in terms of the num- data is provided every rising clock edge. ber of bits. Using the following formula, N = (SINAD – 1.76)/6.02 MUX SELECT DELAY It is possible to get a measure of performance expressed as N, The delay between the change in SELECT pin data level and the effective number of bits. valid data on output pins. Thus, effective number of bits for a device for sine wave inputs POWER SUPPLY REJECTION at a given input frequency can be calculated directly from its The specification shows the maximum change in full scale from measured SINAD. the value with the supply at the minimum limit to the value with the supply at its maximum limit. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- APERTURE JITTER ponents to the rms value of the measured input signal and Aperture jitter is the variation in aperture delay for successive is expressed as a percentage or in decibels. samples and is manifested as noise on the input to the A/D. SIGNAL-TO-NOISE RATIO (SNR) APERTURE DELAY SNR is the ratio of the rms value of the measured input signal to Aperture delay is a measure of the Sample-and-Hold Amplifier the rms sum of all other spectral components below the Nyquist (SHA) performance and is measured from the rising edge of the frequency, excluding the first six harmonics and dc. The value clock input to when the input signal is held for conversion. for SNR is expressed in decibels. SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) SPURIOUS FREE DYNAMIC RANGE (SFDR) RATIO The difference in dB between the rms amplitude of the input S/N+D is the ratio of the rms value of the measured input signal signal and the peak spurious signal. to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. GAIN ERROR The value for S/N+D is expressed in decibels. The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full REV. D –5– AD9201–Typical Characteristic Curves (AVDD = +3 V, DVDD = +3 V, F = 20 MHz (50% duty cycle), 2 V input span from –0.5 V to S +1.5 V, 2 V internal reference unless otherwise noted) 1.5 65 60 –0.5dB 1.0 55 0.5 –6dB 0 50 45 –0.5 –20dB 40 –1.0 35 –1.5 0 128 256 384 512 640 768 896 1024 1.00E+05 1.00E+06 1.00E+07 1.00E+08 INPUT FREQUENCY – Hz CODE OFFSET Figure 6. SNR vs. Input Frequency Figure 3. Typical INL (1 V Internal Reference) 1 65 60 –0.5dB 0.5 55 –6dB 0 50 45 –0.5 –20dB 40 –1.0 35 0 128 256 384 512 640 896 1024 768 1.00E+05 1.00E+06 1.00E+07 1.00E+08 CODE OFFSET INPUT FREQUENCY – Hz Figure 4. Typical DNL (1 V Internal Reference) Figure 7. SINAD vs. Input Frequency 1.00 –30 0.80 –35 0.60 –40 0.40 –45 –20dB 0.20 –50 0.00 –55 –6dB –0.20 –60 –0.40 –65 –0.5dB –0.60 –70 –0.80 –75 –1.00 –80 –1.0 –0.5 0 0.5 1.0 1.5 2.0 1.00E+05 1.00E+06 1.00E+07 1.00E+08 INPUT VOLTAGE – V INPUT FREQUENCY – Hz Figure 8. THD vs. Input Frequency Figure 5. Input Bias Current vs. Input Voltage REV. D –6– I – nA B INL DNL THD – dB SINAD – dB SNR – dB AD9201 –75 1.20E+07 10000000 1.00E+07 –70 8.00E+06 –65 6.00E+06 –60 4.00E+06 –55 2.00E+06 255100 150400 –50 0.00E+00 1.00E+06 1.00E+07 1.00E+08 N–1 N N+1 CLOCK FREQUENCY – Hz CODE Figure 9. THD vs. Clock Frequency (f = 1 MHz) IN Figure 12. Grounded Input Histogram 1.012 0 –3 1.011 –6 –9 1.010 –12 1.009 –15 –18 1.008 –21 –24 1.007 –27 1.006 –30 –40 –20 020 40 60 80 100 1.00E+06 1.00E+07 1.00E+08 1.00E+09 TEMPERATURE – 8C INPUT FREQUENCY – Hz Figure 10. Voltage Reference Error vs. Temperature Figure 13. Full Power Bandwidth 220 60 –0.5dB 215 55 210 –6.0dB 205 50 200 45 195 190 40 –20.0dB 185 180 35 026 4 8 10 12 14 1618 20 1.00E+05 1.00E+07 1.00E+08 1.00E+06 CLOCK FREQUENCY – MHz INPUT FREQUENCY – Hz Figure 11. Power Consumption vs. Clock Frequency Figure 14. SNR vs. Input Frequency (Single Ended) REV. D –7– V – V REF POWER CONSUMPTION – mW THD – dB HITS AMPLITUDE – dB SNR – dB AD9201 10 The AD9201 also includes an on-chip bandgap reference and FUND 0 reference buffer. The reference buffer shifts the ground-referred –10 reference to levels more suitable for use by the internal circuits –20 of the converter. Both converters share the same reference and –30 reference buffer. This scheme provides for the best possible gain –40 match between the converters while simultaneously minimizing –50 the channel-to-channel crosstalk. (See Figure 16.) –60 Each A/D converter has its own output latch, which updates on 5TH –70 6TH 2ND 4TH the rising edge of the input clock. A logic multiplexer, con- 7TH 3RD –80 9TH 8TH trolled through the SELECT pin, determines which channel is –90 passed to the digital output pins. The output drivers have their –100 own supply (DVDD), allowing the part to be interfaced to a –110 variety of logic families. The outputs can be placed in a high –120 impedance state using the CHIP SELECT pin. 0.0E+0 1.0E+6 2.0E+6 3.0E+6 4.0E+6 5.0E+6 6.0E+6 7.0E+6 8.0E+6 9.0E+6 10.0E+6 10 The AD9201 has great flexibility in its supply voltage. The FUND 0 analog and digital supplies may be operated from 2.7 V to 5.5 V, –10 independently of one another. –20 –30 ANALOG INPUT –40 Figure 16 shows an equivalent circuit structure for the analog –50 input of one of the A/D converters. PMOS source-followers –60 buffer the analog input pins from the charge kickback problems 5TH 6TH –70 4TH normally associated with switched capacitor ADC input struc- 7TH 8TH 9TH 3RD –80 2ND tures. This produces a very high input impedance on the part, –90 allowing it to be effectively driven from high impedance sources. –100 This means that the AD9201 could even be driven directly by a –110 passive antialias filter. –120 0.0E+0 1.0E+6 2.0E+6 3.0E+6 4.0E+6 5.0E+6 6.0E+6 7.0E+6 8.0E+6 9.0E+6 10.0E+6 Figure 15. Simultaneous Operation of I and Q Channels IINA (Differential Input) BUFFER OUTPUT WORD ADC THEORY OF OPERATION CORE SHA +FS –FS The AD9201 integrates two A/D converters, two analog input LIMIT LIMIT buffers, an internal reference and reference buffer, and an out- IINB BUFFER put multiplexer. For clarity, this data sheet refers to the two +FS LIMIT = –FS LIMIT = converters as “I” and “Q.” The two A/D converters simulta- V +V V –V REF REF/2 REF REF/2 neously sample their respective inputs on the rising edge of the input clock. The two converters distribute the conversion opera- V REF tion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the result from Figure 16. Equivalent Circuit for AD9201 Analog Inputs stage to stage. As a consequence of the distributed conversion, The source followers inside the buffers also provide a level-shift each converter requires a small fraction of the 1023 comparators function of approximately 1 V, allowing the AD9201 to accept used in a traditional flash-type 10-bit ADC. A sample-and-hold inputs at or below ground. One consequence of this structure is function within each of the stages permits the first stage to oper- that distortion will result if the analog input approaches the ate on a new input sample while the following stages continue to positive supply. For optimum high frequency distortion perfor- process previous samples. This results in a “pipeline processing” mance, the analog input signal should be centered according latency of three clock periods between when an input sample is to Figure 29. taken and when the corresponding ADC output is updated into The capacitance load of the analog input Pin is 4 pF to the the output registers. analog supplies (AVSS, AVDD). The AD9201 integrates input buffer amplifiers to drive the Full-scale setpoints may be calculated according to the following analog inputs of the converters. In most applications, these algorithm (V may be internally or externally generated): input amplifiers eliminate the need for external op amps for the REF input signals. The input structure is fully differential, but the –F = (V – V /2) S REF REF SHA common-mode response has been designed to allow the +F = (V + V /2) S REF REF converter to readily accommodate either single-ended or differ- V = V SPAN REF ential input signals. This differential structure makes the part capable of accommodating a wide range of input signals. REV. D –8– Q CHANNEL I CHANNEL AD9201 The AD9201 can accommodate a variety of input spans be- AC Coupled Inputs tween 1 V and 2 V. For spans of less than 1 V, expect a propor- If the signal of interest has no dc component, ac coupling can be tionate degradation in SNR . Use of a 2 V span will provide the easily used to define an optimum bias point. Figure 18 illus- best noise performance. 1 V spans will provide lower distortion trates one recommended configuration. The voltage chosen for when using a 3 V analog supply. Users wishing to run with the dc bias point (in this case the 1 V reference) is applied to larger full-scales are encouraged to use a 5 V analog supply both IINA and IINB pins through 1 kW resistors (R1 and R2). (AVDD). IINA is coupled to the input signal through Capacitor C1, while IINB is decoupled to ground through Capacitor C2 and C3. Single-Ended Inputs: For single-ended input signals, the signal is applied to one input pin and the other input pin is tied Transformer Coupled Inputs to a midscale voltage. This midscale voltage defines the center Another option for input ac coupling is to use a transformer. of the full-scale span for the input signal. This not only provides dc rejection, but also allows truly differ- ential drive of the AD9201’s analog inputs, which will provide EXAMPLE: For a single-ended input range from 0 V to 1 V the optimal distortion performance. Figure 19 shows a recom- applied to IINA, we would configure the converter for a 1 V mended transformer input drive configuration. Resistors R1 and reference (See Figure 17) and apply 0.5 V to IINB. R2 define the termination impedance of the transformer coupling. The center tap of the transformer secondary is tied to the com- 1V mon-mode reference, establishing the dc bias point for the ana- 0V 0.1mF log inputs. INPUT IINA I OR QREFT 10mF 0.1mF MIDSCALE VOLTAGE IINB I OR QREFB = 0.5V IINA QINA 10mF 0.1mF 0.1mF R1 R2 AD9201 5kV 5kV IINB QINB VREF AD9201 0.1mF REFSENSE COMMON MODE I OR QREFT VOLTAGE 0.1mF10mF 10mF 0.1mF VREF I OR QREFB 0.1mF 10mF 0.1mF REFSENSE Figure 17. Example Configuration for 0 V–1 V Single- Ended Input Signal Figure 19. Example Configuration for Transformer Note that since the inputs are high impedance, this reference Coupled Inputs level can easily be generated with an external resistive divider Crosstalk: The internal layout of the AD9201, as well as its with large resistance values (to minimize power dissipation). A pinout, was configured to minimize the crosstalk between the decoupling capacitor is recommended on this input to minimize two input signals. Users wishing to minimize high frequency the high frequency noise-coupling onto this pin. Decoupling crosstalk should take care to provide the best possible decoupling should occur close to the ADC. for input pins (see Figure 20). R and C values will make a pole Differential Inputs dependant on antialiasing requirements. Decoupling is also Use of differential input signals can provide greater flexibility in required on reference pins and power supplies (see Figure 21). input ranges and bias points, as well as offering improvements in distortion performance, particularly for high frequency input signals. Users with differential input signals will probably want IINA QINA to take advantage of the differential input structure. AD9201 IINB QINB 1.5V 0.1mF 0.5V REFT C1 ANALOG Figure 20. Input Loading IINA 0.1mF 10mF INPUT R1 1kV REFB 0.1mF IINB V ANALOG V DIGITAL C2 C3 AD9201 1.0mF 0.1mF AVDD DVDD VREF 0.1mF 10mF 0.1mF 10mF REFSENSE AD9201 I OR QREFT Figure 18. Example Configuration for 0.5 V–1.5 V ac 0.1mF 0.1mF10mF Coupled Single-Ended Inputs I OR QREFB 0.1mF Figure 21. Reference and Power Supply Decoupling REV. D –9– AD9201 REFERENCE AND REFERENCE BUFFER Externally Set Voltage Mode (Figure 24)—this mode uses The reference and buffer circuitry on the AD9201 is configured the on-chip reference, but scales the exact reference level though for maximum convenience and flexibility. An illustration of the the use of an external resistor divider network. VREF is wired to equivalent reference circuit is show in Figure 26. The user can the top of the network, with the REFSENSE wired to the tap select from five different reference modes through appropriate point in the resistor divider. The reference level (and input full pin-strapping (see Table I below). These pin strapping options scale) will be equal to 1 V · (R1 + R2)/R1. This method can be cause the internal circuitry to reconfigure itself for the appropri- used for voltage levels from 0.7 V to 2.5 V. ate operating mode. 1mF Table I. Table of Modes 0.1mF 1V + Mode Input Span REFSENSE Pin Figure + – VREF – 1 V 1 V VREF 22 R2 REFSENSE 2 V 2 V AGND 23 R1 Programmable 1 + (R1/R2) See Figure 24 0.1mF AVSS I OR QREFT External = External Ref AVDD 25 R2 0.1mF10mF VREF = 1 + R1 1 V Mode (Figure 22)—provides a 1 V reference and 1 V input I OR QREFB AD9201 0.1mF full scale. Recommended for applications wishing to optimize high frequency performance, or any circuit on a supply voltage Figure 24. Programmable Reference of less than 4 V. The part is placed in this mode by shorting the REFSENSE pin to the VREF pin. External Reference Mode (Figure 25)—in this mode, the on- chip reference is disabled, and an external reference is applied to 1V 1V the VREF pin. This mode is achieved by tying the REFSENSE pin to AVDD. 0V 0V IINA QINA 5kV 1V 1V QINB IINB 10mF 0.1mF 0V 0V IINA QINA 5kV AD9201 5kV 1V QINB IINB VREF 0.1mF 10mF REFSENSE 0.1mF AD9201 5kV I OR QREFT 1V EXT 10mF 0.1mF VREF 0.1mF10mF 0.1mF REFERENCE I OR QREFT I OR QREFB 10mF 0.1mF 0.1mF 0.1mF10mF I OR QREFB Figure 22. 0 V to 1 V Input 0.1mF AVDD REFSENSE 2 V Mode (Figure 23)—provides a 2 V reference and 2 V input full scale. Recommended for noise sensitive applications on 5 V Figure 25. External Reference supplies. The part is placed in 2 V reference mode by grounding Reference Buffer—The reference buffer structure takes the (shorting to AVSS) the REFSENSE pin. voltage on the VREF pin and level-shifts and buffers it for use by various subblocks within the two A/D converters. The two 2V 2V converters share the same reference buffer amplifier to maintain 0V 0V the best possible gain match between the two converters. In the IINA QINA interests of minimizing high frequency crosstalk, the buffered 5kV IINB QINB references for the two converters are separately decoupled on 10mF 0.1mF the IREFB, IREFT, QREFB and QREFT pins, as illustrated in AD9201 5kV Figure 26. VREF 0.1mF I OR QREFT 10mF 0.1mF 0.1mF10mF I OR QREFB 0.1mF REFSENSE Figure 23. 0 V to 2 V Input REV. D –10– AD9201 VREF ADC 22V CORE 17 10pF 0.1mF 0.1mF QREFT 1kV IREFT AD8051 ADC 3 0.33mF 16 10mF 0.1mF 0.1mF 10mF 24V 22V 6 50V 2 10pF IREFB 1V QREFB 1kV 0.1mF 0.1mF 0.01mF VREF 1kV 10mF 0.1mF 10kV REFSENSE Figure 27. INTERNAL CONTROL 10kV 10 LOGIC FUND 0 AVSS AD9201 –10 –20 Figure 26. Reference Buffer Equivalent Circuit and Exter- –30 nal Decoupling Recommendation –40 For best results in both noise suppression and robustness –50 2ND 3RD against crosstalk, the 4 capacitor buffer decoupling arrangement –60 shown in Figure 26 is recommended. This decoupling should –70 6TH 7TH 4TH 5TH 8TH feature chip capacitors located close to the converter IC. The –80 capacitors are connected to either IREFT/IREFB or QREFT/ –90 QREFB. A connection to both sides is not required. –100 –110 DRIVING THE AD9201 –120 0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 Figure 27 illustrates the use of an AD8051 to drive the AD9201. 1.0E+6 3.0E+6 5.0E+6 7.0E+6 9.0E+6 Even though the AD8051 is specified with 3 V and 5 V power, Figure 28. AD8051/AD9201 Performance the best results are obtained at –5 V power. The ADC input span is 2 V. REV. D –11– AD9201 Inspection of the curves will yield the following conclusions: COMMON-MODE PERFORMANCE Attention to the common-mode point of the analog input volt- 1. An AD9201 running with AVDD = 5 V is the easiest to age can improve the performance of the AD9201. Figure 29 drive. illustrates THD as a function of common-mode voltage (center 2. Differential inputs are the most insensitive to common-mode point of the analog input span) and power supply. voltage. 3. An AD9201 powered by AVDD = 3 V and a single ended input, should have a 1 V span with a common-mode voltage of 0.75 V. –10 –30 2V SPAN –35 –20 2V SPAN –40 –30 –45 –50 –40 –55 –50 –60 1V SPAN 1V SPAN –65 –60 –70 –70 –75 –80 –80 –0.5 0 0.5 1.0 1.5 –0.5 0 0.5 1.0 1.5 COMMON-MODE LEVEL – V COMMON-MODE LEVEL – V a. Differential Input, 3 V Supplies c. Single-Ended Input, 3 V Supplies –30 –10 –35 –20 –40 2V SPAN –45 –30 –50 –40 2V SPAN –55 –50 –60 –65 –60 –70 1V SPAN 1V SPAN –70 –75 –80 –80 –0.5 0 0.5 1.0 1.5 2.0 2.5 –0.5 0 0.5 1.0 1.5 2.0 2.5 COMMON-MODE LEVEL – V COMMON-MODE LEVEL – V b. Differential Input, 5 V Supplies d. Single-Ended Input, 5 V Supplies Figure 29. THD vs. CML Input Span and Power Supply (Analog Input = 1 MHz) REV. D –12– THD – dB THD – dB THD – dB THD – dB AD9201 DIGITAL INPUTS AND OUTPUTS SELECT Each of the AD9201 digital control inputs, CHIP SELECT, When the select pin is held LOW, the output word will present CLOCK, SELECT and SLEEP are referenced to AVDD and the “Q” level. When the select pin is held HIGH, the “I” level AVSS. Switching thresholds will be AVDD/2. will be presented to the output word (see Figure 1). The format of the digital output is straight binary. A low power The AD9201’s select and clock pins may be driven by a com- mode feature is provided such that for STBY = HIGH and the mon signal source. The data will change in 5 ns to 11 ns after clock disabled, the static power of the AD9201 will drop below the edges of the input pulse. The user must make sure the inter- 22 mW. face latches have sufficient hold time for the AD9201’s delays (see Figure 30). CLOCK INPUT The AD9201 clock input is internally buffered with an inverter CLOCK powered from the AVDD pin. This feature allows the AD9201 CLOCK I LATCH I to accommodate either +5 V or +3.3 V CMOS logic input sig- SOURCE PROCESSING SELECT DATA nal swings with the input threshold for the CLK pin nominally DATA at AVDD/2. CLK OUT DATA The pipelined architecture of the AD9201 operates on both Q Q LATCH rising and falling edges of the input clock. To minimize duty PROCESSING cycle variations the logic family recommended to drive the clock CLOCK input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 20 MSPS Figure 30. Typical De-Mux Connection operation. Running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, APPLICATIONS some slight performance improvements might be realized by USING THE AD9201 FOR QAM DEMODULATION clocking the AD9201 at slower clock rates. QAM is one of the most widely used digital modulation schemes The power dissipated by the output buffers is largely propor- in digital communication systems. This modulation technique tional to the clock frequency; running at reduced clock rates can be found in both FDMA as well as spread spectrum (i.e., provides a reduction in power consumption. CDMA) based systems. A QAM signal is a carrier frequency which is both modulated in amplitude (i.e., AM modulation) DIGITAL OUTPUTS and in phase (i.e., PM modulation). At the transmitter, it can Each of the on-chip buffers for the AD9201 output bits (D0–D9) be generated by independently modulating two carriers of iden- is powered from the DVDD supply pin, separate from AVDD. tical frequency but with a 90° phase difference. This results in The output drivers are sized to handle a variety of logic families an inphase (I) carrier component and a quadrature (Q) carrier while minimizing the amount of glitch energy generated. In all component at a 90° phase shift with respect to the I component. cases, a fan-out of one is recommended to keep the capacitive The I and Q components are then summed to provide a QAM load on the output data bits below the specified 20 pF level. signal at the specified carrier or IF frequency. Figure 31 shows a typical analog implementation of a QAM modulator using a For DVDD = 5 V, the AD9201 output signal swing is compat- dual 10-bit DAC with 2· interpolation, the AD9761. A QAM ible with both high speed CMOS and TTL logic families. For signal can also be synthesized in the digital domain thus requir- TTL, the AD9201 on-chip, output drivers were designed to ing a single DAC to reconstruct the QAM signal. The AD9853 support several of the high speed TTL families (F, AS, S). For is an example of a complete (i.e., DAC included) digital QAM applications where the clock rate is below 20 MSPS, other TTL modulator. families may be appropriate. For interfacing with lower voltage CMOS logic, the AD9201 sustains 20 MSPS operation with DVDD = 3 V. In all cases, check your logic family data sheets IOUT for compatibility with the AD9201’s Specification table. DSP 10 TO CARRIER 0 OR A 2 ns reduction in output delays can be achieved by limiting AD9761 MIXER FREQUENCY 90 ASIC the logic load to 5 pF per output line. QOUT THREE-STATE OUTPUTS NYQUIST QUADRATURE FILTERS MODULATOR The digital outputs of the AD9201 can be placed in a high impedance state by setting the CHIP SELECT pin to HIGH. Figure 31. Typical Analog QAM Modulator Architecture This feature is provided to facilitate in-circuit testing or evaluation. REV. D –13– AD9201 At the receiver, the demodulation of a QAM signal back into its These characteristics result in both a reduction of electro- separate I and Q components is essentially the modulation pro- magnetic interference (EMI) and an overall improvement in cess explain above but in the reverse order. A common and performance. traditional implementation of a QAM demodulator is shown in It is important to design a layout that prevents noise from cou- Figure 32. In this example, the demodulation is performed in pling onto the input signal. Digital signals should not be run in the analog domain using a dual, matched ADC and a quadra- parallel with the input signal traces and should be routed away ture demodulator to recover and digitize the I and Q baseband from the input circuitry. Separate analog and digital grounds signals. The quadrature demodulator is typically a single IC should be joined together directly under the AD9201 in a solid containing two mixers and the appropriate circuitry to generate ground plane. The power and ground return currents must be the necessary 90° phase shift between the I and Q mixers’ local carefully managed. A general rule of thumb for mixed signal oscillators. Before being digitized by the ADCs, the mixed layouts dictates that the return currents from digital circuitry down baseband I and Q signals are filtered using matched ana- should not pass through critical analog circuitry. log filters. These filters, often referred to as Nyquist or Pulse- Transients between AVSS and DVSS will seriously degrade Shaping filters, remove images-from the mixing process and any performance of the ADC. out-of-band. The characteristics of the matching Nyquist filters are well defined to provide optimum signal-to-noise (SNR) If the user cannot tie analog ground and digital ground together performance while minimizing intersymbol interference. The at the ADC, he should consider the configuration in Figure 33. ADC’s are typically simultaneously sampling their respective inputs at the QAM symbol rate or, most often, at a multiple of it LOGIC AVDD SUPPLY DVDD if a digital filter follows the ADC. Oversampling and the use of digital filtering eases the implementation and complexity of the A A D analog filter. It also allows for enhanced digital processing for both carrier and symbol recovery and tuning purposes. The use ADC of a dual ADC such as the AD9201 ensures excellent gain, DIGITAL IC LOGIC C STRAY offset, and phase matching between the I and Q channels. ICs ANALOG DIGITAL CIRCUITS CIRCUITS V IN I B A ADC C A STRAY I I A D FROM DSP CARRIER LO PREVIOUS OR FREQUENCY 90°C STAGE GND ASIC AVSS DVSS Q = ANALOG A DV ADC A A D = DIGITAL NYQUIST D QUADRATURE FILTERS DUAL MATCHED DEMODULATOR ADC Figure 33. Ground and Power Consideration Figure 32. Typical Analog QAM Demodulator Another input and ground technique is shown in Figure 34. A separate ground plane has been split for RF or hard to manage GROUNDING AND LAYOUT RULES signals. These signals can be routed to the ADC differentially or As is the case for any high performance device, proper ground- single ended (i.e., both can either be connected to the driver or ing and layout techniques are essential in achieving optimal RF ground). The ADC will perform well with several hundred performance. The analog and digital grounds on the AD9201 mV of noise or signals between the RF and ADC analog ground. have been separated to optimize the management of return currents in a system. Grounds should be connected near the RF ANALOG DIGITAL ADC. It is recommended that a printed circuit board (PCB) of GROUND GROUND GROUND at least four layers, employing a ground plane and power planes, be used with the AD9201. The use of ground and power planes offers distinct advantages: ADC LOGIC DATA 1. The minimization of the loop area encompassed by a signal AIN and its return path. BIN - 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. Figure 34. RF Ground Scheme REV. D –14– AD9201 EVALUATION BOARD The AD9201 evaluation board is shipped “ready to run.” Power and signal generators should be connected as shown in Figure 35. Then the user can observe the performance of the Q channel. If the user wants to observe the I channel, then he should install a jumper at JP22 Pins 1 and 2. If the user wants to toggle between I and Q channels, then a CMOS level pulse train should be applied to the “strobe” jack after appropriate jumper connections. +3V +3V +5V AGND AVDD DGND1 DVDD DGND2 DRVDD SYNTHESIZER CLOCK 20MHz 2Vp-p DSP P1 EQUIPMENT AD9201 SYNTHESIZER ANTI- 1MHz ALIAS Q IN 1Vp-p FILTER Figure 35. Evaluation Board Connections REV. D –15– REV – 9201EB – C29 C52 C54 C55 C4 C35 +C5 +C36 AD9201 R50 R51 C50 C14 C51 C14 C20 C17 C22 C23 C27 C24 C53 R52 R53 (NOT TO SCALE) Figure 36. Evaluation Board Solder-Side Silkscreen (NOT TO SCALE) Figure 37. Evaluation Board Component-Side Layout REV. D –16– AD9201 (NOT TO SCALE) Figure 38. Evaluation Board Ground Plane Layout (NOT TO SCALE) Figure 39. Evaluation Board Solder-Side Layout REV. D –17– AD9201 I_IN STROBE AGND AVDD CLOCK DGND1 DVDD DGND2 DBVDD C40 BJ4 BJ3 BJ6 BJ5 AGND BJ2 BJ1 J1 J5 J6 AVDD C42 + R38 L2 L3 + C43 L4 + C46 C38 C45 C44 C41 C48 C47 JP16 JP22 R37 R36 R13 JP17 V8 JP19 R11 TP4 JP15 JP21 R32 TP7 JP3 T1 P1 JP13 C7 4 RN1 TP2 V1 C15 TP1 + JP20 C1 JP2 JP1 C3 JP7 C2 C6 J3 JP9 JP10 T2 4 C13 + C25 JP14 RN2 C34 V2 TP5 TP6 V4 R18 C10 C37 JP12JP11 C9 R16 C31 + R14 L5 + R17 R24 JP4 V6 JP6 C32 JP5 R23 + R6 C11 D1 TP3 R7 R10 AGND R8 V3 J4 R12 Q_IN (NOT TO SCALE) Figure 40. Evaluation Board Component-Side Silkscreen (NOT TO SCALE) Figure 41. Evaluation Board Power Plane Layout REV. D –18– R30 R34 R2 R9 R35 R1 C21 C12 R40 R4 R31 R33 C8 C33 C24 + C19 DGND R39 C30 C49 + DBVDD AD9201 Figure 42. Evaluation Board REV. D –19– U1 8 AVDD 16 L2 L3 DVDD B A FERRITE BEAD FERRITE BEAD 9 APWRIN DPWRIN 15 AVDD VCC DVDD BJ3 BJ1 B A 1 1 AVDD DVDD BANA D5 21 3 BD5 BANA C41 C42 C44 C45 B A C40 C43 BD6 D6 20 4 10_10V CAP_NP CAP_NP 10_10V CAP_NP CAP_NP GND BJ4 B A BJ2 1 AGND 1 DGND RESISTOR 5 BD7 BANA D7 19 BANA B A 7PACK J5 6 BD8 D8 18 P1 B A RN1A BNC STROBE L4 DRVDD BD9 D9 17 7 13 31 FERRITE BEAD B A 14 DPWRIN 1 DRVDD 30 BJ5 R37 14 10 RN1B 1 DRVDD B A 4 BANA R-S 49.9V DRVDD 11 DVDD C46 C47 C48 24 1 13 2 2 VCCB VCCA T1 10_10V CAP_NP CAP_NP RN1C 29 BJ6 23 2 C2 C6 TRANSFORMER 1 NC1 T/R 9 28 BANA 12 3 CT 0.1mF 0.1mF 22 11 3 OE GND2 RN1D HDR3 4 3 INA-1 6 J1 7 13 12 JP3 2 GND1 GND3 11 4 26 BNC DRVDD CH1IN 2 JP13 3 RN1E 24 6 1 1 5 2 74LVXC4245 INB-1 22 5 1 10 PS 3 JP17 CLK R2 1 DRVDD JP2 JP2 JP19 8 1 RN1F 2 OUT HDR3 R-S 50V R_VREF 4 2 1 10 3 3 9 6 C7 R1 12 JUMPER JUMPER TP1 HDR3 RN2A 0.1mF HDR3 20 R-S TBDV 33 TP2 C1 0.1mF CON1 14 1 25 R4 18 DCIN1 CON1 U2 RN2B 23 R-S 100V 27 19 5 13 2 B A 16 STROBE RN2C CLK0 20 4 BCLK0 C3 C5 C54 32 C4 21 B A 10_6V3 JP22 14 J3 10_6V3 1000pF JP21 12 3 0.1V 3 3 21 3 MIDSCALE_IN B A 34 2 2 RN2D 1 1 1 D0 6 BD0 20 19 33 AVDD AVDD R6 R7 D0 A 11 4 MIDSCALE_I HDR3 HDR3 40 D1 18 7 BD1 5kV 15kV RN2E D1 A 39 17 D2 17 8 BD2 C8 DUTCLK 10 5 36 D2 A DUTDATA 38 CAP_NP RN2F D3 9 BD3 16 U4 [0...9] R11 D3 A 15 37 9 6 D4 14 10 BD4 1kV TP3 15 14 D[0...9] A AVDD D4 CON40 SLEEP DUTCLK CON1 R13 R8 R50 24 1 VCCA DVDD VCCB DRVDD U3 1kV 5.49kV 10V ADJ_REF JP5 C9 16 13 23 2 C10 VREF INA-1 SELECT NC1 T/R AD822 0.1mF R51 C50 0.1mF 22 11 R9 + R10 JUMPER 10pF OE GND2 10V POT_10kV 8 D9 17 12 R-S 10V 12 C12 13 INB-1 D9 D1 GND3 GND1 C14 C51 0.1kV R12 C11 0.1mF U8F 10pF 11 D4 D8 74LVXC4245 18 JP20 1.5kV 10_6V3 REFT-1 D8 1 13 12 C17 DRVDD 2 DIODE_ZENER C15 C16 3 AVDD 0.1mF C13 CAP_P CAP_NP 10 D7 19 REFB-1 D7 0.1mF HDR3 JP7 R16 R17 74AHC14DW JUMPER 5kV 15kV 9 D6 20 AVSS D6 U8E C21 JP4 TESTCHIP 11 10 1 CAP_NP R14 D5 2 21 8 R18 R-S TBDV REFSENSE D5 3 R_VREF R-S TBDV 7 D4 22 C19 74AHC14DW C20 VREF D4 U6 10_10V ADJ_REF 0.1kV L5 U8D 23 6 D3 AD822 FERRITE_BEAD AVDD DVDD AVDD D3 9 8 R23 + R24 C24 C22 C23 POT_10kV 8 R-S 22V 10_10V 0.1kV 0.1mF C30 C49 24 5 D2 C31 C32 REFB-Q D2 CAP_NP 10_10V R30 10_6V3 C25 C26 0.1mF 74AHC14DW 1.5kV CAP_P CAP_NP D1 25 4 JP9 REFT-Q D1 AVDD AVDD JUMPER C27 0.1mF 3 D0 26 R31 INB-Q D0 J4 T2 500V R53 C52 TP4 R52 BNC TRANSFORMER CT U8A U8B 10pF HDR3 10V JP15 CON1 INA-Q 10V 1 4 3 27 R32 CHOIN 3 1 4 JP16 2 INA-Q DVDD 2 2 3 1 R36 2 POT_2kV CLK0 3 JP14 C53 3 2 1 C29 JP6 INB-Q 1 3 10pF 6 CAP_NP J6 C33 1 1 2 28 JP10 HDR3 2 R-S TBDV CHIP-SELECT DVSS BNC 0.1mF HDR3 R34 AVDD 3 PS HDR4 4 74AHC14DW 74AHC14DW R-S 50V HDR3 JP12 JP11 ADC_CLK R_VREF AVDD AD9201 JUMPER JUMPER R35 R38 C38 C34 R-S 1V R33 TP5 R-S TP6 0.1mF 0.1mF 500V CON1 CON1 50V TP7 DCINO U8C CON1 5 R40 C37 6 C35 C36 C55 DUTCLK R-S 100V 10_6V3 10_6V3 0.1mF 1000pF R39 R-S 50V NOT TO SCALE 74AHC14DW AD9201 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 1 14 0.07 (1.79) 0.078 (1.98) PIN 1 0.068 (1.73) 0.066 (1.67) 0.03 (0.762) 8° 0.0256 0.015 (0.38) 0° 0.022 (0.558) 0.008 (0.203) SEATING 0.009 (0.229) (0.65) 0.010 (0.25) 0.002 (0.050) PLANE BSC 0.005 (0.127) REV. D –20– 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) PRINTED IN U.S.A. C3116d–0–8/99