ANALOG DEVICES AD9200

Complete 10-Bit, 20 MSPS, 80 mW a CMOS A/D Converter AD9200 FEATURES A single clock input is used to control all internal conversion CMOS 10-Bit, 20 MSPS Sampling A/D Converter cycles. The digital output data is presented in straight binary Pin-Compatible with AD876 output format. An out-of-range signal (OTR) indicates an over- Power Dissipation: 80 mW (3 V Supply) flow condition which can be used with the most significant bit Operation Between 2.7 V and 5.5 V Supply to determine low or high overflow. Differential Nonlinearity: 0.5 LSB The AD9200 can operate with supply range from 2.7 V to Power-Down (Sleep) Mode 5.5 V, ideally suiting it for low power operation in high speed Three-State Outputs portable applications. Out-of-Range Indicator The AD9200 is specified over the industrial (–40°C to +85°C) Built-In Clamp Function (DC Restore) and commercial (0°C to +70°C) temperature ranges. Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT HIGHLIGHTS PRODUCT DESCRIPTION Low Power The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS The AD9200 consumes 80 mW on a 3 V supply (excluding the analog-to-digital converter with an on-chip sample-and-hold reference power). In sleep mode, power is reduced to below amplifier and voltage reference. The AD9200 uses a multistage 5 mW. differential pipeline architecture at 20 MSPS data rates and Very Small Package guarantees no missing codes over the full operating temperature The AD9200 is available in both a 28-lead SSOP and 48-lead range. LQFP packages. The input of the AD9200 has been designed to ease the devel- Pin Compatible with AD876 opment of both imaging and communications systems. The user The AD9200 is pin compatible with the AD876, allowing older can select a variety of input ranges and offsets and can drive the designs to migrate to lower supply voltages. input either single-ended or differentially. 300 MHz On-Board Sample-and-Hold The sample-and-hold (SHA) amplifier is equally suited for both The versatile SHA input can be configured for either single- multiplexed systems that switch full-scale voltage levels in suc- ended or differential inputs. cessive channels and sampling single-channel inputs at frequen- Out-of-Range Indicator cies up to and beyond the Nyquist rate. AC coupled input The OTR output bit indicates when the input signal is beyond signals can be shifted to a predetermined level, with an onboard the AD9200’s input range. clamp circuit (AD9200ARS, AD9200KST). The dynamic per- formance is excellent. Built-In Clamp Function Allows dc restoration of video signals with AD9200ARS and The AD9200 has an onboard programmable reference. An AD9200KST. external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP IN CLK AVDD DRVDD STBY SHA SHA GAIN SHA GAIN SHA GAIN SHA GAIN MODE AIN A/D REFTS THREE- A/D D/A A/D D/A A/D D/A A/D D/A REFBS STATE REFTF CORRECTION LOGIC REFBF OTR OUTPUT BUFFERS VREF D9 AD9200 1V REFSENSE (MSB) D0 (LSB) DRVSS AVSS REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 (AVDD = +3 V, DRVDD = +3 V, F = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input S AD9200–SPECIFICATIONS Span from 0.5 V to 2.5 V, External Reference, T to T unless otherwise noted) MIN MAX Parameter Symbol Min Typ Max Units Condition RESOLUTION 10 Bits CONVERSION RATE F 20 MHz S DC ACCURACY Differential Nonlinearity DNL–0.5–1 LSB REFTS = 2.5 V, REFBS = 0.5 V Integral Nonlinearity INL–0.75–2 LSB Offset Error E 0.4 1.2 % FSR ZS Gain Error E 1.4 3.5 % FSR FS REFERENCE VOLTAGES Top Reference Voltage REFTS 1 AVDD V Bottom Reference Voltage REFBS GND AVDD – 1 V Differential Reference Voltage 2 V p-p 1 Reference Input Resistance 10 kWREFTS, REFBS: MODE = AVDD 4.2 kWBetween REFTF and REFBF: MODE = AVSS ANALOG INPUT Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD Input Capacitance C 1 pF Switched IN Aperture Delay t 4ns AP Aperture Uncertainty (Jitter) t 2ps AJ Input Bandwidth (–3 dB) BW Full Power (0 dB) 300 MHz DC Leakage Current 23mA Input = –FS INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode)–10–25 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Load Regulation (1 V Mode) 0.5 2 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V DRVDD 2.7 3 5.5 V Supply Current IAVDD 26.6 33.3 mA AVDD = 3 V, MODE = AVSS Power Consumption P 80 100 mW AVDD = DRVDD = 3 V, MODE = AVSS D Power-Down 4 mW STBY = AVDD, MODE and CLOCK = AVSS Gain Error Power Supply Rejection PSRR 1 % FS DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz 54.5 57 dB f = 10 MHz 54 dB Effective Bits f = 3.58 MHz 9.1 Bits f = 10 MHz 8.6 Bits Signal-to-Noise SNR f = 3.58 MHz 55 57 dB f = 10 MHz 56 dB Total Harmonic Distortion THD f = 3.58 MHz –59 –66 dB f = 10 MHz –58 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz –61 –69 dB f = 10 MHz –61 dB Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.1 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.05 % REV. E –2– AD9200 Parameter Symbol Min Typ Max Units Condition DIGITAL INPUTS High Input Voltage V 2.4 V IH Low Input Voltage V 0.3 V IL DIGITAL OUTPUTS High-Z Leakage I –10 +10mA Output = GND to VDD OZ Data Valid Delay t 25 ns C = 20 pF OD L Data Enable Delay t 25 ns DEN Data High-Z Delay t 13 ns DHZ LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (I = 50 mA) V +2.95 V OH OH High Level Output Voltage (I = 0.5 mA) V +2.80 V OH OH Low Level Output Voltage (I = 1.6 mA) V +0.4 V OL OL Low Level Output Voltage (I = 50 mA) V +0.05 V OL OL LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (I = 50 mA) V +4.5 V OH OH High Level Output Voltage (I = 0.5 mA) V +2.4 V OH OH Low Level Output Voltage (I = 1.6 mA) V +0.4 V OL OL Low Level Output Voltage (I = 50 mA) V +0.1 V OL OL CLOCKING Clock Pulsewidth High t 22.5 ns CH Clock Pulsewidth Low t 22.5 ns CL Pipeline Latency 3 Cycles 2 CLAMP Clamp Error Voltage E–20–40 mV CLAMPIN = 0.5 V–2.7 V, R = 10 WOC IN Clamp Pulsewidth t 2msC = 1 mF (Period = 63.5 ms) CPW IN NOTES 1 See Figures 1a and 1b. 2 Available only in AD9200ARS and AD9200KST. Specifications subject to change without notice. REFTS 10kV REFTS AD9200 AD9200 REFTF 4.2kV 10kV REFBF REFBS 0.4 3 V DD REFBS MODE MODE AV DD Figure 1a. Figure 1b. REV. E –3– AD9200 *Stresses above those listed under Absolute Maximum Ratings may cause perma- ABSOLUTE MAXIMUM RATINGS* nent damage to the device. This is a stress rating only; functional operation of the With device at these or any other conditions above those indicated in the operational Respect sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. Parameter to Min Max Units ORDERING GUIDE AVDD AVSS –0.3 +6.5 V DRVDD DRVSS –0.3 +6.5 V Temperature Package Package AVSS DRVSS –0.3 +0.3 V Model Range Description Options* AVDD DRVDD –6.5 +6.5 V MODE AVSS –0.3 AVDD + 0.3 V AD9200JRS 0°C to +70°C 28-Lead SSOP RS-28 CLK AVSS –0.3 AVDD + 0.3 V AD9200ARS –40°C to +85°C 28-Lead SSOP RS-28 Digital Outputs DRVSS –0.3 DRVDD + 0.3 V AD9200JST 0°C to +70°C 48-Lead LQFP ST-48 AIN AVSS –0.3 AVDD + 0.3 V AD9200KST 0°C to +70°C 48-Lead LQFP ST-48 VREF AVSS –0.3 AVDD + 0.3 V AD9200JRSRL 0°C to +70°C 28-Lead SSOP (Reel) RS-28 REFSENSE AVSS –0.3 AVDD + 0.3 V AD9200ARSRL –40°C to +85°C 28-Lead SSOP (Reel) RS-28 REFTF, REFTB AVSS –0.3 AVDD + 0.3 V AD9200JSTRL 0°C to +70°C 48-Lead LQFP (Reel) ST-48 REFTS, REFBS AVSS –0.3 AVDD + 0.3 V AD9200KSTRL 0°C to +70°C 48-Lead LQFP (Reel) ST-48 Junction Temperature +150 °C AD9200 SSOP-EVAL Evaluation Board Storage Temperature –65 +150 °C AD9200 LQFP-EVAL Evaluation Board Lead Temperature *RS = Shrink Small Outline; ST = Thin Quad Flatpack. 10 sec +300 °C AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS AVSS AVSS DRVSS AVSS AVSS AVSS a. D0–D9, OTR b. Three-State, Standby, Clamp c. CLK AVDD AVDD REFTF REFBS AVDD AVSS AVSS AVDD AVDD REFTS REFBF AVSS AVSS AVSS d. AIN e. Reference AVDD AVDD AVDD AVDD AVSS AVSS AVSS AVSS f. CLAMPIN g. MODE h. REFSENSE i. VREF Figure 2. Equivalent Circuits CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. E –4– AD9200 PIN CONFIGURATIONS 28-Lead Shrink Small Outline (SSOP) 48-Lead Plastic Thin Quad Flatpack (LQFP) AVSS 1 28 AVDD DRVDD 2 27 AIN 48 47 46 45 44 43 42 41 40 39 38 37 D0 3 26 VREF 1 D0 36 NC D1 4 25 REFBS PIN 1 2 D1 IDENTIFIER 35 REFBS D2 5 24 REFBF 3 D2 34 AD9200 REFBF D3 6 23 MODE 4 TOP VIEW D3 33 NC (Not to Scale) D4 7 22 REFTF D4 5 32 MODE AD9200 NC 6 31 NC D5 8 21 REFTS TOP VIEW NC 7 30 REFTF (Not to Scale) D6 9 20 CLAMPIN D5 8 29 REFTS D7 10 19 CLAMP 9 D6 28 CLAMPIN D8 11 18 REFSENSE D7 10 27 CLAMP 11 D9 12 17 STBY D8 26 REFSENSE 12 D9 25 NC OTR 13 16 THREE-STATE DRVSS 14 15 CLK 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS SSOP LQFP Pin No. Pin No. Name Description 1 44 AVSS Analog Ground 2 45 DRVDD Digital Driver Supply 3 1 D0 Bit 0, Least Significant Bit 4 2 D1 Bit 1 5 3 D2 Bit 2 6 4 D3 Bit 3 7 5 D4 Bit 4 8 8 D5 Bit 5 9 9 D6 Bit 6 10 10 D7 Bit 7 11 11 D8 Bit 8 12 12 D9 Bit 9, Most Significant Bit 13 16 OTR Out-of-Range Indicator 14 17 DRVSS Digital Ground 15 22 CLK Clock Input 16 23 THREE-STATE HI: High Impedance State. LO: Normal Operation 17 24 STBY HI: Power-Down Mode. LO: Normal Operation 18 26 REFSENSE Reference Select 19 27 CLAMP HI: Enable Clamp Mode. LO: No Clamp 20 28 CLAMPIN Clamp Reference Input 21 29 REFTS Top Reference 22 30 REFTF Top Reference Decoupling 23 32 MODE Mode Select 24 34 REFBF Bottom Reference Decoupling 25 35 REFBS Bottom Reference 26 38 VREF Internal Reference Output 27 39 AIN Analog Input 28 42 AVDD Analog Supply REV. E –5– NC NC NC NC NC NC DRVDD OTR AVSS DRVSS NC NC AVDD NC NC NC NC NC AIN CLK VREF THREE-STATE NC STBY AD9200 DEFINITIONS OF SPECIFICATIONS Offset Error Integral Nonlinearity (INL) The first transition should occur at a level 1 LSB above “zero.” Integral nonlinearity refers to the deviation of each individual Offset is defined as the deviation of the actual first code transi- code from a line drawn from “zero” through “full scale”. The tion from that point. point used as “zero” occurs 1/2 LSB before the first code transi- Gain Error tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last The first code transition should occur for an analog value 1 LSB code transition. The deviation is measured from the center of above nominal negative full scale. The last transition should each particular code to the true straight line. occur for an analog value 1 LSB below the nominal positive full Differential Nonlinearity (DNL, No Missing Codes) scale. Gain error is the deviation of the actual difference be- An ideal ADC exhibits code transitions that are exactly 1 LSB tween first and last code transitions and the ideal difference apart. DNL is the deviation from this ideal value. It is often between the first and last code transitions. specified in terms of the resolution for which no missing codes Pipeline Delay (Latency) (NMC) are guaranteed. The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every rising edge. (AVDD = +3 V, DRVDD = +3 V, F = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input S Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted) Typical Characterization Curves 60 1.0 –0.5 AMPLITUDE 55 –6.0 AMPLITUDE 50 0.5 45 –20.0 AMPLITUDE 40 0 35 30 –0.5 25 20 –1.0 1.00E+05 1.00E+06 1.00E+07 1.00E+08 0 128 256 384 512 640 768 896 1024 INPUT FREQUENCY – Hz CODE OFFSET Figure 5. SNR vs. Input Frequency Figure 3. Typical DNL 60 1.0 –0.5 AMPLITUDE 55 50 0.5 –6.0 AMPLITUDE 45 40 0 –20.0 AMPLITUDE 35 30 –0.5 25 20 –1.0 0 128 256 384 512 640 768 896 1024 1.00E+05 1.00E+06 1.00E+07 1.00E+08 INPUT FREQUENCY – Hz CODE OFFSET Figure 6. SINAD vs. Input Frequency Figure 4. Typical INL REV. E –6– INL DNL SINAD – dB SNR– dB AD9200 –30 80.5 80.5 CLOCK = 20MHz –35 80.0 80.0 –40 –20.0 AMPLITUDE 79.5 79.5 –45 –50 79.0 79.0 –6.0 AMPLITUDE –55 78.5 78.5 –60 –65 78.0 78.0 –0.5 AMPLITUDE –70 77.5 77.5 –75 –80 77.0 77.0 1.00E+05 1.00E+06 1.00E+07 1.00E+0802 02 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 1800 INPUT FREQUENCY – Hz CLOCK FREQUENCY – MHz CLOCK FREQUENCY – MHz Figure 7. THD vs. Input Frequency Figure 10. Power Consumption vs. Clock Frequency (MODE = AVSS) –70 1M 900k F = 1MHz –60 IN 800k –50 700k 600k –40 499856 500k –30 400k –20 300k 200k –10 100k 54383 54160 0 0 100E+03 1E+06 10E+06 100E+06 N–1 N N+1 CLOCK FREQUENCY – Hz CODE Figure 8. THD vs. Clock Frequency Figure 11. Grounded Input Histogram 20 1.005 0 1.004 CLOCK = 20MHz –20 1.003 –40 1.002 –60 1.001 –80 1.000 –100 0.999 –120 –140 0.998 –40 –20 0 20 40 60 80 100 0E+0 1E+6 2E+6 3E+6 4E+6 5E+6 6E+6 7E+6 8E+6 9E+6 10E+6 TEMPERATURE – °C SINGLE TONE FREQUENCY DOMAIN Figure 9. Voltage Reference Error vs. Temperature Figure 12. Single-Tone Frequency Domain REV. E –7– V – V REF THD – dB THD – dB HITS POWER CONSUMPTION – mW POWER CONSUMPTION – mW AD9200 0 APPLYING THE AD9200 THEORY OF OPERATION –3 The AD9200 implements a pipelined multistage architecture to –6 achieve high sample rate with low power. The AD9200 distrib- –9 utes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes –12 the results from stage to stage. As a consequence of the distrib- –15 uted conversion, the AD9200 requires a small fraction of the 1023 comparators used in a traditional flash type A/D. A –18 sample-and-hold function within each of the stages permits the –21 first stage to operate on a new input sample while the second, –24 third and fourth stages operate on the three preceding samples. –27 1.0E+6 10.0E+6 100.0E+6 1.0E+9 OPERATIONAL MODES FREQUENCY – Hz The AD9200 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation Figure 13. Full Power Bandwidth applications, including pin compatibility with the AD876 A/D. To realize this flexibility, internal switches on the AD9200 are used to reconfigure the circuit into different modes. These modes 25 are selected by appropriate pin strapping. There are three parts of the circuit affected by this modality: the voltage reference, the 20 reference buffer, and the analog input. The nature of the appli- 15 cation will determine which mode is appropriate: the descrip- 10 tions in the following sections, as well as the Table I should REFBS = 0.5V 5 REFTS = 2.5V assist in picking the desired mode. CLOCK = 20MHz 0 –5 –10 –15 –20 –25 0 0.5 1.0 1.5 2.0 2.5 3.0 INPUT VOLTAGE – V Figure 14. Input Bias Current vs. Input Voltage Table I. Mode Selection Input Input MODE REFSENSE Modes Connect Span Pin Pin REF REFTS REFBS Figure TOP/BOTTOM AIN 1 V AVDD Short REFSENSE, REFTS and VREF Together AGND 18 AIN 2 V AVDD AGND Short REFTS and VREF Together AGND 19 CENTER SPAN AIN 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20 AIN 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2 Differential AIN Is Input 1 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29 REFTS and REFBS Are Shorted Together for Input 2 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2 External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22 – REFBS (2 V max) AGND Short to Short to 23 VREFTF VREFBF AD876 AIN 2 V Float or AVDD No Connect Short to Short to 30 AVSS VREFTF VREFBF REV. E –8– SIGNAL AMPLITUDE – dB I – mA B AD9200 SUMMARY OF MODES VOLTAGE REFERENCE AIN A/D SHA 1 V Mode the internal reference may be set to 1 V by connect- CORE REFTS ing REFSENSE and VREF together. 2 V Mode the internal reference my be set to 2 V by connecting AD9200 REFSENSE to analog ground External Divider Mode the internal reference may be set to a REFBS point between 1 V and 2 V by adding external resistors. See Figure 16f. Figure 15. AD9200 Equivalent Functional Input Circuit External Reference Mode enables the user to apply an exter- nal reference to REFTS, REFBS and VREF pins. This mode In single-ended operation, the input spans the range, is attained by tying REFSENSE to VDD. REFBS £ AIN £ REFTS where REFBS can be connected to GND and REFTS con- REFERENCE BUFFER nected to VREF. If the user requires a different reference range, Center Span Mode midscale is set by shorting REFTS and REFBS and REFTS can be driven to any voltage within the REFBS together and applying the midscale voltage to that point power supply rails, so long as the difference between the two is The MODE pin is set to AVDD/2. The analog input will swing between 1 V and 2 V. about that midscale point. In differential operation, REFTS and REFBS are shorted to- Top/Bottom Mode sets the input range between two points. gether, and the input span is set by VREF, The two points are between 1 V and 2 V apart. The Top/Bottom Mode is enabled by tying the MODE pin to AVDD. (REFTS – VREF/2) £ AIN £ (REFTS + VREF/2) where VREF is determined by the internal reference or brought ANALOG INPUT in externally by the user. Differential Mode is attained by driving the AIN pin as one differential input and shorting REFTS and REFBS together and The best noise performance may be obtained by operating the driving them as the second differential input. The MODE pin AD9200 with a 2 V input range. The best distortion perfor- is tied to AVDD/2. Preferred mode for optimal distortion mance may be obtained by operating the AD9200 with a 1 V performance. input range. Single-Ended is attained by driving the AIN pin while the REFERENCE OPERATION REFTS and REFBS pins are held at dc points. The MODE pin is The AD9200 can be configured in a variety of reference topolo- tied to AVDD. gies. The simplest configuration is to use the AD9200’s onboard Single-Ended/Clamped (AC Coupled) the input may be bandgap reference, which provides a pin-strappable option to clamped to some dc level by ac coupling the input. This is done generate either a 1 V or 2 V output. If the user desires a refer- by tying the CLAMPIN to some dc point and applying a pulse ence voltage other than those two, an external resistor divider to the CLAMP pin. MODE pin is tied to AVDD. can be connected between VREF, REFSENSE and analog ground to generate a potential anywhere between 1 V and 2 V. SPECIAL Another alternative is to use an external reference for designs AD876 Mode enables users of the AD876 to drop the AD9200 requiring enhanced accuracy and/or drift performance. A into their socket. This mode is attained by floating or grounding third alternative is to bring in top and bottom references, the MODE pin. bypassing VREF altogether. Figures 16d, 16e and 16f illustrate the reference and input ar- INPUT AND REFERENCE OVERVIEW chitecture of the AD9200. In tailoring a desired arrangement, Figure 16, a simplified model of the AD9200, highlights the the user can select an input configuration to match drive circuit. relationship between the analog input, AIN, and the reference Then, moving to the reference modes at the bottom of the voltages, REFTS, REFBS and VREF. Like the voltages applied figure, select a reference circuit to accommodate the offset and to the resistor ladder in a flash A/D converter, REFTS and amplitude of a full-scale signal. REFBS define the maximum and minimum input voltages to the A/D. Table I outlines pin configurations to match user requirements. The input stage is normally configured for single-ended opera- tion, but allows for differential operation by shorting REFTS and REFBS together to be used as the second input. REV. E –9– AD9200 V* +FS MIDSCALE AD9200 MODE AIN AVDD/2 AD9200 SHA AIN –FS MODE SHA (AVDD) +F/S RANGE OBTAINED 0.1mF 10kV REFTF FROM VREF PIN OR 0.1mF 10kV REFTF EXTERNAL REF 10kV REFTS REFTS 10kV A2 0.1mF A/D 4.2kV REFBS 10mF A2 REFBS 0.1mF CORE A/D 10kV TOTAL 4.2kV 10mF CORE TOTAL 10kV INTERNAL 0.1mF 10kV –F/S RANGE OBTAINED REF 0.1mF 10kV FROM VREF PIN OR REFBF EXTERNAL REF REFBF MIDSCALE OFFSET VOLTAGE IS DERIVED * MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE FROM INTERNAL OR EXTERNAL REF a. Top/Bottom Mode b. Center Span Mode MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO V AD9200 AIN MODE AVDD/2 SHA AVDD/2 0.1mF 10kV REFTF 10kV REFTS A2 0.1mF A/D 4.2kV REFBS 10mF CORE 10kV TOTAL INTERNAL 0.1mF 10kV REF REFBF c. Differential Mode VREF (2V) VREF A1 (1V) A1 1V 0.01mF 1.0mF 1V 10kV REFSENSE 0.1mF 1.0mF REFSENSE 10kV AD9200 AVSS AD9200 AVSS d. 1 V Reference e. 2 V Reference VREF (= 1 + R /R ) A B A1 1V 0.1mF 1.0mF R A A1 VREF 1V REFSENSE REFSENSE R B AVDD AD9200 AVSS AD9200 INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF R AND R . A B f. Variable Reference g. Internal Reference Disable (Between 1 V and 2 V) (Power Reduction) Figure 16. REV. E –10– AD9200 The actual reference voltages used by the internal circuitry of Figure 19 shows the single-ended configuration for 2 V p-p the AD9200 appear on REFTF and REFBF. For proper opera- operation. REFSENSE is connected to GND, resulting in a 2 V tion, it is necessary to add a capacitor network to decouple these reference output. pins. The REFTF and REFBF should be decoupled for all internal and external configurations as shown in Figure 17. 2V AIN AD9200 MODE SHA AVDD 0V REFTF 0.1mF 10kV REFTF 10mF 0.1mF AD9200 10kV REFTS REFBF A2 REFBS 0.1mF A/D 4.2kV 10mF 0.1mF 0.1mF CORE TOTAL 10kV 0.1mF 10kV Figure 17. Reference Decoupling Network REFBF VREF Note: REFTF = reference top, force A1 1V 1.0mF 0.1mF REFBF = reference bottom, force REF REFTS = reference top, sense SENSE REFBS = reference bottom, sense INTERNAL REFERENCE OPERATION Figure 19. Internal Reference, 2 V p-p Input Span Figures 18, 19 and 20 show example hookups of the AD9200 (Top/Bottom Mode) internal reference in its most common configurations. (Figures 18 and 19 illustrate top/bottom mode while Figure 20 illustrates Figure 20 shows the single-ended configuration that gives the center span mode). Figure 29 shows how to connect the AD9200 good high frequency dynamic performance (SINAD, SFDR). for 1 V p-p differential operation. Shorting the VREF pin To optimize dynamic performance, center the common-mode directly to the REFSENSE pin places the internal reference voltage of the analog input at approximately 1.5 V. Connect the amplifier, A1, in unity-gain mode and the resultant reference shorted REFTS and REFBS inputs to a low impedance 1.5 V output is 1 V. In Figure 18 REFBS is grounded to give an input source. In this configuration, the MODE pin is driven to a volt- range from 0 V to 1 V. These modes can be chosen when the age at midsupply (AVDD/2). supply is either +3 V or +5 V. The VREF pin must be bypassed to Maximum reference drive is 1 mA. An external buffer is re- AVSS (analog ground) with a 1.0 mF tantalum capacitor in quired for heavier loads. parallel with a low inductance, low ESR, 0.1 mF ceramic capacitor. 1V AIN AD9200 2V MODE AIN SHA AVDD AD9200 0V MODE SHA AVDD/2 1V 0.1mF 10kV REFTF 0.1mF 10kV REFTF 10kV REFTS 10kV REFTS REFBS A2 0.1mF A/D 4.2kV 10mF +1.5V A2 REFBS 0.1mF CORE 10kV TOTAL A/D 4.2kV 10mF CORE TOTAL 0.1mF 10kV 0.1mF 10kV 10kV REFBF REFBF VREF A1 VREF 1V A1 REF 1V 1.0mF 0.1mF REF 1.0mF 0.1mF SENSE SENSE Figure 18. Internal Reference 1 V p-p Input Span Figure 20. Internal Reference 1 V p-p Input Span, (Top/Bottom Mode) (Center Span Mode) REV. E –11– AD9200 EXTERNAL REFERENCE OPERATION 4V VIN Using an external reference may provide more flexibility and 2V REFTS improve drift and accuracy. Figures 21 through 23 show ex- amples of how to use an external reference with the AD9200. REFTF 4V AD9200 To use an external reference, the user must disable the internal 10 F 0.1 F REFBF reference amplifier by connecting the REFSENSE pin to VDD. 2V 0.1 F 0.1 F The user then has the option of driving the VREF pin, or driv- REFBS ing the REFTS and REFBS pins. VREF The AD9200 contains an internal reference buffer (A2), that REFSENSE AVDD simplifies the drive requirements of an external reference. The MODE external reference must simply be able to drive a 10 kW load. Figure 21 shows an example of the user driving the top and bottom references. REFTS is connected to a low impedance 2 V source Figure 23a. External Reference—2 V p-p Input Span and REFBS is connected to a low impedance 1 V source. REFTS and REFBS may be driven to any voltage within the supply as long as the difference between them is between 1 V and 2 V. REFTS +5V C4 0.1 F 6 2V 8 AIN 7 AD9200 REFTF SHA 5 1V REFT C3 0.1 F C2 C6 AD9200 10 F 0.1 F 0.1mF 10kV REFTF REFBS 10kV REFTS C5 2V 2 0.1 F A2 REFBS 0.1mF 6 1V A/D 4.2kV 10mF REFBF 3 10kV CORE TOTAL REFB C1 4 0.1 F REF 0.1mF SENSE 10kV AVDD MODE REFBF Figure 23b. Kelvin Connected Reference Using the AD9200 Figure 21. External Reference Mode—1 V p-p Input Span STANDBY OPERATION The ADC may be placed into a powered down (sleep) mode by Figure 22 shows an example of an external reference generating driving the STBY (standby) pin to logic high potential and 2.5 V at the shorted REFTS and REFBS inputs. In this in- holding the clock at logic low. In this mode the typical power stance, a REF43 2.5 V reference drives REFTS and REFBS. A drain is approximately 4 mW. If there is no connection to the resistive divider generates a 1 V VREF signal that is buffered by STBY pin, an internal pull-down circuit will keep the ADC in a A3. A3 must be able to drive a 10 kW, capacitive load. Choose “wake-up” mode of operation. this op amp based on noise and accuracy requirements. The ADC will “wake up” in 400 ns (typ) after the standby pulse goes low. AD9200 3.0V 2.5V AIN CLAMP OPERATION AVDD AVDD 2.0V REFTS The AD9200ARS and AD9200KST parts feature an optional clamp circuit for dc restoration of video or ac coupled signals. 0.1mF REFBS REFTF 10mF 0.1mF 1.5kV Figure 24 shows the internal clamp circuitry and the external 0.1mF control signals needed for clamp operation. To enable the 10mF A3 VREF clamp, apply a logic high to the CLAMP pin. This will close 1.0mF 0.1mF 0.1mF the switch SW1. The clamp amplifier will then servo the volt- 0.1mF 1kV REFBF age at the AIN pin to be equal to the clamp voltage applied at MODE the CLAMPIN pin. After the desired clamp level is attained, +5V AVDD REFSENSE SW1 is opened by taking CLAMP back to a logic low. Ignoring REF43 the droop caused by the input bias current, the input capacitor 0.1mF CIN will hold the dc voltage at AIN constant until the next AVDD/2 clamp interval. The input resistor RIN has a minimum recom- Figure 22. External Reference Mode—1 V p-p Input mended value of 10W, to maintain the closed-loop stability of Span 2.5 V CM the clamp amplifier. Figure 23a shows an example of the external references driving The allowable voltage range that can be applied to CLAMPIN the REFTF and REFBF pins that is compatible with the depends on the operational limits of the internal clamp ampli- AD876. REFTS is shorted to REFTF and driven by an external fier. When operating off of 3 volt supplies, the recommended 4 V low impedance source. REFBS is shorted to REFBF and clamp range is between 0.5 volts and 2.0 volts. driven by a 2 V source. The MODE pin is connected to GND in this configuration. REV. E –12– AD9200 The input capacitor should be sized to allow sufficient acquisi- back porch to truncate the SYNC below the AD9200’s mini- tion time of the clamp voltage at AIN within the CLAMP inter- mum input voltage. With a C = 1mF, and R = 20W, the IN IN val, but also be sized to minimize droop between clamping acquisition time needed to set the input dc level to one volt intervals. Specifically, the acquisition time when the switch is with 1 mV accuracy is about 140ms, assuming a full 1 volt V . C closed will equal: With a 1mF input coupling capacitor, the droop across one horizontal can be calculated:   V C T = R C ln ACQ IN IN   I = 10 mA, and t = 63.5 ms, so dV = 0.635 mV, which is less BIAS VŁEł than one LSB. where V is the voltage change required across C , and V is C IN E After the input capacitor is initially charged, the clamp pulse- the error voltage. V is calculated by taking the difference be- C width only needs to be wide enough to correct small voltage tween the initial input dc level at the start of the clamp interval errors such as the droop. The fine scale settling characteristics and the clamp voltage supplied at CLAMPIN. V is a system- E of the clamp circuitry are shown in Table II. dependent parameter, and equals the maximum tolerable devia- Depending on the required accuracy, a CLAMP pulsewidth of tion from V . For example, if a 2-volt input level needs to be C 1ms–3 ms should work in most applications. The OFFSET val- clamped to 1 volt at the AD9200’s input within 10 millivolts, ues ignore the contribution of offset from the clamp amplifier; then V equals 2 – 1 or 1 volt, and V equals 10 mV. Note that C E they simply compare the output code with a “final value” mea- once the proper clamp level is attained at the input, only a very sured with a much longer CLAMP pulse duration. small voltage change will be required to correct for droop. The voltage droop is calculated with the following equation: Table II. I BIAS dV = t () CLAMP OFFSET C IN 10 ms <1 LSB where t = time between clamping intervals. 5 ms 5 LSBs The bias current of the AD9200 will depend on the sampling 4 ms 7 LSBs rate, F . The switched capacitor input AIN appears resistive S 3 ms 11 LSBs over time, with an input resistance equal to 1/C F . Given a S S 2 ms 19 LSBs sampling rate of 20 MSPS and an input capacitance of 1 pF, the 1 ms 42 LSBs input resistance is 50 kW. This input resistance is equivalently terminated at the midscale voltage of the input range. The worst case bias current will thus result when the input signal is at the AD9200 extremes of the input range, that is, the furthest distance from CLAMP IN the midscale voltage level. For a 1-volt input range, the maxi- mum bias current will be –0.5 volts divided by 50 kW, which is CLAMP–10 mA. SW1 If droop is a critical parameter, then the minimum value of C CIN IN RIN AIN TO should be calculated first based on the droop requirement. SHA Acquisition time—the width of the CLAMP pulse—can be adjusted accordingly once the minimum capacitor value is cho- sen. A tradeoff will often need to be made between droop and Figure 24a. Clamp Operation acquisition time, or error voltage V . E Clamp Circuit Example AIN A single supply video amplifier outputs a level-shifted video signal between 2 and 3 volts with the following parameters: 0.1 F REFTF horizontal period = 63.56 ms, REFTS horizontal sync interval = 10.9ms, 10 F 0.1 F AD9200 0.1 F REFBF horizontal sync pulse = 4.7ms, sync amplitude = 0.3 volts, REFBS video amplitude of 0.7 volts, AVDD MODE 2 reference black level = 2.3 volts CLAMP The video signal must be dc restored from a 2- to 3-volt range down to a 1- to 2-volt range. Configuring the AD9200 for a SHORT TO REFBS CLAMPIN OR EXTERNAL DC one volt input span with an input range from 1 to 2 volts (see Figure 24), the CLAMPIN voltage can be set to 1 volt with an external voltage or by direct connection to REFBS. The CLAMP Figure 24b. Video Clamp Circuit pulse may be applied during the SYNC pulse, or during the REV. E –13– AD9200 DRIVING THE ANALOG INPUT In many cases, particularly in single-supply operation, ac cou- Figure 25 shows the equivalent analog input of the AD9200, a pling offers a convenient way of biasing the analog input signal sample-and-hold amplifier (switched capacitor input SHA). at the proper signal range. Figure 25 shows a typical configura- Bringing CLK to a logic low level closes Switches 1 and 2 and tion for ac-coupling the analog input signal to the AD9200. opens Switch 3. The input source connected to AIN must Maintaining the specifications outlined in the data sheet charge capacitor CH during this time. When CLK transitions requires careful selection of the component values. The most from logic “low” to logic “high,” Switches 1 and 2 open, placing important is the f high-pass corner frequency. It is a function of –3 dB the SHA in hold mode. Switch 3 then closes, forcing the output R2 and the parallel combination of C1 and C2. The f point –3 dB of the op amp to equal the voltage stored on CH. When CLK can be approximated by the equation: transitions from logic “high” to logic “low,” Switch 3 opens f = 1/(2 · pi · [R2] C ) –3 dB EQ first. Switches 1 and 2 close, placing the SHA in track mode. where C is the parallel combination of C1 and C2. Note that EQ The structure of the input SHA places certain requirements on C1 is typically a large electrolytic or tantalum capacitor that the input drive source. The combination of the pin capacitance, becomes inductive at high frequencies. Adding a small ceramic CP, and the hold capacitance, CH, is typically less than 5 pF. or polystyrene capacitor (on the order of 0.01mF) that does not The input source must be able to charge or discharge this ca- become inductive until negligibly higher frequencies, maintains pacitance to 10-bit accuracy in one half of a clock cycle. When a low impedance over a wide frequency range. the SHA goes into track mode, the input source must charge or NOTE: AC coupled input signals may also be shifted to a desired discharge capacitor CH from the voltage already stored on CH level with the AD9200’s internal clamp. See Clamp Operation. to the new voltage. In the worst case, a full-scale voltage step on the input, the input source must provide the charging current through the R (50 W) of Switch 1 and quickly (within 1/2 CLK ON C1 R1 V IN AIN period) settle. This situation corresponds to driving a low input R2 I B impedance. On the other hand, when the source voltage equals AD9200 C2 the value previously stored on CH, the hold capacitor requires V BIAS no input current and the equivalent input impedance is ex- tremely high. Adding series resistance between the output of the source and Figure 27. AC Coupled Input the AIN pin reduces the drive requirements placed on the source. Figure 26 shows this configuration. The bandwidth of There are additional considerations when choosing the resistor the particular application limits the size of this resistor. To values. The ac-coupling capacitors integrate the switching tran- maintain the performance outlined in the data sheet specifica- sients present at the input of the AD9200 and cause a net dc tions, the resistor should be limited to 20 W or less. For applica- bias current, I , to flow into the input. The magnitude of the B tions with signal bandwidths less than 10 MHz, the user may bias current increases as the signal magnitude deviates from proportionally increase the size of the series resistor. Alterna- V midscale and the clock frequency increases; i.e., minimum tively, adding a shunt capacitance between the AIN pin and bias current flow when AIN = V midscale. This bias current analog ground can lower the ac load impedance. The value of will result in an offset error of (R1 + R2) · I . If it is necessary B this capacitance will depend on the source resistance and the to compensate this error, consider making R2 negligibly small or required signal bandwidth. modifying VBIAS to account for the resultant offset. The input span of the AD9200 is a function of the reference In systems that must use dc coupling, use an op amp to level- voltages. For more information regarding the input range, see shift a ground-referenced signal to comply with the input re- the Internal and External Reference sections of the data sheet. quirements of the AD9200. Figure 28 shows an AD8041 config- ured in noninverting mode. CH +V CC AIN S1 0.1 F CP S3 SHA NC AD9200 S2 7 0V 1V p-p DC (REFTS CH 2 REFBS) 1 20 CP AD8041 6 AIN AD9200 5 3 4 MIDSCALE NC OFFSET VOLTAGE Figure 25. AD9200 Equivalent Input Structure Figure 28. Bipolar Level Shift < 20V AIN AD9200 V S Figure 26. Simple AD9200 Drive Configuration REV. E –14– AD9200 DIFFERENTIAL INPUT OPERATION The pipelined architecture of the AD9200 operates on both The AD9200 will accept differential input signals. This function rising and falling edges of the input clock. To minimize duty may be used by shorting REFTS and REFBS and driving them cycle variations the recommended logic family to drive the clock as one leg of the differential signal (the top leg is driven into input is high speed or advanced CMOS (HC/HCT, AC/ACT) AIN). In the configuration below, the AD9200 is accepting a logic. CMOS logic provides both symmetrical voltage threshold 1 V p-p signal. See Figure 29. levels and sufficient rise and fall times to support 20 MSPS operation. The AD9200 is designed to support a conversion rate of 20 MSPS; running the part at slightly faster clock rates may AD9200 2V be possible, although at reduced performance levels. Conversely, AIN 0.1mF 1V some slight performance improvements might be realized by AVDD/2 REFTF REFTS clocking the AD9200 at slower clock rates. 0.1mF 10mF REFBS S1 S2 0.1mF ANALOG VREF S4 REFBF t C INPUT S3 1.0mF 0.1mF t t CH CL REFSENSE INPUT AVDD/2 MODE CLOCK 25ns DATA Figure 29. Differential Input DATA 1 OUTPUT AD876 MODE OF OPERATION Figure 31. Timing Diagram The AD9200 may be dropped into the AD876 socket. This will allow AD876 users to take advantage of the reduced power The power dissipated by the output buffers is largely propor- consumption realized when running the AD9200 on a 3.0 V tional to the clock frequency; running at reduced clock rates analog supply. provides a reduction in power consumption. Figure 30 shows the pin functions of the AD876 and AD9200. DIGITAL INPUTS AND OUTPUTS The grounded REFSENSE pin and floating MODE pin effec- Each of the AD9200 digital control inputs, THREE-STATE tively put the AD9200 in the external reference mode. The and STBY are reference to analog ground. The clock is also external reference input for the AD876 will now be placed on referenced to analog ground. the reference pins of the AD9200. The format of the digital output is straight binary (see Figure The clamp controls will be grounded by the AD876 socket. The 32). A low power mode feature is provided such that for STBY AD9200 has a 3 clock cycle delay compared to a 3.5 cycle delay = HIGH and the clock disabled, the static power of the AD9200 of the AD876. will drop below 5 mW. 4V AIN OTR AD9200 2V REFTS 4V REFTF 0.1mF 10mF 2V REFBF 0.1mF 0.1mF REFBS NC MODE AVDD REFSENSE CLAMP CLAMPIN –FS+1LSB +FS OTR VREF –FS +FS–1LSB 0.1mF Figure 32. Output Data Format Figure 30. AD876 Mode THREE- STATE t t DHZ DEN CLOCK INPUT DATA The AD9200 clock input is buffered internally with an inverter (D0–D9) HIGH powered from the AVDD pin. This feature allows the AD9200 IMPEDANCE to accommodate either +5 V or +3.3 V CMOS logic input sig- nal swings with the input threshold for the CLK pin nominally Figure 33. Three-State Timing Diagram at AVDD/2. REV. E –15– AD9200 APPLICATIONS Figure 34 shows a simplified schematic of the AD9200 config- DIRECT IF DOWN CONVERSION USING THE AD9200 ured in an IF sampling application. To reduce the complexity of Sampling IF signals above an ADC’s baseband region (i.e., dc the digital demodulator in many quadrature demodulation ap- to F /2) is becoming increasingly popular in communication plications, the IF frequency and/or sample rate are selected such S applications. This process is often referred to as Direct IF Down that the bandlimited IF signal aliases back into the center of the Conversion or Undersampling. There are several potential ben- ADC’s baseband region (i.e., F /4). For example, if an IF sig- S efits in using the ADC to alias (i.e., or mix) down a narrowband nal centered at 45 MHz is sampled at 20 MSPS, an image of or wideband IF signal. First and foremost is the elimination of a this IF signal will be aliased back to 5.0 MHz which corre- complete mixer stage with its associated amplifiers and filters, sponds to one quarter of the sample rate (i.e., F /4). This S reducing cost and power dissipation. Second is the ability to demodulation technique typically reduces the complexity of the apply various DSP techniques to perform such functions as post digital demodulator ASIC which follows the ADC. filtering, channel selection, quadrature demodulation, data To maximize its distortion performance, the AD9200 is config- reduction, detection, etc. A detailed discussion on using this ured in the differential mode with a 1 V span using a transformer. technique in digital receivers can be found in Analog Devices The center tap of the transformer is biased at midsupply via a Application Notes AN-301 and AN-302. resistor divider. Preceding the AD9200 is a bandpass filter as In Direct IF Down Conversion applications, one exploits the well as a 32 dB gain stage. A large gain stage may be required inherent sampling process of an ADC in which an IF signal to compensate for the high insertion losses of a SAW filter used lying outside the baseband region can be aliased back into the for image rejection. The gain stage will also provide adequate baseband region in a similar manner that a mixer will down- isolation for the SAW filter from the charge “kick back” currents convert an IF signal. Similar to the mixer topology, an image associated with AD9200’s input stage. rejection filter is required to limit other potential interfering The gain stage can be realized using one or two cascaded signals from also aliasing back into the ADC’s baseband region. AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz, A tradeoff exists between the complexity of this image rejection current-feedback op amp having a 3rd order intercept character- filter and the sample rate as well as dynamic range of the ADC. ized up to 250 MHz. A passive bandpass filter following the The AD9200 is well suited for various narrowband IF sampling AD8009 attenuates its dominant 2nd order distortion products applications. The AD9200’s low distortion input SHA has a which would otherwise be aliased back into the AD9200’s full-power bandwidth extending to 300 MHz thus encompassing baseband region. Also, it reduces any out-of-band noise which many popular IF frequencies. A DNL of –0.5 LSB (typ) com- would also be aliased back due to the AD9200’s noise band- bined with low thermal input referred noise allows the AD9200 in width of 220+ MHz. Note, the bandpass filters specifications the 2 V span to provide 60 dB of SNR for a baseband input sine are application dependent and will affect both the total distor- wave. Also, its low aperture jitter of 2 ps rms ensures minimum tion and noise performance of this circuit. SNR degradation at higher IF frequencies. In fact, the AD9200 The distortion and noise performance of an ADC at the given is capable of still maintaining 56 dB of SNR at an IF of 135 MHz IF frequency is of particular concern when evaluating an ADC with a 1 V (i.e., 4 dBm) input span. Note, although the AD9200 for a narrowband IF sampling application. Both single-tone and will typically yield a 3 to 4 dB improvement in SNR when con- dual-tone SFDR vs. amplitude are very useful in an assessing an figured for the 2 V span, the 1 V span provides the optimum ADC’s noise performance and noise contribution due to aper- full-scale distortion performance. Furthermore, the 1 V span ture jitter. In any application, one is advised to test several units reduces the performance requirements of the input driver cir- of the same device under the same conditions to evaluate the cuitry and thus may be more practical for system implementa- given applications sensitivity to that particular device. tion purposes. G = 20dB G = 12dB L-C 1 2 SAW MINI CIRCUITS BANDPASS AD9200 FILTER 50V T4 - 6T FILTER OUTPUT 50V 1:4 AIN 50V 200V 200V REFTS 280V REFBS 22.1V 93.1V VREF REFSENSE 1.0mF 0.1mF 1kV AVDD 1kV 0.1mF Figure 34. Simplified AD9200 IF Sampling Circuit REV. E –16– AD9200 Figures 35–38 combine the dual-tone SFDR as well as single Although not presented, data was also taken with the insertion tone SFDR and SNR performance at IF frequencies of 45 MHz, of an AD8009 gain stage of 32 dB in the signal path. No 70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli- degradation in two-tone SFDR vs. amplitude was noted at an tude data is referenced to dBFS while the single tone SNR data IF of 45 MHz, 70 MHz and 85 MHz. However, at 135 MHz, is referenced to dBc. The performance characteristics in these the AD8009 became the limiting factor in the distortion perfor- figures are representative of the AD9200 without the AD8009. mance until the two input tones were decreased to –15 dBFS The AD9200 was operated in the differential mode (via trans- from their full-scale level of –6.5 dBFS. Note: the SNR perfor- former) with a 1 V span at 20 MSPS. The analog supply mance in each case degraded by approximately 0.5 dB due to (AVDD) and the digital supply (DRVDD) were set to +5 V and the AD8009’s in-band noise contribution. 3.3 V, respectively. 90 90 SINGLE TONE SFDR 80 80 DUAL TONE SFDR 70 70 SINGLE TONE SFDR DUAL TONE SFDR 60 60 50 50 40 40 30 30 SNR SNR 20 CLK = 20MSPS 20 CLK = 20MSPS SINGLE TONE – 45.52MHz SINGLE TONE – 85.52MHz DUAL TONE– F = 44.49MHz DUAL TONE– F = 84.49MHz 10 1 10 1 – F = 45.52MHz – F = 85.52MHz 2 2 0 0 –60 –50 –40 –30 –20 –10 0 –60 –50 –40 –30 –20 –10 0 INPUT POWER LEVEL – dBFS INPUT POWER LEVEL – dBFS Figure 35. SNR/SFDR for IF @ 45 MHz Figure 37. SNR/SFDR for IF @ 85 MHz 90 90 SINGLE TONE SFDR 80 80 DUAL TONE SFDR 70 70 DUAL TONE SFDR 60 60 SINGLE TONE SFDR 50 50 40 40 30 30 SNR SNR 20 20 CLK = 20MSPS CLK = 21.538MSPS SINGLE TONE – 135.52MHz SINGLE TONE – 70.55MHz DUAL TONE – F = 134.44MHz 10 1 10 DUAL TONE– F = 69.50MHz 1 – F = 135.52MHz 2 – F = 70.55MHz 2 0 0 –60 –50 –40 –30 –20 –10 0 –60 –50 –40 –30 –20 –10 0 INPUT POWER LEVEL – dBFS INPUT POWER LEVEL – dBFS Figure 36. SNR/SFDR for IF @ 70 MHz Figure 38. SNR/SFDR for IF @ 135 MHz REV. E –17– WORST CASE SPURIOUS – dBFS WORST CASE SPURIOUS – dBFS SNR – dBc SNR – dBc WORST CASE SPURIOUS – dBFS WORST CASE SPURIOUS – dBFS SNR – dBc SNR – dBc AD9200 R11 R10 +3–5A 15kV 5kV R17 +3–5A TP14 5 R15 316V 0.626V TO 4.8V R7 1kV 7 2 5.49kV AD822 Q1 TP16 4 XXXX U2 2N3906 AD822 1 6 ADJ. U2 3 R8 C7 8 EXTT D1 10kV 0.1mF CW C11 C8 C12 C13 AD1580 0.1mF R19 10/10V 10/10V 0.1mF 178V R9 +3–5A 1.5kV CM R13 11kV R20 TP17 R12 178V C29 10kV 0.1mF 2 XXXX 4 ADJ. EXTB 1 6 AD822 U3 C14 C15 3 7 R14 AD822 Q2 8 0.1mF 10/10V 10kV U3 5 2N3904 CW C10 R16 C9 0.1mF 1kV R18 10/10V 316kV +3–5A TP11 J7 JP5 CLAMP R37 1kV DRVDD R53 49.9V B JP17 1 S3 2 THREE-STATE R38 3 A 1kV B 1 GND S4 2 STBY JP18 3 A R39 1kV 710 13 J8 RN1 DRVDD 22V AVDD 27 J8 C16 C19 611 11 J8 0.1mF 0.1mF 25 J8 RN1 3 J8 22V C17 C18 2 J8 5 12 10/10V 10/10V 9 J8 4 J8 RN1 22V 28 6 J8 2 16 8 OTR B U4 A 413 AVDD DRVDD 8 J8 7 15 9 J8 TP19 B U4 A RN1 U1 D5 21 3 10 J8 B U4 A WHITE 22V D6 4 20 AD9200 B U4 A 12 J8 19 5 13 D7 B U4 A 2 15 OTR D8 18 6 5 J8 14 J8 B U4 A D9 17 7 RN1 D0 15 3 B U4 A DUTCLK CLK D0 16 J8 14 10 B 1 16 4 D1 22V S2 B U4 A THREE-STATE THREE-STATE D1 2 24 1 18 J8 17 5 D2 DRVDD VCCB +3–5D VCCA 116 D2 STBY STBY 3 23 2 18 6 D3 1 J8 NC1 T/R C40 20 REFSENSE REFSENSE D3 C20 J8 22 D4 11 19 7 OE A RN1 CLAMP CLAMP D4 0.1mF GD2 0.1mF 13 20 8 D5 12 22 J8 GD1 22V GD3 CLAMPIN CLAMPIN D5 U4 D6 GND 21 9 REFTS REFTS D6 24 J8 GND GND D7 GND CLK 22 10 74LVXC4245WM JP21 REFTF REFTF D7 23 11 D8 WHITE 26 J8 D8 3 1 MODE MODE 24 12 D9 +3–5D 611 REFBF REFBF D9 2 19 5 NC 39 J8 25 CLK B U5 A 33 J8 REFBS REFBS 20 4 26 C42 RN2 B U5 A 28 J8 VREF VREF CLK_OUT 21 3 0.1mF 27 B U5 A 22V AIN AIN 512 D0 18 6 29 J8 B U5 A 23 J8 17 7 D1 AVSS + DRVSS B RN2 C33 U5 A 30 J8 16 8 D2 10/10V B 22V U5 A 1 14 15 9 D3 31 J8 B U5 A D4 14 10 13 4 B U5 A 32 J8 21 J8 24 1 +3–5D VCCB VCCA RN2 23 2 34 J8 NC1 T/R C21 DRVDD 22 11 22V OE GD2 0.1mF NC 35 J8 13 12 3 14 C41 GD1 GD3 U5 19 J8 36 0.1mF J8 GND RN2 74LVXC4245WM NC 37 J8 GND 22V GND 38 J8 215 32 1 17 J8 40 J8 RN2 JP20 C43 22V 0.1mF GND 16 1 15 J8 GND RN2 22V Figure 39a. Evaluation Board Schematic REV. E –18– AD9200 JP14 REFSENSE AVDD JP1 JP10 EXTB R5 AVDD TP3 MODE C3 JP2 10k 0.1 F TP1 JP15 REFBF TP4 C4 C5 + 0.1 F R6 10/10V JP3 JP9 10k REFTF C6 JP16 JP4 0.1 F VREF AVDDCLK JP22 B TP5 GND AVDD EXTT 1 S5 GND 2 R35 CLAMPIN 4.99k 3 JP11 TP6 A EXTT R34 JP6 2k REFTS CW GND JP12 R36 C36 C37 C38 C35 4.99k U6 U6 0.1 F 0.1 F 0.1 F 10/10V TP7 12 5 6 REFBS GND JP7 JP13 EXTB TP12 C30 B B T1–1T 0.1 F 1 1 AIN S7 S6 2 2 3 J1 A 3 3 2 J5 3 4 A A R51 S8 2 ADC_CLK B 49.9 1 R1 49.9 TP8 6 R4 CLK P 49.9 1 S JP8 REFBS TP13 T1 R52 TP9 R2 U6 JP26 49.9 3 100 4 C1 DUTCLK CM 0.1 F TP10 A R3 DCIN 2 100 3 S1 C2 1 47/10V B TP29 L4 U6 DECOUPLING +3–5D AVDDCLK J9 C32 C31 0.1 F 10/10V TP20 14 U6 L1 74AHC14 PWR 9 8 C28 J2 DRVDD U6 C22 0.1 F C23 GND 0.1 F 10/10V U6 11 10 TP21 7 L2 U6 13 12 J3 AVDD C24 C25 0.1 F 33/16V TP22 L3 +3–5A J4 C26 C27 0.1 F 10/10V TP23 TP24 TP25 TP26 TP27 TP28 GND J6 GND J10 Figure 39b. Evaluation Board Schematic REV. E –19– AD9200 Figure 40a. Evaluation Board, Component Signal (Not to Scale) Figure 40b. Evaluation Board, Solder Signal (Not to Scale) REV. E –20– AD9200 Figure 40c. Evaluation Board Power Plane (Not to Scale) Figure 40d. Evaluation Board Ground Plane (Not to Scale) REV. E –21– AD9200 Figure 40e. Evaluation Board Component Silk (Not to Scale) Figure 40f. Evaluation Board Solder Silk (Not to Scale) REV. E –22– AD9200 GROUNDING AND LAYOUT RULES DIGITAL OUTPUTS As is the case for any high performance device, proper ground- Each of the on-chip buffers for the AD9200 output bits ing and layout techniques are essential in achieving optimal (D0–D9) is powered from the DRVDD supply pins, separate performance. The analog and digital grounds on the AD9200 from AVDD. The output drivers are sized to handle a variety have been separated to optimize the management of return of logic families while minimizing the amount of glitch energy currents in a system. Grounds should be connected near the generated. In all cases, a fan-out of one is recommended to keep ADC. It is recommended that a printed circuit board (PCB) of the capacitive load on the output data bits below the specified at least four layers, employing a ground plane and power planes, 20 pF level. be used with the AD9200. The use of ground and power planes For DRVDD = 5 V, the AD9200 output signal swing is compat- offers distinct advantages: ible with both high speed CMOS and TTL logic families. For 1. The minimization of the loop area encompassed by a signal TTL, the AD9200 on-chip, output drivers were designed to and its return path. support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 20 MSPS, other TTL 2. The minimization of the impedance associated with ground families may be appropriate. For interfacing with lower voltage and power paths. CMOS logic, the AD9200 sustains 20 MSPS operation with 3. The inherent distributed capacitor formed by the power plane, DRVDD = 3 V. In all cases, check your logic family data sheets PCB insulation and ground plane. for compatibility with the AD9200 Digital Specification table. These characteristics result in both a reduction of electro- magnetic interference (EMI) and an overall improvement in THREE-STATE OUTPUTS performance. The digital outputs of the AD9200 can be placed in a high impedance state by setting the THREE-STATE pin to HIGH. It is important to design a layout that prevents noise from cou- This feature is provided to facilitate in-circuit testing or evaluation. pling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD9200 in a solid ground plane. The power and ground return currents must be carefully managed. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. REV. E –23– AD9200 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Plastic Thin Quad Flatpack (LQFP) (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.030 (0.75) 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.018 (0.45) 0.053 (1.35) 0.018 (0.45) 37 48 36 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15) 12 25 13 24 0.002 (0.05) 0° MIN 0° – 7° 0.007 (0.18) 0.011 (0.27) 0.019 (0.5) 0.004 (0.09) BSC 0.006 (0.17) 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 1 14 0.07 (1.79) 0.078 (1.98) PIN 1 0.066 (1.67) 0.068 (1.73) 0.03 (0.762) 8° 0.0256 0.015 (0.38) 0° 0.022 (0.558) 0.008 (0.203) SEATING 0.009 (0.229) (0.65) 0.010 (0.25) 0.002 (0.050) PLANE BSC 0.005 (0.127) REV. E –24– 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 0.276 (7.0) BSC 0.354 (9.00) BSC PRINTED IN U.S.A. C3033e–0–8/99