ANALOG DEVICES AD9148

Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9148 FEATURES GENERAL DESCRIPTION Single-carrier W-CDMA ACLR = 80 dBc at 150 MHz IF The AD9148 is a quad, 16-bit, high dynamic range, digital-to- Channel-to-channel isolation > 90 dB analog converter (DAC) that provides a sample rate of 1000 MSPS. Analog output This device includes features optimized for direct conversion Adjustable 8.7 mA to 31.7 mA transmit applications, including gain, phase, and offset compen- R = 25 Ω to 50 Ω L sation. The DAC outputs are optimized to interface seamlessly with Novel 2×, 4×, and 8× interpolator eases data interface analog quadrature modulators such as the ADL5371/ADL5372/ On-chip fine complex NCO allows carrier placement ADL5373/ADL5374/ADL5375. A serial peripheral interface (SPI) anywhere in DAC bandwidth is provided for programming of the internal device parameters. High performance, low noise PLL clock multiplier Full-scale output current can be programmed over a range of 8.7 mA Multiple chip synchronization interface to 31.7 mA. The device operates from 1.8 V and 3.3 V supplies Programmable digital inverse sinc filter for a total power consumption of 3 W at the maximum sample Auxiliary DACs allow for offset control rate. The AD9148 is enclosed in a 196-ball chip scale package ball Gain DACs allow for I and Q gain matching grid array with the option of an attached heat spreader. Programmable I and Q phase compensation PRODUCT HIGHLIGHTS Digital gain control 1. Low noise and intermodulation distortion (IMD) enable Flexible LVDS digital I/F supports 32- or 16-bit bus width high quality synthesis of wideband signals from baseband 196-ball CSP_BGA, 12 mm × 12 mm to high intermediate frequencies. APPLICATIONS 2. A proprietary DAC output switching technique enhances Wireless infrastructure dynamic performance. LTE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM 3. The current outputs are easily configured for various MIMO/transmit diversity single-ended or differential circuit topologies. Digital high or low IF synthesis 4. The LVDS data input interface includes FIFO to ease input timing. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF LO ± f f IF IF DC DIGITAL INTERPOLATION FILTERS ↑2 ↑2 ↑2 DAC1 POST DAC AQM PA ANALOG FILTER LO ↑2 ↑2 ↑2 DAC2 FPGA/ASIC/DSP ↑2 ↑2 ↑2 DAC3 LO POST DAC AQM PA ↑2 ↑2 ↑2 DAC4 NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 08910-001 AD9148 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Synchronizing Multiple Devices .............................................. 45 Applications ....................................................................................... 1 Synchronization with Clock Multiplication ............................... 45 General Description ......................................................................... 1 Synchronization with Direct Clocking .................................... 47 Product Highlights ........................................................................... 1 Additional Synchronization Features ...................................... 48 Typical Signal Chain ......................................................................... 1 Interface Timing ............................................................................. 49 Revision History ............................................................................... 3 Digital Data Path ............................................................................ 50 Functional Block Diagram .............................................................. 4 Premodulation ............................................................................ 50 Specifications ..................................................................................... 5 Programmable Inverse Sinc Filter ............................................ 50 DC Specifications ......................................................................... 5 Interpolation Filters ................................................................... 51 Input/Output Signal Specifications ............................................ 6 Fine Modulation ......................................................................... 54 Digital Input Data Timing Specifications ................................. 7 Quadrature Phase Correction ................................................... 55 AC Specifications .......................................................................... 8 DC Offset Correction ................................................................ 55 Absolute Maximum Ratings ............................................................ 9 Digital Gain Control .................................................................. 55 Thermal Resistance ...................................................................... 9 Clock Generation ........................................................................... 56 Maximum Safe Power Dissipation ............................................. 9 DAC Input Clock Configurations ............................................ 56 ESD Caution .................................................................................. 9 Driving the CLK_x and REFCLK_x Inputs ............................ 56 Pin Configurations and Function Descriptions ......................... 11 Direct Clocking .......................................................................... 56 Typical Performance Characteristics ........................................... 15 Clock Multiplication .................................................................. 57 Terminology .................................................................................... 21 Analog Outputs............................................................................... 59 Serial Peripheral Interface ............................................................. 22 Transmit DAC Operation .......................................................... 59 General Operation of the Serial Interface ............................... 22 Auxiliary DAC Operation ......................................................... 60 Data Format ................................................................................ 22 Interfacing to Modulators ......................................................... 61 SPI Pin Descriptions .................................................................. 22 Device Power Dissipation .............................................................. 63 SPI Options ................................................................................. 23 Temperature Sensor ....................................................................... 65 SPI Register Map ............................................................................. 24 Interrupt Request Operation ........................................................ 66 SPI Register Descriptions .......................................................... 26 Interrupt Service Routine .......................................................... 66 Input Data Ports .............................................................................. 40 Interface Timing Validation .......................................................... 67 Dual-Port Mode .......................................................................... 40 SED Operation ............................................................................ 67 Single-Port Mode ........................................................................ 40 SED Example .............................................................................. 67 Byte Mode .................................................................................... 41 Example Start-Up Routine ............................................................ 68 Data Interface Options .............................................................. 41 Derived PLL Settings ................................................................. 68 Recommended Frame Input Bias Circuitry ............................ 41 Derived NCO Settings ............................................................... 68 FIFO Operation .............................................................................. 42 Start-Up Sequence ...................................................................... 68 Synchronizing and Resetting the FIFO ................................... 43 Device Verification Sequence ................................................... 68 Monitoring the FIFO Status ...................................................... 44 Outline Dimensions ....................................................................... 69 Device Synchronization ................................................................. 45 Ordering Guide .......................................................................... 70 Rev. B | Page 2 of 72 Data Sheet AD9148 REVISION HISTORY 1/12—Rev. A to Rev. B Deleted LVDS Pad Ctrl Row, Table 13 .......................................... 38 Change to Chip ID Default Value, Table 12 ................................. 25 Deleted Frame Input Levels Section and Table 15 ...................... 41 Change to Chip ID Readback Value, Table 13 ............................. 32 Added Recommended Frame Input Bias Circuitry Section and Changed 0x02 to 0x0A ................................................................... 65 Figure 45; Renumbered Sequentially ............................................ 41 Changes to Timing Optimization Section ................................... 48 9/11—Rev. 0 to Rev. A Added Table 15 ................................................................................ 48 Changes to Filter Implementation Section .................................. 50 Changes to General Description Section ....................................... 1 Deleted Input High Voltage, VIA or VIB Parameter, Table 2, Input Changes to Figure 74 ...................................................................... 57 Low Voltage, VIA or VIB Parameter, Table 2, and Deleted Test Access Port Section, Table 27, Figure 92, and Note 2, Table 2; Renumbered Sequentially .................................... 6 Table 28 ............................................................................................. 68 Added Input Voltage Range, V or V Parameter, Table 2 ......... 6 Changes to Start-Up Sequence Section ........................................ 68 IA IB Changes to Table 10 ........................................................................ 13 Deleted Figure 93 ............................................................................ 69 Changes to Figure 41 and Figure 42 ............................................. 23 Deleted Table 29 .............................................................................. 70 Changes to 0x1E Addr, Table 12 .................................................... 24 Deleted 0x74 Row, Table 12 ........................................................... 26 6/10—Revision 0: Initial Version Changes to PLL Control 2, Table 13 ............................................. 29 Changes to HB3 Control, 1E, Bit 7 Row, Table 13 ...................... 32 Rev. B | Page 3 of 72 AD9148 Data Sheet FUNCTIONAL BLOCK DIAGRAM 310MHz/620MHz 500MHz/1GHz 500MHz/1GHz 310MHz 310MHz 1GHz f /2 IOUT1_P S –1 16-BIT SINC MOD DAC1 IOUT1_N 2× 2× 2× 1.2GHz DCIA_P/ GAIN I OFFSET I GAIN DCIA_N AUX1_P AUX1 Q OFFSET Q GAIN AUX1_N FRAMEA_P/ FRAMEA_N 2× 2× 2× IOUT2_P 16-BIT 16 A[15:0]_P/ f /2 DAC2 IOUT2_N S –1 A[15:0]_N SINC MOD GAIN COS 32-BIT AUX2_P AUX2 NCO SIN AUX2_N f /2 S IOUT3_P –1 16-BIT SINC 16 MOD B[15:0]_P/ DAC3 IOUT3_N B[15:0]_N 2× 2× 2× GAIN I OFFSET I GAIN FRAMEB_P/ AUX3_P AUX3 FRAMEB_N AUX3_N Q OFFSET Q GAIN DCIB_P/ 2× 2× 2× DCIB_N IOUT4_P 16-BIT f /2 DAC4 IOUT4_N S –1 SINC MOD GAIN AUX4_P AUX4 AUX4_N GAIN/ OFFSET_CTRL VREF REFERENCE PLL_CTRL INTERNAL CLOCK TIMING AND CONTROL LOGIC I120 BIAS CLK_P CLK_N DAC_CLK PROGRAMMING SERIAL REFCLK_P/ POWER-ON MULTI-CHIP REGISTERS IN/OUT PORT CLOCK SYNC_P RESET SYNC MULTIPLIER (2× – 16×) REFCLK_N/ SYNC_N SYNC Figure 2. Rev. B | Page 4 of 72 MODE DATA RECEIVER FIFO FIFO PREMOD_CLK PREMOD_EN SDO FILTER SDIO COEFFICIENT SCLK CS INVSINE_EN IRQ HB1_CLK RESET HB1_EN HB2_CLK HB2_EN HB3_CLK HB3_EN PHASE CORRECTION 08910-002 Data Sheet AD9148 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, maximum sample rate, unless MIN MAX OUTFS otherwise noted. Table 1. Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error ±0.001 % FSR Gain Error (with Internal Reference) ±2 % FSR 1 Full-Scale Output Current 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns TEMPERATURE DRIFT Main DAC Offset 0.04 ppm/°C Main DAC Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES IOVDD 1.71 1.8/3.3 3.47 V DVDD18 1.71 1.8 1.89 V −1 POWER CONSUMPTION (NCO OFF, PLL DISABLED, AND SINC FILTER BYPASSED, UNLESS OTHERWISE NOTED) 1 × Mode, f = 300 MSPS, f = 600 MSPS 0.79 W DAC INTERFACE 2 × Mode, f = 500 MSPS, f = 500 MSPS 1.49 W DAC INTERFACE 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS 2.18 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, NCO On 2.47 W 4 × Mode, f = 800 MSPS, f = 400 MSPS, PLL Enabled 2.26 W DAC INTERFACE −1 4 × Mode, f = 800 MSPS, f = 400 MSPS, Sinc Filter Enabled 2.44 W DAC INTERFACE 8 × Mode, f = 800 MSPS, f = 200 MSPS 2.01 2.16 W DAC INTERFACE AVDD33 368 373 mW CVDD18 261 280 mW IOVDD 0.8 1.6 mW DVDD18 1377 1504 mW Power-Down Mode 1 12 mW OPERATING RANGE −40 +25 +85 °C 1 Based on a 10 kΩ external resistor. Rev. B | Page 5 of 72 AD9148 Data Sheet INPUT/OUTPUT SIGNAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter Min Typ Max Unit CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CS, RESET, TMS, TDI, TCK) Input VIN Logic High (IOVDD = 1.8 V) 1.2 V Input VIN Logic High (IOVDD = 3.3 V) 2.0 V Input V Logic Low (IOVDD = 1.8 V) 0.6 V IN Input V Logic Low (IOVDD = 3.3 V) 0.8 V IN CMOS OUTPUT LOGIC LEVEL (SDIO, SDO, IRQ, PLL_LOCK, TDO) Output V Logic High (IOVDD = 1.8 V) 1.4 V OUT Output V Logic High (IOVDD = 3.3 V) 2.4 V OUT Output VOUT Logic Low (IOVDD = 1.8 V) 0.4 V Output VOUT Logic Low (IOVDD = 3.3 V) 0.4 V LVDS RECEIVER INPUTS (A[15:0]_x, B[15:0]_x, DCIA_x, DCIB_x) Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH to VIDTHL 20 mV Receiver Differential Input Impedance, R 80 120 Ω IN LVDS Input Rate, f (See Table 4) 1200 MSPS INTERFACE LVDS RECEIVER INPUTS (FRAMEA_x, FRAMEB_x) Input Voltage Range, V or V 825 1575 mV IA IB DAC CLOCK INPUT (CLK_P, CLK_N) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage (Self-Biasing, AC-Coupled) 1.25 V Maximum Clock Rate 1000 MSPS REFERENCE CLOCK INPUT (REFCLK_x/SYNC_x) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage (Self-Biasing, AC-Coupled) 1.25 V Maximum Clock Rate 500 MSPS Minimum Clock Rate (PLL Enabled) Loop Divider = /2 125 MSPS Loop Divider = /4 62.5 MSPS Loop Divider = /8 31.25 MSPS Loop Divider = /16 15.625 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High (t ) 12.5 ns PWH Minimum Pulse Width Low (tPWL) 12.5 ns Set-Up Time, SDI to SCLK (tDS) 1.9 ns Hold Time, SDI to SCLK (tDH) 0.2 ns Data Valid, SDO to SCLK (t ) 23 ns DV Setup time, CS to SCLK (t ) 1.4 ns DCSB Rev. B | Page 6 of 72 Data Sheet AD9148 DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter Min Typ Max Unit LATENCY (DACCLK CYCLES) 1× Interpolation (with or Without Coarse Modulation) 64 Cycles 2× Interpolation (with or Without Coarse Modulation) 125 Cycles 4× Interpolation (with or Without Coarse Modulation) 254 Cycles 8× Interpolation (with or Without Coarse Modulation) 508 Cycles Inverse Sinc (1× Interpolation) 10 Cycles Inverse Sinc (2× Interpolation) 20 Cycles Inverse Sinc (4× Interpolation) 40 Cycles Inverse Sinc (8× Interpolation) 80 Cycles Fine Modulation 12 Cycles Power–Up Time 100 ms Table 4. Maximum Rate Maximum Rate (MSPS) Interface Mode f f f f f f INTERFACE DATA HB1 HB2 HB3 DAC Dual Port Mode 620 310 620 1000 1000 1000 Single Port Mode or Byte Mode 1200 300 600 1000 1000 1000 DAC1 32 32 32 AND 2× 2× 2× DATA FIFO A DAC2 INPUT DATA PORT A LATCH ASSEMBLER DATAPATH WRITE PTR A DCIA CLK GENERATOR DACCLK AND DISTRIBUTOR DATAPATH DCIB WRITE PTR B ONE DCI 32 32 32 DAC3 INPUT DATA DATA 2× AND 2× 2× PORT B LATCH ASSEMBLER DAC4 FIFO B INTERFACE MODE f f f f f f INTERFACE DATA HB1 HB2 HB3 DAC Figure 3. Defining Maximum Rates Rev. B | Page 7 of 72 READ PTR B READ PTR A 08910-003 AD9148 Data Sheet AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 5. Parameter Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 400 MSPS, fOUT = 80 MHz 72 dBc fDAC = 600 MSPS, fOUT = 100 MHz 67 dBc f = 1000 MSPS, f = 100 MHz 65 dBc DAC OUT TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 400 MSPS, fOUT = 100 MHz 85 dBc f = 600 MSPS, f = 120 MHz 82 dBc DAC OUT f = 1000 MSPS, f = 150 MHz 76 dBc DAC OUT NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING f = 200 MSPS, f = 80 MHz −160 dBm/Hz DAC OUT f = 400 MSPS, f = 100 MHz −161 dBm/Hz DAC OUT fDAC = 800 MSPS, fOUT = 100 MHz −162.5 dBm/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER f = 737.28 MSPS, f = 100 MHz, PLL Off −81 dBc DAC OUT fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL On −78 dBc fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL Off −79 dBc fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL On −72.5 dBc W-CDMA ALTERNATE CHANNEL LEAKAGE RATIO, SINGLE CARRIER fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL Off −87 dBc fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL On −83 dBc f = 737.28 MSPS, f = 200 MHz, PLL Off −84 dBc DAC OUT f = 737.28 MSPS, f = 200 MHz, PLL On −80.5 dBc DAC OUT Rev. B | Page 8 of 72 Data Sheet AD9148 ABSOLUTE MAXIMUM RATINGS Table 6. Table 7. Thermal Resistance With Package Type θ θ θ Unit Notes JA JB JC Parameter Respect To Rating 196-Ball CSP_BGA 24.7 12.6 5.7 °C/W 4-layer board, AVDD33, IOVDD AGND, −0.3 V to +3.6 V 25 PCB vias DGND, 19.2 10.9 5.3 °C/W 8-layer board, CGND 25 PCB vias DVDD18, CVDD18 AGND, −0.3 V to +2.10 V 18.1 10.5 5.3 °C/W 10-layer board, DGND, 25 PCB vias CGND 18.0 10.5 5.3 °C/W 12-layer board, AGND DGND, −0.3 V to +0.3 V 25 PCB vias CGND 196-Ball BGA_ED 20.9 8.6 3.1 °C/W 4-layer board, DGND AGND, −0.3 V to +0.3 V 25 PCB vias CGND 16.2 7.7 3.1 °C/W 8-layer board, CGND AGND, −0.3 V to +0.3 V 25 PCB vias DGND 15.2 7.4 3.1 °C/W 10-layer board, I120, VREF AGND −0.3 V to AVDD33 + 0.3 V 25 PCB vias IOUT1_P, IOUT1_N, AGND −1.0 V to AVDD33 + 0.3 V 15.0 7.4 3.1 °C/W 12-layer board, IOUT2_P, IOUT2_N, 25 PCB vias IOUT3_P, IOUT3_N, IOUT4_P, IOUT4_N MAXIMUM SAFE POWER DISSIPATION A15_P to A0_P, DGND −0.3 V to DVDD18 + 0.3 V The maximum junction temperature for the AD9148 is 125°C. A15_N to A0_N, With the thermal resistance of the molded package (CSP_BGA) B15_P to B0_P, given for a 12 layer board, the maximum power that can be B15_N, B0_N dissipated in this package can be calculated as DCIA_P, DCIA_N, DGND −0.3 V to DVDD18+ 0.3 V FRAMEA_P, FRAMEA_N, (T −T ) (125− 85) J A Power = = = 2.22 W DCIB_P, DCIB_N, MAX θ 18.0 JA FRAMEB_P, FRAMEB_N CLK_P, CLK_N, CGND −0.3 V to CVDD18 + 0.3 V To increase the maximum power, the AD9148 is available in a REFCLK_P, REFCLK_N second package option (BGA_ED), which includes a heat spreader CSB, SCLK, SDIO, SDO, DGND −0.3 V to IOVDD + 0.3 V on top of the package. Also, an external heat sink can be attached to TDO, TDI, TCK, TMS, the top of the AD9148 CSP_BGA package. The adjusted maximum RESET, IRQ, PLL_LOCK power for each of these conditions is shown in Table 8. Junction Temperature 125°C With the thermal resistance of the heat spreader package (BGA_ED) Storage Temperature −65°C to +150°C given for a 12-layer board, the maximum power that can be Range dissipated in this package can be calculated as Stresses above those listed under Absolute Maximum Ratings (T −T ) (125− 85) J A may cause permanent damage to the device. This is a stress Power = = = 2.67 W MAX θ 15.0 rating only; functional operation of the device at these or any JA other conditions above those indicated in the operational To increase the maximum power, an external heat sink can be section of this specification is not implied. Exposure to absolute attached to the top of the AD9148 BGA_ED package. The adjusted maximum rating conditions for extended periods may affect maximum power for an external heat sink is shown in Table 8. device reliability. To aid in the selection of package, the maximum f rate for a given DAC power dissipation over several operating conditions is shown in THERMAL RESISTANCE Table 9. The maximum fDAC rate applies to all interpolation rates. Typical θ , θ , and θ are specified vs. the number of PCB layers in JA JB JC Note that, if the programmable inverse sinc filter is enabled, the still air for each package offering. Airflow increases heat dissipation maximum fDAC rate specified in Table 9 decreases. effectively reducing θ and θ . JA JB ESD CAUTION Rev. B | Page 9 of 72 AD9148 Data Sheet Table 8. Thermal Resistance and Maximum Power PCB Maximum 1 Package Type T (°C) PCB Layers PCB Vias External Heat Sink Case T (°C) θ (°C/W) Power (W) A J JA 196-ball CSP_BGA 85 12 25 No CSP_BGA 125 18.0 2.22 196-ball CSP_BGA 85 12 25 Yes CSP_BGA 125 16.0 2.50 196-ball BGA_ED 85 12 25 No BGA_ED 125 15.0 2.67 196-ball BGA_ED 85 12 25 Yes BGA_ED 125 14.0 2.86 1 Heat sink is used in the thermal model: 13 mm × 13 mm, 15 mm tall. Table 9. Power vs. f Rate and Functionality DAC 1 Maximum f (MSPS) DAC Coarse Modulation Fine Modulation (NCO) 2 Maximum Power (W) Package Heat-Sink Combination PLL Off PLL On PLL Off PLL On 2.22 CSP_BGA No 820 740 695 630 2.50 CSP_BGA Yes 950 875 810 740 2.67 BGA_EP No 1000 945 870 810 2.86 BGA_EP Yes 1000 1000 940 870 1 Typical maximum f rate with inverse sinc filter off. DAC 2 Heat sink is used in the thermal model: 13 mm × 13 mm, 15 mm tall. Rev. B | Page 10 of 72 Data Sheet AD9148 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 2 3 1 4 5 6 7 8 9 10 11 12 13 14 V IOUT2 IOUT2 I120 REF IOUT3 IOUT3 A CLK REF A AUX2 AUX2 CLK NC NC REF AUX3 AUX3 B B IOUT1 AUX1 C AUX4 IOUT4 C IOUT1 AUX1 D AUX4 IOUT4 D + + + + E E F X X X X X X F G G H H J J K K L L M M N N P P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 POSITIVE NEGATIVE + CVDD18 AVSS X AVDD33 CLK CLK TERMINAL TERMINAL Figure 4. Pin Configuration (Top View), Analog and Clock Domain Pins Rev. B | Page 11 of 72 08910-004 AD9148 Data Sheet 1 23 5 67 9 10 11 14 4 8 12 13 A A B B C C D D E E F F TAP SPI INTERFACE INTERFACE SDO CS + + Trch Trch TMS TDI G G SDIO SCLK RESET IRQ NC PLL TCK TDO H H J FrB DCIB B0 B2 X XXXX X B11 B13 DCIA FrA J K FrB DCIB B0 B2 X XXXX X B11 B13 DCIA FrA K A0 A2 B1 B3 B4 B5 B6 B7 B8 B9 B10 B12 B14 B15 L L A0 A2 B1 B3 B4 B5 B6 B7 B8 B9 B10 B12 B14 B15 M M N A1 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 N P A1 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 P 23 67 10 11 14 1 4 5 8 9 12 13 IOVDD + X DVDD18 DVSS A15 +LVDS A15 –LVDS Figure 5. Pin Configuration (Top View), Digital Domain Pins Table 10. Pin Function Description Pin No. Mnemonic Description E6, E7, E8, E9 CVDD18 1.8 V Clock Supply. F5, F6, F7, F8, F9, F10 AVDD33 3.3 V Analog Supply. A1, A2, A5, A10, A13, A14, B1, AVSS Analog Supply Ground. B2, B5, B10, B13, B14, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, E1, E2, E3, E4, E5, E10, E11, E12, E13, E14, F1, F2, F3, F4, F11, F12, F13, F14 G5, G6, G7, G8, G9, G10, H5, H6, DVSS Digital Supply Ground. H7, H8, H9, H10 G3, G4 IOVDD Supply for Serial Ports (SPI and TAP), RESET and IRQ. 1.8 V to 3.3 V can be supplied to these pins. J5, J6, J7, J8, J9, J10, K5, K6, K7, DVDD18 1.8 V Digital Supply. K8, K9, K10 B7, B8, H11 NC No Connect. Do not connect to this pin. C1 IOUT1_N DAC 1 Complementary Output Current. D1 IOUT1_P DAC 1 Positive Output Current. A3 IOUT2_N DAC 2 Complementary Output Current. A4 IOUT2_P DAC 2 Positive Output Current. A11 IOUT3_P DAC 3 Positive Output Current. A12 IOUT3_N DAC 3 Complementary Output Current. Rev. B | Page 12 of 72 08910-005 Data Sheet AD9148 Pin No. Mnemonic Description C14 IOUT4_N DAC 4 Complementary Output Current. D14 IOUT4_P DAC 4 Positive Output Current. C2 AUX1_N Auxiliary DAC 1 Complementary Output Current. D2 AUX1_P Auxiliary DAC 1 Positive Output Current. B3 AUX2_N Auxiliary DAC 2 Complementary Output Current. B4 AUX2_P Auxiliary DAC 2 Positive Output Current. B11 AUX3_P Auxiliary DAC 3 Positive Output Current. B12 AUX3_N Auxiliary DAC 3 Complementary Output Current. C13 AUX4_N Auxiliary DAC 4 Complementary Output Current. D13 AUX4_P Auxiliary DAC 4 Positive Output Current. A8 I120 Tie to analog ground via a 10 kΩ resistor to generate a 120 µA reference current. A7 VREF Band Gap Voltage Reference I/O. Decouple to analog ground via a 0.1 µF capacitor. Output impedance is approximately 5 kΩ. B6, A6 CLK_P/CLK_N Positive/Negative DAC Clock Input (CLK). B9, A9 REFCLK_P/REFCLK_N or PLL Reference Clock Input (REFCLK_x). This pin has a secondary function as SYNC_P/SYNC_N a synchronization input (SYNC_x). H4 IRQ Active Low Open-Drain Interrupt Request Output. Pull up to IOVDD with a 10 kΩ resistor. H3 RESET An active low LVCMOS input resets the device. Pull up to IOVDD. G1 SDO Serial Data Output for SPI. G2 CS Active Low Chip Select for SPI. H1 SDIO Serial Data Input/Output for SPI. H2 SCLK Qualifying Clock Input for SPI. G11, G12 TRENCH Connect this pin to VSS. H12 PLL_LOCK Active High LVCMOS Output. It indicates the lock status of the PLL circuitry. G13 TMS Reserved for Future Use. Connect to DVSS. G14 TDI Reserved for Future Use. Connect to DVSS. H13 TCK Reserved for Future Use. Connect to DVSS. H14 TDO Reserved for Future Use. Leave unconnected. M1, L1 A0_P/A0_N LVDS Data Input Pair, Port A (LSB). P1, N1 A1_P/A1_N LVDS Data Input Pair, Port A. M2, L2 A2_P/A2_N LVDS Data Input Pair, Port A. P2, N2 A3_P/A3_N LVDS Data Input Pair, Port A. P3, N3 A4_P/A4_N LVDS Data Input Pair, Port A. P4, N4 A5_P/A5_N LVDS Data Input Pair, Port A. P5, N5 A6_P/A6_N LVDS Data Input Pair, Port A. P6, N6 A7_P/A7_N LVDS Data Input Pair, Port A. P7, N7 A8_P/A8_N LVDS Data Input Pair, Port A. P8, N8 A9_P/A9_N LVDS Data Input Pair, Port A. P9, N9 A10_P/A10_N LVDS Data Input Pair, Port A. P10, N10 A11_P/A11_N LVDS Data Input Pair, Port A. P11, N11 A12_P/A12_N LVDS Data Input Pair, Port A. P12, N12 A13_P/A13_N LVDS Data Input Pair, Port A. P13, N13 A14_P/A14_N LVDS Data Input Pair, Port A. P14, N14 A15_P/A15_N LVDS Data Input Pair, Port A (MSB). K13, J13 DCIA_P/DCIA_N LVDS Data Clock Input Pair for Port A. K14, J14 FRAMEA_P/FRAMEA_N LVDS Frame Input for Port A. Tie to LVDS logic low if not used. Recommended external bias circuit is shown in Figure 49. K3, J3 B0_P/B0_N LVDS Data Input Pair, Port B (LSB). M3, L3 B1_P/B1_N LVDS Data Input Pair, Port B. K4, J4 B2_P/B2_N LVDS Data Input Pair, Port B. M4, L4 B3_P/B3_N LVDS Data Input Pair, Port B. M5, L5 B4_P/B4_N LVDS Data Input Pair, Port B M6, L6 B5_P/B5_N LVDS Data Input Pair, Port B. Rev. B | Page 13 of 72 AD9148 Data Sheet Pin No. Mnemonic Description M7, L7 B6_P/B6_N LVDS Data Input Pair, Port B. M8, L8 B7_P/B7_N LVDS Data Input Pair, Port B. M9, L9 B8_P/B8_N LVDS Data Input Pair, Port B. M10, L10 B9_P/B9_N LVDS Data Input Pair, Port B. M11, L11 B10_P/B10_N LVDS Data Input Pair, Port B. K11, J11 B11_P/B11_N LVDS Data Input Pair, Port B. M12, L12 B12_P/B12_N LVDS Data Input Pair, Port B. K12, J12 B13_P/B13_N LVDS Data Input Pair, Port B. M13, L13 B14_P/B14_N LVDS Data Input Pair, Port B. M14, L14 B15_P/B15_N LVDS Data Input Pair, Port B (MSB). K2, J2 DCIB_P/DCIB_N LVDS Data Clock Input Pair for Port B. K1, J1 FRAMEB_P/FRAMEB_N LVDS Frame Input for Port B. Tie to LVDS logic low if not used. Recommended external bias circuit is shown in Figure 49. Rev. B | Page 14 of 72 Data Sheet AD9148 TYPICAL PERFORMANCE CHARACTERISTICS –30 –30 –35 –35 f = 200MSPS, SECOND HARMONIC DATA f = 200MSPS, f + f DATA DATA OUT f = 200MSPS, THIRD HARMONIC DATA f = 310MSPS, f + f DATA DATA OUT –40 –40 f = 310MSPS, SECOND HARMONIC DATA f = 310MSPS, THIRD HARMONIC DATA –45 –45 –50 –50 –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 0 50 100 150 200 250 300 0 50 100 150 200 250 300 f (MHz) f (MHz) OUT OUT Figure 6. Harmonic Level vs. f over f , 2× Interpolation, Figure 9. Highest Digital Spur vs. f over f , 2× Interpolation, OUT DATA OUT DATA Digital Scale = 0 dBFS, Full-Scale Current = 20 mA Digital Scale = 0 dBFS, Full-Scale Current = 20 mA –30 –30 –35 –35 f = 150MSPS, SECOND HARMONIC DATA f = 150MSPS, f + f DATA DATA OUT f = 150MSPS, THIRD HARMONIC DATA f = 250MSPS, 2f – f DATA DATA OUT –40 –40 f = 250MSPS, SECOND HARMONIC DATA f = 250MSPS, THIRD HARMONIC DATA –45 –45 –50 –50 –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 f (MHz) f (MHz) OUT OUT Figure 7. Harmonic Level vs. f over f , 4× Interpolation, Figure 10. Highest Digital Spur vs. f over f , 4× Interpolation, OUT DATA OUT DATA Digital Scale = 0 dBFS, Full-Scale Current = 20 mA Digital Scale = 0 dBFS, Full-Scale Current = 20 mA –30 –30 –35 –35 f = 125MSPS, SECOND HARMONIC DATA f = 125MSPS, THIRD HARMONIC DATA –40 –40 –45 –45 –50 –50 –55 –55 –60 –60 –65 –65 f = 125MSPS, f + f DATA DATA OUT –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 f (MHz) f (MHz) OUT OUT Figure 8. Harmonic Level vs. f , 8× Interpolation over f = 125 MSPS, Figure 11. Highest Digital Spur vs. f , 8× Interpolation, f = 125 MSPS, OUT DATA OUT DATA Digital Scale = 0 dBFS, Full-Scale Current = 20 mA Digital Scale = 0 dBFS, Full-Scale Current = 20 mA Rev. B | Page 15 of 72 HARMONIC LEVEL (dBc) HARMONIC LEVEL (dBc) HARMONIC LEVEL (dBc) 08910-008 08910-007 08910-006 SPUR LEVEL (dBc) SPUR LEVEL (dBc) SPUR LEVEL (dBc) 08910-011 08910-010 08910-009 AD9148 Data Sheet –30 –30 –35 0dBFS, SECOND HARMONIC –35 0dBFS, THIRD HARMONIC –6dBFS, SECOND HARMONIC –6dBFS, THIRD HARMONIC –40 –40 –12dBFS, SECOND HARMONIC –12dBFS, THIRD HARMONIC –18dBFS, SECOND HARMONIC –18dBFS, THIRD HARMONIC –45 –45 –50 –50 –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 0 50 100 150 200 250 300 0 50 100 150 200 250 300 f (MHz) f (MHz) OUT OUT Figure 12. Second Harmonic vs. fOUT over Digital Scale, Figure 15. Third Harmonic vs. fOUT over Digital Scale, Full-Scale Current = 20 mA, 4× Interpolation, fDATA = 150 MSPS Full-Scale Current = 20 mA, 4× Interpolation, fDATA = 150 MSPS –30 0 10mA, SECOND HARMONIC –35 –10 10mA, THIRD HARMONIC –40 20mA, SECOND HARMONIC 20mA, THIRD HARMONIC –20 –45 30mA, SECOND HARMONIC –50 30mA, THIRD HARMONIC –30 –55 –40 –60 –50 –65 –70 –60 –75 –70 –80 –80 –85 –90 –90 0 50 100 150 200 250 300 0 100 200 300 400 500 600 f (MHz) FREQUENCY (MHz) OUT Figure 16. 2× Interpolation, f = 310 MSPS, f = 131 MHz Figure 13. Second Harmonic vs. fOUT over Full-Scale Current, DATA OUT Digital Scale = 0 dBFS, 4× Interpolation, fDATA = 150 MSPS 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 0 100 200 300 400 500 600 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. 4× Interpolation, f = 150 MSPS, f = 131 MHz Figure 17. 8× Interpolation, fDATA = 125 MSPS, fOUT = 131 MHz DATA OUT Rev. B | Page 16 of 72 POWER LEVEL (dBm) HARMONIC LEVEL (dBc) HARMONIC LEVEL (dBc) 08910-013 08910-012 08910-014 POWER LEVEL (dBm) POWER LEVEL (dBm) HARMONIC LEVEL (dBc) 08910-015 08910-017 08910-016 Data Sheet AD9148 –30 –30 –35 –35 –40 –40 –45 –45 –50 f = 200MSPS –50 DATA f = 150MSPS DATA f = 310MSPS –55 DATA –55 f = 250MSPS DATA –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 –95 –95 –100 –100 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 400 450 500 f (MHz) OUT f (MHz) OUT Figure 18. IMD vs. f over f , 2× Interpolation, OUT DATA Figure 21. IMD vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, Full-Scale Current = 20 mA Digital Scale = 0 dBFS, Full-Scale Current = 20 mA –30 –30 –35 –35 –40 –40 –45 10mA –45 20mA –50 –50 30mA –55 –55 –60 –60 –65 –65 f = 125MSPS DATA –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 –95 –95 –100 –100 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 f (MHz) OUT f (MHz) OUT Figure 19. IMD vs. f , 8× Interpolation, f = 125 MSPS, OUT DATA Figure 22. IMD vs. f over Full-Scale Current, OUT Digital Scale = 0 dBFS, Full-Scale Current = 20 mA 4× Interpolation, f = 150 MSPS, Digital Scale = 0 dBFS DATA –30 –30 –35 –35 –40 0dBFS –40 –6dBFS –45 –45 PLL OFF –12dBFS –50 PLL ON –18dBFS –50 –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 –95 –95 –100 –100 0 50 100 150 200 250 300 0 50 100 150 200 250 300 f (MHz) OUT f (MHz) OUT Figure 20. IMD vs. fOUT over Digital Scale, 4× Interpolation, Figure 23. IMD vs. f , PLL On and Off, OUT fDATA = 150 MSPS, Full-Scale Current = 20 mA Digital Scale = 0 dBFS, Full-Scale Current = 20 mA Rev. B | Page 17 of 72 IMD (dBc) IMD (dBc) IMD (dBc) 08910-020 08910-018 08910-019 IMD (dBc) IMD (dBc) IMD (dBc) 08910-023 08910-022 08910-021 AD9148 Data Sheet –144 –144 –146 1×, 200MSPS –146 1×, 200MSPS 2×, 200MSPS 2×, 200MSPS –148 4×, 200MSPS –148 4×, 200MSPS 8×, 100MSPS 8×, 100MSPS –150 –150 –152 –152 –154 –154 –156 –156 –158 –158 –160 –160 –162 –162 –164 –164 –166 –166 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 f (MHz) f (MHz) OUT OUT Figure 24. Single-Tone NSD Performance vs. f , Digital Scale = 0 dBFS, Figure 27. Eight-Tone NSD Performance vs. f , Digital Scale = 0 dBFS, OUT OUT 4× f = 200 MSPS, Full-Scale Current = 20 mA Full-Scale Current = 20 mA DATA –144 –144 –146 –146 2×, 200MSPS 2×, 200MSPS –148 –148 4×, 200MSPS 4×, 200MSPS 8×, 100MSPS 8×, 100MSPS –150 –150 –152 –152 –154 –154 –156 –156 –158 –158 –160 –160 –162 –162 –164 –164 –166 –166 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 f (MHz) f (MHz) OUT OUT Figure 25. Single-Tone NSD Performance vs. fOUT, Digital Scale = 0 dBFS, Figure 28. Single-Tone NSD Performance vs. fOUT, Digital Scale = 0 dBFS, 4× fDATA = 200 MSPS, Full-Scale Current = 20 mA, PLL On Full-Scale Current = 20 mA, PLL On –144 –144 0dB –146 0dB –146 –6dB –6dB –12dB –148 –12dB –148 –18dB –18dB –150 –150 –152 –152 –154 –154 –156 –156 –158 –158 –160 –160 –162 –162 –164 –164 –166 –166 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 f (MHz) f (MHz) OUT OUT Figure 26. Single-Tone NSD Performance vs. fOUT over Digital Scale, Figure 29. Eight-Tone NSD Performance vs. fOUT over Digital Scale, 4× fDATA = 200 MSPS, Full-Scale Current = 20 mA 4× fDATA = 200 MSPS, Full-Scale Current = 20 mA Rev. B | Page 18 of 72 NSD (dBm/Hz) NSD (dBm/Hz) NSD (dBm/Hz) 08910-026 08910-025 08910-024 NSD (dBm/Hz) NSD (dBm/Hz) NSD (dBm/Hz) 08910-029 08910-028 08910-027 Data Sheet AD9148 –50 –55 0dB, PLL ON 0dB, PLL OFF –60 –3dB, PLL OFF –6dB, PLL OFF –65 –70 –75 –80 –85 CENTER 150.00MHz SPAN 34.68MHz #RES BW 30kHz VBW 300kHz SWEEP 112.5ms (601 PTS) –90 FREQ LOWER UPPER RMS RESULTS OFFSET REF BW dBc dBm dBc dBm –95 CARRIER POWER 5.000MHz 3.840MHz –78.88 –92.35 –77.98 –91.45 0 50 100 150 200 250 300 350 –13.47dBm/ 10.00MHz 3.840MHz –82.12 –95.59 –82.65 –96.12 f (MHz) 3.84000MHz 15.00MHz 3.840MHz –82.18 –95.65 –82.28 –95.75 OUT Figure 30. One-Carrier W-CDMA ACLR vs. f , Adjacent Channel, OUT Figure 33. One-Carrier W-CDMA ACLR, fOUT = 150 MHz, 4× Interpolation, f = 184.32 MHz DATA 4× Interpolation, fDATA = 184.32 MHz, PLL Off –50 –55 0dB, PLL ON 0dB, PLL OFF –60 –3dB, PLL OFF –6dB, PLL OFF –65 –70 –75 –80 –85 CENTER 150.00MHz SPAN 34.68MHz #RES BW 30kHz VBW 300kHz SWEEP 112.5ms (601 PTS) –90 FREQ LOWER UPPER RMS RESULTS OFFSET REF BW dBc dBm dBc dBm –95 CARRIER POWER 5.000MHz 3.840MHz –74.50 –87.27 –73.79 –86.56 0 50 100 150 200 250 300 350 –12.77dBm/ 10.00MHz 3.840MHz –82.72 –95.49 –82.99 –95.76 f (MHz) 3.84000MHz 15.00MHz 3.840MHz –82.97 –95.74 –83.54 –96.31 OUT Figure 31. One-Carrier W-CDMA ACLR vs. f , Alternate Channel, Figure 34. One-Carrier W-CDMA ACLR, f = 150 MHz, OUT OUT 4× Interpolation, f = 184.32 MHz 4× Interpolation, f = 184.32 MHz, PLL On DATA DATA –50 –55 0dB, PLL ON 0dB, PLL OFF –60 –3dB, PLL OFF –6dB, PLL OFF –65 –70 –75 –80 –85 –90 –95 START 1.0MHz STOP 368.6MHz 0 50 100 150 200 250 300 350 #RES BW 30kHz VBW 30kHz SWEEP 1.685s (601 PTS) f (MHz) OUT Figure 32. One-Carrier W-CDMA ACLR vs. f , Second Alternate Channel, OUT Figure 35. One-Carrier W-CDMA, fOUT = 150 MHz, fDAC = 737.28 MSPS, 4× Interpolation, f = 184.32 MHz DATA 4× Interpolation, −3 dBFS Rev. B | Page 19 of 72 ACLR (dBc) ACLR (dBc) ACLR (dBc) 08910-032 08910-031 08910-030 08910-035 08910-034 08910-033 AD9148 Data Sheet CENTER 150.00MHz SPAN 59.58MHz #RES BW 30kHz VBW 300kHz SWEEP 193.2ms (601 PTS) TOTAL CARRIER POWER –13.30dBm/15.3600MHz REF CARRIER POWER –19.14dBm/3.84000MHz RCC FILTER: ON FILTER ALPHA 0.22 FREQ LOWER UPPER OFFSET INTEG BW dBc dBm dBc dBm 1 –19.14dBm 5.000MHz 3.840MHz –72.59 –91.81 –72.99 –92.22 10.00MHz 3.840MHz –73.58 –92.81 –74.45 –93.67 2 –19.29dBm 15.00MHz 3.840MHz –75.18 –94.40 –75.28 –94.51 START 1.0MHz STOP 368.6MHz 3 –19.24dBm 4 –19.61dBm #RES BW 30kHz VBW 30kHz SWEEP 1.685s (601 PTS) Figure 38. Four-Carrier W-CDMA, f = 150 MHz, f = 737.28 MSPS, Figure 36. Four-Carrier W-CDMA, fOUT = 150 MHz, fDAC = 737.28 MSPS, OUT DAC 4× Interpolation, −3 dBFS 4× Interpolation, −3 dBFS, PLL Off –80 –82 –84 –86 –88 –90 –92 –94 –96 CENTER 150.00MHz SPAN 59.58MHz –98 #RES BW 30kHz VBW 300kHz SWEEP 193.2ms (601 PTS) –100 TOTAL CARRIER POWER –13.28dBm/15.3600MHz –102 REF CARRIER POWER –19.07dBm/3.84000MHz –104 RCC FILTER: ON FILTER ALPHA 0.22 –106 FREQ LOWER UPPER OFFSET dBc dBm dBc dBm INTEG BW –108 1 –19.07dBm 5.000MHz 3.840MHz –64.50 –83.67 –64.39 –83.56 –110 10.00MHz 3.840MHz –65.12 –84.29 –65.20 –84.37 2 –19.42dBm 0 50 100 150 200 250 300 15.00MHz 3.840MHz –65.40 –84.57 –65.35 –84.52 3 –19.28dBm f (MHz) 4 –19.45dBm OUT Figure 39. Crosstalk (DAC Set 1 to DAC Set 2), 4× Interpolation, Figure 37. Four-Carrier W-CDMA, fOUT = 150 MHz, fDAC = 737.28 MSPS, f = 150 MSPS, Digital Scale = 0 dBFS, Full-Scale Current = 20 mA 4× Interpolation, −3 dBFS, PLL On DATA Rev. B | Page 20 of 72 08910-037 08910-036 CROSSTALK (dB) 08910-038 08910-039 Data Sheet AD9148 TERMINOLOGY Integral Nonlinearity (INL) In-Band Spurious Free Dynamic Range (SFDR) INL is defined as the maximum deviation of the actual analog The difference, in decibels, between the peak amplitude of the output from the ideal output, determined by a straight line output signal and the peak spurious signal between dc and the drawn from zero scale to full scale. frequency equal to half the input data rate. Differential Nonlinearity (DNL) Out-of-Band Spurious Free Dynamic Range (SFDR) DNL is the measure of the variation in analog value, normalized The difference, in decibels, between the peak amplitude of the to full scale, associated with a 1 LSB change in digital input code. output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the Monotonicity Nyquist frequency of the DAC output sample rate. Normally, A DAC is monotonic if the output either increases or remains energy in this band is rejected by the interpolation filters. This constant as the digital input increases. specification, therefore, defines how well the interpolation Offset Error filters work and the effect of other parasitic coupling paths on The deviation of the output current from the ideal of zero is called the DAC output. offset error. For IOUTx_P, 0 mA output is expected when the Total Harmonic Distortion (THD) inputs are all 0s. For IOUTx_N, 0 mA output is expected when THD is the ratio of the rms sum of the first six harmonic com- all inputs are set to 1. ponents to the rms value of the measured fundamental. It is Gain Error expressed as a percentage or in decibels. The difference between the actual and ideal output span. The Signal-to-Noise Ratio (SNR) actual span is determined by the difference between the output SNR is the ratio of the rms value of the measured output signal when all inputs are set to 1 and the output when all inputs are to the rms sum of all other spectral components below the set to 0. Nyquist frequency, excluding the first six harmonics and dc. Output Compliance Range The value for SNR is expressed in decibels. The range of allowable voltage at the output of a current-output Interpolation Filter DAC. Operation beyond the maximum compliance limits can An interpolation filter up-samples the input digital data by a cause either output stage saturation or breakdown, resulting in multiple of fDATA (interpolation rate) and then filters out the nonlinear performance. undesired spectral images created by the up-sampling process. Temperature Drift Adjacent Channel Leakage Ratio (ACLR) Temperature drift is specified as the maximum change from the The ratio in dBc between the measured power within a channel ambient (25°C) value to the value at either T or T . For MIN MAX relative to its adjacent channel. offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degrees Celsius. For reference drift, the drift is Complex Image Rejection reported in ppm per degrees Celsius. In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of Power Supply Rejection (PSR) wasting transmitter power and system bandwidth. By placing The maximum change in the full-scale output as the supplies the real part of a second complex modulator in series with the are varied from minimum to maximum specified voltages. first complex modulator, either the upper or lower frequency Settling Time image near the second IF can be rejected. The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Rev. B | Page 21 of 72 AD9148 Data Sheet SERIAL PERIPHERAL INTERFACE DATA FORMAT G1 SDO The instruction byte contains the information shown in Table 11. SDIO H1 SPI PORT SCLK G2 Table 11. SPI Instruction Byte CS H2 I7 (MSB) I6 I5 I4 I3 I2 I1 I0 (LSB) R/W A6 A5 A4 A3 A2 A1 A0 Figure 40. SPI Port W R/ , Bit 7 of the instruction byte, determines whether a read or The serial port is a flexible, synchronous serial communications a write data transfer occurs after the instruction byte write. port allowing easy interface to many industry-standard micro- Logic high indicates a read operation, and Logic 0 indicates a controllers and microprocessors. The serial I/O is compatible write operation. with most synchronous transfer formats, including both the A6 through A0, Bit 6 through Bit 0 of the instruction byte, Motorola SPI and Intel® SSR protocols. The interface allows determine the register that is accessed during the data transfer read/write access to all registers that configure the AD9148. portion of the communication cycle. For multibyte transfers, this Single- or multiple-byte transfers are supported, as well as MSB- address is the starting byte address. The remaining register first or LSB-first transfer formats. The serial interface ports can addresses are generated by the device based on the LSB-first bit be configured as a single pin I/O (SDIO) or two unidirectional (Register 0x00, Bit 6). pins for input/output (SDIO/SDO). SPI PIN DESCRIPTIONS GENERAL OPERATION OF THE SERIAL INTERFACE Serial Clock (SCLK) There are two phases to a communication cycle with the AD9148. Phase 1 is the instruction cycle (the writing of an instruction The serial clock pin synchronizes data to and from the device byte into the device), coincident with the first eight SCLK rising and runs the internal state machines. The maximum frequency edges. The instruction byte provides the serial port controller of SCLK is 40 MHz. All data input is registered on the rising with information regarding the data transfer cycle, Phase 2 of edge of SCLK. All data is driven out on the falling edge of SCLK. the communication cycle. The Phase 1 instruction byte defines Chip Select (CS) whether the upcoming data transfer is a read or a write, and the Active low input starts and gates a communication cycle. It starting register address for the first byte of the data transfer. allows more than one device to be used on the same serial The first eight SCLK rising edges of each communication cycle communications lines. The SDO and SDIO pins go to a high are used to write the instruction byte into the device. impedance state when this input is high. Chip select should stay A logic high on the CS pin followed by a logic low resets the SPI low during the entire communication cycle. port timing to the initial state of the instruction cycle. From this Serial Data I/O (SDIO) state, the next eight rising SCLK edges represent the instruction Data is always written into the device on this pin. However, this bits of the current I/O operation, regardless of the state of the pin can be used as a bidirectional data line. The configuration internal registers or the other signal levels at the inputs to the of this pin is controlled by Register 0x00, Bit 7. The default is SPI port. If the SPI port is in an instruction cycle or a data Logic 0, configuring the SDIO pin as unidirectional. transfer cycle, none of the present data is written. Serial Data Output (SDO) The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and Data is read from this pin for protocols that use separate lines the system controller. Phase 2 of the communication cycle is a for transmitting and receiving data. In the case where the device transfer of one or more data bytes. Registers change immediately operates in a single bidirectional I/O mode, this pin does not upon writing to the last bit of each transfer byte. output data and is set to a high impedance state. Rev. B | Page 22 of 72 08910-040 Data Sheet AD9148 INSTRUCTION CYCLE DATA TRANSFER CYCLE SPI OPTIONS CS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the LSB first bit SCLK (Register 0x00, Bit 6). The default is MSB first (LSB first = 0). A0 A1 A2 A3 A4 A5 A6 R/W D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N When LSB first = 0 (MSB first), the instruction and data bit must SDIO be written from MSB to LSB. Multibyte data transfers in MSB- D0 D1 D2 D4 D5 D6 D7 SDO 0 0 0 N N N N first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes Figure 42. Serial Register Interface Timing LSB First should follow from the high address to the low address. In MSB- t DS t SCLK first mode, the serial port internal byte address generator decrements CS for each data byte of the multibyte communication cycle. t t PWH PWL When LSB first = 1 (LSB first), the instruction and data bit must SCLK be written from LSB to MSB. Multibyte data transfers in LSB- t DCSB first format start with an instruction byte that includes the register t DH address of the least significant data byte followed by multiple data SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 bytes. The serial port internal byte address generator increments Figure 43. Timing Diagram for SPI Register Write for each byte of the multibyte communication cycle. CS The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the SCLK MSB-first mode is active. The serial port controller address t DV increments from the data address written toward 0x1F for SDIO DATA BIT n DATA BIT n – 1 SDO multibyte I/O operations if the LSB-first mode is active. Figure 44. Timing Diagram for SPI Register Read INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 SDIO D7 D6 D5 D3 D2 D1 D0 SDO N N 0 0 0 0 Figure 41. Serial Register Interface Timing MSB First Rev. B | Page 23 of 72 08910-041 08910-044 08910-043 08910-042 AD9148 Data Sheet SPI REGISTER MAP Table 12. Register Map Register Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x00 Comm SDIO LSB/ Software DAC SPI 0x00 direction MSB first reset select 0x01 Power Power- Power- Power- 0x00 control Down DAC Down down data Set 1 DAC Set 2 receiver 0x03 Data format Binary Q first Dual-port Bus swap Byte mode Byte 0x20 format enable mode swap 0x04 Interrupt Enable PLL Enable Enable Enable Enable Enable Enable 0x00 Enable 0 lock lost PLL lock sync sync lock FIFO SPI FIFO FIFO lock lost aligned Warning 1 Warning 2 0x05 Interrupt Enable AED Enable AED Enable 0x00 Enable 1 compare pass compare SED fail compare fail 0x06 Event Flag 0 PLL lock PLL lock Sync lock Sync lock FIFO SPI FIFO FIFO lost lost aligned Warning 1 Warning 2 0x07 Event Flag 1 AED compare AED SED pass compare compare fail fail 0x08 Clock CLK duty REFCLK CLK cross REFCLK cross 0 1 1 1 0x37 receiver correction duty correction correction control correction 0x0A PLL Control 0 PLL enable PLL Manual VCO Band[5:0] 0x40 manual enable 0x0C PLL Control 1 PLL Loop Bandwidth[2:0] 0 1 0 0 1 0xF1 0x0D PLL Control 2 N2[1:0] PLL cross N0[1:0] N1[1:0] 0xD9 control enable 0x0E PLL Status 0 PLL Control Voltage[3:0] 0x0F PLL Status 1 VCO Band Readback[5:0] 0x10 Sync Control 0 Sync FIFO rate/ Rising Sync Averaging[2:0] 0x08 enable data rate edge sync toggle 0x11 Sync Control 1 Sync Phase Request[5:0] 0x00 0x12 Sync Status 0 Sync lost Sync locked 0x14 Data receiver One DCI 0x00 control 0x15 Data receiver LVDS rcvr LVDS rcvr LVDS rcvr LVDS rcvr LVDS rcvr LVDS rcvr LVDS rcvr LVDS rcvr status frame high frame low DCI high DCI low Port B high Port B low Port A Port A low high 0x17 FIFO Status/ FIFO FIFO FIFO reset FIFO SPI FIFO SPI FIFO Phase Offset[2:0] 0x00 Control Port A Warning 1 Warning 2 aligned align ack align requesting 0x18 FIFO Status FIFO Level[7:0] Port A 0x19 FIFO Status/ FIFO FIFO FIFO reset FIFO SPI FIFO SPI FIFO Phase Offset[2:0] 0x00 Control Port B Warning 1 Warning 2 aligned align ack align requesting 0x1A FIFO Status FIFO Level[7:0] Port B 0x1C HB1 control Enable Bypass HB1[1:0] Bypass 0x40 −1 pre mod sinc HB1 0x1D HB2 control HB2[2:0] Bypass 0x00 HB2 0x1E HB3 control Bypass HB3[2:0] Bypass 0x81 digital gain HB3 and phase adjustment Rev. B | Page 24 of 72 Data Sheet AD9148 Register Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x1F Chip ID Chip ID[7:0] 0x07 1 0x20 Coeff I Byte 0 0 Coeff_1i[3:0] Coeff_0i[2:0] 0x00 1 Coeff I Byte 1 Coeff_3i[2:0] Coeff_2i[4:0] 0xC0 0x21 1 0x22 Coeff I Byte 2 Coeff_4i[2:0] 0 Coeff_3i[6:3] 0xEF 1 Coeff I Byte 3 0 Coeff_4i[9:3] 0x7F 0x23 1 Coeff Q Byte 0 0 Coeff_1q[3:0] Coeff_0q[2:0] 0x69 0x24 1 0x25 Coeff Q Byte 1 Coeff_3q[2:0] Coeff_2q[4:0] 0xE6 1 Coeff Q Byte 2 Coeff_4q[2:0] 0 Coeff_3q[6:3] 0x0D 0x26 1 Coeff Q Byte 3 0 Coeff_4q[9:3] 0x00 0x27 1 0x28 I phase adj LSB Phase Word I[7:0] 0x00 1 I phase adj Phase Word I[9:8] 0x00 0x29 MSB 1 Q phase adj Phase Word Q[7:0] 0x00 0x2A LSB 1 0x2B Q phase adj Phase Word Q[9:8] 0x00 MSB 1 I DC offset LSB DC Offset I[7:0] 0x00 0x2C 1 I DC offset DC Offset I[15:8] 0x00 0x2D MSB 1 Q DC offset DC Offset Q[7:0] 0x00 0x2E LSB 1 Q DC offset DC Offset Q[15:8] 0x00 0x2F MSB 1 0x30 IDAC FSC adj IDAC FSC Adj[7:0] 0xF9 1 IDAC control IDAC sleep IDAC FSC Adj[9:8] 0x01 0x31 1 AUX IDAC data AUX IDAC Data[7:0] 0x00 0x32 1 0x33 AUX IDAC AUX IDAC AUX IDAC AUX IDAC AUX IDAC Data[9:8] 0x00 control sign current power- direction down 1 QDAC FSC adj QDAC FSC Adj[7:0] 0xF9 0x34 1 QDAC control QDAC sleep QDAC FSC Adj[9:8] 0x01 0x35 1 0x36 AUX QDAC AUX QDAC Data[7:0] 0x00 data 1 AUX QDAC AUX QDAC AUX QDAC AUX QDAC AUX QDAC Data[9:8] 0x00 0x37 control sign current power- direction down 1 SED_S0_L SED Compare Pattern Sample0[7:0] 0xB6 0x38 1 0x39 SED_S0_H SED Compare Pattern Sample0[15:8] 0x7A 1 SED_S1_L SED Compare Pattern Sample1[7:0] 0x45 0x3A 1 SED_S1_H SED Compare Pattern Sample1[15:8] 0xEA 0x3B 1 0x3C SED3_S2_L SED Compare Pattern Sample2[7:0] 0x16 1 SED3_S2_H SED Compare Pattern Sample2[15:8] 0x1A 0x3D 1 SED4_S3_L SED Compare Pattern Sample3[7:0] 0xC6 0x3E 1 0x3F SED4_S3_H SED Compare Pattern Sample3[15:8] 0xAA 0x40 SED control/ SED Port B Port A Auto- Port B Port A Compare 0x00 status compare error error clear compare compare passed enable detected detected enable failed failed 1 SED_R_L SED Status Rising Edge Samples[7:0] 0x41 1 0x42 SED_R_H SED Status Rising Edge Samples[15:8] 1 SED_F_L SED Status Falling Edge Samples[7:0] 0x43 1 SED_F_H SED Status Falling Edge Samples[15:8] 0x44 1 0x50 I gain control I Gain[7:0] 0x40 1 Q gain control Q Gain[7:0] 0x40 0x51 Rev. B | Page 25 of 72 AD9148 Data Sheet Register Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x54 FTW (LSB) FTW[7:0] 0x00 0x55 FTW FTW [15:8] 0x00 0x56 FTW FTW[23:16] 0x00 0x57 FTW (MSB) FTW[31:24] 0x00 0x58 Phase offset NCO Phase Offset[15:8] 0x00 (MSB) 0x59 Phase offset NCO Phase Offset[7:0] 0x00 (LSB) 0x5A DDS/mod Bypass Frame NCO Frame NCO FTW FTW Sideband 0x80 control DDS/MOD reset ack reset request update ack update select request 0x5C Die Temp Latch Temp sensor 0x01 Control 0 temp power-down data 0x5D Die Temp 0 0 0 0 1 0 1 0 0x20 Control 1 0x5E Die temp LSB Die Temp[7:0] 0x5F Die temp MSB Die Temp[15:8] 0x72 DCI delay DCI Delay[1:0] 0x00 1 Register 0x20 to Register 0x3F and Register 0x41 to Register 0x51 configure DAC 1 (I) and DAC 2 (Q) data paths with DAC SPI select = 0 (Register 0x00[4]). Register 0x20 to Register 0x3F and Register 0x41 to Register 0x51 configure DAC 3 (I) and DAC 4 (Q) data paths with DAC SPI select = 1 (Register 0x00[4]). SPI REGISTER DESCRIPTIONS Table 13. Register Descriptions Addr Register Name (Hex) Bit Name Function Default Comm 00 7 SDIO SDIO operation. 0 0 = SDIO operates as an input only. 1 = SDIO operates as bidirectional input/output. 6 LSB/MSB first SPI communication LSB first (default is MSB first). 0 0 = MSB first. 1 = LSB first. 5 Software Reset Software reset. 0 Reset is asserted when this bit transitions from 0 to 1. 4 DAC SPI select Selects which DAC data path Register 0x20 to Register 0x3F 0 and Register 0x41 to Register 0x51 configure. 0 = DAC 1 (I path) and DAC 2 (Q path) are configured. 0 1 = DAC 3 (I path) and DAC 4 (Q path) are configured. Power Control 01 7 Power-Down Power down DAC 1 and power down DAC 2. 0 DAC Set 1 6 Power-Down Power down DAC 3 and power down DAC 4. 0 DAC Set 2 5 Power-down Power down the input data receiver. 0 data receiver Rev. B | Page 26 of 72 Data Sheet AD9148 Addr Register Name (Hex) Bit Name Function Default Data Format 03 7 Binary format Input data is in twos complement format (0) or unsigned 0 binary format (1). 6 Q first enable Indicates I/Q data pairing on data input; I first (0), Q first (1). 0 5 Dual-port mode Number of input data ports used. 1 Single port (0), dual port (1). 4 Bus swap 0 = normal data input bus pin out (MSB to LSB). 0 1 = inverted data input bus pin out (LSB to MSB). 3 Byte mode 0 = data input bus is 16-bit wide on each port. 0 1 = data input bus is two 8-bit wide buses on Port A. 2 Byte swap 0 = normal data input bus pin out (MSB to LSB). 0 1 = inverted data input bus pin out (LSB to MSB). Interrupt Enable 0 04 7 Enable PLL lock lost Enables interrupt for PLL lock lost. 0 6 Enable PLL lock Enables interrupt for PLL lock. 0 5 Enable sync Enables interrupt for sync lock lost. 0 lock lost 4 Enable sync lock Enables interrupt for sync lock. 0 2 Enable FIFO Enables interrupt for FIFO SPI aligned. 0 SPI aligned 1 Enable FIFO Enables interrupt for FIFO Warning 1. 0 Warning 1 0 Enable FIFO Enables interrupt for FIFO Warning 2. 0 Warning 2 Interrupt Enable 1 05 4 Enable AED Enables interrupt for AED compare pass. 0 compare pass 3 Enables interrupt for AED compare fail. 0 Enable AED compare fail 2 Enable SED Enables interrupt for SED compare fail. 0 compare fail Rev. B | Page 27 of 72 AD9148 Data Sheet Addr Register Name (Hex) Bit Name Function Default Event Flag 0 (All bits 06 7 PLL lock lost 1 = indicates that the PLL that was previously locked has 0 are high when interrupt unlocked from the reference signal. is active. Clear interrupt 6 PLL lock 1 = indicates that the PLL has locked to the reference clock 0 by writing respective input. bit high.) 5 Sync lock lost 1 = indicates that the sync logic that was previously locked 0 has lost alignment. 4 Sync lock 1 = indicates that the sync logic achieved sync alignment. This 0 is indicated when no phase changes are requested for at least a few full averaging cycles. 2 FIFO SPI aligned 1 = indicates that a FIFO reset originating from a serial port- 0 based request has successfully completed. 1 FIFO Warning 1 1 = indicates that the difference between the FIFO read and 0 write pointers is 1. 0 FIFO Warning 2 1 = indicates that the difference between the FIFO read and 0 write pointers is 2. Event Flag 1(All bits are 07 4 AED compare pass 1 = indicates that the SED logic detected a valid input data 0 high when interrupt is pattern comparison against the preprogrammed expected active. Clear interrupt values. by writing respective 3 AED compare fail 1 = indicates that the SED logic detected an invalid input data 0 bit high). pattern comparison against the preprogrammed expected values. This automatically clears when eight valid I/Q data pairs are received. 2 SED compare fail 1 = indicates that the SED logic detected an invalid input data 0 pattern comparison against the preprogrammed expected values. Clock Receiver Control 08 7 CLK duty Enables duty-cycle correction on CLK input. 0 correction 6 REFCLK duty Enables duty-cycle correction on REFCLK input. 0 correction 5 CLK cross Enables differential crossing correction on CLK input. 1 correction 4 REFCLK cross Enables differential crossing correction on REFCLK input. 1 correction 3:0 0111 Always set these bits to 0111 0111 PLL Control 0 0A 7 PLL enable Enables PLL clock multiplier. 0 6 PLL manual Enables PLL band selection mode (0 = auto, and 1 = manual). 1 enable 5:0 Manual VCO band VCO band used in manual mode. 0 PLL Control 1 0C 7:5 PLL loop bandwidth Selects PLL loop filter bandwidth. 110 000 = narrowest bandwidth. … 111 = widest bandwidth. 4:0 01001 Set these bits to 01001 for optimal PLL operation. 10001 Rev. B | Page 28 of 72 Data Sheet AD9148 Addr Register Name (Hex) Bit Name Function Default PLL Control 2 0D 7:6 N2 REFCLK-to-PLL controller clock rate (f ). 11 PC_CLK 00 = 2. 01 = 4. 10 = 8. 11 = 16. fPC_CLK must always be less than 50 MHz. 4 PLL cross Enables PLL cross-point control. control enable 3:2 N0 VCO-to-DACCLK divider. 001 00 = 1. 01 = 2. 10 = 4. 11 = 4. 1:0 N1 DACCLK-to-REFCLK divider. 01 00 = 2. 01 = 4. 10 = 8. 11 = 16. PLL Status 0 0E 3:0 PLL control voltage PLL VCO control voltage readback value. Read- only PLL Status 1 0F 5:0 VCO band readback VCO band value. Read- only Sync Control 0 10 7 Sync enable Enables synchronization logic. 0 6 FIFO rate/data Operates synchronization at the FIFO reset rate (0)/data rate (1). 0 rate toggle 3 Rising edge sync Rising edge of CLK samples sync input (1), falling edge of 1 CLK samples sync input (0). 2:0 Sync averaging Average sync input of number of samples. 000 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128. Rev. B | Page 29 of 72 AD9148 Data Sheet Addr Register Name (Hex) Bit Name Function Default Sync Control 1 11 5:0 Sync phase request Offset of internal divided by 64 clock phase after sync. 000000 000000 = 0 DAC clocks. … 111111 = 63 DAC clocks. Sync Status 0 12 7 Sync Lost Synchronization lost. Read- only 6 Sync locked Synchronization found. Read- only Data Receiver Control 14 6 One DCI 0 = two DCIs used, DCIA_x and DCIB_x. 0 1 = one DCI used, DCIA_x. Data Receiver Status 15 7 Frame input LVDS level > 1.7 V. LVDS receiver Read- frame high only 6 LVDS receiver Frame input LVDS level < 0.7 V. Read- frame low only 5 LVDS receiver DCI input LVDS level > 1.7 V. Read- DCI high only 4 LVDS receiver DCI input LVDS level < 0.7 V. Read- DCI low only 3 LVDS receiver Port B input LVDS level > 1.7 V. Read- Port B high only 2 LVDS receiver Port B input LVDS level < 0.7 V. Read- Port B low only 1 LVDS receiver Port A input LVDS level > 1.7 V. Read- Port A high only 0 LVDS receiver Port A input LVDS level < 0.7 V. Read- Port A low only FIFO Status/ 17 7 FIFO Warning 1 FIFO read and write pointers within ±1. Read- Control Port A only 6 FIFO Warning 2 FIFO read and write pointers within ±2 Read- only 5 FIFO reset aligned FIFO read and write pointers aligned after chip reset. Read- only 4 FIFO SPI align FIFO read and write pointers aligned after SPI driven Read- acknowledge FIFO reset. only 3 FIFO SPI align Request FIFO read and write pointers alignment via SPI. 0 requesting 2:0 FIFO phase offset FIFO read and write pointer phase offset from optimal 000 phase following FIFO reset. 000 = 0 offset from optimal phase. … 111 = 7 offset from optimal phase. The optimal value is 0. Rev. B | Page 30 of 72 Data Sheet AD9148 Addr Register Name (Hex) Bit Name Function Default FIFO Status Port A 18 7:0 FIFO Level Thermometer encoded measure of the FIFO level. Read- only FIFO Status/ 19 7 FIFO Warning 1 FIFO read and write pointers within ±1. Read- Control Port B only 6 FIFO Warning 2 FIFO read and write pointers within ±2. Read- only 5 FIFO reset aligned FIFO read and write pointers aligned after chip reset. Read- only 4 FIFO SPI align FIFO read and write pointers aligned after SPI driven FIFO Read- acknowledge reset. only 3 FIFO SPI align Request FIFO read and write pointers alignment via SPI. 0 requesting 2:0 FIFO phase offset FIFO read and write pointer phase offset from optimal 000 phase following FIFO reset. 000 = 0 offset from optimal phase. … 111 = 7 offset from optimal phase. The optimal value is 0. FIFO Status Port B 1A 7:0 FIFO level Thermometer encoded measure of the FIFO level. Read- only HB1 Control 1C 7 Enable pre mod Enable fS/2 modulation stage that precedes Stage 1 0 interpolation filter. 6 Bypass sinc-1 Sinc-1 filter bypass. 1 2:1 HB1[1:0] Modulation mode for first stage interpolation filter 00 (fHB1 = 2 × fIN1). 00 = input signal modulated by dc. Filter pass band is from −0.2 to +0.2 of fHB1. 01 = input signal modulated by dc. Filter pass band is from 0.05 to 0.45 of fHB1. 10 = input signal modulated by f /2. Filter pass band is HB1 from 0.3 to 0.7 of fHB1. 11 = input signal modulated by f /2. Filter pass band is HB1 from 0.55 to 0.95 of f . HB1 0 Bypass HB1 First stage interpolation filter bypass. 0 Rev. B | Page 31 of 72 AD9148 Data Sheet Addr Register Name (Hex) Bit Name Function Default HB2 Control 1D HB2[2:0] Modulation mode for second stage interpolation filter 000 (f = 2 × f ). HB2 IN2 000 = input signal modulated by dc. Filter pass band is from −0.1 to +0.1 of f . HB2 001 = input signal modulated by dc. Filter pass band is from 0.025 to 0.225 of f . HB2 010 = input signal modulated by fHB2/4. Filter pass band is from 0.15 to 0.35 of fHB2. 011 = input signal modulated by fHB2/4. Filter pass band is from 0.275 to 0.475 of fHB2. 100 = input signal modulated by fHB2/2. Filter pass band is from 0.4 to 0.6 of fHB2. 101 = input signal modulated by f /2. Filter pass band is HB2 from 0.525 to 0.725 of fHB2. 110 = input signal modulated by 3 f /4. Filter pass band is HB2 from 0.65 to 0.85 of fHB2. 111 = input signal modulated by 3 f /4. Filter pass band is HB2 from 0.775 to 0.975 of f . HB2 0 Bypass HB2 Second stage interpolation filter bypass. 0 HB3 Control 1E 7 Bypass digital gain 1 = bypass digital gain and phase compensation. 1 and phase adjustment 3:1 HB3[2:0] Modulation mode for third stage interpolation filter 000 (f = 2 × f ). HB3 IN3 000 = input signal modulated by dc. Filter pass band is from −0.1 to +0.1 of f . HB3 001 = input signal modulated by dc. Filter pass band is from 0.025 to 0.225 of f . HB3 010 = input signal modulated by fHB3/4. Filter pass band is from 0.15 to 0.35 of fHB3. 011 = input signal modulated by fHB3/4. Filter pass band is from 0.275 to 0.475 of fHB3. 100 = input signal modulated by f /2. Filter pass band is HB3 from 0.4 to 0.6 of fHB3. 101: Input signal modulated by f /2. Filter pass band is HB3 from 0.525 to 0.725 of f . HB3 110 = input signal modulated by 3 f /4. Filter pass band is HB3 from 0.65 to 0.85 of f . HB3 111 = input signal modulated by 3 fHB3/4. Filter pass band is from 0.775 to 0.975 of f . HB3 0 Bypass HB3 Third stage interpolation filter bypass. 1 Chip ID 1F 7:0 Chip ID Chip ID readback. 07 Rev. B | Page 32 of 72 Data Sheet AD9148 Addr Register Name (Hex) Bit Name Function Default Coeff I Byte 0 20 7 0 Set this bit to 0. 0 -1 6:3 Coeff_1i[3:0] I-Path DAC Sinc Filter Coefficient 2 in twos complement 0 format. -1 2:0 Coeff_0i I-Path DAC Sinc Filter Coefficient 1 in twos complement 0 format. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. -1 Coeff I Byte 1 21 7:5 Coeff_3i[2:0] I-Path DAC Sinc Filter Coefficient 4 (LSB) in twos 6 complement format. -1 4:0 Coeff_2i I-Path DAC Sinc Filter Coefficient 3 in twos complement 0 format. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. -1 Coeff I Byte 2 22 7:5 Coeff_4i[2:0] I-Path DAC Sinc Filter Coefficient 5 (LSB) in twos 7 complement format. 4 0 Set this bit to 0. 0 -1 3:0 Coeff_3i[6:3] Set I-Path DAC Sinc Filter Coefficient 4 (MSB) in twos F complement format. DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Coeff I Byte 3 23 7 0 Set this bit to 0. 0 -1 6:0 Coeff_4i[9:3] I-Path DAC Sinc Filter Coefficient 5 (MSB) in twos 7F complement format. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Coeff Q Byte 0 24 7 0 Set this bit to 0. 0 -1 6:3 Coeff_1q[3:0] Q-Path DAC Sinc Filter Coefficient 2 in twos complement D format. -1 2:0 Coeff_0q Q-Path DAC Sinc Filter Coefficient 1 in twos complement 1 format. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. -1 Coeff Q Byte 1 25 7:5 Coeff_3q[2:0] Q-Path DAC Sinc Filter Coefficient 4 (LSB) in twos 7 complement format. -1 4:0 Coeff_2q Q-Path DAC Sinc Filter Coefficient 3 in twos complement 6 format. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Rev. B | Page 33 of 72 AD9148 Data Sheet Addr Register Name (Hex) Bit Name Function Default -1 Coeff Q Byte 2 26 7:5 Coeff_4q[2:0] Q-Path DAC Sinc Filter Coefficient 5 (LSB) in twos 0 complement format. 4 0 Set this bit to 0. 0 -1 3:0 Coeff_3q[6:3] Q-Path DAC Sinc Filter Coefficient 4 (MSB) in twos D complement format. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Coeff Q Byte 3 27 7 0 Set this bit to 0. 0 -1 6:0 Coeff_4q[9:3] Q-Path DAC Sinc Filter Coefficient 5 (MSB) in twos 0 complement format. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. I Phase Adj LSB 28 7:0 Phase Word I[7:0] See Register 0x29. 0 I Phase Adj MSB 29 1:0 Phase Word I[9:8] Phase Word I[9:0] is used to insert a phase offset between the 0 I and Q data paths. The adjustment range is ±1.75°. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Q Phase Adj LSB 2A 7:0 Phase Word Q[7:0] See Register 0x2B. 0 Q Phase Adj MSB 2B 1:0 Phase Word Q[9:8] Phase Word Q[9:0] is used to insert a phase offset between 0 the I and Q data paths. The adjustment range is ±1.75°. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. I DC Offset LSB 2C 7:0 DC Offset I[7:0] See Register 0x2D. 0 I DC Offset MSB 2D 7:0 DC Offset I[15:8] DC Offset I[15:0] is a value added directly to the samples 0 . The adjustment written to the IDAC. The LSB bit weight is 2 range is ±10 mA. Set DAC SPI select = 0 to configure DAC 1 path. 0 Set DAC SPI select = 1 to configure DAC 3 path. Q DC Offset LSB 2E 7:0 DC Offset Q[7:0] See Register 0x2F. 0 Q DC Offset MSB 2F 7:0 DC Offset Q[15:8] DC Offset Q[15:0] is a value added directly to the samples 0 written to the QDAC. The LSB bit weight is 2 . The adjustment range is ±10 mA. Set DAC SPI select = 0 to configure DAC 2 path. 0 Set DAC SPI select = 1 to configure DAC 4 path. 0 Rev. B | Page 34 of 72 Data Sheet AD9148 Addr Register Name (Hex) Bit Name Function Default IDAC FSC Adj 30 7:0 IDAC FSC Adj IDAC full-scale current adjustment (LSB part). IDAC FS Adj[9:0] F9 sets the full-scale current of the IDAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 µA. 0x000 = 8.64 mA. ... 0x200 = 20.14 mA. … 0x3FF = 31.66 mA. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. IDAC Control 31 7 IDAC sleep I DAC sleep mode (fast wake-up mode). 0 1:0 IDAC FSC Adj[9:8] IDAC full-scale current adjustment (MSB part) 01 Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Aux IDAC Data 32 7:0 AUX IDAC Data Auxiliary IDAC data (LSB part). AUX IDAC Data[9:0] sets the 00 magnitude of the aux DAC current. The range is 0 mA to 2 mA, and the step size is 2 µA. 0x000 = 0.000 mA. 0x001 = 0x002 mA. … 0x3FF = 2.046 mA. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Aux IDAC Control 33 7 AUX IDAC sign Auxiliary IDAC output sign. 0 0 = positive, current is directed to the AUXx_P pin. 1 = negative, current is directed to the AUXx_N pin. 6 AUX IDAC Auxiliary IDAC current direction. 0 current direction 0 = source. 1 = sink. 5 AUX IDAC Auxiliary IDAC power-down. 0 power-down 1:0 AUX IDAC Data[9:8] Auxiliary IDAC data (MSB part). 00 Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select =1 to configure DAC 3 path. Rev. B | Page 35 of 72 AD9148 Data Sheet Addr Register Name (Hex) Bit Name Function Default QDAC FSC Adj 34 7:0 QDAC FSC Adj Q DAC full-scale current adjustment (LSB part). QDAC FS F9 Adj[9:0] sets the full-scale current of the QDAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 µA. 0x000 = 8.64 mA ... 0x200 = 20.14mA … 0x3FF = 31.66 mA Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. QDAC Control 35 7 QDAC sleep Q DAC sleep mode (fast wake-up mode). 0 1:0 QDAC FSC Adj[9:8] QDAC full-scale current adjustment (MSB part). 01 Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Aux QDAC Data 36 7:0 AUX QDAC Data Auxiliary QDAC data (LSB part). AUX QDAC Data[9:0] sets 00 the magnitude of the AUX DAC current. The range is 0 mA to 2 mA, and the step size is 2 µA. 0x000 = 0.000 mA. 0x001 = 0x002 mA. … 0x3FF = 2.046 mA. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Aux QDAC Control 37 7 AUX QDAC sign Auxiliary QDAC output sign. 0 0 = positive, current is directed to the AUXx_P pin. 1 = negative, current is directed to the AUXx_N pin. 6 AUX QDAC Auxiliary QDAC current direction. 0 current direction 0 = source. 1 = sink. 5 AUX QDAC Auxiliary QDAC power-down. 0 power-down 1:0 AUX QDAC Auxiliary QDAC data (MSB part). 00 Data[9:8] Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Rev. B | Page 36 of 72 Data Sheet AD9148 Addr Register Name (Hex) Bit Name Function Default SED_S0_L 38 7:0 SED Compare Compare Pattern Sample0[15:0] is the word that is compared Pattern Sample0[7:0] with Data Sample 0 captured at the input interface by the rising edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S0_H 39 7:0 SED Compare Compare Pattern Sample0[15:0] is the word that is compared Pattern with Data Sample 0 captured at the input interface by the Sample0[15:8] rising edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S1_L 3A 7:0 SED Compare Compare Pattern Sample1[15:0] is the word that is compared Pattern Sample1[7:0] with Data Sample 1 captured at the input interface by the falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S1_H 3B 7:0 SED Compare Compare Pattern Sample1[15:0] is the word that is compared Pattern with Data Sample 1 captured at the input interface by the Sample1[15:8] falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S2_L 3C 7:0 SED Compare Compare Pattern Sample2[15:0] is the word that is compared Pattern Sample2[7:0] with Data Sample 2 captured at the input interface by the rising edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S2_H 3D 7:0 SED Compare Compare Pattern Sample2[15:0] is the word that is compared Pattern with Data Sample 2 captured at the input interface by the Sample2[15:8] rising edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S3_L 3E 7:0 SED Compare Compare Pattern Sample3[15:0] is the word that is compared Pattern Sample3 with Data Sample 3 captured at the input interface by the [7:0] falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S3_H 3F 7:0 SED Compare Compare Pattern Sample3[15:0] is the word that is compared Pattern with Data Sample 3 captured at the input interface by the Sample3[15:8] falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. Rev. B | Page 37 of 72 AD9148 Data Sheet Addr Register Name (Hex) Bit Name Function Default SED Control/Status 40 7 SED compare enable Enables the SED circuitry. 0 6 Port B error Status of last compare on Port B. 0 detected 5 Port A error Status of last compare on Port A. 0 detected 3 Auto-clear enable Enables the auto reset after eight valid sample sets. 0 2 Port B compare Fail status determined for last sample set on Port B. 0 failed 1 Port A compare Fail status determined for last sample set on Port A. 0 failed 0 Compare passed Pass status determined for last sample set. 0 SED_R_L 41 7:0 SED Status Rising SED Status Rising Edge Samples[15:0] indicate which bits Read- Edge Samples[7:0] were received in error. only Set DAC SPI select = 0 to read back errors on Port A. Set DAC SPI select = 1 to read back errors on Port B. SED_R_H 42 7:0 SED Status Rising SED Status Rising Edge Samples[15:0] indicate which bits Read- Edge Samples[15:8] were received in error. only Set DAC SPI select = 0 to read back errors on Port A. Set DAC SPI select = 1 to read back errors on Port B. SED_F_L 43 7:0 SED Status Falling SED Status Falling Edge Samples[15:0] indicate which bits Read- Edge Samples[7:0] were received in error. only Set DAC SPI select = 0 to read back errors on Port A. Set DAC SPI select = 1 to read back errors on Port B. SED_F_H 44 7:0 SED Status Falling SED Status Falling Edge Samples[15:0] indicate which bits Read- Edge Samples[15:8] were received in error. only Set DAC SPI select = 0 to read back errors on Port A. Set DAC SPI select = 1 to read back errors on Port B. I Gain Control 50 7:0 IGain IGain[7:0] is a value that directly scales the samples written to 40 1 −6 the IDAC. The bit weighting is MSB = 2 and LSB = 2 , which yields a multiplier range of 0 to 3.984375. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Q Gain Control 51 7:0 QGain QGain[7:0] is a value that directly scales the samples written 40 1 −6 to the QDAC. The bit weighting is MSB = 2 and LSB = 2 , which yields a multiplier range of 0 to 3.984375. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Rev. B | Page 38 of 72 Data Sheet AD9148 Addr Register Name (Hex) Bit Name Function Default FTW (LSB) 54 7:0 FTW[7:0] See Register 0x57. 0 FTW 55 7:0 FTW[15:8] See Register 0x57. 0 FTW 56 7:0 FTW [23:16] See Register 0x57. 0 FTW (MSB) 57 7:0 FTW [31:24] FTW[31:0] is the 32-bit frequency tuning word that 0 determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Register 0x5A[2] transitions from 0 to 1. Phase Offset MSB 58 7:0 NCO Phase See Register 0x59. 0 Offset[15:8] Phase Offset LSB 59 7:0 NCO Phase NCO Phase Offset[15:0] sets the phase of the complex carrier 0 Offset[7:0] signal when the NCO is reset. The phase offset spans between 0º and 360º. Each bit represents an offset of 0.0055°. Value is in twos complement format. DDS/Mod Control 5A 7 Bypass DDS/MOD 1 = bypass NCO. 1 5 Frame NCO reset ack 1 = indicates that the NCO has been reset due to an 0 extended FRAMEx_x pulse signal. 4 Frame NCO 0 0→1 = The NCO is reset on the first extended FRAMEx_x reset request pulse after this bit transitions from 0 to 1. 3 FTW update ack 1 = indicates that the FTW has been updated with the 0 SPI value. 2 FTW update request 0 0→1 = FTW is updated with the SPI value on a 0-to-1 transition of this bit. 0 Sideband select 0 = The modulator output high-side image. 0 1 = The modulator output low-side image. The image is spectrally inverted compared to the input data. Die Temp Control 0 5C 1 Latch temp data 0 0 → 1 = latches temp sensor data. This should be completed before the Die Temp[15:0] is readback. 0 Temp sensor 1 = powers down the aux ADC that converts die temperature. 1 power-down Die Temp Control 1 5D 7:0 00001010 Set these bits to 00001010 for optimal temperature sensor 100000 operation. Die Temp (LSBs) 5E 7:0 Die Temp[7:0] Die Temp[15:0] indicates the approximate die temperature. Read- only Die Temp (MSBs) 5F 7:0 Die Temp[15:8] Die Temp[15:0] indicates the approximate die temperature. Read- only DCI Delay 72 1:0 DCI delay Programmable delay added DCI. 00 00 = no added delay. 01 = 200 ps delay. 10 = 400 ps delay. 11 = 600 ps delay. Rev. B | Page 39 of 72 AD9148 Data Sheet INPUT DATA PORTS The AD9148 can operate in three data input modes: dual-port Each data sample, by default, is expected to be formatted as an mode, single-port mode, and byte mode. In dual-port mode, MSB sent to Bit 15 and an LSB sent to Bit 0 for each port. The DAC 1 and DAC 2 receive data from Port A, and DAC 3 and AD9148 contains an option to swap the bus (Register 0x03[4]). DAC 4 receive data from Port B. In single-port mode, all four When this bus swap bit is set, the MSB should be sent to Bit 0, DACs receive data from Port A. In byte mode, all four DACs and the LSB should be sent to Bit 15 for each port. receive data from Port A, but the port is split into two 8-bit wide SINGLE-PORT MODE buses. In all modes, the data input timing is relative to a DCI signal In single-port mode, a FRAME signal must be provided along provided with the data. with the DCI signal and the data. The FRAME signal indicates DUAL-PORT MODE to which DAC the data is intended. When FRAME goes high, In dual-port mode, the DCI signal indicates to which DAC the the first data-word goes to DAC 1, and the second data-word data is intended. On the rising edge of DCI, data is latched into goes to DAC 2. When FRAME goes low, the first data-word DAC 1 and DAC 3. On the falling edge of DCI, data is latched goes to DAC 3, and the second data-word goes to DAC 4. into DAC 2 and DAC 4. This pattern repeats continuously. This pattern repeats continuously as illustrated in Figure 47. There is a SPI programmable option (Register 0x14[6]) to provide DCIA one DCI for both input ports or two DCIs, where each DCI is associated with one input port. Two DCIs are useful when the FRAMEA data for each port is coming from a different data source. These cases are illustrated in Figure 45 and Figure 46. DAC1 DAC2 DAC3 DAC4 DAC1 DAC2 DAC3 DAC4 A[15:0] DCIA Figure 47. Timing Diagram for Single-Port Mode Each data sample, by default, is expected to be formatted as an MSB A[15:0] DAC1 DAC2 DAC1 DAC2 DAC1 DAC2 DAC1 DAC2 sent to Bit 15 and an LSB sent to Bit 0. When the bus swap bit is set (Register 0x03[4]), the MSB should be sent to Bit 0, and the DAC3 DAC4 DAC3 DAC4 DAC3 DAC4 DAC3 DAC4 B[15:0] LSB should be sent to Bit 15 for each port. Figure 45. Timing Diagram for Dual-Port Mode, One DCI The FRAME signal is sampled with the same internal signal as the data and has the same set-up and hold timing relative to DCI. If DCIA desired, only the first FRAME pulse needs to be generated. This initializes the internal clock phases inside the device, and data DAC1 DAC2 DAC1 DAC2 DAC1 DAC2 DAC1 DAC2 A[15:0] latches just as if the periodic FRAME signal were sent. DCIB DAC3 DAC4 DAC3 DAC4 DAC3 DAC4 DAC3 DAC4 B[15:0] Figure 46. Timing Diagram for Dual-Port Mode, Two DCI Rev. B | Page 40 of 72 08910-046 08910-045 08910-047 Data Sheet AD9148 The AD9148 also includes a byte swap feature. By default, the BYTE MODE bytes should be formatted as an MSB sent to Bit 15 on Bus 1 and In byte mode, a FRAME signal must be provided along with the Bit 7 on Bus 2. When byte swap is enabled (Register 0x03[2]), an DCI signal and the data. The most significant byte of the data MSB should be sent to Bit 8 on Bus 1 and Bit 0 on Bus 2. This should correspond with DCI being high, and the least significant is described in Table 14. byte of the data should correspond with DCI being low. The FRAME signal indicates to which DAC the data is intended. Table 14. Byte Swap Formatting When FRAME is high, data on the top half of the port (A[15:8]) Byte Swap Byte A[15:8] A[7:0] is sent to DAC 1 and data on the bottom half of the port (A[7:0]) is 0 MSB Data Set 1[15:8] Data Set 2[15:8] sent to DAC 3. When the FRAME is low, data on the top half of 0 LSB Data Set 1[7:0] Data Set 2[7:0] the port is sent to DAC 2 and data on the bottom half of the port 1 MSB Data Set 1[8:15] Data Set 2[8:15] is sent to DAC 4. This pattern repeats continuously as shown in 1 LSB Data Set 1[0:7] Data Set 2[0:7] Figure 48. DATA INTERFACE OPTIONS DCIA To enable optimization of the data interface, some additional options have been provided in the following registers: FRAMEA • Data format (Register 0x03) DAC1H DAC1L DAC2H DAC2L DAC1H DAC1L DAC2H DAC2L A[15:8] • Data receiver control (Register 0x14) • Data receiver status (Register 0x15) A[7:0] DAC3H DAC3L DAC4H DAC4L DAC3H DAC3L DAC4H DAC4L Depending on the data rate and DCI vs. data skew, the internal Figure 48. Timing Diagram for Byte Mode DCI can be inverted to meet the valid data timing window. RECOMMENDED FRAME INPUT BIAS CIRCUITRY Because the frame signal can be used as a reference clock in the byte mode or as a trigger to reset the FIFO, it is recommended that the frame input be tied to LVDS logic low when it is not used (that is, when it is not driven by an ASIC or FPGA). The external bias circuit shown in Figure 49 is recommended for this purpose. This bias circuit applies to both FRAMEA and FRAMEB ports. AD9148 150Ω FRAMEP 100Ω FRAMEN 51Ω DVDD18 (1.8V) Figure 49. External Bias Circuit Rev. B | Page 41 of 72 08910-048 08910-145 AD9148 Data Sheet FIFO OPERATION 32 BITS REG 0 REG 1 32 REG 2 DAC1 32 32 DATA DATA INPUT DATA AND REG 3 PORT A PATHS LATCH ASSEMBLER DAC2 REG 4 REG 5 32 REG 6 REG 7 WRITE PTR A DCIA WRITE PTR READ RESET PTR RESET LOGIC FRAMEA FIFO RATE/ ÷INT DACCLK DATA RATE SYNC LOGIC FRAMEB WRITE PTR RESET 32 BITS WRITE PTR B DCIB ONE REG 0 DCI REG 1 REG 2 32 INPUT DATA 32 32 DAC3 DATA REG 3 DATA LATCH ASSEMBLER AND PORT B PATHS DAC4 REG 4 REG 5 REG 6 INTERFACE MODE REG 7 Figure 50. Block Diagram of FIFO The AD9148 contains two 32-bit wide, 8-word deep FIFOs (one important to take into account when understanding the overall per dual DAC) designed to relax the timing relationship between pipeline delay of the AD9148. the data arriving at the DAC input ports and the internal DAC In single-port and byte interface modes, the incoming digital data is data rate clock. The FIFOs can also be used to provide an adjustable sampled at twice the data rate (DCIA). The data is then assembled pipeline delay between the DCIx clocks and the DACCLK allowing based on the interface mode. At the output of the data assembler realignment of data input in a multichip system. This significantly block, the data samples for DAC 1 and DAC 2 are written to FIFO A increases the timing budget of the interface. and the data samples for DAC 3 and DAC 4 are written to FIFO B Figure 50 shows the block diagram of the datapath through the at the data rate. FIFO. The data is latched into the device, is formatted, and is then Valid data is transmitted through the FIFO as long as the FIFO written into the FIFO register determined by the FIFO write does not overflow or become empty. An overflow or empty pointer. The value of the write pointer is incremented every time a condition of the FIFO is the same as the write pointer and the new word is loaded into the FIFO. Meanwhile, data is read from read pointer being equal. When both pointers are equal, an attempt the FIFO register determined by the read pointer and fed into is made to read and write a single FIFO register simultaneously. the digital datapath. The value of the read pointer is updated This simultaneous register access leads to unreliable data transfer every time data is read into the datapath from the FIFO. This through the FIFO and must be avoided. happens at the data rate, that is, the DACCLK rate divided by the interpolation ratio. The difference between the write and read pointers represents the FIFO pipeline delay and is Rev. B | Page 42 of 72 FIFO B FIFO A OFS[2:0] OFS[2:0] READ POINTER B READ POINTER A 08910-049 Data Sheet AD9148 Nominally, data is written to the FIFO at the same rate as data is Data Rate Synchronization read from the FIFO. This keeps the data level in the FIFO constant. In this mode, the REFCLK/SYNC signal is used to reset the If data is written to the FIFO faster than data is read, the data FIFO read pointer to 0. The edge of the CLK used to sample the level in the FIFO increases. If the data is written to the device SYNC signal is selected by Bit 3 of Register 0x10. If the PLL is slower than data is read, the data level in the FIFO decreases. For a used, REFCLK is used as a SYNC signal, and the FIFO read maximum timing margin, the FIFO level should be maintained pointer is reset at the REFCLK rate divided by 64. The data rate near half full, which is the same as maintaining a difference of 4 synchronization is selected by setting Bit 6 of Register 0x10 to 0. between the write pointer and read pointer values. As previously mentioned, the FRAME signal is used to reset SYNCHRONIZING AND RESETTING THE FIFO the FIFO write pointer. When the FRAME is asserted, the FIFO To avoid any concurrent reads and writes to the same FIFO address write pointer is reset to the address defined in Bits[2:0] of the and to assure a fixed pipeline delay, it is important to reset the state corresponding FIFO Status/Control Port x register (Register 0x17 of the FIFO pointers to known states. The pipeline delay in the or Register 0x19) the next time the read pointer becomes 0 (see AD9148 comes from two sources, FIFO delay and the delay Figure 51). though the signal processing in the DAC. The data rate synchronization, the write pointer of the FIFO, and To assure a fixed and predictable pipeline delay in the signal the read pointer of the FIFO are synchronized at the SYNC rate processing, the FIFO read operation is synchronized with the and have a fixed phase offset. DACCLK and, more importantly, in case of interpolation, its SYNC divided down version so that the same edge of the slowest clock 0 1 2 3 4 in the signal processing reads the same data in the FIFO. The RDPTRA 3 4 5 6 7 5 6 synchronization is performed by resetting the FIFO read pointer RDPTRB 3 4 5 6 7 0 1 2 3 4 5 6 to a known state relative to the slowest clock used in the signal FIFO_A WRITE RESET VALUE FOR RESET processing. This synchronization is enabled by setting Bit 7 in REGISTER 0x17[2:0] = 0b100 FRAMEA Register 0x10 to 1, and it uses the REFCLK/SYNC signal for its WRPTRA 7 0 1 2 3 4 5 6 7 0 1 2 reference. FIFO_B WRITE RESET RESET VALUE FOR To manage the FIFO pipeline delay, the FIFO write pointer must be REGISTER 0x19[2:0] = 0b100 FRAMEB synchronized with the read pointer to avoid concurrent access WRPTRB 0 1 2 3 4 4 5 6 7 0 1 2 to the FIFO and to potentially compensate for any data input Figure 51. Timing of the FRAME Input vs. Write Pointer Value in Data Rate phase mismatch. This synchronization can be performed either Synchronization at the data rate (see the Data Rate Synchronization section) or at the FIFO rate (see the FIFO Rate Synchronization section). FIFO Rate Synchronization FIFO Synchronization Modes In this mode, the REFCLK/SYNC signal is used to reset the FIFO read pointer to 0. The edge of the CLK_x used to sample To benefit from the advantages of the FIFO functionality in the the SYNC signal is selected by Bit 3 of Register 0x10. As previously different modes of operations, PLL on/off, standalone, or multi- mentioned, the FRAME signal is used to reset the FIFO write chip synchronization, the FIFO can operate in the following ways: pointer. In the FIFO rate synchronization mode, the FIFO write • Synchronization at the data rate pointer is reset immediately after the FRAME signal is asserted • Synchronization at the FIFO rate (data rate/FIFO depth) high for at least the time interval needed to load complete data to • No synchronization the four DACs, and the FIFO write pointer is reset to the address defined in Bits[2:0] of the corresponding FIFO Status/Control As discussed in the Input Data Ports section, in single-port mode Port x register, Register 0x17 or Register 0x19 (see Figure 52). and byte mode, the FRAME input is used as a data select signal SYNC that indicates to which DAC the input data is intended to be FIFO_A AND FIFO_B READ RESET written. When synchronization is needed, the FRAME signal is RDPTRA 0 1 2 3 4 5 6 7 0 1 2 3 given another function, initializing the FIFO write pointer address. When the FRAME signal is asserted high for at least the 0 1 2 3 4 5 6 7 0 1 2 3 RDPTRB time interval needed to load complete data to the four DACs FIFO_A WRITE RESET VALUE FOR RESET (which correspond to one DCI period in dual-port mode and REGISTER 0x17[2:0] = 0b100 FRAMEA two DCI periods in single-port mode or byte mode), the FIFO WRPTRA 4 4 5 6 7 0 1 2 3 4 5 6 write pointer is reset to a value dependent on the synchronization FIFO_B WRITE RESET VALUE FOR RESET mode selected and the FIFO phase offset bits of the corresponding REGISTER 0x19[2:0] = 0b110 FRAMEB FIFO Status/Control Port x register, Register 0x17 or Register 0x19. 2 3 4 6 7 0 1 2 3 4 5 6 WRPTRB Figure 52. Timing of the FRAME Input vs. Write Pointer Value in FIFO Rate Synchronization Rev. B | Page 43 of 72 08910-051 08910-050 AD9148 Data Sheet 3. Remove the request by resetting Bit 3, Register 0x17 or Bit 3, No Synchronization Register 0x19 to 0. In this mode, Bit 7 in Register 0x10 is set to 0, the pipeline delay 4. The FIFO SPI aligned flag in the Event Flag 0 register, Bit 2 in the signal processing is not controlled, and the read pointer in Register 0x06, is set when the reset of the write pointer has of the FIFO is never reset. However, to assure that the FIFO can been realized. Bit 4 in Register 0x17 or Bit 4 in Register 0x19 is operate safely and there is no concurrent access to FIFO from reset to 0 to indicate which FIFO has generated this flag. the write and read pointer to the same address, it is important to ensure that the phase offset between the two pointers is greater Note that the SPI writes to Register 0x17 or Register 0x19 should than 2. In consequence, the only FIFO reset that can be used be done while maintaining a constant value in the FIFO phase safely is the data rate synchronization, Bit 6 of Register 0x10 set offset bits. to 0, where the FIFO is reset with a fixed offset of 4 between the FIFO Reset Using FRAME Signal write and read pointers. Because there is no SYNC signal, the The FIFO pointers can also be reset using the FRAME signals. reset of the FIFO write pointer can only be done by a FRAME If only one DCI is used, only the FRAMEA signal is used for the signal or an SPI command. FIFO reset. This mode is enabled by setting Bit 6 in Register 0x10. FIFO Reset Commands As discussed in the FIFO Synchronization Modes section, the Depending on the configuration of the system, the FIFO reset FRAME input is used to initialize the FIFO data level value. When can be done manually or periodically for a multichip system. the FRAME signal is asserted high for at least the time interval The AD9148 provides two ways to resetting the FIFO pointers: needed to load the complete data to the four DACs, the write SPI interface or periodic reset using the FRAME signal. pointer is reset depending on the mode of synchronization chosen. The SPI also gives access to each FIFO phase offset in Bits [2:0] • Data rate synchronization (default), Bit 6 of Register 0x10, of the corresponding FIFO status/control registers, Register 0x17 is set to 0. When read pointer reaches 0, write pointer reset and Register 0x19. The value in these three bits corresponds either to FIFO offset phase. to the offset between the write and read pointer in the data rate • FIFO rate synchronization, Bit 6 of Register 0x10, is set to 1. synchronization or to the absolute address of the FIFO write On the rising edge of the FRAME signal, write pointer pointer in the FIFO rate synchronization. reset to FIFO start level. SPI Command for Manual Reset MONITORING THE FIFO STATUS If a manual reset is acceptable, the FIFO pointer addresses can The FIFO initialization and status can be read from Register 0x17. be reset using the SPI interface. This register provides information about the FIFO initialization To initialize the FIFO data level through the SPI, Bit 3 of method and whether the initialization was successful. The MSB Register 0x17 (FIFO Port A) or Bit 3 of Register 0x19 (FIFO of Register 0x17 is a FIFO warning flag that can optionally trigger a Port B) should be toggled from 0 to 1 and back. When the device IRQ. This flag is an indication that the FIFO is close to write to the register is complete, the corresponding FIFO data emptying (FIFO level is 1) or overflowing (FIFO level is 7). This level is initialized. is an indication that the data may soon be corrupted, and action The recommended procedure for a SPI FIFO data level should be taken. initialization is The FIFO data level can be read from Register 0x18 at any time. 1. Request FIFO Port A or FIFO Port B level reset by setting The SPI reported FIFO data level is denoted as a 7-bit thermometer Bit 3 in Register 0x17 or Bit 3 in Register 0x19 to Logic 1. The code of the write counter state relative to the absolute read counter FIFO phase offset, Bits [2:0] in Register 0x17 or Bits [2:0] in being 0. The optimum FIFO data level of four is, therefore, Register 0x19, should also be written at the same time to reported as a value of 00001111 in the status register. set the desired value of offset between the FIFO write and Note that, depending on the timing relationship between DCI read pointers. and the main DACCLK, the FIFO level value can be off by a ±1 2. Verify that the part acknowledges the request by ensuring count. Therefore, it is important to keep the difference between the that Bit 4 in Register 0x17 or Bit 4 in Register 0x19 is set read and write points to at least 2. to Logic 1. Rev. B | Page 44 of 72 Data Sheet AD9148 DEVICE SYNCHRONIZATION rate synchronization is increased setup and hold times of DCI SYNCHRONIZING MULTIPLE DEVICES relative to the CLK input. When in data rate synchronization System demands may require that the outputs of multiple DACs mode, the elasticity of the FIFO is not used to absorb timing be synchronized with each other or with a system clock. Systems variations between the data source and DAC, resulting in that support transmit diversity or beam-forming, where multiple tighter setup and hold time requirements. antennas are used to transmit a correlated signal, require multiple The method chosen for providing the DAC sampling clock directly DAC outputs to be phase aligned with each other. Systems with impacts the synchronization methods available. When the device a time-division multiplexing transmit chain may require one or clock multiplier is used, only data rate synchronization is more DACs to be synchronized with a system-level reference clock. available. When the DAC sampling clock is sourced directly, Multiple devices are considered synchronized to each other when both data rate mode and FIFO rate mode synchronization are the state of the clock generation state machines is identical for all available. parts and time aligned data is being read from the FIFOs of all SYNCHRONIZATION WITH CLOCK MULTIPLICATION parts simultaneously. Devices are considered synchronized to a system clock when there is a fixed and known relationship between When using the clock multiplier to generate the DACCLK, the the clock generation state machine and the data being read from REFCLK/SYNC input signal acts as both the reference clock for the FIFO and a particular clock edge of the system clock. The the PLL-based clock multiplier and as the synchronization signal. AD9148 has provisions for enabling multiple devices to be To synchronize devices, the REFCLK/SYNC signal must be synchronized to each other or to a system clock. distributed with low skew to all of the devices to be synchronized. Skew between the REFCLK/SYNC signals of different devices show The AD9148 supports synchronization in two different modes, up directly as a timing mismatch at the DAC outputs. data rate mode and FIFO rate mode. The two modes are distinguished by the lowest rate clock that the synchronization The frequency of the REFCLK/SYNC signal is typically equal to logic attempts to synchronize. In data rate mode, the input data the input data rate. The FRAME signal and DCI signals can be rate represents the lowest synchronized clock. In FIFO rate mode, created in the FPGA along with the data. A circuit diagram of a the FIFO rate, which is the data rate divided by the FIFO depth typical configuration is shown in Figure 53. of 8, represents the lowest rate clock. The advantage of the FIFO MATCHED LENGTH TRACES REFCLK/SYNC OUT1 FRAME DCI LOW SKEW SYSTEM CLOCK CLOCK DRIVER REFCLK/SYNC FRAME OUT2 FPGA DCI MATCHED LENGTH TRACES Figure 53. Typical Circuit Diagram for Synchronizing Devices with Clock Multiplication Enabled Rev. B | Page 45 of 72 08910-052 AD9148 Data Sheet The following procedure outlines the steps required to synchronize To maintain synchronization, the skew between REFCLK/SYNC multiple devices. The procedure assumes that the REFCLK/SYNC signals of the devices must be less than t nanoseconds. There SKEW signal is applied to all of the devices and the PLL of each device is also a setup and hold time to be observed between the DCI and is phase locked to it. Each individual device must follow this data of each device and the REFCLK/SYNC signal. When resetting procedure. the FIFO, the FRAME signal must be held high for at least the time interval needed to load complete data to the four DACs The procedure for synchronization when using the PLL follows: (one DCI period for dual-port mode and two DCI periods for 1. Configure for data rate, periodic synchronization by writing single-port or byte mode). A timing diagram of the input signals is 0xC0 to the sync control register (Register 0x10). shown in Figure 54. 2. Read the sync status register (Register 0x12) and verify that The example in Figure 54 shows a REFCLK/SYNC frequency equal the sync locked bit (Bit 6) is set high indicating that the device to the data rate. Whereas this is the most common situation, it is not achieved back-end synchronization and that the sync lost strictly required for proper synchronization. Any REFCLK/SYNC bit (Bit 7) is low. These levels indicate that the clocks are frequency that satisfies the following equations is acceptable: running with a constant and known phase relative to the N sync signal. fSYNC = fDACCLK/2 and fSYNC ≤ fDATA 3. Reset the FIFO by strobing the FRAME signal high for at where N = 1, 2, 3, or 4. least the time interval needed to load complete data to the For example, a configuration with 4× interpolation and clock four DACs. Resetting the FIFO ensures that the correct data is frequencies of f = 1600 MHz, f = 800 MHz, and VCO DACCLK being read from the FIFO. This completes the synchronization f = 200 MHz, f = 100 MHz would be a viable solution. DATA SYNC procedure, and at this stage, all devices should be synchronized. t SKEW REFCLK(1) REFCLK(2) t t SU_DCI H_DCI DCI(2) FRAME(2) Figure 54. Timing Diagram Required for Synchronizing Two Devices Rev. B | Page 46 of 72 08910-053 Data Sheet AD9148 LOW SKEW CLOCK DRIVER CLK REFCLK/SYNC OUT1 FRAME SAMPLE RATE CLOCK DCI MATCHED LOW SKEW LENGTH TRACES CLOCK DRIVER CLK REFCLK/SYNC OUT2 FRAME SYNC CLOCK DCI MATCHED LENGTH TRACES FPGA Figure 55. Typical Circuit Diagram for Synchronizing Devices to a System Clock must also meet the setup and hold time with respect to the SYNCHRONIZATION WITH DIRECT CLOCKING rising edge of CLK. When resetting the FIFO, the FRAME When directly sourcing the DAC sample rate clock to CLK, a signal must be held high for at least the time interval needed to separate REFCLK/SYNC input signal is required for synchronization. load complete data to the four DACs (one DCI period for dual- To synchronize devices, the CLK signals and the REFCLK/SYNC port mode and two DCI periods for single-port or byte mode). signals must be distributed with low skew to all of the devices When these conditions are met, the outputs of the DACs will be being synchronized. This configuration is shown below in updated within t + t nanoseconds of each other. A timing SKEW OUTDLY Figure 55. diagram that illustrates the timing requirements of the input Data Rate Mode Synchronization signals is shown in Figure 56. The following procedure outlines the steps required to synchronize t SKEW multiple devices in data rate mode. The procedure assumes that the CLK and REFCLK/SYNC signals are applied to all of the CLK(1) devices. Each individual device must follow the procedure. The procedure for data rate synchronization when directly CLK(2) sourcing the DAC sampling clock follows: t t t t SU_DCI H_DCI SU_SYNC H_SYNC 1. Configure for data rate, periodic synchronization by SYNC(2) writing 0xC0 to the sync control register (Register 0x10). Additional synchronization options are available (see the DCI(2) Additional Synchronization Features section). 2. Poll the sync locked bit (Bit 6, Register 0x12) to verify that FRAME(2) the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant Figure 56. Synchronization Signal Timing Requirements in Data Rate Mode, 2× Interpolation and known phase relative to the sync signal. 3. Reset the FIFO by strobing the FRAME signal for at least the Figure 56 shows the synchronization signal timing with 2× time interval needed to load complete data to the four DACs interpolation, so that f = ½ × f . The REFCLK/SYNC input DCI CLK Resetting the FIFO ensures that the correct data is being is shown equal to the DCI rate. The maximum frequency at which read from the FIFO of each of the devices simultaneously. the device can be resynchronized in data rate mode can be This completes the synchronization procedure, and at this expressed as stage, all devices should be synchronized. f DATA f = SYNC N To ensure that each of the DACs are updated with the correct data 2 on the same DACCLK edge, two timing relationships must be for any positive integer, N. met on each DAC. DCI (and data) must meet the setup and hold times with respect to the rising edge of CLK, and REFCLK/SYNC Rev. B | Page 47 of 72 08910-054 08910-055 AD9148 Data Sheet Generally, for values of N equal to or greater than 3, the FIFO Figure 57 shows the synchronization signal timing with 2× rate synchronization mode is chosen. interpolation, so that f = ½ × f . The REFCLK/SYNC input DCI CLK is shown equal to the FIFO rate. The maximum frequency at which FIFO Rate Mode Synchronization the device can be resynchronized in FIFO rate mode can be The following procedure outlines the steps required to synchronize expressed as multiple devices in FIFO rate mode. The procedure assumes f DATA that the CLK and REFCLK/SYNC signals are applied to all of the f = SYNC N 8× 2 devices. Each individual device must follow the procedure. for any positive integer, N. The procedure for FIFO rate synchronization when directly ADDITIONAL SYNCHRONIZATION FEATURES sourcing the DAC sampling clock follows: The synchronization logic incorporates additional features that 1. Configure for FIFO rate, periodic synchronization by writing provide means for querying the status of the synchronization 0x80 to the sync control register (Register 0x10). Additional and for improving the robustness of the synchronization. For synchronization options are available and are described in more information on these features, see the Sync Status Bits the Additional Synchronization Features section. section and the Timing Optimization section. 2. Poll the sync locked bit (Bit 6, Register 0x12) to verify that the device is back-end synchronized. A high level on this Sync Status Bits bit indicates that the clocks are running with a constant When the sync locked bit (Bit 6, Register 0x12) is set, it indicates and known phase relative to the sync signal. that the synchronization logic has reached alignment. This is 3. Reset the FIFO by strobing the FRAME signal high for at determined when the clock generation state machine phase is least the time interval needed to load complete data to the constant. This takes between (11 + Averaging) × 64 and (11 + four DACs. Resetting the FIFO ensures that the correct Averaging) × 128 DACCLK cycles. This bit may optionally trigger data is being read from the FIFO of each of the devices IRQ an , as described in the Interrupt Request Operation section. simultaneously. This completes the synchronization When the sync lost bit (Bit 7, Register 0x12) is set, it indicates that a procedure, and at this stage, all devices should be previously synchronized device has lost alignment. This bit is synchronized. latched and remains set until cleared by overwriting the register. To ensure that each of the DACs is updated with the correct This bit may optionally trigger an IRQ as described in the data on the same DACCLK edge, two timing relationships must Interrupt Request Operation section. be met on each DAC. DCI (and data) must meet the setup and Timing Optimization hold times with respect to the rising edge of CLK, and REFCLK/ SYNC must also meet the setup and hold time with respect to The REFCLK/SYNC signal is sampled by a version of the the rising edge of CLK. When resetting the FIFO, the FRAME DACCLK. If sampling errors are detected, the opposite sampling signal must be held high for at least the time interval needed to edge can be selected to improve the sampling point. The sampling load complete data to the four DACs (one DCI period for dual- edge can be selected by setting Bit 3, Register 0x10 (1 = rising port mode, and two DCI periods for single-port or byte mode). and 0 = falling). When these conditions are met, the outputs of the DACs will be The synchronization logic resynchronizes when a phase change updated within tSKEW + tOUTDLY nanoseconds of each other. A between the REFCLK/SYNC signal and the state of the clock timing diagram that illustrates the timing requirements of the generation state machine exceeds a threshold. To mitigate the input signals is shown in Figure 57. effects of jitter and prevent erroneous resynchronizations, the t SKEW relative phase can be averaged. The amount of averaging is set by the sync averaging bits (Bits[2:0], Register 0x10) and can be CLK(1) set from 1 to 128. The higher the number of averages, the more slowly the device recognizes and resynchronizes to a legitimate phase correction. Generally, the averaging should be made as CLK(2) large as possible while still meeting the allotted resynchronization t t SU_SYNC H_SYNC time interval. SYNC(2) Additional information on synchronization can be found in the AN-1093 Application Note, Synchronization of Multiple AD9122 DCI(2) TxDAC+ Converters. Table 15. Synchronization Setup and Hold Times FRAME(2) Parameter Min Max Unit Figure 57. Synchronization Signal Timing Requirements in FIFO Rate Mode, tSKEW −tDACCLK/2 +tDACCLK/2 ps 2× Interpolation tSU_SYNC −100 ps tH_SYNC +400 ps Rev. B | Page 48 of 72 08910-056 Data Sheet AD9148 INTERFACE TIMING The timing diagram for the digital interface port is shown in t DATA DACCLK/ Figure 59. The sampling point of the data bus nominally occurs REFCLK 250 ps after each edge of the DCI signal and has an uncertainty of ± 250 ps when the DCI delay is set to 00b (Register 0x72[1:0]), SAMPLING INTERVAL as illustrated by the sampling interval. The data and FRAME signals must be valid throughout this sampling interval. The data and FRAME signals may change at any time between sampling intervals. DCI The setup (tS) and hold (tH) times with respect to the edges are t SDCI shown in Figure 59. The minimum setup and hold times are shown in Table 16. t HDCI Table 16. Data Port Setup and Hold Times Figure 58. Timing Diagram for Input Data Port (Data Rate Mode with Sync On) DCI Delay Minimum Setup Minimum Hold Table 17. DCI to DACCLK Setup and Hold Times vs. DCI (Register 0x72, Bits[1:0]) Time, t (ns) Time, t (ns) S H Delay Value 00 −0.02 0.52 DCI Delay Minimum Setup Minimum Hold 01 −0.16 0.78 (Register 0x72,Bits[1:0]) Time, tSDCI (ns) Time, tHDCI (ns) 10 −0.28 1.03 00 −0.06 0.85 11 −0.36 1.16 01 −0.22 1.14 The data interface timing can be verified by using the SED 10 −0.36 1.43 circuitry. See the Interface Timing Validation section for details. 11 −0.45 1.59 In data rate mode with synchronization enabled, a second timing constraint between DCI and DACCLK must be met in addition to the DCI-to-data timing shown in Table 17. In data rate mode, only one FIFO slot is being used. The DCI to DACCLK timing restriction is required to prevent data being written to and read from the FIFO slot at the same time. The required timing between DCI and DACCLK is shown in Figure 58. t DATA SAMPLING DCI INTERVAL SAMPLING INTERVAL DATA t S t H Figure 59. Timing Diagram for Input Data Ports Rev. B | Page 49 of 72 08910-058 08910-057 AD9148 Data Sheet DIGITAL DATA PATH The block diagram in Figure 60 shows the functionality of the Filter Structure complex digital data path. The digital processing includes a The programmable inverse sinc filter is a nine-tap complex FIR premodulation block, a programmable complex filter, three filter using complex conjugate coefficients. The z-transfer half-band interpolation filters with built-in coarse modulation, function is a quadrature modulator with a fine resolution NCO as well as y + j× y I Q phase, gain, and offset adjustment blocks. H(z)= = H + j× H I Q x + j× x I Q −1 −2 −3 −4 = c + c × z + c × z + c × z + c × z 0 1 2 3 4 PROG DIGITAL PREMOD –1 SINC HB1 HB2 HB3 PHASE/GAIN/ −5 −6 −7 −8 f /2 S +c × z + c × z + c × z + c × z FILTER OFFSET ADJ 3 2 1 0 where: Figure 60. Block Diagram of Digital Data Path x and x are the in-phase (real) and quadrature (imaginary) I Q There are two complex digital data paths that feed the four DACs. filter input, respectively. Each digital data path accepts I and Q data streams and processes yI and yQ are the in-phase (real) and quadrature (imaginary) them as a quadrature data stream, resulting in two quadrature filter output, respectively. data streams. All of the signal processing blocks can be used HI and HQ are the in-phase (real) and quadrature (imaginary) when the input data stream is represented as complex data. filter coefficients, respectively. The data path can be used to process an input data stream c , c , c , c , and c are the complex filter coefficient, and their 0 1 2 3 4 cX representing four independent real data streams as well; however, complex conjugate. the functionality is somewhat restricted. The premodulation The filter coefficients must be calculated and programmed into block can be used, as well as any of the nonshifted interpolation the AD9148 registers to perform the operation desired. filter modes. Filter Implementation PREMODULATION To perform the complex filtering of the complex input, the filter The half-band interpolation filters have selectable pass bands is divided in four filters working in parallel, two sets of HI and that allow the center frequencies to be moved in increments two sets of HQ (see Figure 61). of ½ of their input data rate. The premodulation block provides y + j× y =(H + j× H )⋅(x + j× x ) a digital upconversion of the incoming waveform by ½ of I I i Q Q Q the incoming data rate, f Functionally, the premodulation DATA. = H × x − H × x + j⋅(H × x + H × x ) I I I I Q Q Q Q multiplies the incoming data samples alternatively by +1 and −1. + Y I X This can be used to frequency shift baseband input data to the I H I center of the interpolation filters pass band. – + Y Q H Q PROGRAMMABLE INVERSE SINC FILTER + The AD9148 provides a programmable inverse sinc filter to X H Q I compensate the DAC roll-off over frequency. Because this filter is implemented before the interpolation filter, its coefficients H Q must be changed depending on the interpolation rate and DAC output center frequency. Figure 61. Complex Filter Implementation The coefficients for the filter are stored in SPI Register 0x20 to Register 0x27 in twos-complement format. They have variable length, three bits to 10 bits. Rev. B | Page 50 of 72 08910-059 08910-060 Data Sheet AD9148 Table 18. Programmable Inverse Sinc Filter Coefficient Widths and Ranges Coefficient Width Minimum Maximum c0 in-phase (real) 3 100b 011b −4 3 c quadrature (imaginary) 3 0100b 011b 0 −4 3 c in-phase (real) 4 1000b 0111b 1 −8 7 c1 quadrature (imaginary) 4 1000b 0111b −8 7 c in-phase (real) 5 10000b 01111b 2 −16 15 c2 quadrature (imaginary) 5 10000b 01111b −16 15 c3 in-phase (real) 7 1000000b 0111111b −64 63 c quadrature (imaginary) 7 1000000b 0111111b 3 −64 63 c4 in-phase (real) 10 1000000000b 0111111111b −1024 1023 c4 quadrature (imaginary) 10 1000000000b 0111111111b −1024 1023 The real and imaginary filters are implemented using the When there is no interpolation used, the real filter coefficients structure described in Figure 62 and Figure 63. can be fixed at (no imaginary coefficients) INPUT n –1 –1 –1 –1 –1 z z z z z C = 2 ; C = 2 0 8 C = −4 ; C = −4 1 7 c c c c c 0REAL 1REAL 2REAL 3REAL 4REAL C = 10 ; C = 10 2 6 + + + + + C = −35 ; C = −35 c 3 5 5REAL + + + + + + + + + + OUTPUT C4 = 401 n + + + + + INTERPOLATION FILTERS –1 –1 –1 –1 z z z z The transmit path contains three interpolation filters. Each of Figure 62. Real Filter implementation the three interpolation filters provides a 2× increase in output INPUT n –1 –1 –1 –1 –1 z z z z z data rate. The filters can be cascaded to provide 2×, 4×, or 8× interpolation ratios. Each of the half-band filter stages offers a c c c c c 0IMG 1IMG 2IMG 3IMG 4IMG different combination of bandwidths and operating modes. + + + + + c 5IMG The bandwidth of the three half-band filters with respect to the – – – – – + + + + + OUTPUT n + + + + + data rate at the filter input is as follows: –1 –1 –1 –1 z z z z • Bandwidth of HB1 = 0.8 × f IN1 Figure 63. Imaginary Filter implementation • Bandwidth of HB2 = 0.5 × f IN2 • Bandwidth of HB3 = 0.4 × f IN3 The AD9148 evaluation tools provide software that allows for the processing of the filter coefficients based on the DAC sampling The usable bandwidth is defined as the frequency over which frequency, the amount of interpolation used (combination of the filters have a pass-band ripple of less than ±0.001 dB and an HB1, HB2, and HB3), and the desired center frequency. This image rejection of greater than +85 dB. As is discussed in the center frequency is limited to Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. [−0.4 × fDAC + 0.5 × signalBW, 0.4 × fDAC − 0.5 × signalBW] The half-band filters operate in several modes, providing The bandwidth of the inverse sinc filter equals the maximum programmable pass-band center frequencies as well as signal allowable signal bandwidth of the interpolation filters (0.8 × fDATA). modulation. The HB1 filter has four modes of operation, and the HB2 and HB3 filters each have eight modes of operation. Rev. B | Page 51 of 72 08910-062 08910-061 AD9148 Data Sheet 0.02 Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 64. The 0 shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors: the filter center –0.02 frequency and whether the filter modulates the input signal. MODE 0 MODE 2 MODE 1 MODE 3 –0.04 0 –0.06 –20 –0.08 –40 –0.10 0 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 –60 (× f ) IN1 Figure 65. Pass-Band Detail of HB1 –80 Table 20. HB1 Pass-Band and Stop-Band Performance by Bandwidth –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Pass-Band Stop-Band (× f ) IN1 Bandwidth (% of f ) Flatness (dB) Rejection (dB) IN1 Figure 64. HB1 Filter Modes 80 0.001 85 80.4 0.0012 80 As is shown in Figure 64, the center frequency in each mode is 81.2 0.0033 70 offset by ½ of the input data rate (fIN1) of the filter. Mode 0 and 82.0 0.0076 60 Mode 1 do not modulate the input signal. Mode 2 and Mode 3 83.6 0.0271 50 modulate the input signal by fIN1. When operating in Mode 0 85.6 0.1096 40 and Mode 2, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating Half-Band Filter 2 (HB2) in Mode 1 and Mode 3, mixing of the data between the I and Q HB2 has eight modes of operation, as shown in Figure 66 and paths occurs; therefore, the data input into the filter is assumed Figure 67. The shape of the filter response is identical in each of complex. Table 19 summarizes the HB1 modes. the eight modes. The eight modes are distinguished by two factors, the filter center frequency and whether the input signal is Table 19. 2× Interpolation Filter Modes (Register 0x1C to modulated by the filter. Register 0x1E) MODE 0 MODE 4 Filter Modes MODE 2 MODE 6 Interpolation f CENTER 0 Factor Pre-Mod HB1 HB2 HB3 (fDAC) 2 0 0 Off Off 0 –20 2 1 1 Off Off f /4 DAC 2 0 2 Off Off fDAC/2 –40 2 1 3 Off Off −fDAC/4 Figure 65 shows the pass-band filter response for HB1. In most –60 applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not –80 by the pass-band flatness. Table 20 shows the pass-band flatness and stop-band rejection the HB1 filter supports at different –100 bandwidths. 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 (× f ) IN2 Figure 66. HB2, Even Filter Modes Rev. B | Page 52 of 72 MAGNITUDE (dB) 08910-063 MAGNITUDE (dB) MAGNITUDE (dB) 08910-064 08910-065 Data Sheet AD9148 0.02 MODE 7 MODE 1 MODE 5 MODE 3 0 0 –20 –0.02 –40 –0.04 –60 –0.06 –80 –0.08 –100 –0.10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 (× f ) IN2 (× f ) IN2 Figure 67. HB2, Odd Filter Modes Figure 68. Pass-Band Detail of HB2 As shown in Figure 66 and Figure 67, the center frequency in Table 22. HB2 Pass-Band and Stop-Band Performance by each mode is offset by ¼ of the input data rate (fIN2) of the filter. Bandwidth Mode 0 through Mode 3 do not modulate the input signal. Mode 4 Pass-Band Stop-Band through Mode 7 modulate the input signal by fIN2. When operating Bandwidth (% of f ) Flatness (dB) Rejection (dB) IN2 in Mode 0 and Mode 4, the I and Q paths operate independently, 50 0.001 85 and no mixing of the data between channels occurs. When 50.8 0.0012 80 operating in the other six modes, mixing of the data between 52.8 0.0028 70 the I and Q paths occurs; therefore, the data input to the filter 56.0 0.0089 60 is assumed complex. Table 21 summarizes the HB2 modes. 60 0.0287 50 64.8 0.1877 40 Table 21. 4× Interpolation Filter Modes (Register 0x1C to Register 0x1E) Half-Band Filter 3 (HB3) Filter Modes Interpolation f CENTER HB3 has eight modes of operation that function the same as HB2. Factor Pre-Mod HB1 HB2 HB3 (fDAC) The primary difference between HB2 and HB3 are the filter 4 0 0 0 Off 0 bandwidths. Table 23 summarizes the filter modes for HB3. 4 1 1 1 Off fDAC/8 Table 23. 8× Interpolation Filter Modes (Register 0x1C to 4 0 2 2 Off fDAC/4 Register 0x1E) 4 1 3 3 Off 3fDAC/8 4 0 0 4 Off f /2 DAC Filter Modes Interpolation fCENTER 4 1 1 5 Off −3f /8 DAC Factor Pre-Mod HB1 HB2 HB3 (fDAC) 4 0 2 6 Off −f /4 DAC 8 0 0 0 0 0 4 1 3 7 Off −fDAC/8 8 0 2 2 1 fDAC/8 8 0 0 4 2 fDAC/4 Figure 68 shows the pass-band filter response for HB2. In most 8 0 2 6 3 3f /8 DAC applications, the usable bandwidth of the filter is limited by the 8 0 0 0 4 f /2 DAC image suppression provided by the stop-band rejection and not 8 0 2 2 5 −3f /8 DAC by the pass-band flatness. Table 22 shows the pass-band flatness 8 0 0 4 6 −fDAC/4 and stop-band rejection the HB2 filter supports at different 8 0 2 6 7 −fDAC/8 bandwidths. Rev. B | Page 53 of 72 MAGNITUDE (dB) 08910-066 MAGNITUDE (dB) 08910-067 AD9148 Data Sheet ×2 MODE Figure 69 shows the pass-band filter response for HB3. In most ×4 MODE ×8 MODE applications, the usable bandwidth of the filter is limited by the 0.4 image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 24 shows the pass-band flatness 0.3 and stop-band rejection the HB3 filter supports at different bandwidths. 0.2 0.02 0.15 0.1 0 0.075 0.0375 0 –0.02 –1/2 –3/8 –1/4 –1/8 DC 1/8 1/4 3/8 1/2 f (×f ) C DAC CARRIER FREQUENCY –0.04 Figure 70. Complex Signal Bandwidth as a Function of Output Frequency FINE MODULATION –0.06 The fine modulation makes use of a numerically controlled oscillator, –0.08 a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block –0.10 diagram of the fine modulator is shown in Figure 71. The fine 00 0.04 0.08 0.12 0.16 0.20 0.24.28 modulator allows the signal to be placed anywhere in the output (× f ) IN3 spectrum with very fine frequency resolution. Figure 69. Pass-Band Detail of HB3 Table 24. HB3 Pass-Band and Stop-Band Performance by INTERPOLATION I DATA Bandwidth Pass-Band Stop-Band Bandwidth (% of fIN3) Flatness (dB) Rejection (dB) COSINE FTW[31:0] 40 0.001 85 NCO NCO PHASE OFFSET OUT_I WORD [15:0] 40.8 0.0014 80 SINE 42.4 0.002 70 OUT_Q – + 45.6 0.0093 60 –1 49.8 0.03 50 SPECTRAL 0 1 55.6 0.1 40 INVERSION The maximum bandwidth can be achieved if the signal carrier frequency is placed directly at the center of one of the filter INTERPOLATION Q DATA pass bands. In this case, the entire quadrature bandwidth of the Figure 71. Fine Modulator Block Diagram interpolation filter (0.8 × f ) is available. The available signal DATA bandwidth decreases as the carrier frequency of the signal moves The quadrature modulator is used to mix the carrier signal away from the center frequency of the filter. The worst-case generated by the NCO with the I and Q signal. The NCO produces carrier frequency is one that falls directly between the center a quadrature carrier signal to translate the input signal to a new frequency of two adjacent filters. Figure 70 shows how the center frequency. A complex carrier signal is a pair of sinusoidal signal bandwidth changes as a function of placement in the waveforms of the same frequency, offset 90° from each other. The spectrum and interpolation rate. frequency of the complex carrier signal is set via the FTW[31:0] value in Register 0x54 through Register 0x57. The NCO operating frequency, fNCO, is at the DAC rate. The frequency of the complex carrier signal can be set from dc up to fDAC/2. The frequency tuning word (FTW) is calculated as f CENTER 32 FTW 2 f DAC The generated quadrature carrier signal is mixed with the I and Q data. The quadrature products are then summed into the I and Q data paths, as shown in Figure 71. Rev. B | Page 54 of 72 MAGNITUDE (dB) 08910-068 COMPLEX BW (×f ) DAC 08910-069 08910-070 Data Sheet AD9148 When using the fine modulator, the maximum signal bandwidth of Based on these two endpoints, the combined resolution of 0.8 × f is always achieved. the phase compensation register is approximately 3.5°/1024 or DATA 0.00342° per code. When both I Phase Adj, Bits[9:0] (Register 0x28 Updating the Frequency Tuning Word and Register 0x29), and Q Phase Adj, Bits[9:0] (Register 2A and The frequency tuning word registers are not updated immediately Register 2B), are used, the full phase adjustment range is ±3.5°. upon writing as the other configuration registers do. After loading DC OFFSET CORRECTION the FTW registers with the desired values, Bit 2 of Register 0x5A must transition from 0 to 1 for the new FTW to take effect. The dc value of the I data path and the Q data path can be independently controlled by adjusting I DC Offset, Bits[15:0], Phase Offset Adjustment and Q DC Offset, Bits[15:0], values in Register 0x2C through A 16-bit phase offset may be added to the output of the phase Register 0x2F. These values are added directly to the data path accumulator via the serial port. This static phase adjustment values. Care should be taken not to overrange the transmitted results in an output signal that is offset by a constant angle values. relative to the nominal signal. This allows the user to phase Figure 72 shows how the DAC offset current varies as a function of align the NCO output with some external signal, if necessary. I DC Offset, Bits[15:0], and Q DC Offset, Bits[15:0], values. With This can be especially useful when NCOs of multiple AD9148s the digital inputs fixed at midscale (0x000, twos complement are programmed for synchronization. The phase offset allows data format), Figure 72 shows the nominal IOUTxP and IOUTxN for the adjustment of the output timing between the devices. currents as the DC offset value is swept from 0 to 65,535. The static phase adjustment is sourced from the NCO Phase Because IOUTxP and IOUTxN are complementary current outputs, Offset[15:0] value located in Register 0x58 and Register 0x59. the sum of IOUTxP and IOUTxN is always 20 mA. QUADRATURE PHASE CORRECTION The purpose of the quadrature phase correction block is to 20 0 enable compensation of the phase imbalance of the analog quadrature modulator following the DAC. If the quadrature 15 5 modulator has a phase imbalance, the unwanted sideband appears with significant energy. Tuning the quadrature phase adjust value can optimize image rejection in single 10 10 sideband radios. Ordinarily, the I and Q channels have an angle of precisely 90° 5 15 between them. The quadrature phase adjustment is used to change the angle between the I and Q channels. When I Phase Adj, Bits[9:0] (Register 0x28 and Register 0x29), are set to 0 20 0x0000 0x4000 0x8000 0xC000 0xFFFF 1000000000b, the I DAC output moves approximately 1.75° DAC OFFSET VALUE away from the Q DAC output, creating an angle of 91.75° Figure 72. DAC Output Currents vs. DC Offset Value between the channels. When I Phase Adj, Bits[9:0] (Register 0x28 and Register 0x29), are set to 0111111111b, the I DAC output DIGITAL GAIN CONTROL moves approximately 1.75° toward the Q DAC output, creating The last block in each datapath is an 8-bit scalar (Register 0x50 an angle of 88.25° between the channels. and Register 0x51) that can be used for digital gain control. The Q Phase Adj, Bits[9:0] (Register 2A and Register 2B), work in a IGain Control, Bits[7:0] (Register 0x50), and QGain control, similar fashion. When Q Phase Adj, Bits[9:0] (Register 2A and Bits[7:0] (Register 0x51), values directly scale the samples written to 1 Register 2B), are set to 1000000000b, the Q DAC output moves the IDAC and QDAC, respectively. The bit weighting is MSB = 2 -6 approximately 1.75° away from the I DAC output, creating an and LSB = 2 , which yields a multiplier range of 0 to 3.984375. angle of 91.75° between the channels. When Q Phase Adj[9:0] The scale factor for each data path is calculated as is set to 0111111111b, the Q DAC output moves approximately IGain[7 : 0] QGain[7 : 0] 1.75° toward the I DAC output, creating an angle of 88.25° ScaleFactor= or 64 64 between the channels. Take care not to overrange the DAC when using a scale factor greater than 1. Rev. B | Page 55 of 72 I (mA) OUTxP I (mA) OUTxN 08910-131 AD9148 Data Sheet CLOCK GENERATION DRIVING THE CLK_x AND REFCLK_x INPUTS DAC INPUT CLOCK CONFIGURATIONS The REFCLK_x and CLK_x differential inputs share similar The AD9148 DAC sample clock (DACCLK) can be sourced clock receiver input circuitry. Figure 1 shows a simplified circuit directly or by clock multiplying. Clock multiplying employs diagram of the input, along with a recommended drive circuit. the on-chip, phased-locked loop (PLL) that accepts a reference The on-chip clock receiver has a differential input impedance of clock (REFCLK_x) operating at a submultiple of the desired about 10 kΩ. It is self-biased to a common-mode voltage of about DACCLK rate, most commonly the data input frequency. 1.25 V. The recommended circuit for driving the input is a pair The PLL then multiplies the reference clock up to the desired of ac coupling capacitors and a differential 100 Ω termination. DACCLK frequency, which can then be used to generate all the internal clocks required by the DAC. The clock multiplier provides The minimum input drive level to either of the clock inputs is a high quality clock that meets the performance requirements of 100 mV ppd. The optimal performance is achieved when the clock most applications. Using the on-chip clock multiplier removes input signal is between 500 mV ppd and 1.6 V ppd. Whether using the burden of generating and distributing the high speed DACCLK. the on-chip clock multiplier or sourcing the DACCLK directly, it is necessary that the input clock signal to the device have low The second mode bypasses the clock multiplier circuitry and allows jitter and fast edge rates to optimize the DAC noise performance. DACCLK to be sourced directly through the CLK_x pins. This mode enables the user to source a very high quality clock directly DIRECT CLOCKING to the DAC core. Sourcing the DACCLK directly through the When a high quality, sample rate clock is connected to the AD9148, CLK_x pins may be necessary in demanding applications that it provides the lowest noise spectral density at the DAC outputs. require the lowest possible DAC output noise, particularly at To select the differential CLK inputs as the source for the DAC higher output frequencies. sampling clock, set the PLL enable bit to 0 (Register 0x0A, Bit 7). Setting this bit to 0 powers down the internal PLL clock multiplier and selects the input from the CLK_x pins as the source for the internal DACCLK. The device also has duty-cycle correction circuitry and differential input level correction circuitry. Enabling these circuits may provide improved performance in some cases. The control bits for these functions can be found in Register 0x08. DAC DAC CLK_P/ CLK_P/ 1000pF 1000pF REFCLK_P REFCLK_P 200Ω 5kΩ 5kΩ LVPECL LVDS 100Ω 100Ω DRIVER DRIVER 1.25V 1.25V 5kΩ 5kΩ 200Ω CLK_N/ CLK_N/ 1000pF 1000pF REFCLK_N REFCLK_N Figure 73. Clock Receiver Circuitry and Recommended Drive Circuitry using LVPECL (Left) and LVDS (Right) Rev. B | Page 56 of 72 08910-071 Data Sheet AD9148 0x06[7:6] 0x0E[3:0] PLL LOCK ADC PLL CONTROL PLL LOCK LOST VOLTAGE REFCLK_P/REFCLK_N PHASE LOOP VCO (PIN B9 AND PIN A9) DETECTION FILTER ÷N1 ÷N0 0x0D[1:0] 0x0D[3:2] N1 N0 0x0D[7:6] ÷N2 N2 DACCLK CLK_P/CLK_N (PIN B6 AND PIN A6) PC_CLK 0x0A[7] PLL ENABLE Figure 74. PLL Clock Multiplication Circuit Table 25. PLL Settings Address PLL SPI Control Register Bit Optimal Setting PLL Loop Bandwidth 0x0C [7:5] 110 PLL Control 1 Register 0x0C [4:0] 01001 PLL Cross Control Enable 0x0D [4] 1 Therefore, it is required that the optimal PLL band select value CLOCK MULTIPLICATION be determined for each individual device. The on-chip PLL clock multiplier circuit can be used to generate 0 the DAC sample rate clock from a lower frequency reference clock. 4 When the PLL clock multiplier is enabled (Register 0x0A[7] = 1), 8 12 the clock multiplication circuit generates the DAC sample clock 16 from the lower rate REFCLK input. The functional diagram of 20 the clock multiplier is shown in Figure 74. 24 28 The clock multiplication circuit operates such that the VCO 32 outputs a frequency, fVCO, equal to the REFCLK input signal 36 40 frequency multiplied by N0 × N1. 44 48 f = f × (N0 × N1) VCO REFCLK 52 The DAC sample clock frequency, f , is equal to DACCLK 56 60 f = f × N1 DACCLK REFCLK 1000 1200 1400 1600 1800 2000 2200 The output frequency of the VCO must be chosen to keep fVCO in VCO FREQUENCY (MHz) the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency Figure 75. PLL Lock Range Overtemperature for a Typical Device of the reference clock and the values of N1 and N0 must be chosen Automatic VCO Band Select so that the desired DACCLK frequency can be synthesized and The device has an automatic VCO band select feature on chip; the VCO output frequency is in the correct range. using this feature is a simple and reliable method for configuring PLL Bias Settings the VCO frequency band. To use the automatic VCO band select There are four bias settings for the PLL circuitry that should be feature, enable the PLL by writing 0xC0 to Register 0x0A and programmed to their nominal values. The PLL values shown in enable the auto band select mode by writing 0x80 to Register 0x0A. Table 25 are the recommended settings for these parameters. When this value is written, the device executes an automated Configuring the VCO Tuning Band routine that determines the optimal VCO band setting for the device. The setting selected by the device ensures that the PLL The PLL VCO has a valid operating range from approximately remains locked over the full −40°C to +85°C operating temperature 1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands. range of the device without further adjustment. (The PLL remains For any desired VCO output frequency, there may be several locked over the full temperature range even if the temperature valid PLL band select values. The frequency bands of a typical during initialization is at one of the temperature extremes.) device are shown in Figure 75. Device-to-device variations and operating temperature affect the actual band frequency range. Rev. B | Page 57 of 72 PLL BAND 08910-072 08910-073 AD9148 Data Sheet Manual VCO Band Select Table 26. VCO Control Voltage Range Indications VCO Control Voltage Indication The device also has a manual band select mode that allows the 1111 Move to a higher VCO band. user to select the VCO tuning band. When in manual mode 1110 (enabled by setting Bit 6, Register 0x0A to 1), the VCO band is 1101 VCO is operating in the higher end of set directly with the value written to the manual VCO band bit frequency band. enabled (Bits[5:0], Register 0x0A). To properly select the VCO 1100 band, complete the following sequence: 1011 1. Put the device in manual band select mode. 1010 2. Sweep the VCO band over a range of bands that results in 1001 VCO is operating with an optimal region the PLL being locked. of the frequency band. 3. Verify that the PLL is locked and read the VCO control 1000 voltage for each band. 0111 4. Select the band that results in the control voltage being 0110 closest to the center of the range (that is, 1000). See Table 26 0101 VCO is operating in the lower end of for more details. frequency band. 0100 The resulting VCO band should be the optimal setting for the 0011 device. This band should be written to the manual VCO band 0010 register value. 0001 Move to a lower VCO band. If desired, an indication of where the VCO is within the operating 0000 frequency band can be determined by querying the VCO control voltage. Table 26 shows how to interpret the VCO control voltage value. Rev. B | Page 58 of 72 Data Sheet AD9148 ANALOG OUTPUTS For nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC TRANSMIT DAC OPERATION gain (512), the full-scale current of the DAC is typically 20.16 mA. Figure 77 shows a simplified block diagram of one pair of the The DAC full-scale current can be adjusted from 8.66 mA to transmit path DACs. The DAC core consists of a current source 31.66 mA by setting the DAC gain parameter setting as shown array, switch core, digital control logic, and full-scale output current in Figure 76. control. The DAC full-scale output current (IOUTFS) is nominally 35 20 mA. The output currents from the IOUTx_P and IOUTx_N pins are complementary, meaning that the sum of the two currents 30 always equals the full-scale current of the DAC. The digital input 25 code to the DAC determines the effective differential current delivered to the load. 20 The DAC has a 1.2 V band gap reference with an output impedance 15 of 5 kΩ. The reference output voltage appears on the VREF pin. When using the internal reference, the VREF pin should be 10 decoupled to AVSS with a 0.1 µF capacitor. The internal reference should only be used for external circuits that draw dc currents 5 of 2 µA or less. For dynamic loads or static loads greater than 0 2 µA, the VREF pin should be buffered. If desired, an external 0 200 400 600 800 1000 reference (between 1.10 V to 1.30 V) can be applied to the DAC GAIN CODE VREF pin. Figure 76. DAC Full-Scale Current vs. DAC Gain Code A 10 kΩ external resistor, R , must be connected from SET Transmit DAC Transfer Function the RESET pin to AVSS. This resistor, along with the reference The output currents from the IOUTx_P and IOUTx_N pins are control amplifier, sets up the correct internal bias currents for complementary, meaning that the sum of the two currents always the DAC. Because the full-scale current is inversely proportional equals the full-scale current of the DAC. The digital input code to this resistor, the tolerance of R is reflected in the full-scale SET to the DAC determines the effective differential current delivered output amplitude. to the load. IOUTx_P provides the maximum output current The full-scale current can be calculated by when all bits are high. The output currents vs. DACCODE for the DAC outputs are expressed as V  3    REF I = ×72+ × DAC gain    OUTFS R 16   DACCODE     SET I = × I (1) OUT _ P OUTFS N   2   where DAC gain is set individually for the I and Q DACs in I = I – I (2) Register 0x30, Register 0x31, Register 0x34, and Register 0x35, OUT_N OUTFS OUT_P respectively. N where DACCODE = 0 to 2 − 1. 1.2V I DAC GAIN IOUT1_P/IOUT3_P I DAC 5kΩ IOUT1_N/IOUT3_N VREF CURRENT 0.1µF SCALING I120 IOUT2_N/IOUT4_N Q DAC RSET 10kΩ IOUT2_P/IOUT4_P Q DAC GAIN Figure 77. Simplified Block Diagram of the DAC Core Rev. B | Page 59 of 72 I (mA) OUTFS 08910-075 08910-074 AD9148 Data Sheet Transmit DAC Output Configurations Transmit DAC Linear Output Signal Swing The optimum noise and distortion performance of the AD9148 The DAC outputs have a linear output compliance voltage range is realized when it is configured for differential operation. The of ±1 V that must be adhered to achieve optimum performance. common-mode error sources of the DAC outputs are reduced The linear output signal swing is dependent on the full-scale output significantly by the common-mode rejection of a transformer or current, IOUTFS, and the common-mode level of the output. differential amplifier. These common-mode error sources include AUXILIARY DAC OPERATION even-order distortion products and noise. The enhancement in The AD9148 has four 10-bit auxiliary DACs (AUX1, AUX2, AUX3, distortion performance becomes more significant as the frequency and AUX4). The full-scale output current on these DACs is derived content of the reconstructed waveform increases and/or its from the 1.2 V band gap reference and external resistor. The gain amplitude increases. This is due to the first-order cancellation scale from the reference amplifier current, I , to the auxiliary REF of various dynamic common-mode distortion mechanisms, DAC reference current is 16.67 with the auxiliary DAC gain set digital feedthrough, and noise. to full-scale. This gives a full-scale current of approximately 2 mA IOUT1_P/IOUT3_P V + IP for each auxiliary DAC. R O The magnitude of the AUX1 DAC current is controlled via V OUTI Bits[1:0], Register 0x33 (MSBs) and Bits[7:0], Register 0x32 (LSBs) R O V – IN when DAC SPI select = 0 (Bit 4, Register 0x00). The magnitude IOUT1_N/IOUT3_N of the AUX2 DAC current is controlled via Bits[1:0], Register 0x37 (MSBs) and Bits[7:0], Register 0x36 (LSBs) when DAC SPI select = 0 (Bit 4, Register 0x00). Likewise, the magnitudes of AUX3 DAC V + IOUT2_N/IOUT4_N QP current and AUX4 DAC current are controlled via Register 0x33 to R O Register 0x32 and Register 0x37 to Register 0x36, respectively V OUTQ when DAC SPI Select = 1 (Register 0x00, Bit[4]). R O V – QN The auxiliary DAC structure is shown in Figure 80. There are IOUT2_P/IOUT4_P two output signals on each auxiliary DAC. One signal is P, and Figure 78. Basic Transmit DAC Output Circuit the other is N. The auxiliary DAC outputs are not differential. Figure 78 shows the most basic DAC output circuitry. A pair Only one side of the auxiliary DAC (P or N) is active at one of resistors, R , are used to convert each of the complementary O time. The inactive side goes into a high impedance state (100 kΩ). output currents to a differential voltage output, V . Because OUT Control of the P side and N side for the auxiliary DACs is via the current outputs of the DAC are high impedance, the differential Bit 7, Register 0x33 and Bit 7, Register 0x37 (DAC SPI select is 0 driving point impedance of the DAC outputs, ROUT, is equal to to control AUX1 and AUX2, and DAC SPI select is 1 to control 2 × RO. Figure 79 illustrates the output voltage waveforms. AUX3 and AUX4). V V P N V B V PEAK 0mA TO 2mA 0mA TO 2mA (SOURCE) (SINK) V OM AUXDAC[9:0] AUXDAC TIME DIRECTION V P (SOURCE/SINK) AUXDAC SIGN (P/N) Figure 79. Voltage Output Waveforms AUX_P AUX_N The common-mode signal voltage, VCM, is calculated by Figure 80. Auxiliary DAC Structure I FS V   R CM O 2 The peak output voltage, VPEAK, is calculated by VPEAK = IFS × RO With this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage. Rev. B | Page 60 of 72 08910-077 08910-076 08910-078 Data Sheet AD9148 In addition, the P or N output can act as a current source or a Baseband Filter Implementation current sink. When sourcing current, the output compliance Most applications require a baseband anti-imaging filter between voltage is 0 V to 1.6 V. When sinking current, the output compliance the DAC and modulator to filter out Nyquist images and broadband voltage is 0.8 V to 1.6 V. The auxiliary DAC current direction is DAC noise. The filter can be inserted between the I-to-V resistors programmable via Bit 6, Register 0x33 and Bit 6, Register 0x37 at the DAC output and the signal level setting resistor across the (DAC SPI select is 0 to control AUX1 and AUX2, and DAC SPI modulator input. Doing this establishes the input and output select is 1 to control AUX3 and AUX4). The choice of sinking or impedances for the filter. sourcing should be made at circuit design time. There is no Figure 83 shows a fifth-order low-pass filter. A common-mode advantage to switching between sourcing and sinking current choke is used between the I-to-V resistors and the remainder after the circuit is in place. of the filter. This removes the common-mode signal produced These auxiliary DACs can be used for local oscillator (LO) by the DAC and prevents the common-mode signal from being cancellation when the DAC output is followed by a quadrature converted to a differential signal, which would appear as unwanted modulator. More information and example application circuits spurious signals in the output spectrum. The common-mode are given in the Interfacing to Modulators section. choke or balun may not be needed if the layout between the DAC and IQ modulator is optimized and balanced. Splitting INTERFACING TO MODULATORS the second filter capacitor into two and grounding the center The AD9148 interfaces to the ADL537x family with a minimal point creates a common-mode low-pass filter, providing additional number of components. An example of the recommended common-mode rejection of high frequency signals. A purely interface circuitry is shown in Figure 81. differential filter passes common-mode signals. AD9148 ADL537x Driving the ADL5375-15 with the AD9148 IOUT1_P IBBP The ADL5375-15 requires a 1500 mV dc bias and therefore RBIP 50Ω RLI requires a slightly more complex interface than most other 100Ω RBIN 50Ω Analog Devices, Inc., modulators. It is necessary to level shift IOUT1_N IBBN the DAC output from a 500 mV dc bias to the 1500 mV dc bias that the ADL5375-15 requires. Level shifting can be achieved IOUT2_N QBBN with a purely passive network, as shown in Figure 82. In this RBQN 50Ω RLQ network, the dc bias of the DAC remains at 500 mV, while the 100Ω RBQP 50Ω input to the ADL5375-15 is 1500 mV. Note that this passive IOUT2_P QBBP level shifting network introduces approximately 2 dB of loss in the ac signal. Figure 81. Typical Interface Circuitry Between the AD9148 and ADL537x Family of Modulators AD9148 ADL5375-15 RSIN 1kΩ The baseband inputs of the ADL537x family require a dc bias IOUT1_P IBBP RBIP RLIP of 500 mV. The nominal midscale output current on each output 45.3Ω 3480Ω 5V of the DAC is 10 mA (1/2 the full-scale current). Therefore, a RBIN RLIN RSIP 45.3Ω 3480Ω 1kΩ single 50 Ω resistor to ground from each of the DAC outputs IOUT1_N IBBN results in the desired 500 mV dc common-mode bias for the RSQN 1kΩ inputs to the ADL537x. The signal level can be reduced by the IOUT2_N QBBN RBQN RLQN addition of the load resistor in parallel with the modulator inputs 45.3Ω 3480Ω 5V (RLI, RLQ). The peak-to-peak voltage swing of the transmitted RBQP RLQP RSQP 45.3Ω 3480Ω 1kΩ signal is IOUT2_P QBBP [2× R × R] B L V = I × SIGNAL FS Figure 82. Passive Level Shifting Network for Biasing [2× R + R] B L the ADL5375-15 from the AD9148 50Ω 22pF MABACT0043 3pF (OPTIONAL) 33nH 56nH IDAC 2pF 6pF 100Ω ADL537x OR QDAC 33nH 56nH 50Ω 22pF 3pF Figure 83. DAC Modulator Interface with Fifth-Order, Low Pass Filter Rev. B | Page 61 of 72 08910-079 08910-080 08910-081 AD9148 Data Sheet Reducing LO Leakage and Unwanted Sidebands Good sideband suppression requires both gain and phase matching of the I and Q signals. The phase adjust (Register 0x28 to Analog Devices modulators can introduce unwanted signals at Register 0x2B) and gain control (Register 0x50 and Register 0x51) the LO frequency due to dc offset voltages in the I and Q baseband registers can be used to calibrate I and Q transmit paths to optimize inputs as well as feedthrough paths from the LO input to the the sideband suppression. As an alternative to the digital gain output. The LO feedthrough can be nulled by applying the correct scaling, the DAC full-scale output current (Register 0x30, dc offset voltages at the DAC output. This can be done either Register 0x31, Register 0x34, and Register 0x35) can also be by using the auxiliary DACs (Register 0x32, Register 0x33, adjusted to calibrate the I and Q transmit paths; however, changing Register 0x36, and Register 0x37) or by using the digital dc the DAC full-scale output current affects the common-mode offset adjustments (Register 0x2C to Register 0x2F). Using the voltage level. auxiliary DACs has the advantage that none of the main DAC dynamic range is used for performing the dc offset adjustment. For more information on correcting imperfections in IQ The disadvantage is that the common-mode level of the output modulators to improve RF signal fidelity, refer to the AN-1039 signal changes as a function of the auxiliary DAC current. The Application Note. opposite is true when the digital offset adjustment is used. Rev. B | Page 62 of 72 Data Sheet AD9148 DEVICE POWER DISSIPATION 3.25 The AD9148 has four supply rails: AVDD33, IOVDD, DVDD18, 3.00 1× and CVDD18. 2× 2.75 4× The AVDD33 supply powers the DAC core circuitry. The power 2.50 8× dissipation of the AVDD33 supply rail is independent of the digital 2.25 2.00 operating mode and sample rate. The current drawn from the 1.75 AVDD33 supply rail is typically 98 mA (320 mW) when the 1.50 full-scale current of the four main DACs (DAC 1, DAC 2, DAC 3, 1.25 and DAC 4) is set to the nominal value of 20 mA. Changing the 1.00 full-scale current directly impacts the supply current drawn from 0.75 the AVDD33 rail. For example, if the full-scale current of the 0.50 four main DACs is changed to 10 mA, the AVDD33 supply 0.25 current drops by 40 mA to 58 mA. 0 The IOVDD voltage supplies the serial port I/O pins (SCLK, f (MSPS) DATA RESET SDIO, SDO, CSB, TCK, TDI, TDO, TMS), the pin, and Figure 85. Total Power Dissipation vs. fDATA with Fine Modulation, PLL, and IRQ the pin. The voltage applied to the IOVDD pin can range Inverse Sinc Filter Disabled from 1.8 V to 3.3 V. The current drawn by the IOVDD supply 2.00 pin is typically 1 mA. 1× 1.75 2× The DVDD18 supply powers all of the digital signal processing 4× blocks of the device. The power consumption from this supply 1.50 8× is a function of which digital blocks are enabled and the frequency 1.25 at which the device is operating. 1.00 The CVDD18 supply powers the clock receiver and clock distribution circuitry. The power consumption from this 0.75 supply varies directly with the operating frequency of the 0.50 device. CVDD18 also powers the PLL. The power dissipation of the PLL is typically 80 mW. 0.25 Figure 84 to Figure 89 detail the power dissipation of the AD9148 0 under a variety of operating conditions. All of the graphs are taken with data being supplied to all four DACs. The power f (MSPS) DATA consumption of the device does not vary significantly with Figure 86. DVDD18 Power Dissipation vs. fDATA with Coarse Modulation, PLL, changes in the coarse modulation mode selected or analog and Inverse Sinc Filter Disabled output frequency. Graphs of the total power dissipation are 2.50 shown along with the power dissipation of the DVDD18 and 1× 2.25 2× CVDD18 supplies. 2.00 4× 2.75 8× 1.75 2.50 1× 2× 1.50 2.25 4× 8× 1.25 2.00 1.00 1.75 0.75 1.50 1.25 0.50 1.00 0.25 0.75 0 0.50 f (MSPS) 0.25 DATA 0 Figure 87. DVDD18 Power Dissipation vs. fDATA with Fine Modulation, PLL, and Inverse Sinc Filter Disabled f (MSPS) DATA Figure 84. Total Power Dissipation vs. fDATA with Coarse Modulation, PLL, and Inverse Sinc Filter Disabled Rev. B | Page 63 of 72 POWER DISSIPATION (W) 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 08910-082 POWER DISSIPATION (W) POWER DISSIPATION (W) POWER DISSIPATION (W) 0 0 0 20 20 20 40 40 40 60 60 60 80 80 80 100 100 100 120 120 120 140 140 140 160 160 160 180 180 180 200 200 200 220 220 220 240 240 240 260 260 260 280 280 280 300 300 300 08910-085 08910-084 08910-083 AD9148 Data Sheet 0.35 0.25 0.23 0.30 0.20 0.25 0.18 0.15 0.20 0.13 0.15 0.10 0.08 0.10 0.05 0.05 0.03 0 0 0 100 200 300 400 500 600 700 800 900 1000 f (MSPS) DAC f (MSPS) DATA Figure 88. CVDD18 Power Dissipation vs. fDAC, PLL Disabled Figure 89. DVDD18 Power Dissipation vs. f Due to Inverse Sinc Filter DATA Rev. B | Page 64 of 72 POWER (W) 08910-086 POWER (W) 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 08910-087 Data Sheet AD9148 TEMPERATURE SENSOR The AD9148 has a diode-based temperature sensor for measuring Estimates of the ambient temperature can be made if the power the temperature of the die. The temperature reading is accessed dissipation of the device is known. For example, if the device power by Register 0x5E and Register 0x5F. The temperature of the die dissipation is 800 mW and the measured die temperature is 50°C, can be calculated as then the ambient temperature can be calculated as T = T – P × T = 50 – 0.8 × 18 = 35.6°C (DieTemp[15 : 0]−13,700) A DIE D JA T = DIE 130 where: T is the ambient temperature in degrees Celsius. A where T is the die temperature in degrees Celsius. The DIE T is the thermal resistance from junction to ambient of the JA temperature accuracy is ±5°C typical over the +85°C to AD9148 as shown in Table 7. −35°C range. A typical plot of the AD9148 die temperature vs. die temperature code readback is shown in Figure 90. To use the temperature sensor, it must be enabled by setting 27,500 Bit 0, Register 0x5C to 0. Before the temperature sensor data can be read back, it must be latched by toggling Bit 1, Register 0x5C MEASURED DIE TEMPERATURE 25,000 CALCULATED DIE TEMPERATURE from 0 to 1. In addition, to get accurate readings, the die temperature +5°C 22,500 control register (Register 0x5D) should be set to 0x0A. –5°C 20,000 17,500 15,000 12,500 10,000 7,500 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) Figure 90. Die Temperature vs. Die Temperature Code Readback Rev. B | Page 65 of 72 DIE CODE READBACK 08910-189 AD9148 Data Sheet INTERRUPT REQUEST OPERATION The AD9148 provides an interrupt request output signal event_flag_source signal, and the event flag has no effect on the (Pin H4, IRQ) that can be used to notify an external host external IRQ. processor of significant device events. Upon assertion of the The latched version of an event flag (the interupt_source signal) interrupt, the device should be queried to determine the precise can be cleared in two ways. The recommended way is by writing 1 IRQ event that occurred. The pin is an open-drain, active low to the corresponding event flag bit. A hardware or software reset output. also clears the interupt_source. IRQ Pull the pin high external to the device. This pin may be INTERRUPT SERVICE ROUTINE tied to the interrupt pins of other devices with open-drain outputs Interrupt request management starts by selecting the set of event to wired-OR these pins together. flags that require host intervention or monitoring. Those events Ten different event flags provide visibility into the device. These that require host action should be enabled so that the host is 10 flags are located in the two event flag registers (Register 0x06 notified when they occur. For events requiring host intervention, and Register 0x07). The behavior of each of the event flags is IRQ upon activation, run the following routine to clear an independently selected in the interrupt enable registers interrupt request: (Register 0x04 and Register 0x05). When the flag interrupt enable is active, the event flag latches and triggers an external • Read the status of the event flag bits that are being interrupt. When the flag interrupt is disabled, the event flag monitored. simply monitors the source signal, and the external IRQ • Set the interupt enable bit low so that the unlatched remains inactive. event_flag_source can be monitored directly. • Perform any actions that may be required to quiet the Figure 91 shows the IRQ-related circuitry. Figure 91 shows how the event_source_flag. In many cases, no specific actions may IRQ event flag signals propagate to the output. The interupt_enable be required. signal represents one bit from the interrupt enable register. The • Read the event flag to verify that the actions taken have event_flag signal represents one bit from the event flag register. quieted the event_flag_source. The event_flag_source signal represents one of the device signals • Clear the interrupt by writing 1 to the event flag bit. that can be monitored such as the PLL_locked signal from the • Set the interrupt enable bits of the events to be monitored. PLL phase detector or the FIFO Warning 1 signal from the FIFO controller. Noted that some of the event_flag_source signals are latched signals. These are cleared by writing to the corresponding event When an interrupt enable bit is set high, the corresponding event flag bit. Details of each of the event flags can be found in Table 12. flag bit reflects a positively tripped (that is, latched on the rising edge of the event_flag_source version of the event_flag_source signal. IRQ This signal also asserts the external . When an interrupt enable bit is set low, the event flag bit reflects the current status of the 0 EVENT_FLAG 1 IRQ INTERRUPT SOURCE INTERRUPT_ENABLE OTHER INTERRUPT EVENT_FLAG_SOURCE SOURCES WRITE_1_TO_EVENT_FLAG DEVICE_RESET IRQ Figure 91. Simplified Schematic of Circuitry Rev. B | Page 66 of 72 08910-088 Data Sheet AD9148 INTERFACE TIMING VALIDATION The AD9148 provides on-chip sample error detection (SED) SED EXAMPLE circuitry that simplifies verification of the input data interface. Normal Operation The SED compares the input data samples captured at the digital The following example illustrates the SED configuration for input pins with a set of comparison values. The comparison values continuously monitoring the input data and assertion of an IRQ are loaded into registers through the SPI port. Differences between when a single error is detected. the captured values and the comparison values are detected and 1. Write to the following registers to enable the SED and load stored. Options are available for customizing SED test sequencing the comparison values: and error handling. Register 0x40 → 0x80 Register 0x00[4] → 0 (to configure Port A SED) SED OPERATION Register 0x38 → S0[7:0] The SED circuitry operates on two data sets, one for each data Register 0x39 → S0[15:8] port, each made up of four 16-bit input words, denoted as S0, Register 0x3A → S1[7:0] S1, S2, and S3. To properly align the input samples, the first Register 0x3B → S1[15:8] data-word (that is, S0) is indicated by asserting FRAME for at Register 0x3C → S2[7:0] least one complete input sample. Register 0x3D → S2[15:8] Figure 92 shows the input timing of the interface for each port. Register 0x3E → S3[7:0] The FRAME signal can be issued once at the start of the data Register 0x3F → S3[15:8] transmission, or it can be asserted repeatedly at intervals coinciding Register 0x00[4] → 1 (to configure Port B SED) with the S0 and S1 data-words. Register 0x38 → S0[7:0] FRAMEA/ Register 0x39 → S0[15:8] FRAMEB Register 0x3A → S1[7:0] A[15:0]/ Register 0x3B → S1[15:8] S0 S1 S2 S3 S0 S1 B[15:0] Register 0x3C → S2[7:0] Figure 92. Timing Diagram of Extended FRAME Signal Required to Align Register 0x3D → S2[15:8] Input Data for SED Register 0x3E → S3[7:0] The SED has five flag bits (Register 0x40, Bit 0, Bit 1, Bit 2, Bit 5 Register 0x3F → S3[15:8] and Bit 6) that indicate the results of the input sample comparisons. Comparison values can be chosen arbitrarily; however, The sample error detected bit (Bit 5, Register 0x40 for Port A choosing values that require frequent bit toggling provides and Bit 6, Register 0x40 for Port B) is set when an error is detected the most robust test. and remains set until cleared. The SED also provides registers IRQ 2. Enable the SED error detect flag to assert the pin. that indicate which input data bits experienced errors (Register 0x41 Register 0x05 → 0x04 through Register 0x44). These bits are latched and indicate the 3. Begin transmitting the input data pattern. accumulated errors detected until cleared. IRQ If is asserted, read Register 0x40 and Register 0x41 through The autoclear mode has two effects: it activates the compare fail Register 0x44 with Bit 4, Register 0x00 = 0 for Port A and with bits and the compare pass bit (Register 0x40, Bit 2, Bit 1, and Bit 0) Bit 4, Register 0x00 = 1 for Port B, to verify that a SED error was and changes the behavior of Register 0x41 through Register 0x44. detected, and determine which input bits were in error. The bits in The compare pass bit sets if the last comparison indicated that Register 0x41 through Register 0x44 are latched; therefore, the bits the sample was error free. The compare fail bit sets if an error indicate any errors that occurred on those bits throughout the test is detected. The compare fail bit is cleared automatically by the and not just the errors that caused the error detected flag to be set. reception of eight consecutive error-free comparisons. When Note that the FRAME signal is not required during normal autoclear mode is enabled (Bit 3, Register 0x40), Register 0x41 operation when the device is configured for dual-port mode. through Register 0x44 accumulate errors as previously described To enable the alignment of the S0 sample as previously described but reset to all 0s after eight consecutive error-free sample requires the use of both the FRAMEA and FRAMEB signals. comparisons are made. The timing diagrams for single-port and byte modes are the same as The sample error, compare pass, and compare fail flags can be during normal operation and are shown in Figure 47 and Figure 48, configured to trigger an IRQ when active, if desired. This is respectively. For single-port and byte mode, only FRAMEA and done by enabling the appropriate bits in the event flag register the IRQs for Port A should be used. The FRAMEA rising edge (Register 0x07). should always be aligned with the first sample of the data trans- mission. There should not be another rising edge until four complete words of data are received. This means four data samples for dual- port mode and eight data samples for single-port and byte modes. Rev. B | Page 67 of 72 08910-089 AD9148 Data Sheet EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9148, certain sequences START-UP SEQUENCE should be followed. An example start-up routine using the The power clock and register write sequencing for reliable device following device configuration is used for this example. start-up follows: • fDATA = 122.88 MSPS • Power up the device (no specific power supply sequence is • Interpolation = 4×, using HB1 = ’00’ and HB2 = ’000’ required) • Input data = baseband data • Apply a stable REFCLK input signal. • Dual port mode with 1 DCI • Apply a stable DCI input signal. • fOUT = 140 MHz • Issue a hardware reset (optional) • fREFCLK = 122.88 MHz • Configure device registers with the following write • PLL = enabled sequence: • Fine NCO = enabled 0x0C → 0xC9 • Inverse sinc filter = disabled 0x0D → 0xD9 • Synchronization = enabled 0x0A → 0xC0 0x0A → 0x80 DERIVED PLL SETTINGS 0x10 → 0x48 The following PLL settings can be derived from the device 0x14 → 0x40 configuration: 0x17 → 0x08 0x17 → 0x00 • f = f × Interpolation = 491.52 MHz DACCLK DATA 0x19 → 0x08 • f = 4 × f = 1966.08 MHz (1 GHz < f < 2 GHz) VCO DACCLK VCO 0x19 → 0x00 • N1 = f /f = 4 DACCLK REFCLK 0x1C → 0x40 • N0 = f /f = 4 VCO DACCLK 0x1D → 0x00 0x1E → 0x01 DERIVED NCO SETTINGS 0x54 → 0xAA The following NCO settings can be derived from the device 0x55 → 0xAA configuration: 0x56 → 0xEA • f = 140 MHz OUT 0x57 → 0x48 • f = f × Interpolation = 491.52 MHz DACCLK DATA 0x5A → 0x01 32 • FTW = 140/(491.52) × 2 = 0x48, EAAAAA 0x5A → 0x00 DEVICE VERIFICATION SEQUENCE The following device polling can be conducted to verify that the device is working properly: • Read 0x06, Expect Bit 7 = 0, Bit 6 = 1, Bit 5 = 0, Bit 4 = 1, Bit 2 = 1 • Read 0x12, Expect Bit 6 = 1 • Read 0x18, Expect 0x0F (0x07 is also normal) • Read 0x1A, Expect 0x0F (0x07 is also normal) Rev. B | Page 68 of 72 Data Sheet AD9148 OUTLINE DIMENSIONS 12.10 A1 BALL 12.00 SQ CORNER A1 BALL 11.90 14 13 12 11 10 9 8 764 5 312 CORNER A B C D E 10.40 F BSC SQ G H J 0.80 K BSC L M N P 0.80 TOP VIEW BOTTOM VIEW REF DETAIL A * 1.30 MAX 0.96 DETAIL A 0.70 0.35 NOM 0.30 MIN 0.50 COPLANARITY SEATING 0.45 0.12 PLANE 0.40 BALL DIAMETER * COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1 WITH EXCEPTION TO PACKAGE HEIGHT. Figure 93. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-196-7 Dimensions shown in millimeters Rev. B | Page 69 of 72 11-18-2011-B AD9148 Data Sheet 12.10 12.00 SQ A1 BALL A1 BALL 11.90 PAD CORNER PAD CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E 8.20 10.40 F REF SQ BSC SQ G H J 0.80 K 11.20 BSC L REF SQ M N P TOP VIEW BOTTOM VIEW 0.80 REF DETAIL A 1.50 1.09 1.32 0.99 1.17 DETAIL A 0.89 0.75 REF 0.38 0.33 0.28 0.24 REF 0.53 SEATING COPLANARITY PLANE 0.12 0.48 0.43 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192. Figure 94. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-1 Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9148BBCZ −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-7 AD9148BBCZRL −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-7 AD9148BBPZ −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-1 AD9148BBPZRL −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-1 AD9148-EBZ DAC Only Evaluation Board [BGA_ED] BP-196-1 AD9148-M5372-EBZ AD9148 + ADL5372 Evaluation Board [BGA_ED] BP-196-1 AD9148-M5375-EBZ AD9148 + ADL5375-0.5 Evaluation Board [BGA_ED] BP-196-1 1 Z = RoHS Compliant Part. Rev. B | Page 70 of 72 02-07-2012-A Data Sheet AD9148 NOTES Rev. B | Page 71 of 72 AD9148 Data Sheet NOTES ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08910-0-1/12(B) Rev. B | Page 72 of 72