ANALOG DEVICES AD9125

Dual, 16-Bit, 1000 MSPS, TxDAC+ Digital-to-Analog Converter AD9125 FEATURES GENERAL DESCRIPTION Flexible CMOS interface allows dual-word, word, or byte load The AD9125 is a dual, 16-bit, high dynamic range TxDAC+® Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF digital-to-analog converter (DAC) that provides a sample rate of Analog output: adjustable 8.7 mA to 31.7 mA, R = 25 Ω to 50 Ω L 1000 MSPS, permitting a multicarrier generation up to the Nyquist Novel 2×/4×/8× interpolator/complex modulator allows frequency. It includes features optimized for direct conversion carrier placement anywhere in the DAC bandwidth transmit applications, including complex digital modulation, Gain and phase adjustment for sideband suppression and gain and offset compensation. The DAC outputs are optimized Multichip synchronization interface to interface seamlessly with analog quadrature modulators, such High performance, low noise PLL clock multiplier as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire Digital inverse sinc filter serial port interface allows programming/readback of many inter- Low power: 900 mW at 500 MSPS, full operating conditions nal parameters. Full-scale output current can be programmed 72-lead, exposed paddle LFCSP over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a 72-lead LFCSP. APPLICATIONS PRODUCT HIGHLIGHTS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE 1. Ultralow noise and intermodulation distortion (IMD) Digital high or low IF synthesis enable high quality synthesis of wideband signals from Transmit diversity baseband to high intermediate frequencies. Wideband communications: LMDS/MMDS, point-to-point 2. A proprietary DAC output switching technique enhances Cable modem termination systems dynamic performance. 3. The current outputs are easily configured for various single-ended or differential circuit topologies. 4. The flexible CMOS digital interface allows the standard 32-wire bus to be reduced to a 16-wire bus. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF f LO – f DC IF IF I DAC 2 2/4 SIN DIGITAL ANTIALIASING BASEBAND PA AQM FILTER PROCESSOR COS 2 2/4 Q DAC LO NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09016-001 AD9125 TABLE OF CONTENTS Features .............................................................................................. 1  NCO Modulation ....................................................................... 35  Applications ....................................................................................... 1  Datapath Configuration ............................................................ 35  General Description ......................................................................... 1  Determining Interpolation Filter Modes ................................ 36  Product Highlights ........................................................................... 1  Datapath Configuration Example ............................................ 37  Typical Signal Chain ......................................................................... 1  Data Rates vs. Interpolation Modes ......................................... 38  Revision History ............................................................................... 2  Coarse Modulation Mixing Sequences .................................... 38  Functional Block Diagram .............................................................. 3  Quadrature Phase Correction ................................................... 39  Specif ica t ions ..................................................................................... 4  DC Offset Correction ................................................................ 39  DC Specifications ......................................................................... 4  Inverse Sinc Filter ....................................................................... 39  Digital Specifications ................................................................... 5  DAC Input Clock Configurations ................................................ 40  Latency and Power-Up Timing Specifications ......................... 5  DAC Input Clock Configurations ............................................ 40  AC Specifications .......................................................................... 6  Analog Outputs............................................................................... 42  Absolute Maximum Ratings ............................................................ 7  Transmit DAC Operation .......................................................... 42  Thermal Resistance ...................................................................... 7  Auxiliary DAC Operation ......................................................... 43  ESD Caution .................................................................................. 7  Baseband Filter Implementation .............................................. 44  Pin Configuration and Function Descriptions ............................. 8  Driving the ADL5375-15 .......................................................... 44  Typical Performance Characteristics ........................................... 10  Reducing LO Leakage and Unwanted Sidebands .................. 44  Terminology .................................................................................... 16  Device Power Dissipation .............................................................. 45  Theory of Operation ...................................................................... 17  Temperature Sensor ................................................................... 46  Serial Port Operation ................................................................. 17  Multichip Synchronization ............................................................ 47  Data Format ................................................................................ 17  Synchronization with Clock Multiplication ............................... 47  Serial Port Pin Descriptions ...................................................... 17  Synchronization with Direct Clocking .................................... 49  Serial Port Options ..................................................................... 18  Data Rate Mode Synchronization ............................................ 49  Device Configuration Register Map ............................................ 19  FIFO Rate Mode Synchronization ........................................... 50  Device Configuration Register Descriptions .......................... 21  Additional Synchronization Features ...................................... 51  CMOS Input Data Ports ................................................................ 29  Interrupt Request Operation ........................................................ 52  Dual-Word Mode ....................................................................... 29  Interrupt Service Routine .......................................................... 52  Word Mode ................................................................................. 29  Interface Timing Validation .......................................................... 53  Byte Mode .................................................................................... 29  SED Operation ............................................................................ 53  Interface Timing ......................................................................... 30  SED Example .............................................................................. 53  FIFO Operation .......................................................................... 30  Example Start-Up Routine ........................................................ 54  Digital Datapath .............................................................................. 32  Outline Dimensions ....................................................................... 55  Premodulation ............................................................................ 32  Ordering Guide .......................................................................... 55  Interpolation Filters ................................................................... 32  REVISION HISTORY 6/10—Revision 0: Initial Version Rev. 0 | Page 2 of 56 AD9125 FUNCTIONAL BLOCK DIAGRAM IOUT1P 16 1.2G AUX DAC 1 16-BIT IOUT1N 16 f /2 I OFFSET NCO DATA 10 INV DACCLK FIFO PRE HB1 AND HB2 HB3 D[31:0] SINC Q OFFSET MOD MOD 16 DCI 16 IOUT2P 1.2G FRAME AUX DAC 1 16-BIT IOUT2N REF REFIO 10 10 AND BIAS FSADJ INTERNAL CLOCK TIMING AND CONTROL LOGIC DAC CLK_SEL PLL CONTROL DACCLKP CLK 0 RCVR SERIAL DACCLK DACCLKN SYNC PROGRAMMING POWER-ON MULTICHIP INPUT/OUTPUT CLOCK REGISTERS RESET SYNCHRONIZATION REFCLKP CLK PORT 1 MULTIPLIER RCVR REFCLKN (2× TO 16×) PLL_LOCK Figure 2. AD9125 Functional Block Diagram Rev. 0 | Page 3 of 56 MODE DATA RECEIVER SDO SDIO HB1_CLK SCLK CS IRQ RESET HB2_CLK HB3_CLK INTP FACTOR PHASE CORRECTION INVSINC_CLK GAIN 1 GAIN 2 09016-002 AD9125 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, maximum sample rate, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 % FSR Gain Error (with Internal Reference) −3.6 ±2 +3.6 % FSR 1 Full-Scale Output Current 8.66 19.6 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES DVDD18 1.71 1.8 1.89 V IOVDD 1.71 1.8/3.3 3.47 V POWER CONSUMPTION 2× Mode, fDAC = 491.52 MSPS, IF = 10 MHz, PLL Off 834 mW 2× Mode, f = 491.52 MSPS, IF = 10 MHz, PLL On 913 mW DAC 8× Mode, f = 800 MSPS, IF = 10 MHz, PLL Off 1114 1227 mW DAC AVDD33 55 58 mA CVDD18 78 85 mA DVDD18 440 490 mA Power-Down Mode 1.5 2.7 mW Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V OPERATING RANGE −40 +25 +85 °C 1 Based on a 10 kΩ external resistor. Rev. 0 | Page 4 of 56 AD9125 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit CMOS DATA INPUTS Input VIN Logic High 1.2 V Input VIN Logic Low 0.6 V Maximum Bus Speed 250 MHz SERIAL PORT OUTPUT LOGIC LEVELS Output VOUT Logic High IOVDD = 1.8 V 1.4 V IOVDD = 2.5 V 1.8 V IOVDD = 3.3 V 2.0 V Output VOUT Logic Low IOVDD = 1.8 V 0.4 IOVDD = 2.5 V 0.4 V IOVDD = 3.3 V 0.4 V SERIAL PORT INPUT LOGIC LEVELS Input VIN Logic High IOVDD = 1.8 V 1.2 V IOVDD = 2.5 V 1.6 V IOVDD = 3.3 V 2.4 V Input V Logic Low IOVDD = 1.8 V 0.6 V IN IOVDD = 2.5 V 0.8 V IOVDD = 3.3V 0.8 V DACCLK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage Self biased input, ac couple 1.25 V Maximum Clock Rate 1000 MHz REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V REFCLKx Frequency, PLL Mode 1 GHz ≤ f ≤ 2.1 GHz 15.625 600 MHz VCO REFCLKx Frequency, SYNC Mode See the Multichip Synchronization section for conditions 0 600 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High (t) 12.5 ns PWH Minimum Pulse Width Low (t) 12.5 ns PWOL Setup Time, SDI to SCLK (tDS) 1.9 ns Hold Time, SDI to SCLK (tDH) 0.2 ns Data Valid, SDO to SCLK (tDV) 2.3 ns Setup Time, CS to SCLK (t) 1.4 ns DCS LATENCY AND POWER-UP TIMING SPECIFICATIONS Table 3. Parameter Min Typ Max Unit LATENCY (DACCLK Cycles) 1× Interpolation (with or Without Modulation) 64 Cycles 2× Interpolation (with or Without Modulation) 135 Cycles 4× Interpolation (with or Without Modulation) 292 Cycles 8× Interpolation (with or Without Modulation) 608 Cycles Inverse Sinc 20 Cycles Fine Modulation 8 Cycles Power-Up Time 260 ms Rev. 0 | Page 5 of 56 AD9125 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz 78 dBc fDAC = 200 MSPS, fOUT = 50 MHz 80 dBc fDAC = 400 MSPS, fOUT = 70 MHz 69 dBc f = 800 MSPS, f = 70 MHz 72 dBc DAC OUT TWO-TONE INTERMODULATION DISTORTION (IMD) f = 200 MSPS, f = 50 MHz 84 dBc DAC OUT f = 400 MSPS, f = 60 MHz 86 dBc DAC OUT f = 400 MSPS, f = 80 MHz 84 dBc DAC OUT fDAC = 800 MSPS, fOUT = 100 MHz 81 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING f = 200 MSPS, f = 80 MHz −162 dBm/Hz DAC OUT fDAC = 400 MSPS, fOUT = 80 MHz −163 dBm/Hz fDAC = 800 MSPS, fOUT = 80 MHz −164 dBm/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz 82 dBc fDAC = 491.52 MSPS, fOUT = 122.88 MHz 80 dBc fDAC = 983.04 MSPS, fOUT = 122.88 MHz 81 dBc W-CDMA SECOND ACLR, SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz 88 dBc fDAC = 491.52 MSPS, fOUT = 122.88 MHz 86 dBc f = 983.04 MSPS, f = 122.88 MHz 88 dBc DAC OUT Table 5. Interface Speeds Mode Interpolation fBUS fDATA fDAC Byte Mode 1× 250 62.5 62.5 2× (HB1) 250 62.5 125 2× (HB2) 250 62.5 125 4× 250 62.5 250 8× 250 62.5 500 Word Mode 1× 250 125 125 2× (HB1) 250 125 250 2× (HB2) 250 125 250 4× 250 125 500 8× 250 125 1000 Dual-Word Mode 1× 250 250 250 2× (HB1) 250 250 500 2× (HB2) 250 250 500 4× 250 250 1000 8× 125 125 1000 Rev. 0 | Page 6 of 56 AD9125 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. With The exposed paddle (EPAD) must be soldered to the ground Parameter Respect To Rating plane for the 72-lead LFCSP. The EPAD performs as an AVDD33 −0.3 V to +3.6 V AVSS, EPAD, electrical and thermal connection to the board. CVSS, DVSS Typical θJA, θJB, and θJC values are specified for a 4-layer board in IOVDD AVSS, EPAD, −0.3 V to +3.6 V still air. Airflow increases heat dissipation, effectively reducing CVSS, DVSS θJA and θJB. DVDD18, CVDD18 AVSS, EPAD, −0.3 V to +2.1 V CVSS, DVSS Table 7. Thermal Resistance AVSS EPAD, CVSS, −0.3 V to +0.3 V Package θJA θJB θJC Unit Conditions DVSS 72-Lead LFCSP 20.7 10.9 1.1 °C/W EPAD soldered EPAD AVSS, CVSS, −0.3 V to +0.3 V DVSS CVSS AVSS, EPAD, −0.3 V to +0.3 V ESD CAUTION DVSS DVSS AVSS, EPAD, −0.3 V to +0.3 V CVSS FSADJ, REFIO, AVSS −0.3 V to AVDD33 + 0.3 V IOUT1P/IOUT1N, IOUT2P/IOUT2N D[31:0], FRAME, DCI EPAD, DVSS −0.3 V to DVDD18 + 0.3 V DACCLKP/DACCLKN, DVSS −0.3 V to CVDD18 + 0.3 V REFCLKP/REFCLKN RESET, IRQ, CS, SCLK, EPAD, DVSS −0.3 V to IOVDD + 0.3 V SDIO, SDO Junction Temperature 125°C Storage Temperature −65°C to +150°C Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 56 AD9125 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CVDD18 1 54 RESET PIN 1 DACCLKP 2 INDICATOR 53 CS DACCLKN 3 52 SCLK CVSS 4 51 SDIO FRAME 5 50 SDO NC 6 DVDD18 49 IRQ 7 48 D0 AD9125 D31 8 47 D1 D30 9 TOP VIEW 46 D2 (Not to Scale) NC 10 45 D3 IOVDD 11 44 DVSS DVDD18 12 43 DVDD18 D29 13 42 D4 D28 14 41 D5 D27 15 40 D6 D26 16 39 D7 D25 17 38 D8 D24 18 37 D9 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD MUST BE CONNECTED TO AVSS. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 2 DACCLKP DAC Clock Input, Positive. 3 DACCLKN DAC Clock Input, Negative. 4 CVSS Clock Supply Common. 5 FRAME Frame Input. 6 NC No Connect 7 IRQ (INT) Interrupt Request. Open Drain, Active Low Output. Connect external pull-up to IOVDD. 8 D31 Data Bit 31. 9 D30 Data Bit 30. 10 NC No Connect. 11 IOVDD Supply for Serial Port Pin, RESET Pin, and IRQ Pin. 1.8 V to 3.3 V can be applied to this pin. 12 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports. 13 D29 Data Bit 29. 14 D28 Data Bit 28. 15 D27 Data Bit 27. 16 D26 Data Bit 26. 17 D25 Data Bit 25. 18 D24 Data Bit 24. 19 D23 Data Bit 23. 20 D22 Data Bit 22. 21 D21 Data Bit 21. 22 D20 Data Bit 20. 23 D19 Data Bit 19. 24 D18 Data Bit 18. 25 D17 Data Bit 17. 26 D16 Data Bit 16. 27 DCI Data Clock Input. Rev. 0 | Page 8 of 56 D23 19 72 CVDD18 D22 20 71 CVDD18 D21 21 70 REFCLKP D20 22 69 REFCLKN D19 23 68 AVDD33 D18 24 67 IOUT1P D17 25 66 IOUT1N D16 26 65 AVDD33 DCI 27 64 AVSS NC 28 63 FSADJ DVDD18 29 62 REFIO DVSS 30 61 AVSS D15 31 60 AVDD33 D14 32 59 IOUT2N D13 33 58 IOUT2P D12 34 57 AVDD33 D11 35 56 AVSS D10 36 55 NC 09016-003 AD9125 Pin No. Mnemonic Description 28 NC No Connect. 29 DVDD18 1.8 V Digital Supply. 30 DVSS Digital Common. 31 D15 Data Bit 15. 32 D14 Data Bit 14. 33 D13 Data Bit 13. 34 D12 Data Bit 12. 35 D11 Data Bit 11. 36 D10 Data Bit 10. 37 D9 Data Bit 9. 38 D8 Data Bit 8. 39 D7 Data Bit 7. 40 D6 Data Bit 6. 41 D5 Data Bit 5. 42 D4 Data Bit 4. 43 DVDD18 1.8 V Digital Supply. 44 DVSS Digital Supply Common. 45 D3 Data Bit 3. 46 D2 Data Bit 2. 47 D1 Data Bit 1. 48 D0 Data Bit 0. 49 DVDD18 1.8 V Digital Supply. 50 SDO Serial Port Data Output (CMOS levels with respect to IOVDD). 51 SDIO Serial Port Data Input/Output (CMOS levels with respect to IOVDD). 52 SCLK Serial Port Clock Input (CMOS levels with respect to IOVDD). 53 CS Serial Port Chip Select. Active Low (CMOS levels with respect to IOVDD). 54 RESET Reset. Active Low (CMOS levels with respect to IOVDD). 55 NC No Connect. 56 AVSS Analog Supply Common. 57 AVDD33 3.3 V Analog Supply. 58 IOUT2P Q DAC Positive Current Output. 59 IOUT2N Q DAC Negative Current Output. 60 AVDD33 3.3 V Analog Supply. 61 AVSS Analog Supply Common. 62 REFIO Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common. 63 FSADJ Full-Scale Current Output Adjust. Place a 10 kΩ resistor on the analog common. 64 AVSS Analog Common. 65 AVDD33 3.3 V Analog Supply. 66 IOUT1N I DAC Negative Current Output. 67 IOUT1P I DAC Positive Current Output. 68 AVDD33 3.3 V Analog Supply. 69 REFCLKN PLL Reference Clock Input, Negative. This pin has a secondary function as the SYNC input. 70 REFCLKP PLL Reference Clock Input, Positive. This pin has a secondary function as the SYNC input. 71 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 72 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. EPAD Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection to the PCB. Rev. 0 | Page 9 of 56 AD9125 TYPICAL PERFORMANCE CHARACTERISTICS 0 –50 f = 125MSPS, SECOND HARMONIC 0dBFS DATA –10 f = 125MSPS, THIRD HARMONIC –6dBFS DATA –55 –12dBFS f = 250MSPS, SECOND HARMONIC DATA –20 –18dBFS f = 250MSPS, THIRD HARMONIC DATA –60 –30 –65 –40 –50 –70 –60 –75 –70 –80 –80 –85 –90 –100 –90 0 50 100 150 200 250 300 0 50 100150200250300 f (MHz) f (MHz) OUT OUT Figure 4. Harmonics vs. f over f , 2× Interpolation, Figure 7. Second Harmonic vs. f over Digital Scale, 2× Interpolation, OUT DATA OUT Digital Scale = 0 dBFS, f = 20 mA f = 250 MSPS, f = 20 mA SC DATA SC 0 –50 f = 125MSPS, SECOND HARMONIC 0dBFS DATA f = 125MSPS, THIRD HARMONIC –6dBFS –10 –55 DATA f = 250MSPS, SECOND HARMONIC –12dBFS DATA –20 –60 –18dBFS f = 250MSPS, THIRD HARMONIC DATA –30 –65 –40 –70 –50 –75 –60 –80 –70 –85 –80 –90 –90 –95 –100 –100 0 100 200 300 400 500 600 0 50 100150200250300 f (MHz) f (MHz) OUT OUT Figure 5. Harmonics vs. fOUT over fDATA, 4× Interpolation, Figure 8. Third Harmonic vs. fOUT over Digital Scale, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA fDATA = 250 MSPS, fSC = 20 mA 0 –50 f = 125MSPS, SECOND HARMONIC DATA –10 f = 125MSPS, THIRD HARMONIC DATA –55 –20 –60 –30 –65 –40 –70 –50 –75 –60 –80 –70 10mA, SECOND HARMONIC 20mA, SECOND HARMONIC –85 –80 30mA, SECOND HARMONIC 10mA, THIRD HARMONIC –90 –90 20mA, THIRD HARMONIC 30mA, THIRD HARMONIC –100 –95 0 100 200 300 400 500 600 0 50 100150200250300 f (MHz) f (MHz) OUT OUT Figure 6. Harmonics vs. f over f , 8× Interpolation, Figure 9. Harmonics vs. f over f , 2× Interpolation, OUT DATA OUT SC Digital Scale = 0 dBFS, f = 20 mA f = 250 MSPS, Digital Scale = 0 dBFS SC DATA Rev. 0 | Page 10 of 56 HARMONICS (dBc) HARMONICS (dBc) HARMONICS (dBc) 09016-103 09016-102 09016-101 HARMONICS (dBc) HARMONICS (dBc) HARMONICS (dBc) 09016-106 09016-105 09016-104 AD9125 –50 f = 125MSPS DATA 2× INTERPOLATION, f = 250MSPS SINGLE-TONE SPECTRUM, DATA –55 f = 250MSPS, DATA f = 101MHz OUT –60 –65 –70 –75 –80 –85 –90 –95 START 1.0MHz VBW 10kHz STOP 500.0MHz 0 50 100 150 200 250 300 #RES BW 10kHz SWEEP 6.017s (601 PTS) f (MHz) OUT Figure 10. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation, Figure 13. 2× Interpolation, Single-Tone Spectrum Digital Scale = 0 dBFS, fSC = 20 mA –50 f = 125MSPS DATA 4× INTERPOLATION, f = 250MSPS SINGLE-TONE SPECTRUM, DATA –55 f = 125MSPS, DATA f = 101MHz OUT –60 –65 –70 –75 –80 –85 –90 START 1.0MHz VBW 10kHz STOP 500.0MHz 0 100 200 300 400 500 600 #RES BW 10kHz SWEEP 6.017s (601 PTS) f (MHz) OUT Figure 11. Highest Digital Spur vs. f over f , 4× Interpolation, Figure 14. 4× Interpolation, Single-Tone Spectrum OUT DATA Digital Scale = 0 dBFS, f = 20 mA SC –50 f = 125MSPS DATA 8× INTERPOLATION, SINGLE-TONE SPECTRUM, –55 f = 125MSPS, DATA f = 131MHz OUT –60 –65 –70 –75 –80 –85 –90 –95 START 1.0MHz VBW 10kHz STOP 1.0GHz 04 50 100 150 200 250 300 35000 #RES BW 10kHz SWEEP 12.05s (601 PTS) f (MHz) OUT Figure 15. 8× Interpolation, Single-Tone Spectrum Figure 12. Highest Digital Spur vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA Rev. 0 | Page 11 of 56 HIGHEST DIGITAL SPUR (dBc) HIGHEST DIGITAL SPUR (dBc) HIGHEST DIGITAL SPUR (dBc) 09016-109 09016-108 09016-107 09016-112 09016-111 09016-110 AD9125 –50 –50 f = 125MSPS 0dBFS DATA f = 250MSPS –6dBFS DATA –55 –55 –12dBFS –18dBFS –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 0 50 100 150 200 250 300 0 50 100 150 200 250 300 f (MHz) f (MHz) OUT OUT Figure 16. IMD vs. fOUT over fDATA, 2× Interpolation, Figure 19. IMD vs. fOUT over Digital Scale, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA fDATA = 250 MSPS, fSC = 20 mA –50 –50 f = 125MSPS 20mA DATA f = 250MSPS 30mA DATA –55 –55 10mA –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 –90 –90 0 100 200 300 400 500 600 0 50 100 150 200 250 300 f (MHz) f (MHz) OUT OUT Figure 17. IMD vs. fOUT over fDATA, 4× Interpolation, Figure 20. IMD vs. fOUT over fSC, 2× Interpolation, fDATA = 250 MSPS, Digital Scale = 0 dBFS, fSC = 20 mA Digital Scale = 0 dBFS –50 –40 f = 125MSPS DATA –45 –55 –50 –60 –55 PLL ON –65 –60 –70 –65 PLL OFF –70 –75 –75 –80 –80 –85 –85 –90 –90 0 100 200 300 400 500 600 0 50 100 150 200 250 300 f (MHz) f (MHz) OUT OUT Figure 18. IMD vs. fOUT over fDATA, 8× Interpolation, Figure 21. IMD vs. fOUT, PLL On vs. PLL Off Digital Scale = 0 dBFS, fSC = 20 mA Rev. 0 | Page 12 of 56 IMD (dBc) IMD (dBc) IMD (dBc) 09016-115 09016-114 09016-113 IMD (dBc) IMD (dBc) IMD (dBc) 09016-118 09016-117 09016-116 AD9125 –154 –160 2×, f = 250MSPS DATA 4×, f = 125MSPS DATA –156 –161 8×, f = 125MSPS DATA –158 –162 –160 –163 –162 –164 –164 2×, f = 250MSPS –165 DATA –166 4×, f = 125MSPS DATA 8×, f = 125MSPS DATA –168 –166 06 100 200 300 400 50000 0 50 100 150 200 250 300 350 400 450 500 f (MHz) f (MHz) OUT OUT Figure 22. One-Tone NSD vs. fOUT over Interpolation Rate and fDATA, Digital Figure 25. Eight-Tone NSD vs. fOUT over Interpolation Rate and fDATA, Scale = 0 dBFS, fSC = 20 mA, PLL Off Digital Scale = 0 dBFS, fSC = 20 mA, PLL Off –154 –161.5 0dBFS 0dBFS –6dBFS –6dBFS –162.0 –12dBFS –156 –12dBFS –18dBFS –162.5 –18dBFS –158 –163.0 –163.5 –160 –164.0 –162 –164.5 –165.0 –164 –165.5 –166 –166.0 –168 –166.5 02 50 100 150 20050 0 50 100 150 200 250 f (MHz) f (MHz) OUT OUT Figure 23. One-Tone NSD vs. fOUT over Digital Scale, fDATA = 200 MSPS, Figure 26. Eight-Tone NSD vs. fOUT over Digital Scale, fDATA = 200 MSPS, 4× Interpolation, fSC = 20 mA, PLL Off 4× Interpolation, fSC = 20 mA, PLL Off –158 –160 8×, f = 125MSPS 8×, f = 125MSPS DATA DATA –159 –161 –160 –162 –161 –163 –162 –163 –164 –164 –165 –165 –166 –166 –167 –167 06 100 200 300 400 50000 0 100 200 300 400 500 600 f (MHz) f (MHz) OUT OUT Figure 24. One-Tone NSD vs. fOUT over Interpolation Rate and fDATA, Figure 27. Eight-Tone NSD vs. fOUT over Interpolation Rate and fDATA, Digital Scale = 0 dBFS, fSC = 20 mA, PLL On Digital Scale = 0 dBFS, fSC = 20 mA, PLL On Rev. 0 | Page 13 of 56 NSD (dBm/Hz) NSD (dBm/Hz) NSD (dBm/Hz) 09016-121 09016-120 09016-119 NSD (dBm/Hz) NSD (dBm/Hz) NSD (dBm/Hz) 09016-124 09016-123 09016-122 AD9125 –77 –50 0dBFS 2×, PLL OFF 4×, PLL OFF –3dBFS –55 –78 2×, PLL ON –6dBFS 4×, PLL ON –60 –79 –65 –80 –70 –81 –75 –82 –80 –83 –85 –84 –90 0 50 100 150 200 250 0 100 200 300 400 500 f (MHz) f (MHz) OUT OUT Figure 28. One-Carrier W-CDMA ACLR vs. fOUT over Digital Cutback, Figure 31. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation Rate, Adjacent Channel, PLL Off Adjacent Channel, PLL On vs. PLL Off –78 –70 0dBFS 2×, PLL OFF 4×, PLL OFF –3dBFS –72 2×, PLL ON –6dBFS –80 –74 4×, PLL ON –76 –82 –78 –84 –80 –82 –86 –84 –86 –88 –88 –90 –90 0 50 100 150 200 250 0 100 200 300 400 500 f (MHz) f (MHz) OUT OUT Figure 29. One-Carrier W-CDMA ACLR vs. f over f , Figure 32. One-Carrier W-CDMA ACLR vs. f over Interpolation Rate, OUT DAC OUT Alternate Channel, PLL Off Alternate Channel, PLL On vs. PLL Off –70 –70 2×, PLL OFF 0dBFS 4×, PLL OFF –3dBFS 2×, PLL ON –6dBFS –75 4×, PLL ON –75 –80 –80 –85 –85 –90 –90 –95 –95 0 50 100 150 200 250 0 100 200 300 400 500 f (MHz) f (MHz) OUT OUT Figure 30. One-Carrier W-CDMA ACLR vs. fOUT over fDAC, Figure 33. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation Rate, Second Alternate Channel, PLL Off Second Alternate Channel, PLL On vs. PLL Off Rev. 0 | Page 14 of 56 ACLR (dBc) ACLR (dBc) ACLR (dBc) 09016-127 09016-126 09016-125 ACLR (dBc) ACLR (dBc) ACLR (dBc) 09016-130 09016-129 09016-128 AD9125 START 133.06MHz VBW 30kHz STOP 166.94MHz START 125.88MHz VBW 30kHz STOP 174.42MHz #RES BW 30kHz SWEEP 143.6ms (601 PTS) #RES BW 30kHz SWEEP 206.9ms (601 PTS) RMS RESULTS FREQ LOWER UPPER TOTAL CARRIER POWER: –11.19dBm/15.3600MHz OFFSET REF BW dBc dBm dBc dBm RRC FILTER: OFF FILTER ALPHA 0.22 CARRIER POWER 5.00MHz 3.840MHz –75.96 –85.96 –77.13 –87.13 REF CARRIER POWER: –16.89dBm/3.84000MHz –10.00dBm/ 10.00MHz 3.840MHz –85.33 –95.33 –85.24 –95.25 LOWER UPPER 3.840MHz 15.00MHz 2.888MHz –95.81 –95.81 –85.43 –95.43 OFFSET FREQ INTEG BW dBc dBm dBc dBm 1 –16.92dBm 5.000MHz 3.840MHz –65.88 –82.76 –67.52 –84.40 2 –16.89dBm 10.00MHz 3.840MHz –68.17 –85.05 –69.91 –86.79 3 –17.43dBm 15.00MHz 3.840MHz –70.42 –87.31 –71.40 –88.28 4 –17.64dBm Figure 34. Four-Carrier W-CDMA ACLR Performance, IF ≈150 MHz Figure 35. One-Carrier W-CDMA ACLR Performance, IF ≈150 MHz Rev. 0 | Page 15 of 56 09016-131 09016-132 AD9125 TERMINOLOGY Integral Nonlinearity (INL) Settling Time INL is defined as the maximum deviation of the actual analog The time required for the output to reach and remain within a output from the ideal output, determined by a straight line drawn specified error band around its final value, measured from from zero scale to full scale. the start of the output transition. Differential Nonlinearity (DNL) Spurious-Free Dynamic Range (SFDR) DNL is the measure of the variation in analog value, normalized The difference in decibels between the peak amplitude of the to full scale, associated with a 1 LSB change in digital input code. output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC. Typically, energy in this band is Offset Error rejected by the interpolation filters. This specification, therefore, The deviation of the output current from the ideal of zero is defines how well the interpolation filters work and the effect of called offset error. For IOUT1P, 0 mA output is expected when other parasitic coupling paths to the DAC output. the inputs are all 0s. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal Gain Error to the rms sum of all other spectral components below the Nyquist The difference between the actual and ideal output span. The frequency, excluding the first six harmonics and dc. The value actual span is determined by the difference between the outputs for SNR is expressed in decibels. when all inputs are set to 1 vs. when all inputs are set to 0. Interpolation Filter Output Compliance Range If the digital inputs to the DAC are sampled at a multiple rate of The range of allowable voltage at the output of a current output fDATA (interpolation rate), a digital filter can be constructed that DAC. Operation beyond the maximum compliance limits can has a sharp transition band near fDATA/2. Images that typically cause either output stage saturation or breakdown, resulting in appear around f (output data rate) can be greatly suppressed. DAC nonlinear performance. Adjacent Channel Leakage Ratio (ACLR) Temperature Drift The ratio in decibels relative to the carrier (dBc) between the Temperature drift is specified as the maximum change from measured power within a channel and that of its adjacent channel. the ambient (25°C) value to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in ppm of full- Complex Image Rejection scale range (FSR) per degree Celsius. For reference drift, the In a traditional two-part upconversion, two images are created drift is reported in ppm per degree Celsius. around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing Power Supply Rejection (PSR) the real part of a second complex modulator in series with the The maximum change in the full-scale output as the supplies first complex modulator, either the upper or lower frequency are varied from minimum to maximum specified voltages. image near the second IF can be rejected. 16 16 I DAC 2 2 2 32 LATCH DATA DATA SIN INPUT FORMAT NCO FIFO COS 16 16 Q DAC 2 2 2 DCI CLOCK GENERATOR DACCLK AND DISTRIBUTOR WRITE READ POINTER POINTER f f /f f /f f f INTERFACE DATA HB1 NCO HB2 HB3 DAC Figure 36. Defining Data Rates Rev. 0 | Page 16 of 56 09016-136 AD9125 THEORY OF OPERATION The AD9125 combines many features that make it a very attractive The remaining SCLK edges are for Phase 2 of the communication DAC for wired and wireless communications systems. The dual cycle. Phase 2 is the actual data transfer between the device and digital signal path and dual DAC structure allow an easy interface the system controller. Phase 2 of the communication cycle is a to common quadrature modulators when designing single transfer of one or more data bytes. Registers change immediately sideband transmitters. The speed and performance of the AD9125 upon writing to the last bit of each transfer byte, except for the allows wider bandwidths and more carriers to be synthesized than frequency tuning word and NCO phase offsets, which only change in previously available DACs. In addition, these devices include an when the frequency update bit (Register 0x36, Bit 0) is set. innovative low power, 32-bit, complex NCO that greatly increases DATA FORMAT the ease of frequency placement. The instruction byte contains the information shown in Table 9. The AD9125 offers features that allow simplified synchronization with incoming data and between multiple devices. Auxiliary Table 9. Serial Port Instruction Byte DACs are also provided on chip for output dc offset compensation I7 (MSB) I6 I5 I4 I3 I2 I1 I0 (LSB) (for local oscillator [LO] compensation in single sideband [SSB] R/W A6 A5 A4 A3 A2 A1 A0 transmitters) and for gain matching (for image rejection optimization in SSB transmitters). W R/ , Bit 7 of the instruction byte, determines whether a read or SERIAL PORT OPERATION write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation, and Logic 0 indicates a write The serial port is a flexible, synchronous serial communication operation. port, allowing easy interface to many industry-standard micro- controllers and microprocessors. The serial I/O is compatible A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the with most synchronous transfer formats, including both the register that is accessed during the data transfer portion of the Motorola SPI® and Intel® SSR protocols. The interface allows communication cycle. For multibyte transfers, A6 is the starting read/write access to all registers that configure the AD9125. byte address. The remaining register addresses are generated by Single- or multiple-byte transfers are supported, as well as MSB- the device based on the LSB_FIRST bit (Register 0x00, Bit 6). first or LSB-first transfer formats. The serial interface ports can SERIAL PORT PIN DESCRIPTIONS be configured as a single-pin I/O (SDIO) or two unidirectional Serial Clock (SCLK) pins for input/output (SDIO/SDO). The serial clock pin synchronizes data to and from the device SDO 50 and runs the internal state machines. The maximum frequency SDIO 51 SPI of SCLK is 40 MHz. All data input is registered on the rising PORT 52 SCLK edge of SCLK. All data is driven out on the falling edge of SCLK. CS 53 CS Chip Select ( ) Figure 37. Serial Port Interface Pins An active low input starts and gates a communication cycle. There are two phases of a communication cycle with the It allows more than one device to be used on the same serial AD9125. Phase 1 is the instruction cycle (the writing of an communication lines. The SDO and SDIO pins go to a high instruction byte into the device), which is coincident with the impedance state when this input is high. During the first eight SCLK rising edges. The instruction byte provides the CS communication cycle, the pin should stay low. serial port controller with information regarding the data Serial Data I/O (SDIO) transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration data transfer is a read or write and the starting register address of this pin is controlled by Register 0x00, Bit 7. The default is for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the Logic 0, configuring the SDIO pin as unidirectional. instruction byte into the device. Serial Data Out (SDO) CS A logic high on the pin followed by a logic low resets the Data is read from this pin for protocols that use separate lines serial port timing to the initial state of the instruction cycle. for transmitting and receiving data. In the case where the device From this state, the next eight rising SCLK edges represent the operates in a single bidirectional I/O mode, this pin does not instruction bits of the current I/O operation. output data and is set to a high impedance state. Rev. 0 | Page 17 of 56 09016-010 AD9125 INSTRUCTION CYCLE DATA TRANSFER CYCLE SERIAL PORT OPTIONS CS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the LSB_FIRST bit SCLK (Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0). SDIO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 When LSB_FIRST = 0 (MSB-first), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in SDO D7 D6 D5 D3 D2 D1 D0 N N 0 0 0 0 MSB-first format start with an instruction byte that includes the Figure 38. Serial Register Interface Timing, MSB First register address of the most significant data byte. Subsequent data bytes should follow from the high address to the low address. In MSB-first mode, the serial port internal byte address generator INSTRUCTION CYCLE DATA TRANSFER CYCLE decrements for each data byte of the multibyte communi- CS cation cycle. SCLK When LSB_FIRST = 1 (LSB-first), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in SDIO A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N LSB-first format start with an instruction byte that includes the register address of the least significant data byte followed by SDO D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N multiple data bytes. The serial port internal byte address generator Figure 39. Serial Register Interface Timing, LSB First increments for each byte of the multibyte communication cycle. The serial port controller data address decrements from the t DS data address written toward 0x00 for multibyte I/O operations t SCLK if the MSB-first mode is active. The serial port controller address CS increments from the data address written toward 0x7F for t t PWH PWL multibyte I/O operations if the LSB-first mode is active. SCLK t DS t DH SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 40. Timing Diagram for Serial Port Register Write (tDS to tDCS) CS SCLK t DV SDIO, DATA BIT n DATA BIT n – 1 SDO Figure 41. Timing Diagram for Serial Port Register Read Rev. 0 | Page 18 of 56 09016-014 09016-013 09016-012 09016-011 AD9125 DEVICE CONFIGURATION REGISTER MAP Table 10. Device Configuration Register Map Addr Register Name (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Comm 0x00 SDIO LSB_FIRST Reset 0x00 Power Control 0x01 Power- Power- Power- Power- PLL lock 0x10 down down down data down status DAC I DAC Q receiver aux ADC Data Format 0x03 Binary Q data MSB swap Data bus width[1:0] 0x00 data first format Interrupt Enable 1 0x04 Enable Enable Enable Enable Enable Enable Enable Enable 0x00 PLL lock PLL sync sync sync soft FIFO FIFO lost lock signal signal phase FIFO Warning 1 Warning 2 lost lock lock sync Interrupt Enable 2 0x05 0 0 0 Enable Enable Enable 0 0 0x00 AED AED SED compare compare compare pass fail fail Event Flag 1 0x06 PLL PLL Sync Sync Sync Soft FIFO FIFO N/A lock locked signal signal phase FIFO Warning 1 Warning 2 lost lost locked locked sync Event Flag 2 0x07 AED AED SED N/A compare compare compare pass fail fail Clock Receiver 0x08 DACCLK REFCLK DACCLK REFCLK 1 1 1 1 0x3F Control duty duty cross- cross- correction correction correction correction PLL Control 1 0x0A PLL PLL Manual VCO band[5:0] 0x40 enable manual enable PLL Control 2 0x0C PLL loop bandwidth[2:0] PLL charge pump current[4:0] 0xD1 PLL Control 3 0x0D N2[1:0] PLL cross N0[1:0] N1[1:0] 0xD9 control enable PLL Status 1 0x0E PLL lock VCO control voltage[3:0] 0x00 PLL Status 2 0x0F VCO band readback[5:0] 0x00 Sync Control 1 0x10 Sync Data/FIFO Rising Sync Averaging[2:0] 0x48 enable rate toggle edge sync Sync Control 2 0x11 Sync phase request[5:0] 0x00 Sync Status 1 0x12 Sync lost Sync N/A locked Sync Status 2 0x13 Sync phase readback[7:0] (6.2 format) N/A FIFO Control 0x17 FIFO phase offset[2:0] 0x04 FIFO Status 1 0x18 FIFO FIFO FIFO soft FIFO soft FIFO reset N/A Warning 1 Warning 2 align ack align aligned request FIFO Status 2 0x19 FIFO level[7:0] N/A Datapath Control 0x1B Bypass Bypass Bypass NCO gain Bypass Select Send I data 0xE4 −1 premod sinc NCO phase sideband to Q data compen- sation and dc offset HB1 Control 0x1C HB1[1:0] Bypass HB1 0x00 HB2 Control 0x1D HB2[5:0] Bypass HB2 0x00 HB3 Control 0x1E HB3[5:0] Bypass HB3 0x00 Chip ID 0x1F Chip ID[7:0] 0x08 Rev. 0 | Page 19 of 56 AD9125 Addr Register Name (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default FTW 1 (LSB) 0x30 FTW[7:0] 0x00 FTW 2 0x31 FTW[15:8] 0x00 FTW 3 0x32 FTW[23:16] 0x00 FTW 4 (MSB) 0x33 FTW[31:24] 0x00 NCO Phase Offset 0x34 NCO phase offset[7:0] 0x00 LSB NCO Phase Offset 0x35 NCO phase offset[15:8] 0x00 MSB NCO FTW Update 0x36 Frame Frame FTW Update Update 0x00 FTW ack request FTW ack FTW request I Phase Adj LSB 0x38 I phase adjust[7:0] 0x00 I Phase Adj MSB 0x39 I phase adjust[9:8] 0x00 Q Phase Adj LSB 0x3A Q phase adjust[7:0] 0x00 Q Phase Adj MSB 0x3B Q phase adjust[9:8] 0x00 I DAC Offset LSB 0x3C I DAC offset[7:0] 0x00 I DAC Offset MSB 0x3D I DAC offset[15:8] 0x00 Q DAC Offset LSB 0x3E Q DAC offset[7:0] 0x00 Q DAC Offset MSB 0x3F Q DAC offset[15:8] 0x00 I DAC FS Adjust 0x40 I DAC FS adjust[7:0] 0xF9 I DAC Control 0x41 I DAC I DAC FS adjust[9:8] 0x01 sleep Aux DAC I Data 0x42 I aux DAC[7:0] 0x00 I Aux DAC 0x43 I Aux I Aux DAC I aux DAC I aux DAC[9:8] 0x00 Control DAC sign current sleep direction Q DAC FS Adjust 0x44 Q DAC FS adjust[7:0] 0xF9 Q DAC Control 0x45 Q DAC Q DAC FS adjust[9:8] 0x01 sleep Aux DAC Q Data 0x46 Q aux DAC[7:0] 0x00 Q Aux DAC 0x47 Q Aux Q Aux DAC Q aux Q aux DAC[9:8] 0x00 Control DAC sign current DAC direction sleep Die Temperature 0x48 FS current[2:0] Reference current[2:0] Capacitor 0x02 Range Control value Die Temperature 0x49 Die temperature[7:0] N/A LSB Die Temperature 0x4A Die temperature[15:8] N/A MSB SED Control 0x67 SED Sample Auto- Compare Compare 0x00 compare error clear fail pass enable detected enable Compare I0 LSBs 0x68 Compare Value I0[7:0] 0xB6 Compare 0x69 Compare Value I0[15:8] 0x7A I0 MSBs Compare 0x6A Compare Value Q0[7:0] 0x45 Q0 LSBs Compare 0x6B Compare Value Q0[15:8] 0xEA Q0 MSBs Compare I1 LSBs 0x6C Compare Value I1[7:0] 0x16 Compare I1 MSBs 0x6D Compare Value I1[15:8] 0x1A Compare 0x6E Compare Value Q1[7:0] 0xC6 Q1 LSBs Rev. 0 | Page 20 of 56 AD9125 Addr Register Name (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Compare 0x6F Compare Value Q1[15:8] 0xAA Q1 MSBs SED I LSBs 0x70 Errors detected I_BITS[7:0] 0x00 SED I MSBs 0x71 Errors detected I_BITS[15:8] 0x00 SED Q LSBs 0x72 Errors detected Q_BITS[7:0] 0x00 SED Q MSBs 0x73 Errors detected Q_BITS[15:8] 0x00 Die Revsion 0x7F Revision[3:0] 0x0C DEVICE CONFIGURATION REGISTER DESCRIPTIONS Table 11. Device Configuration Register Descriptions Register Address Name (Hex) Bits Name Description Default Comm 0x00 7 SDIO SDIO operation. 0 0 = SDIO operates as an input only. 1 = SDIO operates as a bidirectional input/output. 6 LSB_FIRST Serial port communication LSB or MSB first. 0 0 = MSB first. 1 = LSB first. 5 Reset 1 = device is held in reset when this bit is written high 0 and is held there until the bit is written low. Power Control 0x01 7 Power-down DAC I 1 = powers down DAC I. 0 6 Power-down DAC Q 1 = powers down DAC Q. 0 5 Power-down data 1 = powers down the input data receiver. 0 receiver 4 0 Power-down auxiliary 1 = powers down the auxiliary ADC for temperature ADC sensor. 0 PLL lock status 1 = PLL is locked. 0 Data Format 0x03 7 Binary data format 0 = input data is in twos complement format. 0 1 = input data is in binary format. 6 Q data first Indicates I/Q data pairing on data input. 0 0 = I data sent to data receiver first. 1 = Q data sent to data receiver first. 5 MSB swap Swaps the bit order of the data input port. 0 0 = order of the data bits corresponds to the pin descriptions. 1 = bit designations are swapped; most significant bits become the least significant bits. [1:0] Data bus width Data receiver interface mode. 0 00 = dual-word mode; 32-bit interface bus width. 01 = word mode; 16-bit interleaved interface bus width. 10 = byte mode; 8-bit interleaved interface bus width. 11 = invalid. See the CMOS Input Data Ports section for details on the operation of the different interface modes. Interrupt Enable 1 0x04 7 Enable PLL lock lost 1 = enables interrupt for PLL lock lost. 0 6 Enable PLL lock 1 = enables interrupt for PLL lock. 0 5 Enable sync signal lost 1 = enables interrupt for sync signal lock lost. 0 4 Enable sync signal lock 1 = enables interrupt for sync signal lock. 0 3 Enable sync phase 1 = enables interrupt for clock generation ready. 0 locked 2 Enable soft FIFO sync 1 = enables interrupt for soft FIFO reset. 0 Rev. 0 | Page 21 of 56 AD9125 Register Address Name (Hex) Bits Name Description Default 1 Enable FIFO Warning 1 1 = enables interrupt for FIFO Warning 1. 0 0 Enable FIFO Warning 2 1 = enables interrupt for FIFO Warning 2. 0 Interrupt Enable 2 0x05 7 Set to 0 Set this bit to 0. 0 6 Set to 0 Set this bit to 0. 0 5 Set to 0 Set this bit to 0. 0 4 Enable AED comparison 1 = enables interrupt for AED comparison pass. 0 pass 3 Enable AED comparison 1 = enables interrupt for AED comparison fail. 0 fail 2 Enable SED comparison 1 = enables interrupt for SED comparison fail. 0 fail 1 Set to 0 Set this bit to 0. 0 0 Set to 0 Set this bit to 0. 0 1 Event Flag 1 0x06 7 PLL lock lost 0 1 = indicates that the PLL, which had been previously locked, has unlocked from the reference signal. This is a latched signal. 6 PLL locked 0 1 = indicates that the PLL has locked to the reference clock input. 5 Sync signal lost 1 = indicates that the sync logic, which had been 0 previously locked, has lost alignment. This is a latched signal. 4 Sync signal locked 1 = indicates that the sync logic did achieve sync 0 alignment. This is indicated when no phase changes were requested for at least a few full averaging cycles. 3 Sync phase locked 1 = indicates that the internal digital clock generation logic 0 is ready. This occurs when internal clocks are present and stable. 2 Soft FIFO sync 1 = indicates that a FIFO reset originating from a serial 0 port-based request has successfully completed. This is a latched signal. 1 FIFO Warning 1 0 1 = indicates that the difference between the FIFO read and write pointers is 1. 0 FIFO Warning 2 1 = indicates that the difference between the FIFO read 0 and write pointers is 2. 1 Event Flag 2 0x07 4 AED comparison pass 1 = indicates that the SED logic detected a valid input 0 data pattern compared with the preprogrammed expected values. This is a latched signal. 3 AED comparison fail 1 = indicates that the SED logic detected an invalid 0 input data pattern compared with the preprogrammed expected values. This is a latched signal that auto- matically clears when eight valid I/Q data pairs are received. 2 SED comparison fail 1 = indicates that the SED logic detected an invalid input data pattern compared with the preprogrammed expected values. This is a latched signal. Clock Receiver 0x08 7 DACCLK duty correction 1 = enables duty-cycle correction on the DACCLK input. 0 Control 6 REFCLK duty correction 1 = enables duty-cycle correction on the REFCLK input. 0 5 DACCLK cross-correction 1 = enables differential crossing correction on the DACCLK 1 input. 4 REFCLK cross-correction 1 1 = enables differential crossing correction on the REFCLK input. Rev. 0 | Page 22 of 56 AD9125 Register Address Name (Hex) Bits Name Description Default PLL Control 1 0x0A 7 PLL enable 1 = enables the PLL clock multiplier. REFCLK input is 0 used as the PLL reference clock signal. 6 PLL manual enable Enables the manual selection of the VCO band. 1 1 = manual mode; the correct VCO band must be determined by the user. [5:0] Manual VCO band Selects the VCO band to be used. 0 PLL Control 2 0x0C [7:5] PLL loop Selects the PLL loop filter bandwidth. 110 bandwidth[2:0] 000 = loop bandwidth is nominally 200 kHz 010 = loop bandwidth is nominally 450 kHz 100 = loop bandwidth is nominally 950 kHz 110 = loop bandwidth is nominally 2 MHz [4:0] Sets the nominal PLL charge-pump current. 10001 PLL charge pump current[4:0] 00000 = lowest current setting. 11111 = highest current setting. PLL Control 3 0x0D [7:6] N2[1:0] 3 PLL control clock divider. These bits determine the ratio of the DACCLK rate to the PLL controller clock rate. fPC_CLK must always be less than 80 MHz. 00 = f /f = 2. DACCLK PC_CLK 01 = f /f = 4. DACCLK PC_CLK 10 = f /f = 8. DACCLK PC_CLK 11 = fDACCLK/fPC_CLK = 16. 4 PLL cross control enable Enables PLL cross-point controller. 1 [3:2] N0[1:0] PLL VCO divider. These bits determine the ratio of the 10 VCO output to the DACCLK frequencies. 00 = f /f = 1. VCO DACCLK 01 = f /f = 2. VCO DACCLK 10 = fVCO/fDACCLK = 4. 11 = fVCO/fDACCLK = 4. [1:0] N1[1:0] PLL loop divider. These bits determine the ratio of the 01 DACCLK to the REFCLK frequencies. 00 = fDACCLK/fREFCLK = 2. 01 = fDACCLK/fREFCLK = 4. 10 = f /f = 8. DACCLK REFCLK 11 = f /f = 16. DACCLK REFCLK PLL Status 1 0x0E 7 PLL lock The PLL generated clock is tracking the REFCLK input R signal. [3:0] VCO control VCO control voltage readback (see Table 25). R voltage[3:0] PLL Status 2 0x0F [5:0] VCO band Indicates the VCO band currently selected. R readback[5:0] Sync Control 1 0x10 7 Sync enable 1 = enables the synchronization logic. 0 6 Data/FIFO rate toggle 0 = operates the synchronization at the FIFO reset rate. 1 1 = operates the synchronization at the data rate. 3 Rising edge sync 0 = sync is initiated on the falling edge of the sync input. 1 1 = sync is initiated on the rising edge of the sync input. [2:0] Sync averaging[2:0] Sets the number of input samples that are averaged for 0 determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. Rev. 0 | Page 23 of 56 AD9125 Register Address Name (Hex) Bits Name Description Default 110 = 64. 111 = 128. Sync Control 2 0x11 5:0 Sync phase request[5:0] This sets the requested clock phase offset after sync. 0 The offset unit is in DACCLK cycles. This enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. … 111111 = 63 DACCLK cycles. Sync Status 1 0x12 7 Sync lost 1 = indicates that synchronization had been attained R but was subsequently lost. 6 Sync locked 1 = indicates that synchronization has been attained. R Sync Status 2 0x13 [7:0] Sync phase readback[7:0] Indicates the averaged sync phase offset (6.2 format). If R the value differs from the requested sync phase value, this indicates sync timing errors. 00000000 = 0.0. 00000001 = 0.25. … 11111110 = 63.50. 11111111 = 63.75. FIFO Control 0x17 [2:0] FIFO phase offset[2:0] FIFO write pointer phase offset following FIFO reset. 4 This is the difference between the read pointer and the write pointer values upon FIFO reset. The optimal value is nominally 4. 000 = 0. 001 = 1. … 111 = 7. FIFO Status 1 0x18 7 FIFO Warning 1 FIFO read and write pointers within ±1. 0 6 FIFO Warning 2 FIFO read and write pointers within ±2. 0 2 FIFO soft align FIFO read and write pointers are aligned after a serial acknowledge port initiated FIFO reset. 1 FIFO soft align request Request FIFO read and write pointers alignment via the 0 serial port. 0 FIFO reset aligned FIFO read and write pointers aligned after a hardware 0 reset. FIFO Status 2 0x19 [7:0] FIFO level[7:0] Thermometer encoded measure of the FIFO level. 0 Datapath Control 0x1B 7 Bypass premod 1 = bypasses fS/2 premodulator. 1 −1 6 Bypass sinc 1 = bypasses inverse sinc filter. 1 5 Bypass NCO 1 = bypasses NCO. 1 3 NCO gain 0 = default. No gain scaling is applied to the NCO input 0 to the internal digital modulator. 1 = gain scaling of 0.5 is applied to the NCO input to the internal digital modulator. This can eliminate saturation of the modulator output for some combinations of data inputs and NCO signals. 2 Bypass phase compen- 1 = bypasses phase compensation and dc offset. 1 sation and dc offset Rev. 0 | Page 24 of 56 AD9125 Register Address Name (Hex) Bits Name Description Default 1 Select sideband 0 = the modulator outputs high-side image. 0 1 = the modulator outputs low-side image. The image is spectrally inverted compared with the input data. 0 Send I data to Q data 1 = ignores Q data from the interface and disables the 0 clocks to the Q datapath. Sends I data to both the I and Q DACs. HB1 Control 0x1C [2:1] HB1[1:0] 00 = input signal is not modulated; filter pass band is 0 from −0.4 to +0.4 of f . IN1 01 = input signal is not modulated; filter pass band is from 0.1 to 0.9 of fIN1. 10 = input signal is modulated by f ; filter pass band is IN1 from 0.6 to 1.4 of fIN1. 11 = input signal is modulated by f ; filter pass band is IN1 from 1.1 to 1.9 of f . IN1 0 Bypass HB1 1 = bypasses first-stage interpolation filter. 0 HB2 Control 0x1D [6:1] HB2[5:0] Modulation mode for I Side Half-Band Filter 2. 0 000000 = input signal is not modulated; filter pass band is from −0.25 to +0.25 of f . IN2 001001 = input signal is not modulated; filter pass band is from 0.0 to 0.5 of fIN2. 010010 = input signal is not modulated; filter pass band is from 0.25 to 0.75 of f . IN2 011011 = input signal is not modulated; filter pass band is from 0.5 to 1.0 of fIN2. 100100 = input signal is modulated by fIN2; filter pass band is from 0.75 to 1.25 of fIN2. 101101 = input signal is modulated by f ; filter pass IN2 band is from 1.0 to 1.5 of f . IN2 ; filter pass 110110 = input signal is modulated by fIN2 band is from 1.25 to 1.75 of fIN2. 111111 = input signal is modulated by fIN2; filter pass band is from 1.5 to 2.0 of fIN2. 0 Bypass HB2 1 = bypasses second stage interpolation filter. 0 HB3 Control 0x1E [6:1] HB3[5:0] Modulation mode for I Side Half-Band Filter 3. 0 000000 = input signal is not modulated; filter pass band is from −0.2 to +0.2 of f . IN3 001001 = input signal is not modulated; filter pass band is from 0.05 to 0.45 of f . IN3 010010 = input signal is not modulated; filter pass band is from 0.3 to 0.7 of fIN3. 011011 = input signal is not modulated; filter pass band is from 0.55 to 0.95 of f . IN3 100100 = input signal is modulated by f ; filter pass IN3 band is from 0.8 to 1.2 of f . IN3 101101 = input signal is modulated by fIN3; filter pass band is from 1.05 to 1.45 of fIN3. 110110 = input signal is modulated by fIN3; filter pass band is from 1.3 to 1.7 of f . IN3 111111 = input signal is modulated by f ; filter pass IN3 band is from 1.55 to 1.95 of fIN3. 0 Bypass HB3 1 = bypasses third-stage interpolation filter. 0 Chip ID 0x1F [7:0] Chip ID[7:0] This register identifies the device as an AD9125. 8 Rev. 0 | Page 25 of 56 AD9125 Register Address Name (Hex) Bits Name Description Default FTW 1 (LSB) 0x30 [7:0] FTW[7:0] FTW[31:0] is the 32-bit frequency tuning word that 0 determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Bit 0 of Register 0x36 transitions from 0 to 1. FTW 2 0x31 [7:0] FTW[15:8] See Register 0x30. 0 FTW 3 0x32 [7:0] FTW[23:16] See Register 0x30. 0 FTW 4 (MSB) 0x33 [7:0] FTW[31:24] See Register 0x30. 0 NCO Phase Offset 0x34 [7:0] NCO phase offset[7:0] NCO phase offset[15:0] sets the phase of the complex 0 LSB carrier signal when the NCO is reset. The phase offset spans between 0° and 360°. Each bit represents an offset of 0.0055°. The value is in twos complement format. NCO Phase Offset 0x35 [7:0] NCO phase offset[15:8] See Register 0x34. 0 MSB NCO FTW Update 0x36 5 FRAME FTW 1 = indicates that the NCO has been reset due to an 0 acknowledge extended FRAME pulse signal. 4 FRAME FTW request 0 0 → 1 = the NCO is reset on the first extended FRAME pulse after this bit transitions from 0 to 1. 1 Update FTW 1 = indicates that the FTW has been updated. 0 acknowledge 0 Update FTW request 0 0 → 1 = the FTW is updated on 0-to-1 transition of this bit. I Phase Adj LSB 0x38 [7:0] I phase adjust[7:0] 0 I phase adjust[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. I Phase Adj MSB 0x39 [1:0] I phase adjust[9:8] Register 0x38. 0 Q Phase Adj LSB 0x3A [7:0] Q phase adjust[7:0] Q phase adjust[9:0] is used to insert a phase offset 0 between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. Q Phase Adj MSB 0x3B [1:0] Q phase adjust[9:8] See Register 0x3A. 0 I DAC Offset LSB 0x3C [7:0] I DAC offset[7:0] I DAC offset[15:0] is a value added directly to the 0 samples written to the I DAC. I DAC Offset MSB 0x3D [7:0] I DAC offset[15:8] See Register 0x3C. 0 Q DAC Offset LSB 0x3E [7:0] Q DAC offset[7:0] Q DAC offset[15:0] is a value added directly to the 0 samples written to the Q DAC. Q DAC Offset MSB 0x3F [7:0] Q DAC offset[15:8] See Register 0x3E. 0 I DAC FS Adjust 0x40 [7:0] I DAC FS adjust[7:0] I DAC FS adjust[9:0] sets the full-scale current of the F9 I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.14 mA. … 0x3FF = 31.66 mA. I DAC Control 0x41 7 I DAC sleep 1 = puts the I-channel DAC into sleep mode (fast wake- 0 up mode). [1:0] I DAC FS adjust[9:8] See Register 0x40. 1 Aux DAC I Data 0x42 [7:0] I aux DAC[7:0] I aux DAC[9:0] sets the magnitude of the auxiliary DAC 0 current. The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. Rev. 0 | Page 26 of 56 AD9125 Register Address Name (Hex) Bits Name Description Default I Aux DAC Control 0x43 7 I aux DAC sign 0 = the auxiliary DAC I sign is positive, and the current is 0 directed to the IOUT1P pin (Pin 67). 1 = the auxiliary DAC I sign is negative, and the current is directed to the IOUT1N pin (Pin 66). 6 I aux DAC current 0 = the auxiliary DAC I sources current. 0 direction 1 = the auxiliary DAC I sinks current. 5 I aux DAC sleep I channel auxiliary DAC sleep. 0 [1:0] I Aux DAC[9:8] See Register 0x42. 0 Q DAC FS Adjust 0x44 [7:0] Q DAC FS adjust[7:0] Q DAC FS adjust[9:0] sets the full-scale current of the F9 I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.14 mA. … 0x3FF = 31.66 mA. Q DAC Control 0x45 7 Q DAC sleep 1 = puts the Q-channel DAC into sleep mode (fast wake- 0 up mode). [1:0] Q DAC FS adjust[9:8] See Register 0x44. 1 Aux DAC Q Data 0x46 [7:0] Q aux DAC[7:0] Q aux DAC[9:0] sets the magnitude of the aux DAC current. 0 The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. Q Aux DAC Control 0x47 7 Q aux DAC sign 0 = the auxiliary DAC Q sign is positive, and the current 0 is directed to the IOUT2P pin (Pin 58). 1 = the auxiliary DAC Q sign is negative, and the current is directed to the IOUT2N pin (Pin 59). 6 Q aux DAC current 0 = the auxiliary DAC Q sources current. 0 direction 1 = the auxiliary DAC Q sinks current. 5 Q aux DAC sleep Q-channel auxiliary DAC sleep 0 [1:0] Q aux DAC[9:8] See Register 0x46. 0 Die Temp Range 0x48 [6:4] FS current[2:0] Auxiliary ADC full-scale current. 0 Control 000 = lowest current. … 111 = highest current. [3:1] Reference current[2:0] Auxiliary ADC reference current. 1 000 = lowest current. 111 = highest current. 0 Capacitor value Auxiliary ADC internal capacitor value. 0 0 = 5 pF. 1 = 10 pF. Die Temp LSB 0x49 [7:0] Die temp[7:0] Die Temp[15:0] indicates the approximate die R temperature. 0xADCC = −39.9°C. 0xC422 = 25.1°C. … 0xD8A8 = 84.8°C (see the Temperature Sensor section for details). Die Temp MSB 0x4A [7:0] Die temp[15:8] See Register 0x49. R Rev. 0 | Page 27 of 56 AD9125 Register Address Name (Hex) Bits Name Description Default SED Control 0x67 7 SED compare enable 1 = enables the SED circuitry. None of the flags in this 0 register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled. 5 Sample error detected 1 = indicates an error is detected. The bit remains set 0 until cleared. Any write to this register clears this bit to 0. 3 Autoclear enable 0 1 = enables autoclear mode. This activates Bit 1 and Bit 0 of this register and causes Register 0x70 through Register 0x73 to be autocleared whenever eight consecutive error-free sample data sets are received. 1 Compare fail 1 = indicates an error has been detected. This bit 0 remains high until it is autocleared by the reception of eight consecutive error-free comparisons or until it is cleared by writing to this register. 0 Compare pass 1 = indicates that the last sample comparison was error free. 0 Compare I0 LSBs 0x68 [7:0] Compare Value I0[7:0] B6 Compare Value I0[15:0] is the word that is compared with the I0 input sample captured at the input interface. Compare I0 MSBs 0x69 [7:0] Compare Value I0[15:8] See Register 0x68. 7A Compare Q0 LSBs 0x6A [7:0] Compare Value Q0[7:0] Compare Value Q0[15:0] is the word that is compared 45 with the Q0 input sample captured at the input interface. Compare Q0 MSBs 0x6B [7:0] Compare Value See Register 0x6A EA Q0[15:8] Compare I1 LSBs 0x6C [7:0] Compare Value I1[7:0] Compare Value I1[15:0] is the word that is compared 16 with the I1 input sample captured at the input interface. Compare I1 MSBs 0x6D [7:0] Compare Value I1[15:8] See Register 0x6C. 1A Compare Q1 LSBs 0x6E [7:0] Compare Value Q1[7:0] Compare Value Q1[15:0] is the word that is compared C6 with the Q1 input sample captured at the input interface. Compare Q1 MSBs 0x6F [7:0] Compare Value See Register 0x6E. AA Q1[15:8] SED I LSBs 0x70 [7:0] Errors Detected Errors detected I_BITS[15:0] indicates which bits were 0 I_BITS[7:0] received in error. SED I MSBs 0x71 [7:0] Errors detected See Register 0x70. 0 I_BITS[15:8] SED Q LSBs 0x72 [7:0] Errors detected Errors detected Q_BITS[15:0] indicates which bits were 0 Q_BITS[7:0] received in error. SED Q MSBs 0x73 [7:0] Errors detected See Register 0x72. 0 Q_BITS[15:8] Die Revision 0x7F [5:2] Revision[3:0] Corresponds to device die revision. 3 1 All bit event flags are cleared by writing the respective bit high. Rev. 0 | Page 28 of 56 AD9125 CMOS INPUT DATA PORTS The AD9125 input data port consists of a data clock (DCI), WORD MODE data bus, and FRAME signal. The data port can be configured In word mode, the DCI signal is supplied as a qualifying clock to operate in three modes: dual-word mode, word mode, and that is time aligned with the input data. The rising edge of the byte mode. DCI signal should be aligned with the changing data of the In dual-word mode, I and Q data is received simultaneously on interleaved I and Q input data stream. The FRAME signal two 16-pin buses. One bus receives I datapath input words, and indicates to which DAC the data is sent. When FRAME is high, the other bus receives Q datapath input words. In word mode, data is sent to the I DAC. When FRAME is low, data is sent to one 16-pin bus is used to receive interleaved I and Q input the Q DAC. For 14- and 12-bit resolution devices, the two and words. In byte mode, an 8-pin bus is used to receive interleaved four LSBs are not significant, respectively. The complete timing I and Q input bytes. The pin assignments of the bus in each diagram is shown in Figure 43. mode is described in Table 12. DCI Table 12. Data Bit Pin Assignments for Data Input Modes Mode Data Bus Pin Assignments I AND I Q I 1 1 2 Q DATA Dual Word I data: D[31:16] Q data: D[15:0] Word I and Q data: D[29:28], D[25:24], D[21:20], D[17:16], FRAME D[15:14], D[11:10], D[7:6], D[3:2] Figure 43. Timing Diagram for Word Mode Byte I and Q data: D[21:20], D[17:16], D[15:14], D[11:10] BYTE MODE In byte and word modes, a FRAME signal is required for In byte mode, the DCI signal is supplied as a qualifying clock controlling which DAC receives the data. In dual-word mode, that is time aligned with the input data. The rising edge of the the FRAME signal is not required because each DAC has a DCI signal should be aligned with the changing data of the dedicated bus. interleaved I and Q input data stream. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, DUAL-WORD MODE data is sent to the I DAC. When FRAME is low, data is sent to In dual-word mode, the DCI signal is supplied as a qualifying the Q DAC. Both bytes must be written to each datapath for clock that is time aligned with the input data. The rising edge of proper operation. For 14- and 12-bit resolution devices, the the DCI signal should be aligned with the changing data of each LSBs in the second byte are not significant. The complete of the I and Q input data streams. timing diagram is shown in Figure 44. DCI DCI I AND I DATA I I I 2 Q I I Q Q I I Q Q 1 3 LSB 1MSB 1LSB 1MSB 1LSB 2MSB 2LSB 2MSB 2LSB Q DATA Q DATA Q Q Q 1 2 3 FRAME Figure 42. Timing Diagram for Dual-Word Mode Figure 44. Timing Diagram for Byte Mode Rev. 0 | Page 29 of 56 09016-142 09016-143 09016-144 AD9125 The data interface timing can be verified by using the sample INTERFACE TIMING error detection (SED) circuitry. See the Interface Timing The timing diagram for the digital interface port is shown in Validation section for details. Figure 45. The sampling point of the data bus occurs on the falling edge of the DCI signal and has an uncertainty of 2.1 ns, FIFO OPERATION as illustrated by the sampling interval shown in Figure 45. The The AD9125 contains a 2-channel, 16-bit wide, eight-word-deep D[31:0] and FRAME signals must be valid throughout this FIFO designed to relax the timing relationship between the data sampling interval. arriving at the DAC input ports and the internal DAC data rate The setup (tS) and hold (tH) times with respect to the edges clock. The FIFO acts as a buffer that absorbs timing variations are shown in Figure 45. The minimum setup and hold times between the data source and DAC, such as the clock-to-data are shown in Table 13. variation of an FPGA or ASIC, which significantly increases the timing budget of the interface. Figure 47 shows the block diagram of the datapath through the DCI FIFO. The data is latched into the device and is formatted, and then it is written into the FIFO register determined by the FIFO write pointer. The value of the write pointer is incremented every D[31:0] time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register determined by the read pointer and t t fed into the digital datapath. The value of the read pointer is S H updated every time data is read into the datapath from the FIFO. FRAME This happens at the data rate, that is, the DACCLK rate divided by the interpolation ratio. Figure 45. Timing Diagram for Input Data Ports Valid data is transmitted through the FIFO as long as the Table 13. Data Port Setup and Hold Times FIFO does not overflow or become empty. Note that an over- Minimum Setup Time, t (ns) Minimum Hold Time, t (ns) S H flow or empty condition of the FIFO is the same as the write 0.86 1.24 pointer and read pointer being equal. When both pointers are equal, an attempt is made to read and write a single FIFO register simultaneously. This simultaneous register access leads to unreliable data transfer through the FIFO and must be avoided. DCI Nominally, data is written to the FIFO at the same rate that data is t S-FRAME read from the FIFO, which keeps the data level in the FIFO constant. If data is written to the FIFO faster than data is read, the data level t H-FRAME in the FIFO increases. If data is written to the device slower than data is read, the data level in the FIFO decreases. For an optimum FRAME timing margin, the FIFO level should be maintained near half full, which is the same as maintaining a difference of four between Figure 46. Timing Diagram for Frame input the write pointer and read pointer values. Table 14. FRAME Setup and Hold Times Minimum Setup Time, tS-FRAME Minimum Hold Time, tH_FRAME (ns) (ns) −0.04 +1.05 32 BITS REG 0 REG 1 REG 2 16 16 DATA INPUT DATA REG 3 DACS DATA PATHS LATCH ASSEMBLER REG 4 REG 5 REG 6 REG 7 WRITE POINTER READ POINTER DCI ÷ INT DACCLK 32 BITS Figure 47. Block Diagram of Datapath Through FIFO Rev. 0 | Page 30 of 56 09016-147 09016-146 09016-018 AD9125 corresponds to one DCI period in dual-word mode, two DCI Initializing the FIFO Data Level periods in word mode, and four DCI periods in byte mode. To avoid a concurrent read and write to the same FIFO address To initiate a relative FIFO reset with the FRAME signal, the device and to ensure a fixed pipeline delay, it is important to initialize must be configured in data rate mode (Register 0x10, Bit 6). When the FIFO pointers to known states. The FIFO pointers can be FRAME is asserted in data rate mode, the write pointer is set to 4 initialized in two ways: via a write sequence to the serial port or (by default or to the FIFO start level) the next time the read pointer by strobing the FRAME input. There are two types of FIFO pointer becomes 0 (see Figure 48). resets: a relative reset and an absolute reset. A relative reset enforces a defined FIFO depth. An absolute reset enforces a particular READ 0 1 2 3 4 5 6 7 0 1 2 3 POINTER write pointer value when the reset is initiated. A serial port initiated FIFO reset is always a relative reset. A FRAME strobe FIFO WRITE RESETS FRAME initiated reset can be either a relative or an absolute reset. The operation of the FRAME initiated FIFO reset depends on WRITE 3 4 5 6 7 0 1 2 4 5 6 7 POINTER the synchronization mode chosen. When synchronization is Figure 48. FRAME Input vs. Write Pointer Value, Data Rate Mode disabled or when the device is configured for data rate mode synchronization, the FRAME strobe initiates a relative FIFO Write Pointer Initialization via FRAME Signal reset. When FIFO mode synchronization is chosen, the FRAME In FIFO rate synchronization mode, the REFCLK/SYNC signal strobe initiates an absolute FIFO reset. More details on the is used to reset the FIFO read pointer to 0. The edge of the synchronization function can be found in the Multichip DAC clock used to sample the SYNC signal is selected by Bit 3 Synchronization section. of Register 0x10. The FRAME signal is used to reset the FIFO A summary of the synchronization modes and the type of FIFO write pointer. In the FIFO rate synchronization mode, the FIFO reset employed is listed in Table 15. write pointer is reset immediately after the FRAME signal is asserted high for at least the time interval needed to load complete Table 15. Summary of FIFO Resets data to the I and Q DACs. The FIFO write pointer is initialized to Synchronization Mode FIFO the value of the FIFO phase offset[2:0] (Register 0x17). FIFO rate Reset Signal Disabled Data Rate FIFO Rate synchronization is selected by setting Bit 6 of Register 0x10 to 0. Serial Port Relative reset Relative reset Relative reset SYNC FIFO READ RESET FRAME Relative reset Relative reset Absolute reset READ 01 2 3 4 5 6 7 0 1 2 3 POINTER FIFO Level Initialization via Serial Port FIFO WRITE RESET FIFO PHASE OFFSET[2:0] FRAME A serial port initiated FIFO reset can be issued in any mode REGISTER 0x17, BITS[2:0] = 0b101 and always results in a relative FIFO reset. To initialize the FIFO WRITE 66 5 6 7 0 1 2 347 5 POINTER data level through the serial port, Bit 1 of Register 0x18 should Figure 49. FRAME Input vs. Write Pointer Value, FIFO Rate Mode be toggled from 0 to 1 and then back to 0. When the write to the register is complete, the FIFO data level is initialized. When the Monitoring the FIFO Status initialization is triggered, the next time the read pointer becomes The FIFO initialization and status can be read from Register 0x18. 0, the write pointer is set to the value of the FIFO phase offset level This register provides information on the FIFO initialization (Register 0x17, Bits[2:0]) variable upon initialization. By default, method and whether the initialization was successful. The MSB this is 4, but it can be programmed to a value between 0 and 7. of Register 0x18 is a FIFO warning flag that can optionally The recommended procedure for a serial port FIFO data level trigger a device interrupt (IRQ). This flag is an indication that initialization is as follows: the FIFO is close to emptying (FIFO level is 1) or overflowing 1. Request FIFO level reset by setting Register 0x18, Bit 1, to 1. (FIFO level is 7). This is an indication that data may soon be 2. Verify that the part acknowledges the request by ensuring corrupted and action should be taken. that Register 0x18, Bit 2, is 1. The FIFO data level can be read from Register 0x19 at any time. 3. Remove the request by setting Register 0x18, Bit 1, to 0. The FIFO data level reported by the serial port is denoted as a 4. Verify that the part drops the acknowledge signal by 7-bit thermometer code of the write counter state relative to the ensuring that Register 0x18, Bit 2, is 0. absolute read counter being at 0. The optimum FIFO data level of 4 is, therefore, reported as a value of 00001111 in the status register. It FIFO Level Initialization via FRAME Signal should be noted that, depending on the timing relationship between The primary function of the FRAME input is indicating to which DCI and the main DACCLK, the FIFO level value can be off by DAC the input data is written. Another function of the FRAME ±1 count. Therefore, it is important to keep the difference between input is initializing the FIFO data level value. This is done by the read and write pointers to at least 2. asserting the FRAME signal high for at least the time interval needed to load complete data to the I and Q DACs. This Rev. 0 | Page 31 of 56 09016-148 09016-019 AD9125 DIGITAL DATAPATH The block diagram in Figure 50 shows the functionality of the Half-Band Filter 1 (HB1) digital datapath. The digital processing includes a premodulation HB1 has four modes of operation, as shown in Figure 51. The block, three half-band interpolation filters, a quadrature modulator shape of the filter response is identical in each of the four modes. with a fine resolution NCO, a phase and offset adjustment The four modes are distinguished by two factors: the filter center block, and an inverse sinc filter. frequency and whether the input signal is modulated by the filter. MODE 0 MODE 2 MODE 1 MODE 3 0 PHASE AND –1 PREMOD HB1 HB2 HB3 SINC OFFSET ADJUST –20 Figure 50. Block Diagram of Digital Datapath The digital datapath accepts I and Q data streams and processes –40 them as a quadrature data stream. The signal processing blocks can be used when the input data stream is represented as complex data. –60 The datapath can be used to process an input data stream –80 representing two independent real data streams as well, but the functionality is somewhat restricted. The premodulation block can be used, as well as any of the nonshifted interpolation –100 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 filter modes (see the Premodulation section for more details). NORMALIZED FREQUENCY (× f ) IN1 PREMODULATION Figure 51. HB1 Filter Modes The half-band interpolation filters have selectable pass bands As shown in Figure 51, the center frequency in each mode is that allow the center frequencies to be moved in increments of offset by ½ the input data rate (f ) of the filter. Mode 0 and IN1 ½ of their input data rate. The premodulation block provides a Mode 1 do not modulate the input signal. Mode 2 and Mode 3 digital upconversion of the incoming waveform by ½ of the modulate the input signal by f . When HB1 operates in Mode 0 IN1 incoming data rate, fDATA. This can be used to frequency-shift and Mode 2, the I and Q paths operate independently and no baseband input data to the center of the interpolation filters’ mixing of the data between channels occurs. When HB1 operates pass band. in Mode 1 and Mode 3, mixing of the data between the I and Q paths occurs; therefore, the data input into the filter is assumed INTERPOLATION FILTERS complex. Table 16 summarizes the HB1 modes. The transmit path contains three interpolation filters. Each of the three interpolation filters provides a 2× increase in output data Table 16. HB1 Filter Mode Summary rate. The half-band (HB) filters can be individually bypassed or Mode f f Input Data CENTER MOD cascaded to provide 1×, 2×, 4×, or 8× interpolation ratios. Each 0 DC None Real or complex of the half-band filter stages offers a different combination of 1 fIN/2 None Complex bandwidths and operating modes. 2 f f Real or complex IN IN The bandwidth of the three half-band filters with respect to the 3 3f/2 f Complex IN IN data rate at the filter input is as follows: • Bandwidth of HB1 = 0.8 × fIN1 • Bandwidth of HB2 = 0.5 × f IN2 • Bandwidth of HB3 = 0.4 × f IN3 The usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than +85 dB. As is discussed in the Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. The half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. The HB1 filter has four modes of operation, and the HB2 and HB3 filters each have eight modes of operation. Rev. 0 | Page 32 of 56 09016-020 GAIN (dB) 09016-021 AD9125 Half-Band Filter 2 (HB2) Figure 52 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the HB2 has eight modes of operation, as shown in Figure 53 and image suppression provided by the stop-band rejection, not by Figure 54. The shape of the filter response is identical in each of the pass-band flatness. Table 17 shows the pass-band flatness the eight modes. The eight modes are distinguished by two factors: and stop-band rejection that the HB1 filter supports at different the filter center frequency and whether the input signal is bandwidths. modulated by the filter. 0.02 MODE 0 MODE 4 MODE 2 MODE 6 0 0 –20 –0.02 –40 –0.04 –60 –0.06 –80 –0.08 –100 –0.10 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 00 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36.40 NORMALIZED FREQUENCY (× f ) IN2 NORMALIZED FREQUENCY (× f ) IN1 Figure 53. HB2, Even Filter Modes Figure 52. Pass-Band Detail of HB1 MODE 7 MODE 1 MODE 5 MODE 3 Table 17. HB1 Pass-Band Flatness and Stop-Band Rejection 0 Pass-Band Stop-Band Bandwidth (% of fIN1) Flatness (dB) Rejection (dB) –20 80 0.001 85 80.4 0.0012 80 –40 81.2 0.0033 70 82.0 0.0076 60 –60 83.6 0.0271 50 85.6 0.1096 40 –80 –100 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 NORMALIZED FREQUENCY (× f ) IN2 Figure 54. HB2, Odd Filter Modes As shown in Figure 53 and Figure 54, the center frequency in each mode is offset by ¼ of the input data rate (f ) of the filter. IN2 Mode 0 through Mode 3 do not modulate the input signal. Mode 4 through Mode 7 modulate the input signal by fIN2. When HB2 operates in Mode 0 and Mode 4, the I and Q paths operate independently and no mixing of the data between channels occurs. When HB2 operates in the other six modes, mixing of the data between the I and Q paths occurs; therefore, the data input to the filter is assumed complex. Rev. 0 | Page 33 of 56 GAIN (dB) 09016-022 GAIN (dB) GAIN (dB) 09016-024 09016-023 AD9125 Table 18 summarizes the HB2 and HB3 modes. Half-Band Filter 3 (HB3) HB3 has eight modes of operation that function the same as Table 18. HB2 and HB3 Filter Mode Summary HB2. The primary difference between HB2 and HB3 is the filter Mode f f Input Data CENTER MOD bandwidths. 0 DC None Real or complex Figure 56 shows the pass-band filter response for HB3. In most 1 f/4 None Complex IN applications, the usable bandwidth of the filter is limited by the 2 f/2 None Complex IN image suppression provided by the stop-band rejection, not by 3 3f/4 None Complex IN the pass-band flatness. Table 20 shows the pass-band flatness 4 fIN fIN Real or complex and stop-band rejection that the HB3 filter supports at different 5 5fIN/4 fIN Complex bandwidths. 6 6fIN/4 fIN Complex 0.02 7 7f/4 f Complex IN IN 0 Figure 55 shows the pass-band filter response for HB2. In most applications, the usable bandwidth of the filter is limited by the –0.02 image suppression provided by the stop-band rejection, not by the pass-band flatness. Table 19 shows the pass-band flatness –0.04 and stop-band rejection that the HB2 filter supports at different bandwidths. –0.06 0.02 –0.08 0 –0.10 00 0.04 0.08 0.12 0.16 0.20 0.24.28 –0.02 NORMALIZED FREQUENCY (× f ) IN3 Figure 56. Pass-Band Detail of HB3 –0.04 Table 20. HB3 Pass-Band Flatness and Stop-Band Rejection –0.06 Complex Bandwidth Pass-Band Stop-Band (% of f ) Flatness (dB) Rejection (dB) IN3 –0.08 40 0.001 85 40.8 0.0014 80 –0.10 00 0.04 0.08 0.12 0.16 0.20 0.24 0.28.32 42.4 0.002 70 NORMALIZED FREQUENCY (× f ) IN2 45.6 0.0093 60 Figure 55. Pass-Band Detail of HB2 49.8 0.03 50 55.6 0.1 40 Table 19. HB2 Pass-Band Flatness and Stop-Band Rejection Complex Bandwidth Pass-Band Stop-Band (% of f ) Flatness (dB) Rejection (dB) IN2 50 0.001 85 50.8 0.0012 80 52.8 0.0028 70 56.0 0.0089 60 60 0.0287 50 64.8 0.1877 40 Rev. 0 | Page 34 of 56 GAIN (dB) 09016-025 GAIN (dB) 09016-026 AD9125 NCO MODULATION DATAPATH CONFIGURATION The digital quadrature modulator makes use of a numerically Configuring the AD9125 datapath starts with the application controlled oscillator, a phase shifter, and a complex modulator requirements of the input data rate, the interpolation ratio, the to provide a means for modulating the signal by a programmable output signal bandwidth, and the output signal center frequency. carrier signal. A block diagram of the digital modulator is shown in Given these four parameters, the first step in configuring the Figure 57. The fine modulation provided by the digital modulator, datapath is to verify that the device supports the bandwidth in conjunction with the coarse modulation of the interpolation requirements. The modes of the interpolation filters are then filters and premodulation block, allows the signal to be placed chosen. Finally, any additional frequency offset requirements anywhere in the output spectrum with very fine frequency are determined and applied with premodulation and NCO resolution. modulation. Determining Datapath Signal Bandwidth INTERPOLATION I DATA The available signal bandwidth of the datapath is dependent on the center frequency of the output signal in relation to the center COSINE frequency of the interpolation filters used. Signal center frequencies FTW[31:0] NCO that are offset from the center frequencies of the half-band NCO PHASE OFFSET I OUTPUT [15:0] SINE filters lower the available signal bandwidth. Q OUTPUT – When correctly configured, the available complex signal band- + width for 2× interpolation is always 80% of the input data rate. –1 The available signal bandwidth for 4× interpolation vs. output SPECTRAL 0 1 frequency varies between 50% and 80% of the input data rate, INVERSION as shown in Figure 58. Note that in 4× interpolation mode, fDAC = 4 × fDATA; therefore, the data shown in Figure 58 repeats Q DATA INTERPOLATION four times from dc to fDAC. Figure 57. Digital Quadrature Modulator Block Diagram HB1 AND HB2 The quadrature modulator is used to mix the carrier signal 0.8 generated by the NCO with the I and Q signal. The NCO produces a quadrature carrier signal to translate the input signal to a new center frequency. A complex carrier signal is a pair of sinusoidal 0.5 waveforms of the same frequency, offset 90° from each other. HB2 AND HB3 The frequency of the complex carrier signal is set via FTW[31:0] 0.3 in Register 0x30 through Register 0x33. The NCO operating frequency, f , is at either f (HB1 NCO DATA bypassed) or twice f (HB1 enabled). The frequency of DATA 0.2 0.4 0.6 0.8 1.0 the complex carrier signal can be set from dc up to fNCO. The f /f OUT DATA frequency tuning word (FTW) is calculated as Figure 58. Signal Bandwidth vs. Center Frequency of the Output Signal, f 4× Interpolation CARRIER 32 FTW= ×2 f NCO Configuring 4× interpolation using the HB2 and HB3 filters can lower the power consumption of the device at the expense The generated quadrature carrier signal is mixed with the I and of reduced bandwidth. The lower curve in Figure 58 shows that the Q data. The quadrature products are then summed into the I supported bandwidth in this mode varies from 30% to 50% of fDATA. and Q datapaths, as shown in Figure 57. The available signal bandwidth for 8× interpolation vs. output Updating the Frequency Tuning Word frequency varies between 50% and 80% of the input data rate, The frequency tuning word registers do not update immediately as shown in Figure 59. Note that in 8× interpolation mode, upon writing as other configuration registers. After loading the fDAC = 8 × fDATA; therefore, the data shown in Figure 59 repeats FTW registers with the desired values, Bit 0 of Register 0x36 eight times from dc to fDAC. must transition from 0 to 1 for the new FTW to take effect. Rev. 0 | Page 35 of 56 09016-027 BANDWIDTH/f DATA 09016-028 AD9125 DETERMINING INTERPOLATION FILTER MODES HB1, HB2, AND HB3 0.8 Table 21 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, 0.6 and signal modulation. The interpolation modes were chosen based on the final center frequency of the signal and by 0.5 determining the frequency shift of the signal required. When these are known and put in terms of the input data rate (f ), DATA the filter configuration that comes closest to matching should be chosen from Table 21. 0.1 0.4 0.6 0.9 0.25 0.50 0.75 1.00 f /f OUT DATA Figure 59. Signal Bandwidth vs. Center Frequency of the Output Signal, 8× Interpolation Table 21. Recommended Interpolation Filter Modes (Register 0x1C through Register 0x1E) Filter Modes Interpolation Factor HB1[1:0] HB2[5:0] HB3[5:0] fSIGNAL Modulation fCENTER Shift 8 00 (0) 000000 000000 DC 0 1 8 01 (1) 001001 000000 DC f /2 DATA 2 8 10 (2) 010010 001001 fDATA fDATA 1 8 11 (3) 011011 001001 fDATA 3 × fDATA/2 8 00 (0) 100100 010010 2 × fDATA 2 × fDATA 1 8 01 (1) 101101 010010 2 × f 5 × f /2 DATA DATA 8 10 (2) 110110 011011 3 × f 3 × f DATA DATA 1 8 11 (3) 111111 011011 3 × fDATA 7 × fDATA/2 8 00 (0) 000000 100100 4 × fDATA 4 × fDATA 1 8 01 (1) 001001 100100 4 × fDATA 9 × fDATA/2 8 10 (2) 010010 101101 5 × f 5 × f DATA DATA 1 8 11 (3) 011011 101101 5 × f 11 × f /2 DATA DATA 8 00 (0) 100100 110110 6 × f 6 × f DATA DATA 1 8 01 (1) 101101 110110 6 × fDATA 13 × fDATA/2 8 10 (2) 110110 111111 7 × fDATA 7 × fDATA 1 8 11 (3) 111111 111111 7 × fDATA 15 × fDATA/2 4 00 (0) 000000 Bypass DC 0 3 1 4 01 (1) 001001 Bypass DC fDATA/2 4 10 (2) 010010 Bypass f f DATA DATA 1 4 11 (3) 011011 Bypass f 3 × f /2 DATA DATA 4 00 (0) 100100 Bypass 2 × f 2 × f DATA DATA 1 4 01 (1) 101101 Bypass 2 × fDATA 5 × fDATA/2 4 10 (2) 110110 Bypass 3 × fDATA 3 × fDATA 1 4 11 (3) 111111 Bypass 3 × fDATA 7 × fDATA/2 2 00 (0) Bypass Bypass DC 0 1 2 01 (1) Bypass Bypass DC fDATA/2 2 10 (2) Bypass Bypass fDATA fDATA 1 2 11 (3) Bypass Bypass f 3 × f /2 DATA DATA 1 When HB1 Mode 1 or Mode 3 is used, enabling premodulation provides an addition frequency translation of the input signal by f /2, which centers a baseband DATA input signal in the filter pass band. 2 This configuration was used in the 8× interpolation without NCO example. In addition, see the 8× Interpolation Without NCO section. 3 This configuration was used in the 4× interpolation with NCO example. In addition, see the 4× Interpolation with NCO section Rev. 0 | Page 36 of 56 BANDWIDTH/f DATA 09016-029 AD9125 4× Interpolation with NCO DATAPATH CONFIGURATION EXAMPLE 8× Interpolation Without NCO Given the following conditions, the desired 140 MHz of bandwidth is 56% of fDATA: Given the following conditions, the desired 75 MHz of bandwidth is 75% of f : DATA • fDATA = 250 MSPS • 4× interpolation • f = 100 MSPS DATA • fBW = 140 MHz • 8× interpolation • fCENTER = 175 MHz • f = 75 MHz BW • f = 100 MHz CENTER As shown in Figure 58, the value at 0.7 × fDATA is 0.6. This is calculated as 0.8 − 2(0.7 − 0.6) = 0.6. Therefore, the AD9125 In this case, the ratio of f /f = 100/100 = 1.0. From Figure 59, OUT DATA supports a bandwidth of 60% of fDATA, which exceeds the the bandwidth supported at f is 0.8, which verifies that the DATA required 56%. AD9125 supports the bandwidth required in this configuration. The signal center frequency is 0.7 × f , and assuming the DATA The signal center frequency is fDATA, and assuming the input input signal is at baseband, the frequency shift required is also signal is at baseband, the frequency shift required is also fDATA. 0.7 × f . Using the settings detailed in the second row in the IF DATA Using the settings detailed in the third row of the IF column column in the 4× interpolation section in Table 21 selects the from Table 21 (these settings use the configuration in the 8× filter modes that give a center frequency of fDATA/2 and no interpolation without NCO example) selects filter modes that frequency translation. The selected modes for the three half- result in a center frequency of f and a frequency translation DATA band filters are HB1, Mode 1; HB2, Mode 1; and HB3, . The selected modes for the three half-band filters are of fDATA bypassed. HB1, Mode 2; HB2, Mode 2; and HB3, Mode 1. Figure 60 shows how the signal propagates through the interpolation filters. Because Mode 1 of HB1 was selected, the premodulation block should be enabled. This provides f /2 modulation, which DATA Because 2 × fIN1 = fIN2 and 2 × fIN2 = fIN3, the signal appears centers the baseband input data at the center frequency of HB1. frequency scaled by ½ into each consecutive stage. The output The digital modulator can be used to provide the final frequency signal band spans 0.15 to 0.35 of f (400 MHz). Therefore, IN3 translation of 0.2 × fDATA to place the output signal at 0.7 × fDATA, the output frequency supported is 60 MHz to 140 MHz, which as desired. covers the 75 MHz bandwidth centered at 100 MHz, as desired. The formula for calculating the FTW of the NCO is f CARRIER 32 FTW= ×2 f NCO where: f = 0.2 × f . CARRIER DATA 32 f = 2 × f . Therefore, FTW = 2 /10. NCO DATA 0 2 0 1 3 HB1 0.1 0.4 0.6 × f IN1 –0.5 0 0.5 1.0 1.5 2.0 1 3 5 7 0 4 HB2 2 6 0.25 0.75 1.25 1.75 × f IN2 –0.5 0 0.5 1.0 1.5 2.0 0.3 0.7 0 1 3 5 7 4 HB3 2 6 –0.2 0.2 0.3 0.7 × f IN3 –0.5 0 0.5 1.0 1.5 2.0 0.15 0.35 Figure 60. Signal Propagation for 8× Interpolation (f Modulation) DATA Rev. 0 | Page 37 of 56 09016-030 AD9125 In practice, this modulation results in mixing functions as DATA RATES VS. INTERPOLATION MODES shown in Table 22. Table 23 summarizes the maximum bus speed (fBUS), the supported input data rates, and the signal bandwidths for Table 22. Modulation Mixing Sequences various combinations of bus width modes and interpolation Modulation Mixing Sequence rates. The maximum bus speed in any mode is 250 MHz. The fS/2 I = I, −I, I, −I, … maximum DAC update rate (f ) in any mode is 1000 MHz. DAC Q = Q, −Q, Q, −Q, … The real signal bandwidth supported is a fraction of the input fS/4 I = I, Q, −I, −Q, … data rate, which depends on the interpolation filter (HB1, HB2, Q = Q, −I, −Q, I, … or HB3) selected. The complex signal bandwidth supported is 3 × fS/4 I = I, −Q, −I, Q, … twice the real signal bandwidth. Q = Q, I, −Q, −I, … In general, 2× interpolation is best supported by enabling HB1, fS/8 I = I, r(I + Q), Q, r(−I + Q), −I, −r(I + Q), −Q, r(I − Q), … and 4× interpolation is best supported enabling HB1 and HB2. Q = Q, r(Q − I), −I, −r(Q + I), −Q, r(−Q + I),I, r(Q + I), … In some cases, power dissipation can be lowered by avoiding 2 HB1. If the bandwidth required is low enough, 2× interpolation Note that r= 2 can be supported by using HB2, and 4× interpolation can be supported by using HB2 and HB3. As shown in Table 22, the mixing functions of most of the modes result in cross coupling samples between the I and Q channels. COARSE MODULATION MIXING SEQUENCES The I and Q channels only operate independently in fS/2 mode. The coarse digital quadrature modulation occurs within the This means that real modulation using both the I and Q DAC interpolation filters. The modulation shifts the frequency outputs can only be done in fS/2 mode. All other modulation spectrum of the incoming data by the frequency offset selected. modes require complex input data and produce complex output The frequency offsets available are multiples of the input data signals. rate. The modulation is equivalent to multiplying the quadrature input signal by a complex carrier signal, C(t), of the form C(t) = cos(ω t) + j sin(ω t) c c Table 23. Summary of Data Rates and Bandwidths vs. Interpolation Modes Filter Modes Bus Width HB3 HB2 HB1 f (Mbps) f (Mbps) Real Signal Bandwidth (MHz) f (MHz) BUS DATA DAC Byte Mode 0 0 0 250 62.5 31.25 62.5 (8 Bits) 0 0 1 250 62.5 25 125 0 1 0 250 62.5 15.625 125 0 1 1 250 62.5 25 250 1 1 0 250 62.5 15.625 250 1 1 1 250 62.5 25 500 Word Mode 0 0 0 250 125 62.5 125 (16 Bits) 0 0 1 250 125 50 250 0 1 0 250 125 31.25 250 0 1 1 250 125 50 500 1 1 0 250 125 31.25 500 1 1 1 250 125 50 1000 Dual-Word Mode 0 0 0 250 250 125 250 (32 Bits) 0 0 1 250 250 100 500 0 1 0 250 250 62.5 500 0 1 1 250 250 100 1000 1 1 0 250 250 62.5 1000 1 1 1 125 125 50 1000 Rev. 0 | Page 38 of 56 AD9125 QUADRATURE PHASE CORRECTION 20 0 The purpose of the quadrature phase correction block is to enable compensation of the phase imbalance of the analog quadrature modulator following the DAC. If the quadrature 15 5 modulator has a phase imbalance, the unwanted sideband appears with significant energy. Tuning the quadrature phase adjust value 10 10 can optimize image rejection in single sideband radios. Ordinarily, the I and Q channels have an angle of precisely 90° 5 15 between them. The quadrature phase adjustment is used to change the angle between the I and Q channels. When the I phase adjust[9:0] is set to 1000000000, the I DAC output 20 0 moves approximately 1.75° away from the Q DAC output, 0x0000 0x4000 0x8000 0xC000 0xFFFF DAC OFFSET VALUE creating an angle of 91.75° between the channels. When the I phase adjust[9:0] is set to 0111111111, the I DAC output moves Figure 61. DAC Output Currents vs. DAC Offset Value approximately 1.75° toward the Q DAC output, creating an INVERSE SINC FILTER angle of 88.25° between the channels. −1 The inverse sinc (sinc ) filter is a nine-tap FIR filter. The The Q phase adjust bits (Bits[9:0]) work in a similar fashion. −1 composite response of the sinc and the sin(x)/x response of When the Q phase adjust[9:0]) is set to 1000000000, the Q DAC the DAC is shown in Figure 62. The composite response has less output moves approximately 1.75° away from the I DAC output, than ±0.05 dB pass-band ripple up to a frequency of 0.4 × f . DACCLK creating an angle of 91.75° between the channels. When the To provide the necessary peaking at the upper end of the pass Q phase adjust[9:0] is set to 0111111111, the Q DAC output band, the inverse sinc filters have an intrinsic insertion loss of moves approximately 1.75° toward the I DAC output, creating about 3.2 dB. Figure 62 shows the composite frequency response. an angle of 88.25° between the channels. –3.0 Based on these two endpoints, the combined resolution of the phase compensation register is approximately 3.5°/1024, or –3.2 0.00342°, per code. DC OFFSET CORRECTION –3.4 The dc value of the I datapath and the Q datapath can be inde- pendently controlled by adjusting the I DAC offset[15:0] and –3.6 Q DAC offset[15:0] values in Register 0x3C through Register 0x3F. These values are added directly to the datapath values. Care should –3.8 be taken not to overrange the transmitted values. Figure 61 shows how the DAC offset current varies as a function of –4.0 the I DAC offset[15:0] and Q DAC offset[15:0] values. With the 00 0.1 0.2 0.3 0.4.5 digital inputs fixed at midscale (0x0000, twos complement data f /f OUT DAC format), Figure 61 shows the nominal IOUTxP and IOUTxN currents −1 Figure 62. Sample Composite Responses of the Sinc Filter with Sin(x)/x Roll-Off as the DAC offset value is swept from 0 to 65,535. Because IOUTxP −1 The sinc filter is enabled by default. It can be bypassed by setting and IOUTxN are complementary current outputs, the sum of IOUTxP −1 the bypass sinc bit (Register 0x1B, Bit 6). and I is always 20 mA. OUTxN Rev. 0 | Page 39 of 56 I (mA) OUTxP MAGNITUDE (dB) I (mA) OUTxN 09016-032 09016-031 AD9125 DAC INPUT CLOCK CONFIGURATIONS The minimum input drive level to either clock input is DAC INPUT CLOCK CONFIGURATIONS 200 mV p-p differential. The optimal performance is achieved The AD9125 DAC sample clock (DACCLK) can be sourced when the clock input signal is between 800 mV p-p differential and directly or by clock multiplying. Clock multiplying employs the 1.6 V p-p differential. Whether using the on-chip clock multiplier on-chip phased-locked loop (PLL) that accepts a reference clock or sourcing the DACCLK directly, it is necessary that the input operating at a submultiple of the desired DACCLK rate, most clock signal to the device has low jitter and fast edge rates to commonly the data input frequency. The PLL then multiplies optimize the DAC noise performance. the reference clock up to the desired DACCLK frequency, which Direct Clocking can be used to generate all the internal clocks required by the DAC. The clock multiplier provides a high quality clock that Direct clocking with a low noise clock produces the lowest noise meets the performance requirements of most applications. Using spectral density at the DAC outputs. To select the differential clock the on-chip clock multiplier removes the burden of generating inputs as the source for the DAC sampling clock, set the PLL and distributing the high speed DACCLK. enable bit (Register 0x0A, Bit 7) to 0. This powers down the internal PLL clock multiplier and selects the input from the The second mode bypasses the clock multiplier circuitry and DACCLKP and DACCLKN pins as the source for the internal allows DACCLK to be sourced directly to the DAC core. This DAC sample clock. mode enables the user to source a very high quality clock directly to the DAC core. Sourcing the DACCLK directly through the The device also has duty-cycle correction circuitry and differential REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may input-level correction circuitry. Enabling these circuits can provide be necessary in demanding applications that require the lowest improved performance in some cases. The control bits for these possible DAC output noise, particularly when directly synthesizing functions can be found in Register 0x08 (see Table 11). signals above 150 MHz. Clock Multiplication Driving the DACCLK and REFCLK Inputs The on-chip PLL clock multiplier circuit can be used to generate The REFCLK and DACCLK differential inputs share similar the DAC sample rate clock from a lower frequency reference clock receiver input circuitry. Figure 63 shows a simplified circuit clock. When the PLL enable bit (Register 0x0A, Bit 7) is set to 1, diagram of the input. The on-chip clock receiver has a differential the clock multiplication circuit generates the DAC sample clock input impedance of about 10 kΩ. It is self-biased to a common- from the lower rate REFCLK input. The functional diagram of the clock multiplier is shown in Figure 64. mode voltage of about 1.25 V. The inputs can be driven by directly coupling differential PECL or LVDS drivers. The inputs can also be The clock multiplication circuit operates such that the VCO ac-coupled if the driving source cannot meet the input compliance outputs a frequency, fVCO, equal to the REFCLK input signal voltage of the receiver. frequency multiplied by N1 × N0. DACCLKP, REFCLKP fVCO = fREFCLK × (N1 × N0) 5kΩ The DAC sample clock frequency, fDACCLK, is equal to 1.25V f = f × N1 DACCLK REFCLK 5kΩ The output frequency of the VCO must be chosen to keep f VCO DACCLKN, in the optimal operating range of 1.0 GHz to 2.1 GHz. The REFCLKN Figure 63. Clock Receiver Input Equivalent Circuit frequency of the reference clock and the values of N1 and N0 must be chosen so that the desired DACCLK frequency can be synthesized and the VCO output frequency is in the correct range. REGISTER 0x06, BITS[7:6] REGISTER 0x0E, BITS[3:0] PLL LOCK LOST ADC VCO CONTROL PLL LOCKED VOLTAGE REFCLKP/REFCLKN PHASE LOOP (PIN 69 AND PIN 70) VCO DETECTION FILTER ÷N1 ÷N0 REGISTER 0x0D, REGISTER 0x0D, BITS[1:0] BITS[3:2] N1 N0 DACCLK DACCLKP/DACCLKN (PIN 2 AND PIN 3) REGISTER 0x0D, BITS[7:6] ÷N2 N2 REGISTER 0x0A, BIT 7 PLL ENABLE PLL LOGIC CONTROL CLOCK Figure 64. PLL Clock Multiplication Circuit Rev. 0 | Page 40 of 56 09016-033 09016-034 AD9125 PLL Settings Manual VCO Band Select There are three settings for the PLL circuitry that should be The device also has a manual band select mode (PLL manual programmed to their nominal values. Table 24 lists the enable, Register 0x0A, Bit 6 = 1) that allows the user to select recommended PLL settings for these parameters. the VCO tuning band. When in manual mode, the VCO band is set directly with the value written to the manual VCO band, Table 24. PLL Settings (Register 0x0A, Bits[5:0]). To properly select the VCO band, Address Optimal follow these steps: PLL SPI Control Register Bits Setting 1. Put the device in manual band select mode. PLL Loop Bandwidth[2:0] 0x0C [7:5] 110 2. Sweep the VCO band over a range of bands that result in PLL Charge Pump Current[4:0] 0x0C [4:0] 10001 the PLL being locked. PLL Cross Control Enable 0x0D 4 1 3. For each band, verify that the PLL is locked and read the PLL using the VCO control voltage (Register 0x0E, Configuring the VCO Tuning Band Bits[3:0]). The PLL VCO has a valid operating range from approximately 4. Select the band that results in the control voltage being 1.0 GHz to 2.1 GHz, covered in 63 overlapping frequency bands. closest to the center of the range, that is, 0000 or 1000 (see For any desired VCO output frequency, there may be several valid Table 25 for more details). The resulting VCO band should PLL band select values. The frequency bands of a typical device be the optimal setting for the device. Write this band to the are shown in Figure 65. Device-to-device variations and operating manual VCO band (Register 0x0A, Bits[5:0]) value. temperature affect the actual band frequency range. Therefore, 5. If desired, an indication of where the VCO is within the it is required that the optimal PLL band select value be determined operating frequency band can be determined by querying for each individual device. the VCO control voltage. Table 25 shows how to interpret the PLL VCO control voltage (Register 0x0E, Bits[3:0]) value. Automatic VCO Band Select The device has an automatic VCO band select feature on chip. Table 25. VCO Control Voltage Range Indications Using the automatic VCO band select feature is a simple and VCO Control Voltage Indication reliable method of configuring the VCO frequency band. This 1111 Move to a higher VCO band feature is enabled by writing 0x80 to Register 0x0A. When this 1110 value is written, the device executes an automated routine that 1101 VCO is operating in the higher end of determines the optimal VCO band setting for the device. The the frequency band 1100 setting selected by the device ensures that the PLL remains 1011 locked over the full −40°C to +85°C operating temperature 1010 range of the device without further adjustment. (The PLL 1001 VCO is operating within an optimal remains locked over the full temperature range even if the region of the frequency band 1000 temperature during initialization is at one of the temperature 0111 extremes.) 0110 0 0101 VCO is operating in the lower end of 4 the frequency band 8 0100 12 0011 16 0010 20 24 0001 Move to a lower VCO band 28 0000 32 36 40 44 48 52 56 60 1000 1200 1400 1600 1800 2000 2200 VCO FREQUENCY (MHz) Figure 65. PLL Lock Range over Temperature for a Typical Device Rev. 0 | Page 41 of 56 PLL BAND 09016-035 AD9125 ANALOG OUTPUTS For nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC gain TRANSMIT DAC OPERATION (512), the full-scale current of the DAC is typically 20.16 mA. Figure 66 shows a simplified block diagram of the transmit path The DAC full-scale current can be adjusted from 8.66 mA to DACs. The DAC core consists of a current source array, a switch 31.66 mA by setting the DAC gain code, as shown in Figure 67. core, a digital control logic, and a full-scale output current 35 control. The DAC full-scale output current (IOUTFS) is nominally 20 mA. The output currents from the IOUT1P/IOUT2P and 30 IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of 25 the DAC. The digital input code to the DAC determines the 20 effective differential current delivered to the load. 15 I DAC FS ADJUST 1.2V REGISTER 0x40 IOUT1P I DAC 10 5kΩ IOUT1N REFIO CURRENT 5 0.1µF SCALING FSADJ IOUT2N 10kΩ 0 Q DAC 0 200 400 600 800 1000 IOUT2P DAC GAIN CODE Q DAC FS ADJUST REGISTER 0x44 Figure 67. DAC Full-Scale Current vs. DAC Gain Code Figure 66. Simplified Block Diagram of DAC Core Transmit DAC Transfer Function The DAC has a 1.2 V band gap reference with an output impedance The output currents from the IOUT1P/IOUT2P and IOUT1N/ of 5 kΩ. The reference output voltage appears on the REFIO pin. IOUT2N pins are complementary, meaning that the sum of the When using the internal reference, the REFIO pin should be two currents always equals the full-scale current of the DAC. decoupled to AVSS with a 0.1 μF capacitor. Only use the internal The digital input code to the DAC determines the effective reference for external circuits that draw dc currents of 2 μA or differential current delivered to the load. IOUT1P/IOUT2P less. For dynamic loads or static loads greater than 2 μA, buf- provide maximum output current when all bits are high. The fer the REFIO pin. If desired, an external reference (between output currents vs. DACCODE for the DAC outputs are 1.10 V and 1.30 V) can be applied to the REFIO pin. The internal expressed as reference can either be overdriven or powered down by setting Register 0x43, Bit 5. DACCODE ⎡ ⎤ I = × I (1) OUTP OUTFS N ⎢ ⎥ 2 ⎣ ⎦ A 10 kΩ external resistor, RSET, must be connected from the FSADJ pin to AVSS. This resistor, along with the reference I = I − I (2) OUTN OUTFS OUTP control amplifier, sets up the correct internal bias currents for N where DACCODE = 0 to 2 − 1. the DAC. Because the full-scale current is inversely proportional to this resistor, the tolerance of R is reflected in the full-scale Transmit DAC Output Configurations SET output amplitude. The optimum noise and distortion performance of the AD9125 is realized when it is configured for differential operation. The The full-scale current equation, where the DAC gain is set indi- common-mode error sources of the DAC outputs are significantly vidually for the I and Q DACs in Register 0x40 and Register 0x44, reduced by the common-mode rejection of a transformer or respectively, follows: differential amplifier. These common-mode error sources include V ⎛ 3 ⎞ ⎛ ⎞ REF even-order distortion products and noise. The enhancement in I = × 72+ × DAC gain ⎜ ⎟ ⎜ ⎟ FS R 16 ⎝ ⎠ ⎝ ⎠ SET distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Rev. 0 | Page 42 of 56 09016-037 I (mA) FS 09016-036 AD9125 –60 Figure 68 shows the most basic DAC output circuitry. A pair of 10mA 20mA resistors, R , is used to convert each of the complementary output O 30mA –65 currents to a differential voltage output, V . Because the current OUT outputs of the DAC are high impedance, the differential driving –70 point impedance of the DAC outputs, ROUT, is equal to 2 × RO. Figure 69 illustrates the output voltage waveforms. –75 + V IP IOUT1P R O –80 V OUTI R O V – IN –85 IOUT1N –90 01 0.2 0.4 0.6 0.8 1.0 1.2.4 V + QP IOUT2P V (V) CMD R Figure 70. IMD vs. Common-Mode Output Voltage (f = 61 MHz, O OUT V R = 50 Ω differential, I = 10 mA, 20 mA, and 30 mA) OUTQ LOAD FS R O –50 V – QN 10mA IOUT2N 20mA –55 30mA Figure 68. Basic Transmit DAC Output Circuit V PEAK –60 V –65 CM –70 0 V V –75 P N –80 V OUT –V PEAK –85 Figure 69. Voltage Output Waveforms 01 0.2 0.4 0.6 0.8 1.0 1.2.4 V (V) CMD The common-mode signal voltage, V , is calculated as CM Figure 71. IMD vs. Common-Mode Output Voltage (fOUT = 161 MHz, I RLOAD = 50 Ω differential, IFS = 10 mA, 20 mA, and 30 mA) FS V = × R CM O 2 AUXILIARY DAC OPERATION The peak output voltage, V , is calculated as PEAK The AD9125 has two auxiliary DACs; one is associated with the V = I × R PEAK FS O I path, and the other is associated with the Q path. These auxiliary DACs can be used to compensate for dc offsets in the transmitted With this circuit configuration, the single-ended peak voltage is signal. Each auxiliary DAC has a single-ended current that can sink the same as the peak differential output voltage. or source current into either the P or N output of the associated Transmit DAC Linear Output Signal Swing transmit DAC. The auxiliary DAC structure is shown in Figure 72. To achieve optimum performance, the DAC outputs have a linear AVDD3 output compliance voltage range that must be adhered to. The linear output signal swing is dependent on the full-scale output AUX DAC current, IOUTFS, and the common-mode level of the output. Figure 70 and Figure 71 show the IMD performance vs. the AUX DAC CURRENT common-mode output voltage at various full-scale currents and DIRECTION output frequencies. AUX DAC SIGN IOUTP I DAC IOUTN Figure 72. Auxiliary DAC Structure The control registers for controlling the I and Q auxiliary DACs are in Register 0x42, Register 0x43, Register 0x46, and Register 0x47. Rev. 0 | Page 43 of 56 09016-038 09016-039 IMD (dBc) IMD (dBc) 09016-040 09016-169 09016-168 AD9125 Interfacing to Modulators DRIVING THE ADL5375-15 The AD9125 interfaces to the ADL537x family of modulators The ADL5375-15 is the version of the ADL5375 that offers an with a minimal number of components. An example of the input baseband bias levels of 1500 mV. Because the ADL5375-15 recommended interface circuitry is shown in Figure 73. requires a 1500 mV dc bias, it requires a slightly more complex interface than most other Analog Devices, Inc., modulators. The The baseband inputs of the ADL537x family require a dc bias DAC output must be level-shifted from a 500 mV dc bias to the of 500 mV. The nominal midscale output current on each output 1500 mV dc bias. Level-shifting can be achieved with a purely of the DAC is 10 mA (½ the full-scale current). Therefore, a passive network, as shown in Figure 74. In this network, the single 50 Ω resistor to ground from each DAC output results in dc bias of the DAC remains at 500 mV while the input to the the desired 500 mV dc common-mode bias for the inputs to the ADL5375-15 is 1500 mV. This passive level-shifting network ADL537x. The signal level can be reduced through the addition introduces approximately 2 dB of loss in the ac signal. of the load resistor in parallel with the modulator inputs. The peak-to-peak voltage swing of the transmitted signal is AD9125 ADL5375-15 R SIN 67 1kΩ 21 [] 2× R × R IOUT1P IBBP B L V = I × SIGNAL FS R R BIP LIP [] 2× R + R B L 45.3Ω 3480Ω 5V R R BIN R LIN SIP 66 45.3Ω 3480Ω 22 1kΩ AD9125 ADL537x IOUT1N IBBN 67 IOUT1P IBBP R SQN R 59 1kΩ 9 BIP R IOUT2N QBBN 50Ω LI 100Ω R R R BQN LQN BIN 45.3Ω 3480Ω 50Ω 66 5V IOUT1N IBBN R R BQP R LQP SQP 58 45.3Ω 3480Ω 10 1kΩ IOUT2P QBBP 59 IOUT2N QBBN R BQN Figure 74. Passive Level-Shifting Network for Biasing ADL5375-15 50Ω R LQ R 100Ω BQP REDUCING LO LEAKAGE AND UNWANTED 58 50Ω IOUT2P QBBP SIDEBANDS Analog quadrature modulators can introduce unwanted signals at Figure 73. Typical Interface Circuitry Between the AD9125 and the ADL537x Family of Modulators the LO frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the BASEBAND FILTER IMPLEMENTATION output. The LO feedthrough can be nulled by applying the correct Most applications require a baseband anti-imaging filter between dc offset voltages at the DAC output. This can be done using the the DAC and the modulator to filter out Nyquist images and auxiliary DACs (Register 0x42, Register 0x43, Register 0x46, and broadband DAC noise. The filter can be inserted between the Register 0x47) or by using the digital dc offset adjustments I-V resistors at the DAC output and the signal-level setting resistor (Register 0x3C through Register 0x3F). across the modulator input. This configuration establishes the The advantage of using the auxiliary DACs is that none of the input and output impedances for the filter. main DAC dynamic range is used to perform the dc offset Figure 75 shows a fifth-order low-pass filter. A common-mode adjustment. However, the disadvantage is that the common- choke is used between the I-V resistors and the remainder of mode level of the output signal changes as a function of the the filter. This removes the common-mode signal produced by auxiliary DAC current. The opposite is true when the digital the DAC and prevents the common-mode signal from being offset adjustment is used. converted to a differential signal, which can appear as unwanted Good sideband suppression requires both gain and phase spurious signals in the output spectrum. Splitting the first filter matching of the I and Q signals. The I phase adjust capacitor into two and grounding the center point creates a (Register 0x38 and Register 0x39), Q phase adjust (Register common-mode low-pass filter, providing additional common- 0x3A and Register 0x3B), I DAC FS adjust (Register 0x40 and mode rejection of high frequency signals. A purely differential Register 0x41), and Q DAC FS adjust (Register 0x44 and filter can pass common-mode signals. Register 0x45) registers can be used to calibrate I and Q transmit paths to optimize the sideband suppression. 22pF 50Ω 3pF 33nH 56nH 2pF 6pF 140Ω ADL537x AD9125 33nH 56nH 50Ω 22pF 3pF Figure 75. DAC Modulator Interface with Fifth-Order, Low Pass Filter Rev. 0 | Page 44 of 56 09016-041 09016-042 09016-043 AD9125 DEVICE POWER DISSIPATION 1800 The AD9125 has four supply rails: AVDD33, IOVDD, DVDD18, and CVDD18. 1600 8× The AVDD33 supply powers the DAC core circuitry. The power 1400 dissipation of the AVDD33 supply rail is independent of the digital 1200 4× operating mode and sample rate. The current drawn from the 1000 AVDD33 supply rail is typically 57 mA (188 mW) when the 2× full-scale current of the I and Q DACs is set to the nominal value 800 of 20 mA. Changing the full-scale current directly impacts the 600 supply current drawn from the AVDD33 rail. For example, if 1× 400 the full-scale current of the I DAC and the Q DAC is changed to 200 10 mA, the AVDD33 supply current drops by 20 mA to 37 mA. 0 RESET The IOVDD voltage supplies the serial port I/O pins, the 0 50 100 150 200 250 300 IRQ pin, and the pin. The voltage applied to the IOVDD pin can f (MHz) DATA range from 1.8 V to 3.3 V. The current drawn by the IOVDD Figure 76. Total Power Dissipation vs. fDATA Without PLL, Fine NCO, and supply pin is typically 3 mA. Inverse Sinc 1400 The DVDD18 supply powers all of the digital signal processing blocks of the device. The power consumption from this supply 1200 is a function of which digital blocks are enabled and the frequency 8× 4× at which the device is operating. 1000 The CVDD18 supply powers the clock receiver and clock 800 distribution circuitry. The power consumption from this supply varies directly with the operating frequency of the 600 2× device. CVDD18 also powers the PLL. The power dissipation of the PLL is typically 80 mA when enabled. 400 Figure 76 through Figure 80 detail the power dissipation of the 200 1× AD9125 under a variety of operating conditions. All of the graphs are taken with data being supplied to both the I and Q channels. 0 0 50 100 150 200 250 300 The power consumption of the device does not vary significantly f (MHz) DATA with changes in the coarse modulation mode selected or analog Figure 77. DVDD18 Power Dissipation vs. f Without Fine NCO and DATA output frequency. Graphs of the total power dissipation are shown Inverse Sinc along with the power dissipation of the DVDD18 and CVDD18 250 supplies. Maximum power dissipation can be estimated to be 20% higher 8× 200 than the typical power dissipation. 4× 150 2× 100 1× 50 0 0 50 100 150 200 250 300 f (MHz) DATA Figure 78. CVDD18 Power Dissipation vs. fDATA with PLL Disabled Rev. 0 | Page 45 of 56 POWER (mW) POWER (mW) POWER (mW) 09016-046 09016-045 09016-044 AD9125 300 TEMPERATURE SENSOR The AD9125 has a diode-based temperature sensor for measuring 250 the temperature of the die. The temperature reading is accessed through Register 0x49 and Register 0x4A. The temperature of 200 the die can be calculated by 150 (Die Temp[15:0]− 47,925) T = DIE 88 100 o where T is the die temperature in C. The temperature DIE o accuracy is ±5 C typical. 50 Estimates of the ambient temperature can be made if the power 0 dissipation of the device is known. For example, if the device power 0 200 400 600 800 1000 1200 o dissipation is 800 mW and the measured die temperature is 50 C, f (MHz) DAC then the ambient temperature can be calculated as Figure 79. DVDD18 Power Dissipation vs. f Due to Inverse Sinc Filter DAC T = T – P × T = 50 – 0.8 × 20.7 = 33.4°C A DIE D JA 300 where: o T is the ambient temperature in C. A 250 o is the die temperature in C. TDIE PD is the power dissipation. 200 TJA is the thermal resistance from junction to ambient of the 2×, 4×, 8× 150 AD9125, as shown in Table 7. To use the temperature sensor, it must be enabled by setting 100 Register 0x01, Bit 4, to 0. In addition, to obtain accurate readings, 1× the range control register (Register 0x48) should be set to 0x02. 50 0 50 100 150 200 250 300 f (MHz) DATA Figure 80. DVDD18 Power Dissipation vs. fDATA Due to Fine NCO Rev. 0 | Page 46 of 56 POWER (mW) POWER (mW) 09016-048 09016-047 AD9125 MULTICHIP SYNCHRONIZATION MATCHED System demands may require that the outputs of multiple DACs LENGTH TRACES be synchronized with each other or with a system clock. Systems REFCLKP/ REFCLKN that support transmit diversity or beam forming, where multiple FRAME IOUT1P/ IOUT1N antennas are used to transmit a correlated signal, require multiple DCI DAC outputs to be phase aligned with each other. Systems with SYSTEM CLOCK a time division multiplexing transmit chain may require one or LOW SKEW CLOCK DRIVER more DACs to be synchronized with a system-level reference clock. REFCLKP/ REFCLKN Multiple devices are considered synchronized to each other when IOUT2P/ FRAME FPGA IOUT2N the state of the clock generation state machine is identical for all DCI parts and when time aligned data is being read from the FIFOs of all parts simultaneously. Devices are considered synchronized Figure 81. Typical Circuit Diagram for Synchronizing Devices to a system clock when there is a constant, known relationship The Procedure for Synchronization when Using the PLL section among the clock generation state machine, the data being read outlines the steps required to synchronize multiple devices. The from the FIFO, and a particular clock edge of the system clock. procedure assumes that the REFCLK signal is applied to all devices The AD9125 has provisions for enabling multiple devices to be and that the PLL of each device is phase locked to this signal. This synchronized to each other or to a system clock. procedure must be carried out on each individual device. The AD9125 supports synchronization in two modes: data rate Procedure for Synchronization when Using the PLL mode and FIFO rate mode. Each of these modes has a different To synchronize all devices, lowest rate clock that the synchronization logic attempts to syn- chronize to. In data rate mode, the input data rate represents the 1. Configure the device for data rate mode and periodic lowest synchronized clock. In FIFO rate mode, the FIFO rate, synchronization by writing 0xC0 to the Sync Control 1 which is the data rate divided by the FIFO depth of 8, represents register (Register 0x10). Additional synchronization the lowest rate clock. The advantage of FIFO rate synchronization options are available. is increased time between keep-out windows for DCI changes 2. Read the Sync Status 1 register (Register 0x12) and verify that relative to the DACCLK or REFCLK input. the sync locked bit (Bit 6) is set high, indicating that the device achieved back-end synchronization and that the When in data rate mode, the elasticity of the FIFO is not used to sync lost bit (Bit 7) is low. These levels indicate that the clocks absorb timing variations between the data source and the DAC, are running with a constant, known phase relative to the resulting in keep-out widows repeating at the input data rate. sync signal. The method chosen for providing the DAC sampling clock directly Reset the FIFO by strobing the FRAME signal high for the 3. impacts the synchronization methods available. When the device time required to write two complete input data-words. clock multiplier is used, only data rate mode is available. When Resetting the FIFO ensures that the correct data is being the DAC sampling clock is sourced directly, both data rate mode read from the FIFO. and FIFO rate mode synchronization are available. This section To maintain synchronization, the skew between the REFCLK details the synchronization methods for enabling both clocking signals of the devices must be less than t . There are also setup SKEW modes and for querying the status of the synchronization logic. and hold times to be observed among the DCI, the data of each SYNCHRONIZATION WITH CLOCK MULTIPLICATION device, and the REFCLK signal. When resetting the FIFO, the When using the clock multiplier to generate the DAC sample FRAME signal must be held high for the time interval required rate clock, the REFCLK input signal acts both as the reference to write two complete input data-words. A timing diagram of clock for the PLL-based clock multiplier and as the synchronization the input signals is shown in Figure 82. signal. To synchronize devices, distribute the REFCLK signal This example shows a REFCLK frequency equal to the data rate. with low skew to all of the devices that need to be synchronized. Although this is the most common situation, it is not strictly Skew between the REFCLK signals of the devices shows up required for proper synchronization. Any REFCLK frequency directly as a timing mismatch at the DAC outputs. that satisfies the following equation is acceptable: The frequency of the REFCLK signal is typically equal to the N fSYNC_I = fDACCLK/2 and fSYNC_I ≤ fDATA input data rate. The FRAME and DCI signals, along with the where N = 0, 1, 2, or 3. data, can be created in the FPGA. A circuit diagram of a typical configuration is shown in Figure 81. As an example, a configuration with 4× interpolation and clock frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, fDATA = 200 MHz, and fSYNC_I = 100 MHz is a viable solution. Rev. 0 | Page 47 of 56 09016-049 AD9125 t SKEW REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) t t SU_DCI H_DCI DCI(2) FRAME(2) Figure 82. Timing Diagram Required for Synchronizing Devices DACCLKP/ DACCLKN REFCLKP/ IOUT1P/ REFCLKN IOUT1N FRAME SAMPLE DCI RATE CLOCK LOW SKEW MATCHED CLOCK DRIVER LENGTH TRACES DACCLKP/ DACCLKN REFCLKP/ REFCLKN IOUT2P/ SYNC IOUT2N FRAME CLOCK LOW SKEW CLOCK DRIVER DCI FPGA Figure 83. Typical Circuit Diagram for Synchronizing Devices to a System Clock Rev. 0 | Page 48 of 56 09016-050 09016-051 AD9125 To ensure that each DAC is updated with the correct data on SYNCHRONIZATION WITH DIRECT CLOCKING the same CLK edge, two timing relationships must be met on When directly sourcing the DAC sample rate clock, a separate each DAC. DCI and D[31:0] must meet the setup and hold REFCLK input signal is required for synchronization. To times with respect to the rising edge of DACCLK, and REFCLK synchronize devices, the DACCLK signal and the REFCLK must meet the setup and hold times with respect to the rising signal must be distributed with low skew to all of the devices edge of DACCLK. When resetting the FIFO, the FRAME signal being synchronized. If the devices need to be synchronized must be held high for the time required to input two complete to a master clock, then use the master clock directly for generating input data-words. When these conditions are met, the outputs the REFCLK input (see Figure 83). of the DACs are updated within t + t of each other. A SKEW OUTDLY DATA RATE MODE SYNCHRONIZATION timing diagram that illustrates the timing requirements of the input signals is shown in Figure 84. The Procedure for Data Rate Synchronization when Directly Sourcing the DAC Sampling Clock section outlines the steps Figure 84 shows the synchronization signal timing with 2× required to synchronize multiple devices in data rate mode. The interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is procedure assumes that the DACCLK and REFCLK signals are shown to be equal to the data rate. The maximum frequency at applied to all of the devices. The procedure must be carried out which the device can be resynchronized in data rate mode can on each individual device. be expressed as Procedure for Data Rate Synchronization When Directly N f = f /2 SYNC_I DATA Sourcing the DAC Sampling Clock where N is any nonnegative integer. To synchronize all devices, Generally, for values of N equal to or greater than 3, select the 1. Configure the device for data rate mode and periodic FIFO rate synchronization mode. synchronization by writing 0xC0 to the Sync Control 1 register (Register 0x10). Additional synchronization Table 26. DCI-DAC Setup and Hold Times options are available and are described in the Additional Minimum Setup Time, tSU_DCI Minimum Hold Time, tH_DCI (ns) (ns) Synchronization Features section. 2. Poll the sync locked bit (Register 0x12, Bit 6) to verify that 0.16 0.59 the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant, known phase relative to the sync signal. 3. Reset the FIFO by strobing the FRAME signal high for the time required to write two complete input data-words. Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously. t SKEW DACCLKP(1)/ DACCLKN(1) DACCLKP(2)/ DACCLKN(2) t t SU_SYNC H_SYNC REFCLKP(2)/ REFCLKN(2) t t SU_DCI H_DCI DCI2(2) FRAME(2) Figure 84. Data Rate Synchronization Signal Timing Requirements, 2× Interpolation Rev. 0 | Page 49 of 56 09016-052 AD9125 To ensure that each DAC is updated with the correct data on the FIFO RATE MODE SYNCHRONIZATION same CLK edge, two timing relationships must be met on each The Procedure for FIFO Rate Synchronization when Directly DAC. DCI and D[31:0] must meet the setup and hold times with Sourcing the DAC Sampling Clock section outlines the steps respect to the rising edge of DACCLK, and REFCLK must meet the required to synchronize multiple devices in FIFO rate mode. setup and hold times with respect to the rising edge of DACCLK. The procedure assumes that the REFCLK and DACCLK signals When resetting the FIFO, the FRAME signal must be held high are applied to all of the devices. The procedure must be carried for at least three data periods (that is, 1.5 cycles of DCI). When out on each individual device. these conditions are met, the outputs of the DACs are updated Procedure for FIFO Rate Synchronization When Directly within t + t of each other. A timing diagram that illustrates SKEW OUTDLY Sourcing the DAC Sampling Clock the timing requirements of the input signals is shown in Figure 85. To synchronize all devices, Figure 85 shows the synchronization signal timing with 2× 1. Configure the device for FIFO rate mode and periodic interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is synchronization by writing 0x80 to the Sync Control 1 shown to be equal to the FIFO rate. More generally, the maximum register (Register 0x10). Additional synchronization frequency at which the device can be resynchronized in FIFO options are available and are described in the Additional rate mode can be expressed as Synchronization Features section. N f = f /(8 × 2 ) SYNC_I DATA 2. Poll the sync locked bit (Register 0x12, Bit 6) to verify that where N is any nonnegative integer. the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant and known phase relative to the sync signal. 3. Reset the FIFO by strobing the FRAME signal high for the time required to write two complete input data-words. Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously. t SKEW DACCLKP(1)/ DACCLKN(1) DACCLKP(2)/ DACCLKN(2) t t SU_SYNC H_SYNC REFCLKP(2)/ REFCLKN(2) DCI2 FRAME2 Figure 85. FIFO Rate Synchronization Signal Timing Requirements, 2× Interpolation Rev. 0 | Page 50 of 56 09016-053 AD9125 The synchronization logic resynchronizes when a phase change ADDITIONAL SYNCHRONIZATION FEATURES between the REFCLK signal and the state of the clock generation The synchronization logic incorporates additional features that state machine exceeds a threshold. To mitigate the effects of provide means for querying the status of the synchronization, jitter and prevent erroneous resynchronizations, the relative improving the robustness of the synchronization, and enabling phase can be averaged. The amount of averaging is set by the a one-shot synchronization mode. These features are detailed in sync averaging bits (Register 0x10, Bits[2:0]) and can be set the Sync Status Bits and Timing Optimization sections. from 1 to 128. The higher the number of averages, the more Sync Status Bits slowly the device recognizes and resynchronizes to a legitimate When the sync locked bit (Register 0x12, Bit 6) is set, it indicates phase correction. Generally, the averaging should be made as large that the synchronization logic has reached alignment. This as possible while still meeting the allotted resynchronization alignment is determined when the clock generation state machine time interval. phase is constant. It takes between (11 + averaging) × 64 and The value of the sync phase request bits (Register 0x11, (11 + averaging) × 128 DACCLK cycles. This bit can optionally Bits[5:0]) is the state to which the clock generation state IRQ trigger an , as described in the Interrupt Request Operation machine resets upon initialization. By varying this value, the section. timing of the internal clocks with respect to the REFCLK signal can be adjusted. Every increment in the value of the sync phase When the sync lost bit (Register 0x12, Bit 7) is set, it indicates request bits (Register 0x11, Bits[5:0]) advances the internal a previously synchronized device has lost alignment. This bit is clocks by one DACCLK period. This offset can be used for two latched and remains set until cleared by overwriting the register. IRQ purposes: to skew the outputs of two synchronized DAC This bit can optionally trigger an , as described in the outputs in increments of the DACCLK period and to change the Interrupt Request Operation section. relative timing between the DCI input and REFCLK. This may The sync phase readback bits (Register 0x13, Bits[7:0]) report allow for more optimal placement of the DCI sampling point in the current clock phase in a 6.2 format. Bits[7:2] report which data rate synchronization mode. of the 64 states (0 to 63) the clock is currently in. When averaging is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾). Table 27. Synchronization Setup and Hold Times The lower two bits give an indication of the timing margin issues Parameter Min Max Unit that may exist. If the sync sampling is error free, the fractional tSKEW −tDACCLK/2 +tDACCLK/2 ps clock state should be 00. tSV_SYNC 100 ps Timing Optimization T 330 ps H_SYNC The REFCLK signal is sampled by a version of the DACCLK. If sampling errors are being detected, the opposite sampling edge can be selected to improve the sampling point. The sampling edge can be selected by setting Register 0x10, Bit 3 (1 = rising and 0 = falling). Rev. 0 | Page 51 of 56 AD9125 INTERRUPT REQUEST OPERATION The AD9125 provides an interrupt request output signal (on also asserts the external IRQ. When an interrupt enable bit is set Pin 7, IRQ) that can be used to notify an external host processor low, the event flag bit reflects the current status of the EVENT_ of significant device events. Upon assertion of the interrupt, FLAG_SOURCE signal, but the event flag has no effect on the the device should be queried to determine the precise event that external IRQ. IRQ occurred. The pin is an open-drain, active low output. Pull The latched version of an event flag (the INTERRUPT_SOURCE IRQ the pin high external to the device. This pin can be tied to signal) can be cleared in two ways. The recommended way is by the interrupt pins of other devices with open-drain outputs to writing 1 to the corresponding event flag bit; however, a hardware wire-OR these pins together. or software reset can also clear the INTERRUPT_SOURCE. Sixteen event flags provide visibility into the device. These 16 INTERRUPT SERVICE ROUTINE flags are located in the two event flag registers (Register 0x06 The interrupt request management starts by selecting the set of and Register 0x07). The behavior of each of the event flags event flags that require host intervention or monitoring. Those is independently selected in the interrupt enable registers events that require host action should be enabled so that the (Register 0x04 and Register 0x05). When the flag interrupt host is notified when they occur. For events requiring host enable is active, the event flag latches and triggers an external intervention, upon IRQ activation, run the following routine to interrupt. When the flag interrupt is disabled, the event flag clear an interrupt request: simply monitors the source signal and the external IRQ remains 1. Read the status of the event flag bits that are being monitored. inactive. 2. Set the interrupt enable bit low so that the unlatched EVENT_ Figure 86 shows the IRQ-related circuitry. This diagram shows how FLAG_SOURCE signal can be monitored directly. event flag signals propagate to the IRQ output. The INTERRUPT_ 3. Perform any actions that are required to clear the EVENT_ ENABLE signal represents one bit from the interrupt enable SOURCE_FLAG signal. In many cases, no specific actions registers. The EVENT_FLAG_SOURCE signal represents one are required. bit from the event flag registers. The EVENT_FLAG_SOURCE 4. Read the event flag to verify that the EVENT_FLAG_ signal represents one of the device signals that can be monitored, SOURCE signal has been cleared. such as the PLL_LOCKED signal from the PLL phase detector 5. Clear the interrupt by writing 1 to the event flag bit. or the FIFO_WARNING_1 signal from the FIFO controller. 6. Set the interrupt enable bits of the events to be monitored. When an interrupt enable bit is set high, the corresponding event Note that some of the EVENT_FLAG_SOURCE signals are latched flag bit reflects a positively tripped signal (that is, latched on the signals. These are cleared by writing to the corresponding event rising edge of the EVENT_FLAG_SOURCE signal). This signal flag bit. Details of each of the event flags can be found in Table 11. 0 EVENT_FLAG 1 IRQ INTERRUPT SOURCE INTERRUPT_ENABLE OTHER INTERRUPT EVENT_FLAG_SOURCE SOURCES WRITE_1_TO_EVENT_FLAG DEVICE_RESET IRQ Figure 86. Simplified Schematic of Circuitry Rev. 0 | Page 52 of 56 09016-054 AD9125 INTERFACE TIMING VALIDATION The AD9125 provides on-chip sample error detection (SED) changes the behavior of Register 0x70 through Register 0x73. The circuitry that simplifies verification of the input data interface. compare pass bit is set if the last comparison indicated that the The SED compares the input data samples captured at the digital sample was error free. The compare fail bit is set if an error is input pins with a set of comparison values, which are loaded into detected. The compare fail bit is automatically cleared by the registers through the SPI port. Differences between these values reception of eight consecutive error-free comparisons. When are detected and stored. Options are available for customizing SED autoclear mode is enabled, Register 0x70 through Register 0x73 test sequencing and error handling. accumulate errors as previously described but reset to all 0s after eight consecutive error-free sample comparisons are made. SED OPERATION The sample error, compare pass, and compare fail flags can be The SED circuitry operates on a data set made up of four 16-bit configured to trigger an IRQ when active, if desired. This is input words, denoted as I0, Q0, I1, and Q1. To properly align the done by enabling the appropriate bits in the Event Flag 2 register input samples, the first I and Q data-words (that is, I0 and Q0) (Register 0x07). Table 28 shows a progression of the input sample are indicated by asserting the FRAME signal for a minimum of comparison results and the corresponding states of the error flags. two complete input samples. SED EXAMPLE Figure 87 shows the input timing of the interface in dual-word mode. The FRAME signal can be issued once at the start of the Normal Operation data transmission, or it can be asserted repeatedly at intervals The following example illustrates the SED configuration for coinciding with the I0 and Q0 data-words. IRQ continuously monitoring the input data and assertion of an when a single error is detected. FRAME 1. Write to the following registers to enable the SED and load D[31:16] I0 I1 I0 I1 I0 the comparison values. Register 0x67: 0x80 D[15:0] Q0 Q1 Q0 Q1 Q0 Register 0x68: I0[7:0] Figure 87. Timing Diagram for Dual-Word Mode SED Operation Register 0x69: I0[15:8] Register 0x6A: Q0[7:0] In word mode, the FRAME signal required to align the data Register 0x6B: Q0[15:8] samples needs to be extended. The FRAME signal can be issued Register 0x6C: I1[7:0] once at the start of the data transmission, or it can be asserted Register 0x6D: I1[15:8] repeatedly at intervals coinciding with the I0 and Q0 data-words. Register 0x6E: Q1[7:0] FRAME Register 0x6F: Q1[15:8] Comparison values can be chosen arbitrarily; however, D[15:0] I0 Q0 I1 Q1 I0 Q0 choosing values that require frequent bit toggling provides Figure 88. Timing Diagram for Two-Port Mode SED Operation the most robust test. 2. Enable the SED error detect flag to assert the IRQ pin by The SED has three flag bits (Register 0x67, Bit 0, Bit 1, and writing 0x04 to Register 0x05. Bit 5) that indicate the results of the input sample comparisons. 3. Begin transmitting the input data pattern. The sample error detected bit (Register 0x67, Bit 5) is set when an error is detected and remains set until the bit is cleared. The If IRQ is asserted, read Register 0x67 and Register 0x70 through SED also provides registers that indicate which input data bits Register 0x73 to verify that a SED error was detected and to deter- experienced errors (Register 0x70 through Register 0x73). mine which input bits were in error. The bits in Register 0x70 These bits are latched and indicate the accumulated errors through Register 0x73 are latched; therefore, the bits indicate detected until cleared. any errors that occurred on those bits throughout the test, not just the errors that caused the error detected flag to be set. The autoclear mode has two effects: it activates the compare fail bit and the compare pass bit (Register 0x67, Bit 1 and Bit 0) and Table 28. Progression of Comparison Outcomes and the Resulting SED Register Values Compare Results (Pass/Fail) P F F F P P P P P P P P P F P F Register 0x67, Bit 5 (Sample Error Detected) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Register 0x67, Bit 1 (Compare Fail) 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 Register 0x67, Bit 0 (Compare Pass) 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 2 Register 0x70 to Register 0x73 (Errors Detected x_BITS[15:0]) Z N N N N N N N N N N N Z N N N 1 Z = all 0s. 2 N = nonzero. Rev. 0 | Page 53 of 56 09016-056 09016-055 AD9125 Start-Up Sequence EXAMPLE START-UP ROUTINE The following procedure sets the power clock and register write There are certain sequences that should be followed to ensure sequencing for reliable device start-up: reliable startup of the AD9125. 1. Power up the device (no specific power supply sequence is The example start-up routine assumes the following device required). configuration: 2. Apply stable REFCLK input signal. • f = 122.88 MSPS DATA 3. Apply stable DCI input signal. • Interpolation = 4×, using HB1 = 10 and HB2 = 010010 4. Issue a hardware reset (optional). • Input data = baseband data As a result, the device configuration register write sequence is • fOUT = 140 MHz • f = 122.88 MHz REFCLK 0x00 Æ 0x20 /* Issue software reset */ • PLL = enabled 0x00 Æ 0x00 • Fine NCO = enabled • Inverse SINC filter = enabled 0x0C Æ 0xD1 /* Start PLL */ • Synchronization = enabled 0x0D Æ 0xD9 The following PLL settings can be derived from the device 0x0A Æ 0xC0 configuration: 0x0A Æ 0x80 • f = f × Interpolation = 491.52 MHz DACCLK DATA /* ??Verify PLL is locked?? */ • f = 4 × f = 1966.08 MHz (1 GHz < f < 2.1 GHz) VCO DACCLK VCO Read 0x0E, expect Bit 7 = 1, Bit 6 = 0 • N1 = f /f = 4 DACCLK REFCLK Read 0x06, expect 0x5C • N2 = f /f = 4 VCO DACCLK The following NCO settings can be derived from the device 0x10 Æ 0x48 /* Choose data rate mode */ configuration: 0x17 Æ 0x04 /* Issue software FIFO reset */ • f = 2 × f NCO DATA • f = f − f = 140 − 122.88 = 17.12 MHz 0x18 Æ 0x02 CARRIER OUT MODHB1 32 • FTW = 17.12/(2 × 122.88) × 2 = 0x11D55555 0x18 Æ 0x00 /* ??Verify FIFO reset?? */ Read 0x18, expect 0x05 Read 0x19, expect 0x07 0x1B Æ 0x84 /* Configure interpolation filters */ 0x1C Æ 0x04 0x1D Æ 0x24 0x1E Æ 0x01 /* Configure NCO */ 0x30 Æ 0x55 0x31 Æ 0x55 0x32 Æ 0xD5 0x33 Æ 0x11 0x36 Æ 0x01 /* Update frequency tuning word */ 0x36 Æ 0x00 Rev. 0 | Page 54 of 56 AD9125 OUTLINE DIMENSIONS 0.60 10.00 0.42 0.60 BSC SQ 0.24 0.42 0.24 PIN 1 55 72 INDICATOR 54 1 PIN 1 INDICATOR 0.50 9.75 BSC 6.15 BSC SQ TOP VIEW EXPOSED PAD 6.00 SQ (BOTTOM VIEW) 5.85 0.50 37 18 0.40 36 19 0.30 12° MAX 0.80 MAX 8.50 REF 1.00 0.65 TYP 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY 0.30 SEATING FUNCTION DESCRIPTIONS 0.08 PLANE 0.20 REF SECTION OF THIS DATA SHEET. 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 Figure 89. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-7) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9125BCPZ −40°C to +85°C 72-lead LFCSP_VQ CP-72-7 AD9125BCPZRL −40°C to +85°C 72-lead LFCSP_VQ CP-72-7 AD9125-M5372-EBZ Evaluation Board Connected to ADL5372 Modulator AD9125-M5375-EBZ Evaluation Board Connected to ADL5375 Modulator 1 Z = RoHS Compliant Part. Rev. 0 | Page 55 of 56 052809-A AD9125 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09016-0-6/10(0) Rev. 0 | Page 56 of 56