ANALOG DEVICES AD9122

Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter AD9122 The AD9122 TxDAC+® includes features optimized for direct FEATURES conversion transmit applications, including complex digital mod- Flexible LVDS interface allows word, byte, or nibble load ulation, and gain and offset compensation. The DAC outputs Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF are optimized to interface seamlessly with analog quadrature Analog output: adjustable 8.7 mA to 31.7 mA, modulators, such as the ADL537x F-MOD series from Analog R = 25 Ω to 50 Ω L Devices, Inc. A 4-wire serial port interface provides for program- Integrated 2×/4×/8× interpolator/complex modulator allows ming/readback of many internal parameters. Full-scale output carrier placement anywhere in the DAC bandwidth current can be programmed over a range of 8.7 mA to 31.7 mA. Gain, dc offset, and phase adjustment for sideband The AD9122 comes in a 72-lead LFCSP. suppression Multiple chip synchronization interfaces PRODUCT HIGHLIGHTS High performance, low noise PLL clock multiplier 1. Ultralow noise and intermodulation distortion (IMD) Digital inverse sinc filter enable high quality synthesis of wideband signals from Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS, baseband to high intermediate frequencies (IF). full operating conditions 2. Proprietary DAC output switching technique enhances 72-lead, exposed paddle LFCSP dynamic performance. 3. Current outputs are easily configured for various single- APPLICATIONS ended or differential circuit topologies. Wireless infrastructure 4. Flexible LVDS digital interface allows the standard 32-wire W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE bus to be reduced to one-half or one-quarter of the width. Digital high or low IF synthesis Transmit diversity COMPANION PRODUCTS Wideband communications: LMDS/MMDS, point-to-point IQ Modulators: ADL5370, ADL537x family GENERAL DESCRIPTION IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family Clock Drivers: AD9516, AD951x family The AD9122 is a dual, 16-bit, high dynamic range digital-to- Voltage Regulator Design Tool: ADIsimPower analog converter (DAC) that provides a sample rate of 1230 MSPS, Additional companion products on the AD9122 product page permitting multicarrier generation up to the Nyquist frequency. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF f LO – f DC IF IF 2 2/4 I DAC SIN DIGITAL ANTIALIASING PA BASEBAND AQM FILTER PROCESSOR COS 2 2/4 Q DAC LO NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08281-001 AD9122 TABLE OF CONTENTS Features .............................................................................................. 1  Data Rates vs. Interpolation Modes ......................................... 42  Applications ....................................................................................... 1  Coarse Modulation Mixing Sequences .................................... 42  General Description ......................................................................... 1  Quadrature Phase Correction ................................................... 43  Product Highlights ........................................................................... 1  DC Offset Correction ................................................................ 43  Companion Products ....................................................................... 1  Inverse Sinc Filter ....................................................................... 43  Typical Signal Chain ......................................................................... 1  DAC Input Clock Configurations ................................................ 44  Revision History ............................................................................... 3  Driving the DACCLK and REFCLK Inputs ........................... 44  Functional Block Diagram .............................................................. 4  Direct Clocking .......................................................................... 44  Specif ica t ions ..................................................................................... 5  Clock Multiplication .................................................................. 44  DC Specifications ......................................................................... 5  PLL Settings ................................................................................ 45  Digital Specifications ................................................................... 6  Configuring the VCO Tuning Band ........................................ 45  Digital Input Data Timing Specifications ................................. 6  Analog Outputs............................................................................... 46  AC Specifications .......................................................................... 7  Transmit DAC Operation .......................................................... 46  Absolute Maximum Ratings ............................................................ 8  Auxiliary DAC Operation ......................................................... 47  Thermal Resistance ...................................................................... 8  Interfacing to Modulators ......................................................... 48  ESD Caution .................................................................................. 8  Baseband Filter Implementation .............................................. 48  Pin Configuration and Function Descriptions ............................. 9  Driving the ADL5375-15 .......................................................... 48  Typical Performance Characteristics ........................................... 11  Reducing LO Leakage and Unwanted Sidebands .................. 49  Terminology .................................................................................... 17  Device Power Management ........................................................... 50  Differences Between AD9122R1 and AD9122R2 ...................... 18  Power Dissipation....................................................................... 50  Device Marking of AD9122R1 and AD9122R2 ..................... 18  Temperature Sensor ................................................................... 51  Theory of Operation ...................................................................... 19  Multichip Synchronization ............................................................ 52  Serial Port Operation ................................................................. 19  Synchronization with Clock Multiplication ............................... 52  Data Format ................................................................................ 19  Synchronization with Direct Clocking .................................... 53  Serial Port Pin Descriptions ...................................................... 19  Data Rate Mode Synchronization ............................................ 53  Serial Port Options ..................................................................... 20  FIFO Rate Mode Synchronization ........................................... 54  Device Configuration Register Map and Descriptions ......... 21  Additional Synchronization Features ...................................... 55  LVDS Input Data Ports .................................................................. 32  Interrupt Request Operation ........................................................ 56  Word Interface Mode ................................................................. 32  Interrupt Service Routine .......................................................... 56  Byte Interface Mode ................................................................... 32  Interface Timing Validation .......................................................... 57  Nibble Interface Mode ............................................................... 32  SED Operation ............................................................................ 57  Interface Timing ......................................................................... 32  SED Example .............................................................................. 58  FIFO Operation .......................................................................... 33  Example Start-Up Routine ............................................................ 59  Digital Datapath .............................................................................. 36  Device Configuration ................................................................ 59  Premodulation ............................................................................ 36  Derived PLL Settings ................................................................. 59  Interpolation Filters ................................................................... 36  Derived NCO Settings ............................................................... 59  NCO Modulation ....................................................................... 39  Start-Up Sequence ...................................................................... 59  Datapath Configuration ............................................................ 39  Outline Dimensions ....................................................................... 60  Determining Interpolation Filter Modes ................................ 40  Ordering Guide .......................................................................... 60  Datapath Configuration Examples........................................... 41  Rev. B | Page 2 of 60 AD9122 REVISION HISTORY 5/11—Rev. A to Rev. B Moved Table 25 and Figure 85 ...................................................... 54 Change to General Description Section ......................................... 1 Changes to Procedure for FIFO Rate Synchronization When Added Companion Products Section ............................................. 1 Directly Sourcing the DAC Sampling Clock Section ................. 54 Moved Power Supply Rejection Ratio Parameter from Power Changes to Additional Synchronization Features Section and Consumption Section of Table 1 to Main DAC Outputs Section Timing Optimization Section ........................................................ 55 of Table 1 ............................................................................................. 5 Added One-Time Synchronization Section ................................ 55 Changes to Interrupt Request Operation Section ...................... 56 Moved Power-Up Time Parameter from Table 3 to Table 1 ........ 5 Changed Maximum Clock Rate Parameter in Table 2 ................. 6 Changes to SED Operation Section .............................................. 57 Changes to Table 3 ............................................................................ 6 Changes to SED Example Section ................................................. 58 Changes to Table 5 ............................................................................ 7 Changes to Example Start-Up Routine Section .......................... 59 Changes to Table 6 ............................................................................ 8 Changes to Figure 3 and Table 8 ..................................................... 9 3/10—Rev. 0 to Rev. A Changes to Differences Between AD9122R1 and AD9122R2 Changes to Reflect Differences Between R1 and R2 Section and Device Marking of AD9122R1 and AD9122R2 Silicon .................................................................................. Universal Changes to Features Section ............................................................ 1 Section .............................................................................................. 18 Changes to Figure 40 and Figure 41 ............................................. 20 Changes to Table 1 ............................................................................ 5 Changes to Table 10 ........................................................................ 21 Changes to Table 2 ............................................................................ 6 Changes to Table 11 ........................................................................ 23 Changes to Table 5 ............................................................................ 7 Changes to LVDS Input Data Ports Section and Figure 45 ....... 32 Change to IOVDD Rating in Table 6 ............................................. 8 Moved Interface Timing Section ................................................... 32 Changes to Table 8 ............................................................................ 9 Moved Figure 46 and Table 13; Changes to Interface Changes to Figure 10 through Figure 15 ...................................... 12 Timing Section ................................................................................ 33 Added Differences Between AD9122R1 and AD9122R2 Section; Added Figure 36 and Figure 37; Renumbered Figures Changes to Resetting the FIFO Section, Serial Port Initiated FIFO Reset Section, and Figure 48 ............................................... 34 Sequentially ...................................................................................... 18 Changes to FRAME Initiated Absolute FIFO Reset Section Changes to Table 10 ........................................................................ 21 and Monitoring the FIFO Status Section ..................................... 35 Changes to Table 11 ........................................................................ 23 Changes to Table 22 ........................................................................ 42 Changes to FIFO Operation Section ............................................ 33 Changes to Inverse Sinc Filter Section ......................................... 43 Changes to Resetting the FIFO Section; Replaced Table 13; Change to Driving the DACCLK and REFCLK Inputs Section .... 44 Added Serial Port Initiated FIFO Reset Section and FRAME Initiated Relative FIFO Reset Section ........................................... 34 Changes to Manual VCO Band Select Section ............................ 45 Changes to Transmit DAC Operation Section ............................ 46 Added FRAME Initiated Absolute FIFO Reset Section; Changes to Figure 69, Figure 70, Figure 71, and Figure 72 ....... 47 Replaced Table 14 ............................................................................ 35 Changes to Power Dissipation Section ......................................... 50 Changes to Figure 54 ...................................................................... 38 Replaced Temperature Sensor Section ......................................... 51 Changes to Table 18 ........................................................................ 39 Changes to Multichip Synchronization Section, Synchronization Changes to SED Example Section ................................................. 58 with Clock Multiplication Section, and Procedure for Added Example Start-Up Routine Section .................................. 59 Synchronization When Using the PLL Section ........................... 52 9/09—Revision 0: Initial Version Changes to Procedure for Data Rate Synchronization When Directly Sourcing the DAC Sampling Clock Section ................. 53 Rev. B | Page 3 of 60 AD9122 FUNCTIONAL BLOCK DIAGRAM IOUT1P 16 1.2G AUX DAC 1 16-BIT IOUT1N 16 D15P/D15N f /2 I OFFSET NCO DATA 10 INV DAC_CLK FIFO PRE HB1 AND HB2 HB3 SINC Q OFFSET MOD MOD 16 D0P/D0N IOUT2P 16 1.2G DCI AUX DAC 2 16-BIT FRAME IOUT2N REF REFIO 10 10 AND BIAS FSADJ INTERNAL CLOCK TIMING AND CONTROL LOGIC DAC CLK_SEL PLL DACCLKP CLK CONTROL 0 RCVR DACCLKN SERIAL SYNC PROGRAMMING POWER-ON MULTICHIP INPUT/OUTPUT CLOCK REGISTERS RESET SYNCHRONIZATION DAC_CLK REFCLKP CLK PORT 1 MULTIPLIER RCVR REFCLKN (2× TO 16×) PLL_LOCK Figure 2. Rev. B | Page 4 of 60 MODE DATA RECEIVER SDO SDIO HB1_CLK SCLK CS IRQ RESET HB2_CLK HB3_CLK INTP FACTOR PHASE CORRECTION INVSINC_CLK GAIN 1 GAIN 2 08281-002 AD9122 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I = 20 mA, maximum sample rate, unless otherwise noted. MIN MAX FS Table 1. Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 % FSR Gain Error (with Internal Reference) −3.6 ±2 +3.6 % FSR 1 Full-Scale Output Current 8.66 19.6 31.66 mA Output Compliance Range −1.0 +1.0 V Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES DVDD18 1.71 1.8 1.89 V IOVDD 1.71 1.8/3.3 3.47 V POWER CONSUMPTION 2× Mode, f = 491.22 MSPS, IF = 10 MHz, PLL Off 834 mW DAC 2× Mode, f = 491.22 MSPS, IF = 10 MHz, PLL On 913 mW DAC 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off 1135 1241 mW AVDD33 55 57 mA CVDD18 85 90 mA DVDD18 444 495 mA Power-Down Mode (Register 0x01 = 0xF0) 6.5 18.8 mW POWER-UP TIME 260 ms OPERATING RANGE −40 +25 +85 °C 1 Based on a 10 kΩ external resistor between FSADJ and AVSS. Rev. B | Page 5 of 60 AD9122 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input VIN Logic High IOVDD = 1.8 V 1.2 V IOVDD = 2.5 V 1.6 V IOVDD = 3.3 V 2.0 V Input V Logic Low IOVDD = 1.8 V 0.6 V IN IOVDD = 2.5 V, 3.3 V 0.8 V CMOS OUTPUT LOGIC LEVEL Output V Logic High IOVDD = 1.8 V 1.4 V OUT IOVDD = 2.5 V 1.8 V IOVDD = 3.3 V 2.4 V Output VOUT Logic Low IOVDD = 1.8 V, 2.5 V, 3.3 V 0.4 V 1 LVDS RECEIVER INPUTS Applies to data, DCI, and FRAME inputs Input Voltage Range, VIA or VIB 825 1675 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, V to V 20 mV IDTHH IDTHL Receiver Differential Input Impedance, R 80 120 Ω IN LVDS Input Rate See Table 5 DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage Self-biased input, ac-coupled 1.25 V Maximum Clock Rate 1230 MHz REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V REFCLK Frequency (PLL Mode) 1 GHz ≤ fVCO ≤ 2.1 GHz 15.625 600 MHz REFCLK Frequency (SYNC Mode) See the Multichip Synchronization section 0 600 MHz for conditions SERIAL PORT INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High (t) 12.5 ns PWH Minimum Pulse Width Low (t) 12.5 ns PWL Setup Time, SDIO to SCLK (tDS) 1.9 ns Hold Time, SDIO to SCLK (tDH) 0.2 ns Data Valid, SDO to SCLK (tDV) 2.3 ns Setup Time, CS to SCLK (t ) 1.4 ns DCSB 1 LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted. DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter Value Unit LATENCY (DACCLK CYCLES) 1× Interpolation (With or Without Modulation) 64 Cycles 2× Interpolation (With or Without Modulation) 135 Cycles 4× Interpolation (With or Without Modulation) 292 Cycles 8× Interpolation (With or Without Modulation) 608 Cycles Inverse Sinc 20 Cycles Fine Modulation 8 Cycles Rev. B | Page 6 of 60 AD9122 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz 78 dBc fDAC = 200 MSPS, fOUT = 50 MHz 80 dBc fDAC = 400 MSPS, fOUT = 70 MHz 69 dBc f = 800 MSPS, f = 70 MHz 72 dBc DAC OUT TWO-TONE INTERMODULATION DISTORTION (IMD) f = 200 MSPS, f = 50 MHz 84 dBc DAC OUT f = 400 MSPS, f = 60 MHz 86 dBc DAC OUT f = 400 MSPS, f = 80 MHz 84 dBc DAC OUT fDAC = 800 MSPS, fOUT = 100 MHz 81 dBc NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING f = 200 MSPS, f = 80 MHz −162 dBm/Hz DAC OUT fDAC = 400 MSPS, fOUT = 80 MHz −163 dBm/Hz fDAC = 800 MSPS, fOUT = 80 MHz −164 dBm/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE-CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz 84 dBc fDAC = 491.52 MSPS, fOUT = 122.88 MHz 82 dBc fDAC = 983.04 MSPS, fOUT = 122.88 MHz 83 dBc W-CDMA SECOND ACLR, SINGLE-CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz 88 dBc fDAC = 491.52 MSPS, fOUT = 122.88 MHz 86 dBc f = 983.04 MSPS, f = 122.88 MHz 88 dBc DAC OUT Table 5. Maximum Rate (MSPS) with DVDD and CVDD Supply Regulation fINTERFACE (MSPS) fDAC (MSPS) DVDD18, CVDD18 = DVDD18, CVDD18 = Interpolation Bus Width Factor 1.8 V ± 5% 1.8 V ± 2% 1.9 V ± 2% 1.8 V ± 5% 1.8 V ± 2% 1.9 V ± 2% Nibble (4 Bits) 1× 1100 1200 1230 137.5 150 153.75 2× 1100 1200 1230 275 300 307.5 4× 1100 1200 1230 550 600 615 8× 1100 1200 1230 1100 1200 1230 Byte (8 Bits) 1× 1100 1200 1230 275 300 307.5 2× 1100 1200 1230 550 600 615 4× 1100 1200 1230 1100 1200 1230 8× 550 600 615 1100 1200 1230 Word (16 Bits) 1× 1100 1200 1230 550 600 615 2× (HB1) 900 1000 1000 900 1000 1000 2× (HB2) 1100 1200 1230 1100 1200 1230 4× 550 600 615 1100 1200 1230 8× 275 300 307.5 1100 1200 1230 Rev. B | Page 7 of 60 AD9122 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Rating The exposed pad (EPAD) of the 72-lead LFCSP must be soldered to the ground plane (AVSS). The EPAD provides an AVDD33 to AVSS, EPAD, CVSS, DVSS −0.3 V to +3.6 V electrical, thermal, and mechanical connection to the board. IOVDD to AVSS, EPAD, CVSS, DVSS −0.3 V to +3.6 V DVDD18, CVDD18 to AVSS, EPAD, −0.3 V to +2.1 V Typical θJA, θJB, and θJC values are specified for a 4-layer board in CVSS, DVSS still air. Airflow increases heat dissipation, effectively reducing AVSS to EPAD, CVSS, DVSS −0.3 V to +0.3 V θJA and θJB. EPAD to AVSS, CVSS, DVSS −0.3 V to +0.3 V CVSS to AVSS, EPAD, DVSS −0.3 V to +0.3 V Table 7. Thermal Resistance DVSS to AVSS, EPAD, CVSS −0.3 V to +0.3 V Package θJA θJB θJC Unit Conditions FSADJ, REFIO, IOUT1P, IOUT1N, −0.3 V to AVDD33 + 0.3 V 72-Lead LFCSP 20.7 10.9 1.1 °C/W EPAD soldered IOUT2P, IOUT2N to AVSS to ground plane D[15:0]P, D[15:0]N, FRAMEP, FRAMEN, −0.3 V to DVDD18 + 0.3 V DCIP, DCIN to EPAD, DVSS DACCLKP, DACCLKN, REFCLKP, −0.3 V to CVDD18 + 0.3 V ESD CAUTION REFCLKN to CVSS RESET, IRQ, CS, SCLK, SDIO, SDO −0.3 V to IOVDD + 0.3 V to EPAD, DVSS Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 8 of 60 AD9122 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CVDD18 1 54 RESET PIN 1 DACCLKP 2 INDICATOR 53 CS DACCLKN 3 52 SCLK CVSS 4 51 SDIO FRAMEP 5 50 SDO FRAMEN 6 49 DVDD18 IRQ 7 48 D0N D15P 8 AD9122 47 D0P D15N 9 D1N TOP VIEW 46 NC 10 (Not to Scale) 45 D1P IOVDD 11 44 DVSS DVDD18 12 43 DVDD18 D14P 13 42 D2N D14N 14 41 D2P D13P 15 40 D3N D13N 16 39 D3P D12P 17 38 D4N D12N 18 37 D4P NOTES 1. EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND PLANE (AVSS). THE EPAD PROVIDES AN ELECTRICAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD. 2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 2 DACCLKP DAC Clock Input, Positive. 3 DACCLKN DAC Clock Input, Negative. 4 CVSS Clock Supply Common. 5 FRAMEP Frame Input, Positive. This pin must be tied to DVSS if not used. 6 FRAMEN Frame Input, Negative. This pin must be tied to DVDD18 if not used. 7 IRQ Interrupt Request. Open-drain, active low output. Connect an external pull-up to IOVDD through a 10 kΩ resistor. 8 D15P Data Bit 15 (MSB), Positive. 9 D15N Data Bit 15 (MSB), Negative. 10 NC No Connect. Do not connect to this pin. 11 IOVDD Supply Pin for Serial Port I/O Pins, RESET, and IRQ. 1.8 V to 3.3 V can be supplied to this pin. 12 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports. 13 D14P Data Bit 14, Positive. 14 D14N Data Bit 14, Negative. 15 D13P Data Bit 13, Positive. 16 D13N Data Bit 13, Negative. 17 D12P Data Bit 12, Positive. 18 D12N Data Bit 12, Negative. 19 D11P Data Bit 11, Positive. 20 D11N Data Bit 11, Negative. 21 D10P Data Bit 10, Positive. 22 D10N Data Bit 10, Negative. 23 D9P Data Bit 9, Positive. 24 D9N Data Bit 9, Negative. Rev. B | Page 9 of 60 D11P 19 72 CVDD18 D11N 20 71 CVDD18 D10P 21 70 REFCLKP D10N 22 69 REFCLKN D9P 23 68 AVDD33 D9N 24 67 IOUT1P D8P 25 66 IOUT1N D8N 26 65 AVDD33 DCIP 27 64 AVSS DCIN 28 63 FSADJ DVDD18 29 62 REFIO DVSS 30 61 AVSS D7P 31 60 AVDD33 D7N 32 59 IOUT2N D6P 33 58 IOUT2P D6N 34 57 AVDD33 D5P 35 56 AVSS D5N 36 55 NC 08281-003 AD9122 Pin No. Mnemonic Description 25 D8P Data Bit 8, Positive. 26 D8N Data Bit 8, Negative. 27 DCIP Data Clock Input, Positive. 28 DCIN Data Clock Input, Negative. 29 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports. 30 DVSS Digital Common. 31 D7P Data Bit 7, Positive. 32 D7N Data Bit 7, Negative. 33 D6P Data Bit 6, Positive. 34 D6N Data Bit 6, Negative. 35 D5P Data Bit 5, Positive. 36 D5N Data Bit 5, Negative. 37 D4P Data Bit 4, Positive. 38 D4N Data Bit 4, Negative. 39 D3P Data Bit 3, Positive. 40 D3N Data Bit 3, Negative. 41 D2P Data Bit 2, Positive. 42 D2N Data Bit 2, Negative. 43 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports. 44 DVSS Digital Common. 45 D1P Data Bit 1, Positive. 46 D1N Data Bit 1, Negative. 47 D0P Data Bit 0 (LSB), Positive. 48 D0N Data Bit 0 (LSB), Negative. 49 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports. 50 SDO Serial Port Data Output (CMOS Levels with Respect to IOVDD). 51 SDIO Serial Port Data Input/Output (CMOS Levels with Respect to IOVDD). 52 SCLK Serial Port Clock Input (CMOS Levels with Respect to IOVDD). 53 CS Serial Port Chip Select, Active Low (CMOS Levels with Respect to IOVDD). 54 RESET Reset, Active Low (CMOS Levels with Respect to IOVDD). 55 NC No Connect. Do not connect to this pin. 56 AVSS Analog Supply Common. 57 AVDD33 3.3 V Analog Supply. 58 IOUT2P Q DAC Positive Current Output. 59 IOUT2N Q DAC Negative Current Output. 60 AVDD33 3.3 V Analog Supply. 61 AVSS Analog Supply Common. 62 REFIO Voltage Reference. Nominally 1.2 V output. Should be decoupled to AVSS. 63 FSADJ Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS. 64 AVSS Analog Supply Common. 65 AVDD33 3.3 V Analog Supply. 66 IOUT1N I DAC Negative Current Output. 67 IOUT1P I DAC Positive Current Output. 68 AVDD33 3.3 V Analog Supply. 69 REFCLKN PLL Reference Clock Input, Negative. This pin has a secondary function as a synchronization input. 70 REFCLKP PLL Reference Clock Input, Positive. This pin has a secondary function as a synchronization input. 71 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 72 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. EPAD The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical, thermal, and mechanical connection to the board. Rev. B | Page 10 of 60 AD9122 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 f = 250MSPS, SECOND HARMONIC 0dBFS DATA f = 250MSPS, THIRD HARMONIC –6dBFS –10 –10 DATA f = 400MSPS, SECOND HARMONIC –12dBFS DATA –20 –20 f = 400MSPS, THIRD HARMONIC –18dBFS DATA –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 4. Harmonics vs. f over f , 2× Interpolation, Figure 7. Second Harmonic vs. f over Digital Scale, 2× Interpolation, OUT DATA OUT = 20 mA = 400 MSPS, I = 20 mA Digital Scale = 0 dBFS, IFS fDATA FS 0 0 f = 100MSPS, SECOND HARMONIC 0dBFS DATA –10 f = 100MSPS, THIRD HARMONIC –10 –6dBFS DATA f = 200MSPS, SECOND HARMONIC –12dBFS DATA –20 –20 f = 200MSPS, THIRD HARMONIC –18dBFS DATA –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 5. Harmonics vs. fOUT over fDATA, 4× Interpolation, Figure 8. Third Harmonic vs. fOUT over Digital Scale, 2× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA fDATA = 400 MSPS, IFS = 20 mA 0 0 f = 100MSPS, SECOND HARMONIC I = 10mA, SECOND HARMONIC DATA FS f = 100MSPS, THIRD HARMONIC I = 20mA, SECOND HARMONIC –10 –10 FS DATA f = 150MSPS, SECOND HARMONIC I = 30mA, SECOND HARMONIC FS DATA –20 –20 I = 10mA, THIRD HARMONIC f = 150MSPS, THIRD HARMONIC DATA FS I = 20mA, THIRD HARMONIC FS –30 –30 I = 30mA, THIRD HARMONIC FS –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 100 200 300 400 500 600 700 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 6. Harmonics vs. f over f , 8× Interpolation, Figure 9. Harmonics vs. f over I , 2× Interpolation, OUT DATA OUT FS = 20 mA = 400 MSPS, Digital Scale = 0 dBFS Digital Scale = 0 dBFS, IFS fDATA Rev. B | Page 11 of 60 HARMONICS (dBc) HARMONICS (dBc) HARMONICS (dBc) 08281-103 08281-102 08281-101 HARMONICS (dBc) THIRD HARMONIC (dBc) SECOND HARMONIC (dBc) 08281-106 08281-105 08281-104 AD9122 –69 f = 250MSPS DATA 2× INTERPOLATION, f = 400MSPS –70 SINGLE-TONE SPECTRUM, DATA f = 250MSPS, DATA –71 f = 101MHz OUT –72 –73 –74 –75 –76 –77 –78 –79 0 50 100 150 200 250 300 350 400 450 START 1.0MHz VBW 10kHz STOP 500.0MHz #RES BW 10kHz SWEEP 6.017s (601 PTS) f (MHz) OUT Figure 10. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation, Figure 13. Single-Tone Spectrum, 2× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA f = 250 MSPS, f = 101 MHz DATA OUT –60 f = 100MSPS DATA 4× INTERPOLATION, f = 200MSPS DATA SINGLE-TONE SPECTRUM, f = 200MSPS, DATA –65 f = 151MHz OUT –70 –75 –80 –85 0 50 100 150 200 250 300 350 400 450 START 1.0MHz VBW 10kHz STOP 800.0MHz #RES BW 10kHz SWEEP 9.634s (601 PTS) f (MHz) OUT Figure 11. Highest Digital Spur vs. fOUT over fDATA, 4× Interpolation, Figure 14. Single-Tone Spectrum, 4× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA fDATA = 200 MSPS, fOUT = 151 MHz –60 f = 100MSPS DATA 8× INTERPOLATION, f = 150MSPS DATA SINGLE-TONE SPECTRUM, –65 f = 100MSPS, DATA f = 131MHz OUT –70 –75 –80 –85 –90 –95 0 100 200 300 400 500 600 700 START 1.0MHz VBW 10kHz STOP 800.0MHz #RES BW 10kHz SWEEP 9.634s (601 PTS) f (MHz) OUT Figure 12. Highest Digital Spur vs. f over f , 8× Interpolation, OUT DATA Figure 15. Single-Tone Spectrum, 8× Interpolation, Digital Scale = 0 dBFS, I = 20 mA FS fDATA = 100 MSPS, fOUT = 131 MHz Rev. B | Page 12 of 60 HIGHEST DIGITAL SPUR (dBc) HIGHEST DIGITAL SPUR (dBc) HIGHEST DIGITAL SPUR (dBc) 08281-107 08281-109 08281-108 08281-112 08281-111 08281-110 AD9122 0 0 f = 250MSPS 0dBFS DATA f = 400MSPS –6dBFS DATA –10 –10 –12dBFS –18dBFS –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 16. IMD vs. fOUT over fDATA, 2× Interpolation, Figure 19. IMD vs. fOUT over Digital Scale, 2× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA fDATA = 400 MSPS, IFS = 20 mA 0 –50 I = 10mA f = 100MSPS DATA FS f = 200MSPS I = 20mA –10 DATA FS –55 I = 30mA FS –20 –60 –30 –65 –40 –50 –70 –60 –75 –70 –80 –80 –90 –85 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 17. IMD vs. fOUT over fDATA, 4× Interpolation, Figure 20. IMD vs. fOUT over IFS, 2× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA fDATA = 400 MSPS, Digital Scale = 0 dBFS 0 –40 f = 100MSPS DATA –10 –45 –20 –50 PLL ON –30 –55 –40 –60 –50 –65 PLL OFF –60 –70 –70 –75 –80 –80 –90 –85 –100 –90 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 18. IMD vs. f , 8× Interpolation, f = 100 MSPS, Figure 21. IMD vs. f , 4× Interpolation, f = 200 MSPS, OUT DATA OUT DATA Digital Scale = 0 dBFS, I = 20 mA Digital Scale = 0 dBFS, I = 20 mA, PLL On and PLL Off FS FS Rev. B | Page 13 of 60 IMD (dBc) IMD (dBc) IMD (dBc) 08281-115 08281-114 08281-113 IMD (dBc) IMD (dBc) IMD (dBc) 08281-118 08281-117 08281-116 AD9122 –152 –161.0 1×, f = 200MSPS 1×, f = 200MSPS DATA DATA 2×, f = 200MSPS 2×, f = 200MSPS DATA DATA –161.5 –154 4×, f = 200MSPS 4×, f = 200MSPS DATA DATA 8×, f = 100MSPS 8×, f = 100MSPS –162.0 DATA DATA –156 –162.5 –158 –163.0 –163.5 –160 –164.0 –162 –164.5 –164 –165.0 –166 –165.5 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 22. One-Tone NSD vs. fOUT over Interpolation, Figure 25. Eight-Tone NSD vs. fOUT over Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA, PLL Off Digital Scale = 0 dBFS, IFS = 20 mA, PLL Off –154 –161.0 0dBFS 0dBFS –161.5 –6dBFS –6dBFS –156 –12dBFS –12dBFS –162.0 –18dBFS –18dBFS –162.5 –158 –163.0 –160 –163.5 –164.0 –162 –164.5 –164 –165.0 –165.5 –166 –166.0 –168 –166.5 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 23. One-Tone NSD vs. fOUT over Digital Scale, 4× Interpolation, Figure 26. Eight-Tone NSD vs. fOUT over Digital Scale, 4× Interpolation, fDATA = 200 MSPS, IFS = 20 mA, PLL Off fDATA = 200 MSPS, IFS = 20 mA, PLL Off –158 –160 2×, f = 200MSPS 2×, f = 200MSPS DATA DATA 4×, f = 200MSPS 4×, f = 200MSPS DATA DATA –159 8×, f = 100MSPS 8×, f = 100MSPS –161 DATA DATA –160 –162 –161 –162 –163 –163 –164 –164 –165 –165 –166 –166 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 f (MHz) f (MHz) OUT OUT Figure 24. One-Tone NSD vs. f over Interpolation, Figure 27. Eight-Tone NSD vs. f over Interpolation, OUT OUT Digital Scale = 0 dBFS, I = 20 mA, PLL On Digital Scale = 0 dBFS, I = 20 mA, PLL On FS FS Rev. B | Page 14 of 60 NSD (dBm/Hz) NSD (dBm/Hz) NSD (dBm/Hz) 08281-121 08281-120 08281-119 NSD (dBm/Hz) NSD (dBm/Hz) NSD (dBm/Hz) 08281-124 08281-123 08281-122 AD9122 –77 –50 0dBFS INTERPOLATION FACTOR = 2×, PLL OFF INTERPOLATION FACTOR = 4×, PLL OFF –3dBFS –55 –78 INTERPOLATION FACTOR = 2×, PLL ON –6dBFS INTERPOLATION FACTOR = 4×, PLL ON –60 –79 –65 –80 –70 –81 –75 –82 –80 –83 –85 –84 –90 0 50 100 150 200 250 0 100 200 300 400 500 f (MHz) f (MHz) OUT OUT Figure 28. One-Carrier W-CDMA ACLR vs. fOUT over Digital Scale, Figure 31. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation, Adjacent Channel, PLL Off Adjacent Channel, PLL On and PLL Off –78 –70 0dBFS INTERPOLATION FACTOR = 2×, PLL OFF INTERPOLATION FACTOR = 4×, PLL OFF –3dBFS –72 INTERPOLATION FACTOR = 2×, PLL ON –80 –6dBFS –74 INTERPOLATION FACTOR = 4×, PLL ON –76 –82 –78 –84 –80 –82 –86 –84 –86 –88 –88 –90 –90 0 50 100 150 200 250 0 100 200 300 400 500 f (MHz) f (MHz) OUT OUT Figure 29. One-Carrier W-CDMA ACLR vs. fOUT over Digital Scale, Figure 32. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation, First Alternate Channel, PLL Off First Alternate Channel, PLL On and PLL Off –70 –70 0dBFS INTERPOLATION FACTOR = 2×, PLL OFF INTERPOLATION FACTOR = 4×, PLL OFF –3dBFS INTERPOLATION FACTOR = 2×, PLL ON –6dBFS –75 INTERPOLATION FACTOR = 4×, PLL ON –75 –80 –80 –85 –85 –90 –90 –95 –95 0 50 100 150 200 250 0 100 200 300 400 500 f (MHz) f (MHz) OUT OUT Figure 30. One-Carrier W-CDMA ACLR vs. f over Digital Scale, Figure 33. One-Carrier W-CDMA ACLR vs. f over Interpolation, OUT OUT Second Alternate Channel, PLL Off Second Alternate Channel, PLL On and PLL Off Rev. B | Page 15 of 60 ACLR (dBc) ACLR (dBc) ACLR (dBc) 08281-127 08281-126 08281-125 ACLR (dBc) ACLR (dBc) ACLR (dBc) 08281-130 08281-129 08281-128 AD9122 START 133.06MHz VBW 30kHz STOP 166.94MHz START 125.88MHz VBW 30kHz STOP 174.42MHz #RES BW 30kHz SWEEP 143.6ms (601 PTS) #RES BW 30kHz SWEEP 206.9ms (601 PTS) RMS RESULTS FREQ LOWER UPPER TOTAL CARRIER POWER –11.19dBm/15.3600MHz OFFSET REF BW dBc dBm dBc dBm RRC FILTER: OFF FILTER ALPHA 0.22 CARRIER POWER 5.00MHz 3.840MHz –75.96 –85.96 –77.13 –87.13 REF CARRIER POWER –16.89dBm/3.84000MHz –10.00dBm/ 10.00MHz 3.840MHz –85.33 –95.33 –85.24 –95.25 LOWER UPPER 3.840MHz 15.00MHz 2.888MHz –95.81 –95.81 –85.43 –95.43 OFFSET FREQ INTEG BW dBc dBm dBc dBm 1 –16.92dBm 5.000MHz 3.840MHz –65.88 –82.76 –67.52 –84.40 2 –16.89dBm 10.00MHz 3.840MHz –68.17 –85.05 –69.91 –86.79 3 –17.43dBm 15.00MHz 3.840MHz –70.42 –87.31 –71.40 –88.28 4 –17.64dBm Figure 34. One-Carrier W-CDMA ACLR Performance, IF = ~150 MHz Figure 35. Four-Carrier W-CDMA ACLR Performance, IF = ~150 MHz Rev. B | Page 16 of 60 08281-131 08281-132 AD9122 TERMINOLOGY Integral Nonlinearity (INL) Settling Time INL is the maximum deviation of the actual analog output from Settling time is the time required for the output to reach and the ideal output, determined by a straight line drawn from zero remain within a specified error band around its final value, scale to full scale. measured from the start of the output transition. Differential Nonlinearity (DNL) Spurious-Free Dynamic Range (SFDR) DNL is the measure of the variation in analog value, normalized SFDR is the difference, in decibels, between the peak amplitude to full scale, associated with a 1 LSB change in digital input code. of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, energy in this band Offset Error is rejected by the interpolation filters. This specification, there- Offset error is the deviation of the output current from the ideal fore, defines how well the interpolation filters work and the of 0 mA. For IOUT1P, 0 mA output is expected when all inputs effect of other parasitic coupling paths on the DAC output. are set to 0. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal Gain Error to the rms sum of all other spectral components below the Nyquist Gain error is the difference between the actual and ideal output frequency, excluding the first six harmonics and dc. The value span. The actual span is determined by the difference between for SNR is expressed in decibels. the output when all inputs are set to 1 and the output when all inputs are set to 0. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of Output Compliance Range fDATA (interpolation rate), a digital filter can be constructed that The output compliance range is the range of allowable voltage has a sharp transition band near fDATA/2. Images that typically at the output of a current output DAC. Operation beyond the appear around f (output data rate) can be greatly suppressed. DAC maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between Temperature Drift the measured power within a channel and that of its adjacent Temperature drift is specified as the maximum change from channel. the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale Complex Image Rejection range (FSR) per degree Celsius. For reference voltage drift, the In a traditional two-part upconversion, two images are created drift is reported in ppm per degree Celsius. around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing Power Supply Rejection (PSR) the real part of a second complex modulator in series with the PSR is the maximum change in the full-scale output as the first complex modulator, either the upper or lower frequency supplies are varied from minimum to maximum specified image near the second IF can be rejected. voltages. Rev. B | Page 17 of 60 AD9122 DIFFERENCES BETWEEN AD9122R1 AND AD9122R2 The AD9122 underwent a die revision in early 2010, which DEVICE MARKING OF AD9122R1 AND AD9122R2 incremented the die revision from R1 to R2. The following list Revision 1 devices are marked as shown in Figure 36. Revision 1 explains the differences between the revisions. devices with TxDAC® as the top line have date codes earlier than #1001. Revision 1 devices with AD80255 as the top line have date • IOVDD supply voltage range. codes of #1001 or later. For the AD9122R1, the valid operational voltage range for IOVDD is 1.8 V to 2.5 V ± 10%. For the AD9122R2, the valid operational voltage range for IOVDD is 1.8 V ® TxDAC AD80255 AD9122BCPZ AD9122BCPZ to 3.3 V ± 10%. DATE CODE #0935 #1001 • Reduction in spurs level variation. 1688587.1 1688586.1 KOREA KOREA The AD9122R1 has variation in the f ± f spur level DATA OUT between device startups. The AD9122R2 has a consistent Figure 36. Revision 1 Silicon, AD9122BCPZ Marking and lower fDATA ± fOUT spur level. (The AD9122R2 still has Revision 2 devices are marked as shown in Figure 37. Revision 2 a spur level variation between power cycles of about 5 dB devices have TxDAC® as the top line and date codes of #1001 or if the PLL is enabled.) later. • DCI delay feature added. The AD9122R2 has a programmable delay associated with ® the DCI signal. There are four programmable delay options. TxDAC AD9122BCPZ The 00 setting gives the minimum delay and leaves the DATE CODE #1021 timing unchanged from the AD9122R1. Additional delay 1688782.1 KOREA can be added to improve timing margins in some systems. The resulting timing options are shown in Table 13. Figure 37. Revision 2 Silicon, AD9122BCPZ Marking • Power-down mode power consumption increase. The maximum power-down mode power consumption of the R1 devices is 9.8 mW. This power consumption increased to 18.8 mW in the R2 devices. • Configuration register map changes. Register 0x0B, Bit 5: AD9122R1 Æ Enable VCO AD9122R2 Æ Inactive bit. The VCO is now enabled when the PLL is enabled. Register 0x16, Bits[1:0]: AD9122R1 Æ Unused AD9122R2 Æ These bits control the delay of the DCI signal (00 = minimum delay, 11 = maximum delay). Register 0x7F: AD9122R1 Æ Version ID = 0x04 AD9122R2 Æ Version ID = 0x0C Rev. B | Page 18 of 60 08281-137 08281-136 AD9122 THEORY OF OPERATION The AD9122 combines many features that make it a very attractive The remaining SCLK edges are for Phase 2 of the communication DAC for wired and wireless communications systems. The dual cycle. Phase 2 is the actual data transfer between the device and digital signal path and dual DAC structure allow an easy interface the system controller. Phase 2 of the communication cycle is a to common quadrature modulators when designing single side- transfer of one or more data bytes. Registers change immediately band (SSB) transmitters. The speed and performance of the upon writing to the last bit of each transfer byte, except for the AD9122 allow wider bandwidths and more carriers to be syn- frequency tuning word and NCO phase offsets, which change thesized than in previously available DACs. In addition, the only when the frequency tuning word (FTW) update bit AD9122 includes an innovative low power, 32-bit, complex (Register 0x36, Bit 0) is set. NCO that greatly increases the ease of frequency placement. DATA FORMAT The AD9122 offers features that allow simplified synchroniza- The instruction byte contains the information shown in Table 9. tion with incoming data and between multiple devices. Auxiliary DACs are also provided on chip. The auxiliary DACs can be used Table 9. Serial Port Instruction Byte for output dc offset compensation (for LO compensation in SSB I7 (MSB) I6 I5 I4 I3 I2 I1 I0 (LSB) transmitters) and for gain matching (for image rejection optimiza- R/W A6 A5 A4 A3 A2 A1 A0 tion in SSB transmitters). R/W, Bit 7 of the instruction byte, determines whether a read SERIAL PORT OPERATION or a write data transfer occurs after the instruction byte write. The serial port is a flexible, synchronous serial communications Logic 1 indicates a read operation, and Logic 0 indicates a write port that allows easy interfacing to many industry-standard micro- operation. controllers and microprocessors. The serial I/O is compatible A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the with most synchronous transfer formats, including both the register that is accessed during the data transfer portion of the Motorola SPI and Intel® SSR protocols. The interface allows communication cycle. For multibyte transfers, A6 is the starting read/write access to all registers that configure the AD9122. byte address. The remaining register addresses are generated by Single-byte or multiple-byte transfers are supported, as well as the device based on the LSB_FIRST bit (Register 0x00, Bit 6). MSB first or LSB first transfer formats. The serial port interface SERIAL PORT PIN DESCRIPTIONS can be configured as a single-pin I/O (SDIO) or as two unidi- rectional pins for input and output (SDIO and SDO). Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device SDO 50 and runs the internal state machines. The maximum frequency SDIO 51 SPI of SCLK is 40 MHz. All data input is registered on the rising edge PORT 52 SCLK of SCLK. All data is driven out on the falling edge of SCLK. CS 53 CS Chip Select ( ) Figure 38. Serial Port Interface Pins An active low input starts and gates a communication cycle. A communication cycle with the AD9122 has two phases. It allows more than one device to be used on the same serial Phase 1 is the instruction cycle (the writing of an instruction communications lines. When the CS pin is high, the SDO and byte into the device), coincident with the first eight SCLK rising SDIO pins go to a high impedance state. During the communica- edges. The instruction byte provides the serial port controller CS tion cycle, the pin should stay low. with information regarding the data transfer cycle—Phase 2 of Serial Data I/O (SDIO) the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, along with Data is always written into the device on this pin. However, this the starting register address for the first byte of the data transfer. pin can be used as a bidirectional data line. The configuration The first eight SCLK rising edges of each communication cycle of this pin is controlled by Register 0x00, Bit 7. The default is are used to write the instruction byte into the device. Logic 0, configuring the SDIO pin as unidirectional. A logic high on the CS pin followed by a logic low resets the Serial Data Output (SDO) serial port timing to the initial state of the instruction cycle. Data is read from this pin for protocols that use separate lines From this state, the next eight rising SCLK edges represent the for transmitting and receiving data. If the device operates in a instruction bits of the current I/O operation. single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Rev. B | Page 19 of 60 08281-010 AD9122 INSTRUCTION CYCLE DATA TRANSFER CYCLE SERIAL PORT OPTIONS CS The serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSB_FIRST bit SCLK (Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0). A0 A1 A2 A3 A4 A5 A6 R/W D0 D1 D2 D4 D5 D6 D7 SDIO When LSB_FIRST = 0 (MSB first), the instruction and data bits 0 0 0 N N N N must be written from MSB to LSB. Multibyte data transfers in SDO D0 D1 D2 D4 D5 D6 D7 0 0 0 N N N N MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent Figure 40. Serial Port Interface Timing, LSB First data bytes should follow from high address to low address. In MSB first mode, the serial port internal byte address generator t DCSB decrements for each data byte of the multibyte communication t SCLK cycle. CS When LSB_FIRST = 1 (LSB first), the instruction and data bits t t PWH PWL must be written from LSB to MSB. Multibyte data transfers in SCLK LSB first format start with an instruction byte that includes the t DS t DH register address of the least significant data byte. Subsequent SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 data bytes should follow from low address to high address. In Figure 41. Timing Diagram for Serial Port Register Write LSB first mode, the serial port internal byte address generator increments for each data byte of the multibyte communication cycle. CS If the MSB first mode is active, the serial port controller data address decrements from the data address written toward 0x00 SCLK for multibyte I/O operations. If the LSB first mode is active, the t DV serial port controller data address increments from the data SDIO, DATA BIT n DATA BIT n – 1 address written toward 0x7F for multibyte I/O operations. SDO Figure 42. Timing Diagram for Serial Port Register Read INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 N N N 0 0 0 0 SDO D7 D6 D5 D3 D2 D1 D0 N N N 0 0 0 0 Figure 39. Serial Port Interface Timing, MSB First Rev. B | Page 20 of 60 08281-011 08281-014 08281-013 08281-012 AD9122 DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10. Device Configuration Register Map Addr (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x00 Comm SDIO LSB_FIRST Reset 0x00 0x01 Power control Power Power Power Power 0x10 down down down data down I DAC Q DAC receiver aux ADC 0x03 Data format Binary Q data MSB swap Data Bus Width[1:0] 0x00 data first format 0x04 Interrupt enable Enable Enable Enable Enable Enable Enable 0x00 PLL lock PLL sync sync FIFO FIFO lost locked signal lost signal Warning 1 Warning 2 locked 0x05 Interrupt enable 0 0 0 Enable Enable Enable 0 0 0x00 AED AED SED compare compare compare pass fail fail 0x06 Event flag PLL lock PLL Sync Sync FIFO FIFO N/A lost locked signal signal Warning 1 Warning 2 lost locked 0x07 Event flag AED AED SED N/A compare compare compare pass fail fail 0x08 Clock receiver DACCLK REFCLK DACCLK REFCLK 1 1 1 1 0x3F control duty duty cross- cross- correction correction correction correction 0x0A PLL control PLL PLL Manual VCO Band[5:0] 0x40 enable manual enable 0x0C PLL control PLL Loop PLL Charge Pump Current[4:0] 0xD1 Bandwidth[1:0] 0x0D PLL control N2[1:0] PLL cross- N0[1:0] N1[1:0] 0xD9 control enable 0x0E PLL status PLL locked VCO Control Voltage[3:0] N/A 0x0F PLL status VCO Band Readback[5:0] N/A 0x10 Sync control Sync Data/FIFO Rising Sync Averaging[2:0] 0x48 enable rate toggle edge sync 0x11 Sync control Sync Phase Request[5:0] 0x00 0x12 Sync status Sync lost Sync N/A locked 0x13 Sync status Sync Phase Readback[7:0] (6.2 format) N/A 0x15 Data receiver LVDS LVDS LVDS DCI LVDS DCI LVDS data LVDS data N/A status FRAME FRAME level high level low level high level low level high level low 0x16 DCI delay DCI Delay[1:0] 0x00 0x17 FIFO control FIFO Phase Offset[2:0] 0x04 0x18 FIFO status FIFO FIFO FIFO soft FIFO soft N/A Warning 1 Warning 2 align ack align request 0x19 FIFO status FIFO Level[7:0] N/A 0x1B Datapath Bypass Bypass Bypass NCO gain Bypass Select Send 0xE4 −1 control premod sinc NCO phase sideband I data to comp and Q data dc offset Rev. B | Page 21 of 60 AD9122 Addr (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x1C HB1 control HB1[1:0] Bypass HB1 0x00 0x1D HB2 control HB2[5:0] Bypass HB2 0x00 0x1E HB3 control HB3[5:0] Bypass HB3 0x00 0x1F Chip ID Chip ID[7:0] 0x08 0x30 FTW LSB FTW[7:0] 0x00 0x31 FTW FTW[15:8] 0x00 0x32 FTW FTW[23:16] 0x00 0x33 FTW MSB FTW[31:24] 0x00 0x34 NCO phase NCO Phase Offset[7:0] 0x00 offset LSB 0x35 NCO phase NCO Phase Offset[15:8] 0x00 offset MSB 0x36 NCO FTW FRAME FRAME Update Update 0x00 update FTW ack FTW FTW ack FTW request request 0x38 I phase adj LSB I Phase Adj[7:0] 0x00 0x39 I phase adj MSB I Phase Adj[9:8] 0x00 0x3A Q phase adj LSB Q Phase Adj[7:0] 0x00 0x3B Q phase adj MSB Q Phase Adj[9:8] 0x00 0x3C I DAC offset LSB I DAC Offset[7:0] 0x00 0x3D I DAC offset MSB I DAC Offset[15:8] 0x00 0x3E Q DAC offset Q DAC Offset[7:0] 0x00 LSB 0x3F Q DAC offset Q DAC Offset[15:8] 0x00 MSB 0x40 I DAC FS adjust I DAC FS Adj[7:0] 0xF9 0x41 I DAC control I DAC I DAC FS Adj[9:8] 0x01 sleep 0x42 I aux DAC data I Aux DAC[7:0] 0x00 0x43 I aux DAC I aux I aux DAC I aux DAC I Aux DAC[9:8] 0x00 control DAC sign current sleep direction 0x44 Q DAC FS adjust Q DAC FS Adj[7:0] 0xF9 0x45 Q DAC control Q DAC Q DAC FS Adj[9:8] 0x01 sleep 0x46 Q aux DAC data Q Aux DAC[7:0] 0x00 0x47 Q aux DAC Q aux Q aux DAC Q aux Q Aux DAC[9:8] 0x00 control DAC sign current DAC direction sleep 0x48 Die temp range FS Current[2:0] Reference Current[2:0] Capacitor 0x02 control value 0x49 Die temp LSB Die Temp[7:0] N/A 0x4A Die temp MSB Die Temp[15:8] N/A 0x67 SED control SED Sample Autoclear Compare Compare 0x00 compare error enable fail pass enable detected 0x68 Compare I0 LSBs Compare Value I0[7:0] 0xB6 0x69 Compare Compare Value I0[15:8] 0x7A I0 MSBs 0x6A Compare Compare Value Q0[7:0] 0x45 Q0 LSBs 0x6B Compare Compare Value Q0[15:8] 0xEA Q0 MSBs Rev. B | Page 22 of 60 AD9122 Addr (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x6C Compare I1 LSBs Compare Value I1[7:0] 0x16 0x6D Compare Compare Value I1[15:8] 0x1A I1 MSBs 0x6E Compare Value Q1[7:0] 0xC6 Compare Q1 LSBs 0x6F Compare Compare Value Q1[15:8] 0xAA Q1 MSBs 0x70 SED I LSBs Errors Detected I_BITS[7:0] 0x00 0x71 SED I MSBs Errors Detected I_BITS[15:8] 0x00 0x72 SED Q LSBs Errors Detected Q_BITS[7:0] 0x00 0x73 SED Q MSBs Errors Detected Q_BITS[15:8] 0x00 0x7F Revision 0 0 Revision[3:0] 0 0 N/A Table 11. Device Configuration Register Descriptions Register Address Name (Hex) Bits Name Description Default Comm 0x00 7 SDIO SDIO pin operation. 0 0 = SDIO operates as an input only. 1 = SDIO operates as a bidirectional input/output. 6 LSB_FIRST Serial port communication, LSB or MSB first. 0 0 = MSB first. 1 = LSB first. 5 Reset The device is placed in reset when this bit is written high 0 and remains in reset until the bit is written low. Power 0x01 7 Power down I DAC 1 = power down I DAC. 0 Control 6 Power down Q DAC 1 = power down Q DAC. 0 5 Power down data 1 = power down the input data receiver. 0 receiver 4 Power down auxiliary 1 = power down the auxiliary ADC for temperature sensor. 1 ADC Data 0x03 7 Binary data format 0 = input data is in twos complement format. 0 Format 1 = input data is in binary format. 6 Q data first Indicates I/Q data pairing on data input. 0 0 = I data sent to data receiver first. 1 = Q data sent to data receiver first. 5 MSB swap Swaps the bit order of the data input port. 0 0 = order of the data bits corresponds to the pin descriptions. 1 = bit designations are swapped; most significant bits become the least significant bits. [1:0] Data Bus Width[1:0] Data receiver interface mode. See the LVDS Input Data Ports 00 section for information about the operation of the different interface modes. 00 = word mode; 16-bit interface bus width. 01 = byte mode; 8-bit interface bus width. 10 = nibble mode; 4-bit interface bus width. 11 = invalid. Interrupt 0x04 7 Enable PLL lock lost 1 = enable interrupt for PLL lock lost. 0 Enable 6 Enable PLL locked 1 = enable interrupt for PLL locked. 0 5 Enable sync signal lost 1 = enable interrupt for sync signal lost. 0 4 Enable sync signal locked 1 = enable interrupt for sync signal locked. 0 1 Enable FIFO Warning 1 1 = enable interrupt for FIFO Warning 1. 0 0 Enable FIFO Warning 2 1 = enable interrupt for FIFO Warning 2. 0 Rev. B | Page 23 of 60 AD9122 Register Address Name (Hex) Bits Name Description Default Interrupt 0x05 [7:5] Set to 0 Set these bits to 0. 000 Enable 4 Enable AED compare pass 1 = enable interrupt for AED comparison pass. 0 3 Enable AED compare fail 1 = enable interrupt for AED comparison fail. 0 2 Enable SED compare fail 1 = enable interrupt for SED comparison fail. 0 [1:0] Set to 0 Set these bits to 0. 00 Event Flag 0x06 7 PLL lock lost 1 = indicates that the PLL, which had been previously N/A locked, has unlocked from the reference signal. This is a latched signal. 6 PLL locked 1 = indicates that the PLL has locked to the reference N/A clock input. 5 Sync signal lost 1 = indicates that the sync logic, which had been previously N/A locked, has lost alignment. This is a latched signal. 4 Sync signal locked 1 = indicates that the sync logic has achieved sync N/A alignment. This is indicated when no phase changes were requested for at least a few full averaging cycles. 1 FIFO Warning 1 1 = indicates that the difference between the FIFO read N/A and write pointers is 1. 0 FIFO Warning 2 1 = indicates that the difference between the FIFO read N/A and write pointers is 2. Note that all event flags are cleared by writing the respective bit high. 0x07 4 AED compare pass N/A 1 = indicates that the SED logic detected a valid input data pattern compared against the preprogrammed expected values. This is a latched signal. 3 AED compare fail N/A 1 = indicates that the SED logic detected an invalid input data pattern compared against the preprogrammed expected values. This latched signal is automatically cleared when eight valid I/Q data pairs are received. 2 SED compare fail 1 = indicates that the SED logic detected an invalid input N/A data pattern compared against the preprogrammed expected values. This is a latched signal. Note that all event flags are cleared by writing the respective bit high. 0x08 7 DACCLK duty correction 1 = enable duty cycle correction on the DACCLK input. 0 Clock Receiver 6 REFCLK duty correction 1 = enable duty cycle correction on the REFCLK input. 0 Control 5 DACCLK cross-correction 1 = enable differential crossing correction on the DACCLK 1 input. 4 REFCLK cross-correction 1 = enable differential crossing correction on the REFCLK 1 input. PLL Control 0x0A 7 PLL enable 1 = enable the PLL clock multiplier. The REFCLK input is used 0 as the PLL reference clock signal. 6 PLL manual enable 1 = enable manual selection of the VCO band. The correct 1 VCO band must be determined by the user and written to Bits[5:0]. [5:0] Manual VCO Band[5:0] Selects the VCO band to be used. 000000 0x0C [7:6] PLL Loop Bandwidth[1:0] Selects the PLL loop filter bandwidth. 11 00 = widest bandwidth. … 11 = narrowest bandwidth. [4:0] PLL Charge Pump Sets the nominal PLL charge pump current. 10001 Current[4:0] 00000 = lowest current setting. … 11111 = highest current setting. Rev. B | Page 24 of 60 AD9122 Register Address Name (Hex) Bits Name Description Default PLL Control 0x0D [7:6] N2[1:0] PLL control clock divider. This divider determines the ratio of 11 the DACCLK frequency to the PLL controller clock frequency. f must always be less than 75 MHz. PC_CLK 00 = f /f = 2. DACCLK PC_CLK 01 = fDACCLK/fPC_CLK = 4. 10 = fDACCLK/fPC_CLK = 8. 11 = fDACCLK/fPC_CLK = 16. 4 PLL cross-control enable 1 = enable PLL cross-point controller. 1 [3:2] N0[1:0] PLL VCO divider. This divider determines the ratio of the VCO 10 frequency to the DACCLK frequency. 00 = fVCO/fDACCLK = 1. 01 = fVCO/fDACCLK = 2. 10 = f /f = 4. VCO DACCLK 11 = f /f = 4. VCO DACCLK [1:0] N1[1:0] PLL loop divider. This divider determines the ratio of the 01 DACCLK frequency to the REFCLK frequency. 00 = f /f = 2. DACCLK REFCLK 01 = f /f = 4. DACCLK REFCLK 10 = fDACCLK/fREFCLK = 8. 11 = fDACCLK/fREFCLK = 16. PLL Status 0x0E 7 PLL locked 1 = the PLL-generated clock is tracking the REFCLK input N/A signal. [3:0] VCO Control Voltage[3:0] VCO control voltage readback. See Table 24. N/A 0x0F [5:0] VCO Band Readback[5:0] Indicates the VCO band currently selected. N/A Sync 0x10 7 Sync enable 1 = enable the synchronization logic. 0 Control 6 Data/FIFO rate toggle 0 = operate the synchronization at the FIFO reset rate. 1 1 = operate the synchronization at the data rate. 3 Rising edge sync 0 = sync is initiated on the falling edge of the sync input. 1 1 = sync is initiated on the rising edge of the sync input. [2:0] Sync Averaging[2:0] Sets the number of input samples that are averaged in 000 determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128. 0x11 [5:0] Sync Phase Request[5:0] This register sets the requested clock phase offset after sync. 000000 The offset unit is in DACCLK cycles. This register enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. … 111111 = 63 DACCLK cycles. Rev. B | Page 25 of 60 AD9122 Register Address Name (Hex) Bits Name Description Default Sync Status 0x12 7 Sync lost 1 = synchronization was attained but has been lost. N/A 6 Sync locked 1 = synchronization has been attained. N/A 0x13 [7:0] Sync Phase Readback[7:0] Indicates the averaged sync phase offset (6.2 format). If N/A this value differs from the Sync Phase Request[5:0] value in Register 0x11, a sync timing error has occurred. For more information, see the Sync Status Bits section. 00000000 = 0.0. 00000001 = 0.25. … 11111110 = 63.50. 11111111 = 63.75. Data 0x15 5 LVDS FRAME level high One or both LVDS FRAME input signals have exceeded 1.7 V. N/A Receiver 4 LVDS FRAME level low One or both LVDS FRAME input signals have crossed below N/A Status 0.7 V. 3 LVDS DCI level high One or both LVDS DCI input signals have exceeded 1.7 V. N/A 2 LVDS DCI level low One or both LVDS DCI input signals have crossed N/A below 0.7 V. 1 LVDS data level high One or more LVDS Dx input signals have exceeded 1.7 V. N/A 0 LVDS data level low One or more LVDS Dx input signals have crossed below 0.7 V. N/A DCI Delay 0x16 [1:0] DCI Delay[1:0] This option is available for the Revision 2 silicon only. The 00 DCI delay bits control the delay applied to the DCI signal. The DCI delay affects the sampling interval of the DCI with respect to the Dx inputs. See Table 13. 00 = 350 ps delay of DCI signal. 01 = 590 ps delay of DCI signal. 10 = 800 ps delay of DCI signal. 11 = 925 ps delay of DCI signal. FIFO 0x17 [2:0] FIFO Phase Offset[2:0] FIFO write pointer phase offset following FIFO reset. This 100 Control is the difference between the read pointer and the write pointer values upon FIFO reset. The optimal value is nominally 4 (100). 000 = 0. 001 = 1. … 111 = 7. FIFO Status 0x18 7 FIFO Warning 1 1 = FIFO read and write pointers are within ±1. N/A 6 FIFO Warning 2 1 = FIFO read and write pointers are within ±2. N/A 2 FIFO soft align 1 = FIFO read and write pointers are aligned after a serial N/A acknowledge port initiated FIFO reset. 1 FIFO soft align request 1 = request FIFO read and write pointer alignment via the 0 serial port. 0x19 [7:0] FIFO Level[7:0] Thermometer encoded measure of the FIFO level. N/A Rev. B | Page 26 of 60 AD9122 Register Address Name (Hex) Bits Name Description Default Datapath 0x1B 7 Bypass premod 1 = bypass the fS/2 premodulator. 1 Control −1 6 Bypass sinc 1 = bypass the inverse sinc filter. 1 5 Bypass NCO 1 = bypass the NCO. 1 3 NCO gain 0 = no gain scaling is applied to the NCO input to the 0 internal digital modulator (default). 1 = gain scaling of 0.5 is applied to the NCO input to the internal digital modulator. Gain scaling can eliminate satu- ration of the modulator output for some combinations of data inputs and NCO signals. 2 Bypass phase 1 = bypass phase compensation and dc offset. 1 compensation and dc offset 1 Select sideband 0 = the modulator outputs the high-side image. 0 1 = the modulator outputs the low-side image. The image is spectrally inverted compared to the input data. 0 Send I data to Q data 1 = ignore Q data from the interface and disable the clocks 0 to the Q datapath. Send I data to both the I and Q DACs. HB1 Control 0x1C [2:1] HB1[1:0] Modulation mode for I Side Half-Band Filter 1. 00 00 = input signal not modulated; filter pass band is from −0.4 to +0.4 of fIN1. 01 = input signal not modulated; filter pass band is from 0.1 to 0.9 of f . IN1 10 = input signal modulated by fIN1; filter pass band is from 0.6 to 1.4 of f . IN1 11 = input signal modulated by fIN1; filter pass band is from 1.1 to 1.9 of fIN1. 0 Bypass HB1 1 = bypass the first-stage interpolation filter. 0 HB2 Control 0x1D [6:1] HB2[5:0] Modulation mode for I Side Half-Band Filter 2. 000000 000000 = input signal not modulated; filter pass band is from −0.25 to +0.25 of fIN2. 001001 = input signal not modulated; filter pass band is from 0.0 to 0.5 of fIN2. 010010 = input signal not modulated; filter pass band is from 0.25 to 0.75 of f . IN2 011011 = input signal not modulated; filter pass band is from 0.5 to 1.0 of fIN2. 100100 = input signal modulated by fIN2; filter pass band is from 0.75 to 1.25 of f . IN2 101101 = input signal modulated by f ; filter pass band is IN2 from 1.0 to 1.5 of f . IN2 110110 = input signal modulated by fIN2; filter pass band is from 1.25 to 1.75 of fIN2. 111111 = input signal modulated by fIN2; filter pass band is from 1.5 to 2.0 of f . IN2 0 Bypass HB2 1 = bypass the second-stage interpolation filter. 0 Rev. B | Page 27 of 60 AD9122 Register Address Name (Hex) Bits Name Description Default HB3 Control 0x1E [6:1] HB3[5:0] Modulation mode for I Side Half-Band Filter 3. 000000 000000 = input signal not modulated; filter pass band is from −0.2 to +0.2 of f . IN3 001001 = input signal not modulated; filter pass band is from 0.05 to 0.45 of fIN3. 010010 = input signal not modulated; filter pass band is from 0.3 to 0.7 of fIN3. 011011 = input signal not modulated; filter pass band is from 0.55 to 0.95 of f . IN3 100100 = input signal modulated by fIN3; filter pass band is from 0.8 to 1.2 of fIN3. 101101 = input signal modulated by fIN3; filter pass band is from 1.05 to 1.45 of f . IN3 110110 = input signal modulated by f ; filter pass band is IN3 from 1.3 to 1.7 of f . IN3 111111 = input signal modulated by fIN3; filter pass band is from 1.55 to 1.95 of fIN3. 0 Bypass HB3 1 = bypass the third-stage interpolation filter. 0 Chip ID 0x1F [7:0] Chip ID[7:0] This register identifies the device as an AD9122. 00001000 FTW LSB 0x30 [7:0] FTW[7:0] See Register 0x33. 00000000 FTW 0x31 [7:0] FTW[15:8] See Register 0x33. 00000000 FTW 0x32 [7:0] FTW[23:16] See Register 0x33. 00000000 FTW MSB 0x33 [7:0] FTW[31:24] FTW[31:0] is the 32-bit frequency tuning word that deter- 00000000 mines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Bit 0 of Register 0x36 transitions from 0 to 1. NCO Phase 0x34 [7:0] NCO Phase Offset[7:0] See Register 0x35. 00000000 Offset LSB NCO Phase 0x35 [7:0] NCO Phase Offset[15:8] The NCO sets the phase of the complex carrier signal when 00000000 Offset MSB the NCO is reset. The phase offset spans from 0° to 360°. Each bit represents an offset of 0.0055°. This value is in twos complement format. NCO FTW 0x36 5 FRAME FTW acknowledge 1 = the NCO has been reset due to an extended FRAME 0 Update pulse signal. 4 FRAME FTW request 0 = the NCO is reset on the first extended FRAME pulse after 0 this bit is set to 1. 1 Update FTW acknowledge 1 = the FTW has been updated. 0 0 Update FTW request The FTW is updated on the 0-to-1 transition of this bit. 0 I Phase Adj 0x38 [7:0] I Phase Adj[7:0] See Register 0x39. 00000000 LSB I Phase Adj 0x39 [1:0] I Phase Adj[9:8] I Phase Adj[9:0] is used to insert a phase offset between 00 MSB the I and Q datapaths. This offset can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for more information. 0x3A [7:0] Q Phase Adj[7:0] See Register 0x3B. 00000000 Q Phase Adj LSB Q Phase Adj 0x3B [1:0] Q Phase Adj[9:8] Q Phase Adj[9:0] is used to insert a phase offset between 00 MSB the I and Q datapaths. This offset can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for more information. I DAC Offset 0x3C [7:0] I DAC Offset[7:0] See Register 0x3D. 00000000 LSB I DAC Offset 0x3D [7:0] I DAC Offset[15:8] I DAC Offset[15:0] is a value that is added directly to the 00000000 MSB samples written to the I DAC. Rev. B | Page 28 of 60 AD9122 Register Address Name (Hex) Bits Name Description Default Q DAC 0x3E [7:0] Q DAC Offset[7:0] See Register 0x3F. 00000000 Offset LSB Q DAC 0x3F [7:0] Q DAC Offset[15:8] Q DAC Offset[15:0] is a value that is added directly to the 00000000 Offset MSB samples written to the Q DAC. I DAC 0x40 [7:0] I DAC FS Adj[7:0] See Register 0x41, Bits[1:0]. 11111001 FS Adjust I DAC 0x41 7 I DAC sleep 1 = puts the I DAC into sleep mode (fast wake-up mode). 0 Control [1:0] I DAC FS Adj[9:8] I DAC FS Adj[9:0] sets the full-scale current of the I DAC. 01 The full-scale current can be adjusted from 8.64 mA to 31.68 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.16 mA. … 0x3FF = 31.68 mA. I Aux DAC 0x42 [7:0] I Aux DAC[7:0] See Register 0x43, Bits[1:0]. 00000000 Data I Aux DAC 0x43 7 I aux DAC sign 0 = the I auxiliary DAC sign is positive, and the current is 0 Control directed to the IOUT1P pin (Pin 67). 1 = the I auxiliary DAC sign is negative, and the current is directed to the IOUT1N pin (Pin 66). 6 I aux DAC current 0 = the I auxiliary DAC sources current. 0 direction 1 = the I auxiliary DAC sinks current. 5 I aux DAC sleep 1 = puts the I auxiliary DAC into sleep mode. 0 [1:0] I Aux DAC[9:8] I Aux DAC[9:0] sets the magnitude of the auxiliary DAC 00 current. The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. Q DAC 0x44 [7:0] Q DAC FS Adj[7:0] See Register 0x45, Bits[1:0]. 11111001 FS Adjust Q DAC 0x45 7 Q DAC sleep 1 = puts the Q DAC into sleep mode (fast wake-up mode). 0 Control [1:0] Q DAC FS Adj[9:8] Q DAC FS Adj[9:0] sets the full-scale current of the Q DAC. 01 The full-scale current can be adjusted from 8.64 mA to 31.68 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.16 mA. … 0x3FF = 31.68 mA. Q Aux DAC 0x46 [7:0] Q Aux DAC[7:0] See Register 0x47, Bits[1:0]. 00000000 Data Rev. B | Page 29 of 60 AD9122 Register Address Name (Hex) Bits Name Description Default Q Aux DAC 0x47 7 Q aux DAC sign 0 = the Q auxiliary DAC sign is positive, and the current is 0 Control directed to the IOUT2P pin (Pin 58). 1 = the Q auxiliary DAC sign is negative, and the current is directed to the IOUT2N pin (Pin 59). 6 Q aux DAC current 0 = the Q auxiliary DAC sources current. 0 direction 1 = the Q auxiliary DAC sinks current. 5 Q aux DAC sleep 1 = puts the Q auxiliary DAC into sleep mode. 0 [1:0] Q Aux DAC[9:8] Q Aux DAC[9:0] sets the magnitude of the auxiliary DAC 00 current. The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. Die Temp 0x48 [6:4] FS Current[2:0] Auxiliary ADC full-scale current. 000 Range 000 = lowest current. Control … 111 = highest current. [3:1] Reference Current[2:0] Auxiliary ADC reference current. 001 000 = lowest current. … 111 = highest current. 0 Capacitor value Auxiliary ADC internal capacitor value. 0 0 = 5 pF. 1 = 10 pF. Die Temp 0x49 [7:0] Die Temp[7:0] See Register 0x4A. N/A LSB Die Temp 0x4A [7:0] Die Temp[15:8] Die Temp[15:0] indicates the approximate die temperature. N/A MSB For more information, see the Temperature Sensor section. SED Control 0x67 7 SED compare enable 0 1 = enable the SED circuitry. None of the flags in this register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled. 5 Sample error detected 0 1 = indicates an error was detected. The bit remains set until cleared. Any write to this register clears this bit to 0. 3 Autoclear enable 1 = enable autoclear mode. This activates Bit 1 and Bit 0 of 0 this register and causes Register 0x70 through Register 0x73 to be autocleared when eight consecutive sample data sets are received error free. 1 Compare fail 1 = indicates an error was detected. This bit remains set until 0 it is autocleared by the reception of eight consecutive error- free comparisons or is cleared by a write to this register. 0 Compare pass 1 = indicates that the last sample comparison was error free. 0 Compare 0x68 [7:0] Compare Value I0[7:0] See Register 0x69. 10110110 I0 LSBs Compare 0x69 [7:0] Compare Value I0[15:8] Compare Value I0[15:0] is the word that is compared with 01111010 I0 MSBs the I0 input sample captured at the input interface. Compare 0x6A [7:0] Compare Value Q0[7:0] See Register 0x6B. 01000101 Q0 LSBs Compare 0x6B [7:0] Compare Value Q0[15:8] Compare Value Q0[15:0] is the word that is compared with 11101010 Q0 MSBs the Q0 input sample captured at the input interface. Compare 0x6C [7:0] Compare Value I1[7:0] See Register 0x6D. 00010110 I1 LSBs Compare 0x6D [7:0] Compare Value I1[15:8] Compare Value I1[15:0] is the word that is compared 00011010 I1 MSBs with the I1 input sample captured at the input interface. Rev. B | Page 30 of 60 AD9122 Register Address Name (Hex) Bits Name Description Default Compare 0x6E [7:0] Compare Value Q1[7:0] See Register 0x6F. 11000110 Q1 LSBs Compare 0x6F [7:0] Compare Value Q1[15:8] Compare Value Q1[15:0] is the word that is compared 10101010 Q1 MSBs with the Q1 input sample captured at the input interface. SED I 0x70 [7:0] Errors Detected See Register 0x71. 00000000 LSBs I_BITS[7:0] SED I 0x71 [7:0] Errors Detected Errors Detected I_BITS[15:0] indicates which bits were 00000000 MSBs I_BITS[15:8] received in error. SED Q 0x72 [7:0] Errors Detected See Register 0x73. 00000000 LSBs Q_BITS[7:0] SED Q 0x73 [7:0] Errors Detected Errors Detected Q_BITS[15:0] indicates which bits were 00000000 MSBs Q_BITS[15:8] received in error. Revision 0x7F [5:2] Revision[3:0] This value corresponds to the die revision number. N/A 0001 = Die Revision 1. 0011 = Die Revision 2. Rev. B | Page 31 of 60 AD9122 LVDS INPUT DATA PORTS The AD9122 has one LVDS data port that receives data for BYTE INTERFACE MODE both the I and Q transmit paths. The device can accept data in In byte mode, the DCI signal is a reference bit used to generate word, byte, and nibble formats. In word, byte, and nibble modes, the data sampling clock. The DCI signal should be time aligned the data is sent over 16-bit, 8-bit, and 4-bit LVDS data buses, with the data. The most significant byte of the data should corre- respectively. The pin assignments of the bus in each mode are spond to DCI high, and the least significant byte of the data should shown in Table 12. correspond to DCI low. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the Table 12. Data Bit Pair Assignments for Data Input Modes I DAC; when FRAME is low, data is sent to the Q DAC. The Mode MSB to LSB complete timing diagram is shown in Figure 44. Word D15, D14, …, D0 1 Byte D14, D12, D10, D8, D7, D5, D3, D1 NIBBLE INTERFACE MODE 1 Nibble D10, D8, D7, D5 In nibble mode, the DCI signal is a reference bit used to generate 1 the data sampling clock. The DCI signal should be time aligned In byte and nibble modes, the unused pins can be left floating. with the data. The FRAME signal indicates to which DAC the The data is accompanied by a reference bit (DCI) that is used data is sent. When FRAME is high, data is sent to the I DAC; to generate a double data rate (DDR) clock. In byte and nibble when FRAME is low, data is sent to the Q DAC. All four nibbles modes, a FRAME signal is required for controlling to which DAC must be written to the device for proper operation. For 12-bit the data is sent. All of the interface signals are time aligned, so resolution devices, the data in the fourth nibble acts as a place- there is a maximum skew requirement on the bus. holder for the data framing structure. The complete timing WORD INTERFACE MODE diagram is shown in Figure 45. In word mode, the DCI signal is a reference bit used to generate INTERFACE TIMING the data sampling clock. The DCI signal should be time aligned The timing diagram for the digital interface port is shown in with the data. The I DAC data should correspond to DCI high, Figure 46. The sampling point of the data bus nominally occurs and the Q DAC data should correspond to DCI low, as shown 350 ps after each edge of the DCI signal and has an uncertainty in Figure 43. of ±300 ps, as illustrated by the sampling interval shown in DCI Figure 46. The data and FRAME signals must be valid through- out this sampling interval. The data and FRAME signals may change at any time between sampling intervals. Q I Q I Q I Q DATA[15:0] 0 1 1 2 2 3 3 Figure 43. Timing Diagram for Word Mode DCI Q I I Q Q I I Q Q DATA[15:0] 0LSB 1MSB 1LSB 1MSB 1LSB 2MSB 2LSB 2MSB 2LSB FRAME Figure 44. Timing Diagram for Byte Mode DCI DATA[15:0] Q I I I I Q Q Q Q I 0N0 1N3 1N2 1N1 1N0 1N3 1N2 1N1 1N0 2N3 FRAME Figure 45. Timing Diagram for Nibble Mode Rev. B | Page 32 of 60 08281-015 08281-016 08281-017 AD9122 The setup (t ) and hold (t ) times, with respect to the edges, S H FIFO OPERATION are shown in Figure 46. The minimum setup and hold times The AD9122 contains a 2-channel, 16-bit wide, eight-word deep are shown in Table 13. FIFO designed to relax the timing relationship between the data t t DATA DATA arriving at the DAC input ports and the internal DAC data rate clock. The FIFO acts as a buffer that absorbs timing variations between the data source and the DAC, such as the clock-to-data DCI variation of an FPGA or ASIC, which significantly increases the timing budget of the interface. SAMPLING SAMPLING Figure 47 shows the block diagram of the datapath through INTERVAL INTERVAL the FIFO. The data is latched into the device, is formatted, and is then written into the FIFO register determined by the FIFO write pointer. The value of the write pointer is incremented DATA every time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register determined by the read pointer t t S S and fed into the digital datapath. The value of the read pointer t t H H is incremented every time data is read into the datapath from Figure 46. Timing Diagram for Input Data Port the FIFO. The FIFO pointers are incremented at the data rate (DACCLK rate divided by the interpolation ratio). Table 13. Data to DCI Setup and Hold Times Valid data is transmitted through the FIFO as long as the FIFO DCI Delay Register 0x16, Minimum Setup Minimum Hold Sampling does not overflow or become empty. An overflow or empty Bits[1:0] Time, t (ns) Time, t (ns) Interval (ns) S H condition of the FIFO occurs when the write pointer and read 00 −0.05 0.65 0.6 pointer point to the same FIFO location. This simultaneous 01 −0.23 0.95 0.72 access of data leads to unreliable data transfer through the FIFO 10 −0.38 1.22 0.84 and must be avoided. 11 −0.47 1.38 0.91 Nominally, data is written to and read from the FIFO at the same The data interface timing can be verified by using the sample rate. This keeps the FIFO depth constant. If data is written to error detection (SED) circuitry. See the Interface Timing the FIFO faster than data is read out, the FIFO depth increases. Validation section for more information. If data is read out of the FIFO faster than data is written to it, the FIFO depth decreases. For optimum timing margin, the FIFO depth should be maintained near half full (a difference of 4 between the write pointer and read pointer values). The FIFO depth represents the FIFO pipeline delay and is part of the over- all latency of the AD9122. 32 BITS WRITE READ POINTER POINTER REG 0 REG 1 REG 2 I AND Q 32 32 32 I AND Q INPUT DATA DATA REG 3 DATA DACS LATCH FORMAT PATHS REG 4 REG 5 REG 6 REG 7 DACCLK DCI ÷ INT FRAME RESET LOGIC FIFO SOFT ALIGN REQUEST SYNC REG 0x18[1] FIFO PHASE OFFSET DATA/FIFO RATE REG 0x10[6] REG 0x17[2:0] Figure 47. Block Diagram of FIFO Rev. B | Page 33 of 60 08281-146 WRITE POINTER RESET READ POINTER RESET 08281-018 AD9122 Resetting the FIFO The recommended procedure for a serial port FIFO data level initialization is as follows: When the AD9122 is powered on, the FIFO depth is unknown. To avoid a concurrent read and write to the same FIFO address 1. Program Register 0x17 to 0x05. and to ensure a fixed pipeline delay, it is important to reset the 2. Request FIFO level reset by setting Register 0x18, Bit 1, to 1. FIFO pointers to known states. The FIFO pointers can be initial- 3. Verify that the part acknowledges the request by ensuring ized in two ways: via a write sequence to the serial port or by that Register 0x18, Bit 2, is set to 1. strobing the FRAME input. There are two types of FIFO resets: 4. Remove the request by setting Register 0x18, Bit 1, to 0. a relative reset and an absolute reset. A relative reset enforces a 5. Verify that the part drops the acknowledge signal by defined FIFO depth. An absolute reset enforces a particular write ensuring that Register 0x18, Bit 2, is set to 0. pointer value when the reset is initiated. A serial port initiated 6. Read back Register 0x19 to verify that the pointer spacing FIFO reset is always a relative reset. A FRAME strobe initiated is set to 3 (0x07) or 4 (0x0F). reset can be either a relative or an absolute reset. 7. If the readback of Register 0x19 shows a pointer spacing of 2 (0x03), increment Register 0x17 to a spacing of 0x06 and If the FRAME differential inputs are not used for FIFO reset repeat Step 2 through Step 5. Read back Register 0x19 again or for framing the word width, they must be tied to logic low. to verify that the pointer spacing is now set to 3 (0x07). FRAMEP must be tied to DVSS, and FRAMEN must be tied 8. If the readback of Register 0x19 shows a pointer spacing of to DVDD18 to avoid accidental reset of the FIFO due to noise. 5 (0x1F) after Step 6, decrement Register 0x17 to a spacing The operation of the FRAME initiated FIFO reset depends on of 0x04 and repeat Step 2 through Step 5. Read back the synchronization mode chosen. Register 0x19 again to verify that the pointer spacing is • When synchronization is disabled or when it is configured now set to 4 (0x0F). for data rate mode synchronization, the FRAME strobe FRAME Initiated Relative FIFO Reset initiates a relative FIFO reset. The reference point of the The primary function of the FRAME input is to indicate to relative reset is the position of the read pointer. which DAC the input data is written. Another function of the • When FIFO mode synchronization is chosen, the FRAME FRAME input is to initialize the FIFO data level value. This is strobe initiates an absolute FIFO reset. done by asserting the FRAME signal high for at least the time For more information about the synchronization function, see interval required to load complete data to the I and Q DACs. the Multichip Synchronization section. This corresponds to one DCI period in word mode, two DCI periods in byte mode, and four DCI periods in nibble mode. A summary of the synchronization modes and the types of FIFO reset used is provided in Table 14. To initiate a relative FIFO reset with the FRAME signal, the device must be configured in data rate mode (Register 0x10, Table 14. Summary of FIFO Resets Bit 6 = 1). When FRAME is asserted in data rate mode, the Synchronization Mode write pointer is set to 4 by default (or to the FIFO start level) FIFO Reset Signal Disabled Data Rate FIFO Reset the next time that the read pointer becomes 0 (see Figure 48). Serial Port Relative Relative Relative READ 0 1 2 3 4 5 6 7 0 1 2 3 FRAME Relative Relative Absolute POINTER FIFO WRITE RESETS FRAME Serial Port Initiated FIFO Reset A serial port initiated FIFO reset can be issued in any synchro- WRITE 3 4 5 6 7 0 1 2 3 4 5 6 nization mode and always results in a relative FIFO reset. To POINTER initialize the FIFO data level through the serial port, Bit 1 of Figure 48. FRAME Input vs. Write Pointer Value, Data Rate Mode Register 0x18 should be toggled from 0 to 1 and back. When the write to this register is complete, the FIFO data level is initialized. When the initialization is triggered, the next time that the read pointer becomes 0, the write pointer is set to the value of the FIFO start level variable (Register 0x17, Bits[2:0]) upon initialization. By default, this value is 4, but it can be programmed to a value from 0 to 7. It is recommended that a value of 5 (0x05) be pro- grammed in Register 0x17. Rev. B | Page 34 of 60 08281-019 AD9122 FRAME Initiated Absolute FIFO Reset Monitoring the FIFO Status In FIFO rate synchronization mode, the write pointer of the FIFO The FIFO initialization and status can be read from Register 0x18. is reset in an absolute manner. The synchronization signal aligns This register provides information about the FIFO status and the internal clocks on the part to a common reference clock so whether the initialization was successful. The MSB of Register 0x18 that the pipeline delay in the digital circuit stays the same during is a FIFO warning flag that can optionally trigger a device IRQ. power cycles. The synchronization signal is sampled by the DAC This flag indicates that the FIFO is close to emptying (FIFO clock in the AD9122. The edge of the DAC clock used to sample level is 1) or overflowing (FIFO level is 7). In this case, data the synchronization signal is selected by Bit 3 of Register 0x10. may soon be corrupted, and action should be taken. The FRAME signal is used to reset the FIFO write pointer. In The FIFO data level can be read from Register 0x19 at any time. the FIFO rate synchronization mode, the FIFO write pointer is The serial port reported FIFO data level is denoted as a 7-bit reset immediately after the FRAME signal is asserted high for at thermometer code (Base 1 code) of the write counter state least the time interval required to load complete data to the I relative to the absolute read counter being at 0. The optimum and Q DACs. The FIFO write pointer is reset to the value of the FIFO data level of 4 is therefore reported as a value of 00001111 FIFO Phase Offset[2:0] bits in Register 0x17. FIFO rate synchro- in the status register. nization is selected by setting Bit 6 of Register 0x10 to 0. Note that, depending on the timing relationship between the SYNC DCI and the main DACCLK, the FIFO level value can be off FIFO READ RESET by a ±1 count, that is, the readback of Register 0x19 can be READ 01 2 3 4 5 6 7 0 1 2 3 POINTER 00011111 in the case of a +1 count and 00000111 in the case of FIFO WRITE a −1 count. Therefore, it is important to keep the difference RESET FIFO PHASE OFFSET[2:0] FRAME REG 0x17[2:0] = 101 between the read and write pointers to a value of at least 2. WRITE 66 5 6 7 0 1 2 347 5 POINTER Figure 49. FRAME Input vs. Write Pointer Value, FIFO Rate Mode Rev. B | Page 35 of 60 08281-148 AD9122 DIGITAL DATAPATH The block diagram in Figure 50 shows the functionality of the The half-band filters operate in several modes, providing digital datapath. The digital processing includes a premodulation programmable pass-band center frequencies as well as signal block, three half-band (HB) interpolation filters, a quadrature modulation. The HB1 filter has four modes of operation, and modulator with a fine resolution NCO, phase and offset adjust- the HB2 and HB3 filters each have eight modes of operation. ment blocks, and an inverse sinc filter. Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 51. The PHASE shape of the filter response is identical in each of the four modes. AND –1 PREMOD HB1 HB2 HB3 SINC OFFSET The four modes are distinguished by two factors: the filter center ADJUST frequency and whether the input signal is modulated by the filter. Figure 50. Block Diagram of Digital Datapath MODE 0 MODE 2 MODE 1 MODE 3 The digital datapath accepts I and Q data streams and processes 0 them as a quadrature data stream. The signal processing blocks can be used when the input data stream is represented as complex data. –20 The digital datapath can also be used to process an input data stream representing two independent real data streams, but the –40 functionality is somewhat restricted. The premodulation block and any of the nonshifted interpolation filter modes can be used –60 for an input data stream representing two independent real data streams. See the Coarse Modulation Mixing Sequences section –80 for more information. –100 PREMODULATION 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 The half-band interpolation filters have selectable pass bands FREQUENCY (× f ) (Hz) IN1 that allow the center frequencies to be moved in increments of Figure 51. HB1 Filter Modes one-half their input data rate. The premodulation block provides As shown in Figure 51, the center frequency in each mode is a digital upconversion of the incoming waveform by one-half the offset by one-half the input data rate (fIN1) of the filter. Mode 0 incoming data rate, fDATA. This can be used to frequency-shift base- and Mode 1 do not modulate the input signal. Mode 2 and band input data to the center of the interpolation filter pass band. Mode 3 modulate the input signal by fIN1. When operating in INTERPOLATION FILTERS Mode 0 and Mode 2, the I and Q paths operate independently and no mixing of the data between channels occurs. When oper- The transmit path contains three interpolation filters. Each of the ating in Mode 1 and Mode 3, mixing of the data between the three interpolation filters provides a 2× increase in output data I and Q paths occurs; therefore, the data input into the filter is rate. The half-band (HB) filters can be individually bypassed or assumed to be complex. Table 15 summarizes the HB1 modes. cascaded to provide 1×, 2×, 4×, or 8× interpolation ratios. Each half-band filter stage offers a different combination of bandwidths Table 15. HB1 Filter Modes and operating modes. Mode fCENTER fMOD Input Data The bandwidth of the three half-band filters with respect to the 0 DC None Real or complex data rate at the filter input is as follows: 1 f/2 None Complex IN • Bandwidth of HB1 = 0.8 × fIN1 2 fIN fIN Real or complex 3 3fIN/2 fIN Complex • Bandwidth of HB2 = 0.5 × fIN2 • Bandwidth of HB3 = 0.4 × fIN3 The usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than +85 dB. As described in the Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. Rev. B | Page 36 of 60 08281-020 MAGNITUDE (dB) 08281-021 AD9122 Figure 52 shows the pass-band filter response for HB1. In most Half-Band Filter 2 (HB2) applications, the usable bandwidth of the filter is limited by the HB2 has eight modes of operation, as shown in Figure 53 and image suppression provided by the stop-band rejection and not Figure 54. The shape of the filter response is identical in each of by the pass-band flatness. Table 16 shows the pass-band flatness the eight modes. The eight modes are distinguished by two factors: and stop-band rejection supported by the HB1 filter at different the filter center frequency and whether the input signal is bandwidths. modulated by the filter. 0.02 MODE 0 MODE 4 MODE 2 MODE 6 0 0 –20 –0.02 –40 –0.04 –60 –0.06 –80 –0.08 –0.10 –100 00 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36.40 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 FREQUENCY (× f ) (Hz) FREQUENCY (× f ) (Hz) IN1 IN2 Figure 52. Pass-Band Detail of HB1 Figure 53. HB2, Even Filter Modes Table 16. HB1 Pass-Band and Stop-Band Performance by MODE 7 MODE 1 MODE 5 MODE 3 Bandwidth 0 Pass-Band Stop-Band Bandwidth (% of fIN1) Flatness (dB) Rejection (dB) –20 80 0.001 85 80.4 0.0012 80 –40 81.2 0.0033 70 82 0.0076 60 –60 83.6 0.0271 50 85.6 0.1096 40 –80 –100 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 FREQUENCY (× f ) (Hz) IN2 Figure 54. HB2, Odd Filter Modes As shown in Figure 53 and Figure 54, the center frequency in each mode is offset by one-fourth the input data rate (f ) of IN2 the filter. Mode 0 through Mode 3 do not modulate the input signal. Mode 4 through Mode 7 modulate the input signal by fIN2. When operating in Mode 0 and Mode 4, the I and Q paths operate independently and no mixing of the data between chan- nels occurs. When operating in the other six modes, mixing of the data between the I and Q paths occurs; therefore, the data input to the filter is assumed to be complex. Rev. B | Page 37 of 60 MAGNITUDE (dB) 08281-022 MAGNITUDE (dB) MAGNITUDE (dB) 08281-024 08281-023 AD9122 Table 17 summarizes the HB2 and HB3 modes. Half-Band Filter 3 (HB3) HB3 has eight modes of operation that function the same as Table 17. HB2 and HB3 Filter Modes HB2. The primary difference between HB2 and HB3 is the Mode f f Input Data CENTER MOD filter bandwidths. 0 DC None Real or complex Figure 56 shows the pass-band filter response for HB3. In most 1 f/4 None Complex IN applications, the usable bandwidth of the filter is limited by the 2 f/2 None Complex IN image suppression provided by the stop-band rejection and not 3 3f/4 None Complex IN by the pass-band flatness. Table 19 shows the pass-band flatness 4 fIN fIN Real or complex and stop-band rejection supported by the HB3 filter at different 5 5fIN/4 fIN Complex bandwidths. 6 3fIN/2 fIN Complex 0.02 7 7f/4 f Complex IN IN 0 Figure 55 shows the pass-band filter response for HB2. In most applications, the usable bandwidth of the filter is limited by the –0.02 image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 18 shows the pass-band flatness –0.04 and stop-band rejection supported by the HB2 filter at different bandwidths. –0.06 0.02 –0.08 0 –0.10 00 0.04 0.08 0.12 0.16 0.20 0.24.28 –0.02 FREQUENCY (× f ) (Hz) IN3 Figure 56. Pass-Band Detail of HB3 –0.04 Table 19. HB3 Pass-Band and Stop-Band Performance by –0.06 Bandwidth Pass-Band Stop-Band –0.08 Bandwidth (% of fIN3) Flatness (dB) Rejection (dB) 40 0.001 85 –0.10 00 0.04 0.08 0.12 0.16 0.20 0.24 0.28.32 40.8 0.0014 80 FREQUENCY (× f ) (Hz) IN2 42.4 0.002 70 Figure 55. Pass-Band Detail of HB2 45.6 0.0093 60 49.8 0.03 50 Table 18. HB2 Pass-Band and Stop-Band Performance by 55.6 0.1 40 Bandwidth Pass-Band Stop-Band Bandwidth (% of f ) Flatness (dB) Rejection (dB) IN2 50 0.001 85 50.8 0.0012 80 52.8 0.0028 70 56 0.0089 60 60 0.0287 50 64.8 0.1877 40 Rev. B | Page 38 of 60 MAGNITUDE (dB) 08281-025 MAGNITUDE (dB) 08281-026 AD9122 I DATA INTERPOLATION COSINE FTW[31:0] NCO NCO PHASE OFFSET OUT_I [15:0] SINE OUT_Q – + –1 1 SPECTRAL 0 INVERSION INTERPOLATION Q DATA Figure 57. Digital Quadrature Modulator Block Diagram Given these four parameters, the first step in configuring the NCO MODULATION datapath is to verify that the device supports the bandwidth The digital quadrature modulator makes use of a numerically requirements. The modes of the interpolation filters are then controlled oscillator (NCO), a phase shifter, and a complex chosen. Finally, any additional frequency offset requirements modulator to provide a means for modulating the signal by a are determined and applied with premodulation and NCO programmable carrier signal. A block diagram of the digital modulation. modulator is shown in Figure 57. The fine modulation provided by the digital modulator, in conjunction with the coarse modu- Determining the Datapath Signal Bandwidth lation of the interpolation filters and premodulation block, The available signal bandwidth of the datapath is dependent allows the signal to be placed anywhere in the output spectrum on the center frequency of the output signal in relation to the with very fine frequency resolution. center frequency of the interpolation filters used. Signal center frequencies offset from the center frequencies of the half-band The quadrature modulator is used to mix the carrier signal filters lower the available signal bandwidth. generated by the NCO with the I and Q signal. The NCO produces a quadrature carrier signal to translate the input signal to a new When correctly configured, the available complex signal band- center frequency. A complex carrier signal is a pair of sinusoidal width for 2× interpolation is always 80% of the input data rate. waveforms of the same frequency, offset 90° from each other. The available signal bandwidth for 4× interpolation vs. output The frequency of the complex carrier signal is set via FTW[31:0] frequency varies between 50% and 80% of the input data rate, in Register 0x30 through Register 0x33. as shown in Figure 58. Note that in 4× interpolation mode, f = 4 × f ; therefore, the data shown in Figure 58 repeats The NCO operating frequency, f , is at either f (HB1 DAC DATA NCO DATA four times from dc to f . bypassed) or 2× f (HB1 enabled). The frequency of the DAC DATA complex carrier signal can be set from dc up to fNCO. The HB1 AND HB2 frequency tuning word (FTW) is calculated as 0.8 f CARRIER 32 FTW= ×2 f NCO 0.5 The generated quadrature carrier signal is mixed with the I and Q data. The quadrature products are then summed into the I HB2 AND HB3 0.3 and Q data paths, as shown in Figure 57. Updating the Frequency Tuning Word The frequency tuning word registers are not updated immediately upon writing, as other configuration registers are. After loading 0.2 0.4 0.6 0.8 1.0 f /f OUT DATA the FTW registers with the desired values, Bit 0 of Register 0x36 Figure 58. Signal Bandwidth vs. Center Frequency of the Output Signal, must transition from 0 to 1 for the new FTW to take effect. 4× Interpolation DATAPATH CONFIGURATION Configuring 4× interpolation using the HB2 and HB3 filters can Configuring the AD9122 datapath starts with the application lower the power consumption of the device at the expense of band- requirements of the input data rate, the interpolation ratio, the width. The lower curve in Figure 58 shows that the supported output signal bandwidth, and the output signal center frequency. bandwidth in this mode varies from 30% to 50% of f . DATA Rev. B | Page 39 of 60 BANDWIDTH/f DATA 08281-027 08281-028 AD9122 The available signal bandwidth for 8× interpolation vs. output DETERMINING INTERPOLATION FILTER MODES frequency varies between 50% and 80% of the input data rate, Table 20 shows the recommended interpolation filter settings as shown in Figure 59. Note that in 8× interpolation mode, for a variety of filter interpolation factors, filter center frequencies, fDAC = 8 × fDATA; therefore, the data shown in Figure 59 repeats and signal modulation. The interpolation modes were chosen eight times from dc to fDAC. based on the final center frequency of the signal and by deter- mining the frequency shift of the signal required. When these HB1, HB2, AND HB3 parameters are known and put in terms of the input data rate 0.8 (fDATA), the filter configuration that comes closest to matching is selected from Table 20. 0.6 0.5 0.1 0.4 0.6 0.9 0.25 0.50 0.75 1.00 f /f OUT DATA Figure 59. Signal Bandwidth vs. Center Frequency of the Output Signal, 8× Interpolation Table 20. Recommended Interpolation Filter Modes (Register 0x1C Through Register 0x1E) Filter Modes Interpolation Factor HB1[1:0] HB2[5:0] HB3[5:0] f Modulation f Shift SIGNAL CENTER 8 00 (Mode 0) 000000 000000 DC 0 1 8 01 (Mode 1) 001001 000000 DC f /2 DATA 2 8 10 (Mode 2) 010010 001001 f f DATA DATA 1 8 11 (Mode 3) 011011 001001 f 3f /2 DATA DATA 8 00 (Mode 0) 100100 010010 2fDATA 2fDATA 1 8 01 (Mode 1) 101101 010010 2fDATA 5fDATA/2 8 10 (Mode 2) 110110 011011 3fDATA 3fDATA 1 8 11 (Mode 3) 111111 011011 3f 7f /2 DATA DATA 8 00 (Mode 0) 000000 100100 4f 4f DATA DATA 1 8 01 (Mode 1) 001001 100100 4fDATA 9fDATA/2 8 10 (Mode 2) 010010 101101 5fDATA 5fDATA 1 8 11 (Mode 3) 011011 101101 5fDATA 11fDATA/2 8 00 (Mode 0) 100100 110110 6f 6f DATA DATA 1 8 01 (Mode 1) 101101 110110 6f 13f /2 DATA DATA 8 10 (Mode 2) 110110 111111 7f 7f DATA DATA 1 8 11 (Mode 3) 111111 111111 7fDATA 15fDATA/2 4 00 (Mode 0) 000000 Bypass DC 0 3 1 4 01 (Mode 1) 001001 Bypass DC f /2 DATA 4 10 (Mode 2) 010010 Bypass fDATA fDATA 1 4 11 (Mode 3) 011011 Bypass fDATA 3fDATA/2 4 00 (Mode 0) 100100 Bypass 2f 2f DATA DATA 1 4 01 (Mode 1) 101101 Bypass 2f 5f /2 DATA DATA 4 10 (Mode 2) 110110 Bypass 3f 3f DATA DATA 1 4 11 (Mode 3) 111111 Bypass 3fDATA 7fDATA/2 2 00 (Mode 0) Bypass Bypass DC 0 1 2 01 (Mode 1) Bypass Bypass DC f /2 DATA 2 10 (Mode 2) Bypass Bypass fDATA fDATA 1 2 11 (Mode 3) Bypass Bypass fDATA 3fDATA/2 1 When HB1 Mode 1 or Mode 3 is used, enabling premodulation provides an additional frequency translation of the input signal by f /2, which centers a baseband DATA input signal in the filter pass band. 2 This configuration was used in the 8× interpolation without NCO example (see the 8× Interpolation Without NCO section). 3 This configuration was used in the 4× interpolation with NCO example (see the 4× Interpolation with NCO section). Rev. B | Page 40 of 60 BANDWIDTH/f DATA 08281-029 AD9122 4× Interpolation with NCO DATAPATH CONFIGURATION EXAMPLES 8× Interpolation Without NCO For this example, the following parameters are given: For this example, the following parameters are given: f = 250 MSPS • DATA • 4× interpolation • f = 100 MSPS DATA • f = 140 MHz BW • 8× interpolation • f = 175 MHz CENTER • f = 75 MHz BW • f = 100 MHz CENTER The desired 140 MHz of bandwidth is 56% of fDATA. As shown in Figure 58, the value at 0.7 × fDATA is 0.6. This is calculated as The desired 75 MHz of bandwidth is 75% of f . In this case, DATA 0.8 − 2(0.7 − 0.6) = 0.6. This verifies that the AD9122 supports the ratio of f /f = 100/100 = 1.0. From Figure 59, the band- OUT DATA a bandwidth of 60% of fDATA, which exceeds the required 56%. width supported at f is 0.8, which verifies that the AD9122 DATA supports the bandwidth required in this configuration. The signal center frequency is 0.7 × f and, assuming the DATA input signal is at baseband, the frequency shift required is also The signal center frequency is fDATA and, assuming the input 0.7 × f . Choosing the second row in the Interpolation Factor DATA signal is at baseband, the frequency shift required is also fDATA. column in the 4× interpolation section of Table 20 selects the filter Choosing the third row (highlighted by the superscripted modes that give a center frequency of fDATA/2 with no frequency number 2) of the Interpolation Factor column from Table 20 translation. The selected modes for the three half-band filters selects filter modes that give a center frequency of f and a DATA are HB1, Mode 1; HB2, Mode 1; and HB3, bypassed. frequency translation of f . The selected modes for the three DATA half-band filters are HB1, Mode 2; HB2, Mode 2; and HB3, Because Mode 1 of HB1 was selected, the premodulation block Mode 1. Figure 60 shows how the signal propagates through the should be enabled. This provides f /2 modulation, which DATA interpolation filters. centers the baseband input data at the center frequency of HB1. The digital modulator can be used to provide the final frequency Because 2 × fIN1 = fIN2 and 2 × fIN2 = fIN3, the signal appears translation of 0.2 × fDATA to place the output signal at 0.7 × fDATA, frequency scaled by one-half into each consecutive stage. The as desired. output signal band spans 0.15 to 0.35 of f (400 MHz). There- IN3 fore, the output frequency supported is 60 MHz to 140 MHz, The formula for calculating the FTW of the NCO is as follows: which covers the 75 MHz bandwidth centered at 100 MHz, as f CARRIER 32 desired. FTW= ×2 f NCO where: f = 0.2 × f . CARRIER DATA f = 2 × f . NCO DATA 32 Therefore, FTW = 2 /10. 0 2 0 1 3 HB1 0.1 0.4 0.6 × f IN1 –0.5 0 0.5 1.0 1.5 2.0 1 3 5 7 0 4 HB2 2 6 0.25 0.75 1.25 1.75 × f IN2 –0.5 0 0.5 1.0 1.5 2.0 0.3 0.7 0 1 3 5 7 4 HB3 2 6 –0.2 0.2 0.3 0.7 × f IN3 –0.5 0 0.5 1.0 1.5 2.0 0.15 0.35 Figure 60. Signal Propagation for 8× Interpolation (f Modulation) DATA Rev. B | Page 41 of 60 08281-030 AD9122 In practice, this modulation results in the mixing functions DATA RATES vs. INTERPOLATION MODES shown in Table 21. Table 22 summarizes the maximum bus speed (fBUS), supported input data rates, and signal bandwidths with the various combi- Table 21. Modulation Mixing Sequences nations of bus width modes and interpolation rates. The real Modulation Mixing Sequence signal bandwidth supported is a fraction of the input data rate, fS/2 I = I, −I, I, −I, … which depends on the interpolation filters (HB1, HB2, or HB3) Q = Q, −Q, Q, −Q, … selected. The complex signal bandwidth supported is twice the fS/4 I = I, Q, −I, −Q, … real signal bandwidth. Q = Q, −I, −Q, I, … In general, 2× interpolation is best supported by enabling HB1, 3fS/4 I = I, −Q, −I, Q, … and 4× interpolation is best supported by enabling HB1 and HB2. Q = Q, I, −Q, −I, … However, in some cases, power dissipation can be lowered by not fS/8 I = I, r(I + Q), Q, r(−I + Q), −I, −r(I + Q), −Q, r(I − Q), … using HB1. If the bandwidth required is low enough, 2× interpo- Q = Q, r(Q − I), −I, −r(Q + I), −Q, r(−Q + I), I, r(Q + I), … lation can be supported by using HB2, and 4× interpolation can 2 be supported by using HB2 and HB3. Note that r= 2 COARSE MODULATION MIXING SEQUENCES As shown in Table 21, the mixing functions of most of the modes The coarse digital quadrature modulation occurs within the cross-couple samples between the I and Q channels. The I and interpolation filters. The modulation shifts the frequency Q channels operate independently only in fS/2 mode. This means spectrum of the incoming data by the frequency offset selected. that real modulation using both the I and Q DAC outputs can The frequency offsets available are multiples of the input data only be done in fS/2 mode. All other modulation modes require rate. The modulation is equivalent to multiplying the quadra- complex input data and produce complex output signals. ture input signal by a complex carrier signal, C(t), of the form C(t) = cos(ωct) + j sin(ωct) Table 22. Summary of Data Rates and Bandwidths vs. Interpolation Modes (DVDD18, CVDD18 = 1.9 V ± 2%) Filter Modes Bus Width HB3 HB2 HB1 fBUS (Mbps) fDATA (Mbps) Real Signal Bandwidth (MHz) fDAC (MHz) Nibble (4 Bits) 0 0 0 1230 153.75 75 153.75 0 0 1 1230 153.75 60 307.5 0 1 0 1230 153.75 37.5 307.5 0 1 1 1230 153.75 60 615 1 1 0 1230 153.75 37.5 615 1 1 1 1230 153.75 60 1230 Byte (8 Bits) 0 0 0 1230 307.5 150 307.5 0 0 1 1230 307.5 120 615 0 1 0 1230 307.5 75 615 0 1 1 1230 307.5 120 1230 1 1 0 1230 307.5 75 1230 1 1 1 615 153.75 60 1230 Word (16 Bits) 0 0 0 1230 615 300 615 0 0 1 1000 500 200 1000 0 1 0 1230 615 150 1230 0 1 1 615 307.5 120 1230 1 1 0 615 307.5 75 1230 1 1 1 307.5 153.75 60 1230 Rev. B | Page 42 of 60 AD9122 QUADRATURE PHASE CORRECTION 20 0 The purpose of the quadrature phase correction block is to enable compensation of the phase imbalance of the analog quadrature modulator following the DAC. If the quadrature 15 5 modulator has a phase imbalance, the unwanted sideband appears with significant energy. Tuning the quadrature phase 10 10 adjust value can optimize image rejection in single sideband radios. 5 15 Ordinarily, the I and Q channels have an angle of precisely 90° between them. The quadrature phase adjustment is used to change the angle between the I and Q channels. When I Phase Adj[9:0] 20 0 (Register 0x38 and Register 0x39) is set to 1000000000, the I DAC 0x0000 0x4000 0x8000 0xC000 0xFFFF DAC OFFSET VALUE output moves approximately 1.75° away from the Q DAC output, creating an angle of 91.75° between the channels. When I Phase Figure 61. DAC Output Currents vs. DAC Offset Value Adj[9:0] is set to 0111111111, the I DAC output moves approx- INVERSE SINC FILTER imately 1.75° toward the Q DAC output, creating an angle of −1 The inverse sinc (sinc ) filter is a nine-tap FIR filter. The composite 88.25° between the channels. −1 response of the sinc filter and the sin(x)/x response of the DAC Q Phase Adj[9:0] (Register 0x3A and Register 0x3B) works in is shown in Figure 62. The composite response has a pass-band a similar fashion. When Q Phase Adj[9:0] is set to 1000000000, ripple of less than ±0.05 dB up to a frequency of 0.4 × f . To DACCLK the Q DAC output moves approximately 1.75° away from the provide the necessary peaking at the upper end of the pass band, I DAC output, creating an angle of 91.75° between the channels. the inverse sinc filters shown have an intrinsic insertion loss of When Q Phase Adj[9:0] is set to 0111111111, the Q DAC output about 3.2 dB. Figure 62 shows the composite frequency response. moves approximately 1.75° toward the I DAC output, creating –3.0 an angle of 88.25° between the channels. Based on these two endpoints, the combined resolution of the –3.2 phase compensation register is approximately 3.5°/1024 or 0.00342° per code. –3.4 DC OFFSET CORRECTION The dc value of the I datapath and the Q datapath can be –3.6 independently controlled by adjusting the I DAC Offset[15:0] and Q DAC Offset[15:0] values in Register 0x3C through –3.8 Register 0x3F. These values are added directly to the datapath values. Care should be taken not to overrange the transmitted values. –4.0 00 0.1 0.2 0.3 0.4.5 Figure 61 shows how the DAC offset current varies as a function f /f OUT DAC of the I DAC Offset[15:0] and Q DAC Offset[15:0] values. With −1 Figure 62. Sample Composite Responses of the Sinc Filter with sin(x)/x Roll-Off the digital inputs fixed at midscale (0x0000, twos complement data −1 The sinc filter is disabled by default. It can be enabled by format), Figure 61 shows the nominal IOUTxP and IOUTxN currents −1 setting the bypass sinc bit to 0 (Register 0x1B, Bit 6). as the DAC offset value is swept from 0 to 65,535. Because I OUTxP and I are complementary current outputs, the sum of I OUTxN OUTxP and I is always 20 mA. OUTxN Rev. B | Page 43 of 60 I (mA) OUTxP MAGNITUDE (dB) I (mA) OUTxN 08281-032 08281-031 AD9122 DAC INPUT CLOCK CONFIGURATIONS The AD9122 DAC sampling clock (DACCLK) can be sourced when the clock input signal is between 800 mV p-p differential directly or by clock multiplying. Clock multiplying uses the and 1.6 V p-p differential. Whether using the on-chip clock on-chip phase-locked loop (PLL), which accepts a reference clock multiplier or sourcing the DACCLK directly, it is necessary that operating at a submultiple of the desired DACCLK rate, most the input clock signal to the device have low jitter and fast edge commonly the data input frequency. The PLL then multiplies rates to optimize the DAC noise performance. the reference clock up to the desired DACCLK frequency, which DIRECT CLOCKING can then be used to generate all the internal clocks required by Direct clocking with a low noise clock produces the lowest noise the DAC. The clock multiplier provides a high quality clock that spectral density at the DAC outputs. To select the differential meets the performance requirements of most applications. Using CLK inputs as the source for the DAC sampling clock, set the the on-chip clock multiplier eliminates the need to generate and PLL enable bit (Register 0x0A, Bit 7) to 0. This powers down the distribute the high speed DACCLK. internal PLL clock multiplier and selects the input from the The second mode bypasses the clock multiplier circuitry and DACCLKP and DACCLKN pins as the source for the internal allows the DACCLK to be sourced directly to the DAC core. DAC sampling clock. This mode enables the user to source a very high quality clock The device also has duty cycle correction circuitry and differ- directly to the DAC core. Sourcing the DACCLK directly through ential input level correction circuitry. Enabling these circuits can the REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may provide improved performance in some cases. The control bits be necessary in demanding applications that require the lowest for these functions are in Register 0x08 (see Table 11). possible DAC output noise, particularly when directly synthesizing signals above 150 MHz. CLOCK MULTIPLICATION DRIVING THE DACCLK AND REFCLK INPUTS The on-chip PLL clock multiplication circuit can be used to gen- erate the DAC sampling clock from a lower frequency reference The differential DACCLK and REFCLK inputs share similar clock. When the PLL enable bit (Register 0x0A, Bit 7) is set to 1, clock receiver input circuitry. Figure 63 shows a simplified circuit the clock multiplication circuit generates the DAC sampling clock diagram of the inputs. The on-chip clock receiver has a differential from the lower rate REFCLK input. The functional diagram of input impedance of about 10 kΩ. It is self-biased to a common- the clock multiplier is shown in Figure 64. mode voltage of about 1.25 V. The inputs can be driven by direct coupling differential PECL or LVDS drivers. The inputs The clock multiplication circuit operates such that the VCO can also be ac-coupled if the driving source cannot meet the outputs a frequency, fVCO, equal to the REFCLK input signal input compliance voltage of the receiver. frequency multiplied by N1 × N0. DACCLKP, f = f × (N1 × N0) VCO REFCLK REFCLKP The DAC sampling clock frequency, f , is equal to DACCLK 5kΩ f = f × N1 DACCLK REFCLK 1.25V 5kΩ The output frequency of the VCO must be chosen to keep fVCO DACCLKN, in the optimal operating range of 1.0 GHz to 2.1 GHz. The REFCLKN frequency of the reference clock and the values of N1 and N0 Figure 63. Clock Receiver Input Simplified Equivalent Circuit must be chosen so that the desired DACCLK frequency can be The minimum input drive level to either of the clock inputs is synthesized and the VCO output frequency is in the correct range. 100 mV p-p differential. The optimal performance is achieved REG 0x06[7:6] REG 0x0E[3:0] PLL LOCK LOST ADC VCO CONTROL PLL LOCKED VOLTAGE REFCLKP/REFCLKN PHASE LOOP (PIN 69 AND PIN 70) VCO DETECTION FILTER ÷N1 ÷N0 REG 0x0D[1:0] REG 0x0D[3:2] N1 N0 DACCLK DACCLKP/DACCLKN (PIN 2 AND PIN 3) REG 0x0D[7:6] ÷N2 N2 REG 0x0A[7] PLL ENABLE PC_CLK Figure 64. PLL Clock Multiplication Circuit Rev. B | Page 44 of 60 08281-033 08281-034 AD9122 Manual VCO Band Select PLL SETTINGS The device also has a manual band select mode (PLL manual Three settings for the PLL circuitry should be programmed to enable, Register 0x0A, Bit 6 = 1) that allows the user to select their nominal values. The PLL values shown in Table 23 are the the VCO tuning band. In manual mode, the VCO band is set recommended settings for these parameters. directly with the value written to the manual VCO band bits Table 23. PLL Settings (Register 0x0A, Bits[5:0]). To properly select the VCO band, Register Optimal follow these steps: PLL Control Register Address Bits Setting 1. Put the device in manual band select mode by setting PLL Loop Bandwidth[1:0] 0x0C [7:6] 11 Register 0x0A, Bit 6 = 1. PLL Charge Pump Current[4:0] 0x0C [4:0] 10001 2. Sweep the VCO band over a range of bands that results in PLL Cross-Control Enable 0x0D 4 1 the PLL being locked. 3. For each band, verify that the PLL is locked and read the PLL CONFIGURING THE VCO TUNING BAND using the VCO control voltage bits (Register 0x0E, Bits[3:0]). The PLL VCO has a valid operating range from approximately 4. Select the band that results in the control voltage being 1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands. closest to the center of the range, that is, 1001 or 1000 (see For any desired VCO output frequency, there may be several Table 24). The resulting VCO band should be the optimal valid PLL band select values. The frequency bands of a typical setting for the device. Write this value to the manual VCO device are shown in Figure 65. Device-to-device variations and band bits (Register 0x0A, Bits[5:0]). operating temperature affect the actual band frequency range. 5. If desired, an indication of where the VCO is within the Therefore, it is required that the optimal PLL band select value operating frequency band can be determined by querying the be determined for each individual device. VCO control voltage. Table 24 shows how to interpret the 0 PLL VCO control voltage value (Register 0x0E, Bits[3:0]). 4 8 Table 24. VCO Control Voltage Range Indications 12 VCO Control Voltage 16 (Register 0x0E, Bits[3:0]) Indication 20 24 1111 Move to higher VCO band 28 1110 32 1101 VCO is operating in the higher end 36 40 of the frequency band 1100 44 1011 48 52 1010 56 1001 VCO is operating within an optimal 60 region of the frequency band 1000 1000 1200 1400 1600 1800 2000 2200 0111 VCO FREQUENCY (MHz) 0110 Figure 65. PLL Lock Range over Temperature for a Typical Device 0101 VCO is operating in the lower end Automatic VCO Band Select of the frequency band 0100 The device has an automatic VCO band select feature on chip. 0011 0010 Using the automatic VCO band select feature is a simple and reliable method of configuring the VCO frequency band. This 0001 Move to lower VCO band feature is enabled by starting the PLL in manual mode, then 0000 placing the PLL in auto band select mode. This is done by setting Register 0x0A to a value of 0xCF, then to a value of 0xA0. When these values are written, the device executes an automated routine that determines the optimal VCO band setting for the device. The setting selected by the device ensures that the PLL remains locked over the full −40°C to +85°C operating temperature range of the device without further adjustment. (The PLL remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes.) Rev. B | Page 45 of 60 PLL BAND 08281-035 AD9122 ANALOG OUTPUTS For the nominal values of VREF (1.2 V), RSET (10 kΩ), and TRANSMIT DAC OPERATION DAC gain (512), the full-scale current of the DAC is typically Figure 66 shows a simplified block diagram of the transmit path 20.16 mA. The DAC full-scale current can be adjusted from DACs. The DAC core consists of a current source array, a switch 8.64 mA to 31.68 mA by setting the DAC gain parameter, as core, digital control logic, and full-scale output current control. shown in Figure 67. The DAC full-scale output current (IFS) is nominally 20 mA. 35 The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the 30 two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective 25 differential current delivered to the load. 20 I DAC FS ADJUST 1.2V REGISTER 0x40 IOUT1P 15 I DAC 5kΩ IOUT1N REFIO 10 CURRENT 0.1µF SCALING FSADJ 5 10kΩ IOUT2N R SET Q DAC IOUT2P 0 Q DAC FS ADJUST 0 200 400 600 800 1000 REGISTER 0x44 DAC GAIN CODE Figure 66. Simplified Block Diagram of DAC Core Figure 67. DAC Full-Scale Current vs. DAC Gain Code The DAC has a 1.2 V band gap reference with an output imped- Transmit DAC Transfer Function ance of 5 kΩ. The reference output voltage appears on the REFIO The output currents from the IOUT1P/IOUT2P and IOUT1N/ pin. When using the internal reference, decouple the REFIO pin IOUT2N pins are complementary, meaning that the sum of the to AVSS with a 0.1 μF capacitor. Use the internal reference only for two currents always equals the full-scale current of the DAC. The external circuits that draw dc currents of 2 μA or less. For dynamic digital input code to the DAC determines the effective differential loads or static loads greater than 2 μA, buffer the REFIO pin. If current delivered to the load. IOUT1P/IOUT2P provide maxi- desired, the internal reference can be overdriven by applying an mum output current when all bits are high. The output currents external reference (from 1.10 V to 1.30 V) to the REFIO pin. vs. DACCODE for the DAC outputs are expressed as A 10 kΩ external resistor, R , must be connected from the SET DACCODE ⎡ ⎤ FSADJ pin to AVSS. This resistor, along with the reference control I = × I (1) OUTxP FS N ⎢ ⎥ 2 ⎣ ⎦ amplifier, sets up the correct internal bias currents for the DAC. Because the full-scale current is inversely proportional to this I = I − I (2) OUTxN FS OUTxP resistor, the tolerance of RSET is reflected in the full-scale output N where DACCODE = 0 to 2 − 1. amplitude. Transmit DAC Output Configurations The full-scale current equation, where the DAC gain is set individ- The optimum noise and distortion performance of the AD9122 ually for the I and Q DACs in Register 0x40 and Register 0x44, is realized when it is configured for differential operation. The respectively, is as follows: common-mode error sources of the DAC outputs are significantly V ⎛ 3 ⎞ ⎛ ⎞ REF reduced by the common-mode rejection of a transformer or I = ×⎜72+ × DAC gain ⎟ ⎜ ⎟ FS R 16 ⎝ ⎠ ⎝ ⎠ SET differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Rev. B | Page 46 of 60 08281-037 I (mA) FS 08281-036 AD9122 –60 Figure 68 shows the most basic transmit DAC output circuitry. I = 10mA FS A pair of resistors, R , is used to convert each of the comple- O I = 20mA FS –65 I = 30mA mentary output currents to a differential voltage output, V . OUT FS Because the current outputs of the DAC are high impedance, –70 the differential driving point impedance of the DAC outputs, ROUT, is equal to 2 × RO. Figure 69 illustrates the output voltage –75 waveforms. V + IP IOUT1P –80 R O V OUTI –85 R O – V IN IOUT1N –90 01 0.2 0.4 0.6 0.8 1.0 1.2.4 V (V) CM V + IOUT2P QP Figure 70. IMD vs. Output Common-Mode Voltage (fOUT = 61 MHz, RLOAD = 50 Ω Differential, IFS = 10 mA, 20 mA, and 30 mA) R O V OUTQ –50 I = 10mA R O FS V – QN I = 20mA FS –55 IOUT2N I = 30mA FS Figure 68. Basic Transmit DAC Output Circuit –60 –65 +V PEAK –70 V CM –75 V V N P –80 0 –85 01 0.2 0.4 0.6 0.8 1.0 1.2.4 V (V) CM Figure 71. IMD vs. Output Common-Mode Voltage (f = 161 MHz, OUT R = 50 Ω Differential, I = 10 mA, 20 mA, and 30 mA) LOAD FS V OUT AUXILIARY DAC OPERATION –V PEAK The AD9122 has two auxiliary DACs: one associated with the Figure 69. Output Voltage Waveforms I path and one associated with the Q path. These auxiliary DACs The common-mode signal voltage, VCM, is calculated as can be used to compensate for dc offsets in the transmitted signal. Each auxiliary DAC has a single-ended current that can sink or I FS V = × R CM O source current into either the positive (P) or negative (N) output 2 of the associated transmit DAC. The auxiliary DAC structure is The peak output voltage, VPEAK, is calculated as shown in Figure 72. V = I × R PEAK FS O V B With this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage. I AUX DAC[9:0] Transmit DAC Linear Output Signal Swing I AUX DAC To achieve optimum performance, the DAC outputs have a CURRENT DIRECTION linear output compliance voltage range that must be adhered to. The linear output signal swing is dependent on the full-scale output current, I , and the common-mode level of the output. FS I AUX DAC SIGN Figure 70 and Figure 71 show the IMD performance vs. the output common-mode voltage at different full-scale currents IOUT1P and output frequencies. I DAC IOUT1N Figure 72. Auxiliary DAC Structure Rev. B | Page 47 of 60 08281-038 08281-039 IMD (dBc) IMD (dBc) 08281-040 08281-169 08281-168 AD9122 The control registers for the I and Q auxiliary DACs are Figure 75 shows a fifth-order, low-pass filter. A common-mode Register 0x42, Register 0x43, Register 0x46, and Register 0x47. choke is used between the I-V resistors and the remainder of the filter. This removes the common-mode signal produced by INTERFACING TO MODULATORS the DAC and prevents the common-mode signal from being The AD9122 interfaces to the ADL537x family of modulators converted to a differential signal, which can appear as unwanted with a minimal number of components. An example of the spurious signals in the output spectrum. Splitting the first filter recommended interface circuitry is shown in Figure 73. capacitor into two and grounding the center point creates a common-mode low-pass filter, providing additional common- AD9122 ADL537x mode rejection of high frequency signals. A purely differential 67 IOUT1P IBBP filter can pass common-mode signals. RBIP 50Ω RLI 100Ω DRIVING THE ADL5375-15 RBIN 50Ω 66 IOUT1N IBBN The ADL5375-15 requires a 1500 mV dc bias and, therefore, requires a slightly more complex interface than most other 59 IOUT2N QBBN Analog Devices modulators. It is necessary to level-shift the RBQN DAC output from a 500 mV dc bias to the 1500 mV dc bias 50Ω RLQ RBQP 100Ω required by the ADL5375-15. Level-shifting can be achieved 50Ω 58 IOUT2P QBBP with a purely passive network, as shown in Figure 74. In this network, the dc bias of the DAC remains at 500 mV, whereas Figure 73. Typical Interface Circuitry Between the AD9122 and the ADL537x the input to the ADL5375-15 is 1500 mV. This passive, level- Family of Modulators shifting network introduces approximately 2 dB of loss in the The baseband inputs of the ADL537x family require a dc bias ac signal. of 500 mV. The nominal midscale output current on each output AD9122 ADL5375-15 RSIP of the DAC is 10 mA (one-half the full-scale current). Therefore, 1kΩ 67 21 IOUT1P IBBP a single 50 Ω resistor to ground from each of the DAC outputs RBIP RLIP 45.3Ω 3480Ω results in the desired 500 mV dc common-mode bias for the 5V RBIN RLIN RSIN inputs to the ADL537x. The signal level can be reduced through 45.3Ω 3480Ω 66 22 1kΩ IBBN IOUT1N the addition of the load resistor in parallel with the modulator RSQN inputs. The peak-to-peak voltage swing of the transmitted signal is 1kΩ 59 9 IOUT2N QBBN (2×R ×R ) RBQN RLQN B L V =I × 45.3Ω 3480Ω SIGNAL FS 5V (2×R +R ) B L RBQP RLQP RSQP 45.3Ω 3480Ω 58 1kΩ 10 QBBP IOUT2P BASEBAND FILTER IMPLEMENTATION Most applications require a baseband anti-imaging filter between Figure 74. Passive, Level-Shifting Network for Biasing the ADL5375-15 the DAC and the modulator to filter out Nyquist images and broadband DAC noise. The filter can be inserted between the I-V resistors at the DAC output and the signal level setting resistor across the modulator input. This establishes the input and output impedances for the filter. 22pF 50Ω 3pF 33nH 56nH 2pF 6pF 140Ω ADL537x AD9122 33nH 56nH 50Ω 22pF 3pF Figure 75. DAC Modulator Interface with Fifth-Order, Low-Pass Filter Rev. B | Page 48 of 60 08281-041 08281-042 08281-043 AD9122 The advantage of using the auxiliary DACs is that none of REDUCING LO LEAKAGE AND UNWANTED the main DAC dynamic range is used to perform the dc offset SIDEBANDS adjustment. The disadvantage is that the common-mode level Analog quadrature modulators can introduce unwanted signals at of the output signal changes as a function of the auxiliary DAC the LO frequency due to dc offset voltages in the I and Q baseband current. The opposite is true when the digital offset adjustment inputs, as well as feedthrough paths from the LO input to the out- is used. put. The LO feedthrough can be nulled by applying the correct Good sideband suppression requires both gain and phase dc offset voltages at the DAC output. This can be done using the matching of the I and Q signals. The I/Q phase adjust registers auxiliary DACs (Register 0x42, Register 0x43, Register 0x46, and (Register 0x38 through Register 0x3B) and the DAC FS adjust Register 0x47) or by using the digital dc offset adjustments registers (Register 0x40 and Register 0x44) can be used to calibrate (Register 0x3C through Register 0x3F). the I and Q transmit paths to optimize sideband suppression. Rev. B | Page 49 of 60 AD9122 DEVICE POWER MANAGEMENT 1700 POWER DISSIPATION 1× INTERPOLATION 2× INTERPOLATION 1500 The AD9122 has four supply rails: AVDD33, IOVDD, DVDD18, 4× INTERPOLATION 8× INTERPOLATION and CVDD18. 1300 The AVDD33 supply powers the DAC core circuitry. The power 1100 dissipation of the AVDD33 supply rail is independent of the digital 900 operating mode and sample rate. The current drawn from the AVDD33 supply rail is typically 55 mA (182 mW) when the full- 700 scale current of the I and Q DACs is set to the nominal value of 500 20 mA. Changing the full-scale current directly affects the supply current drawn from the AVDD33 rail. For example, if the full-scale 300 current of the I DAC and the Q DAC is changed to 10 mA, the 100 AVDD33 supply current drops by 20 mA to 35 mA. 0 50 100 150 200 250 300 The IOVDD voltage supplies the serial port I/O pins, the RESET f (MHz) DATA pin, and the IRQ pin. The voltage applied to the IOVDD pin can Figure 76. Total Power Dissipation vs. fDATA Without PLL, Fine NCO, or Inverse Sinc range from 1.8 V to 3.3 V. The current drawn by the IOVDD supply pin is typically 3 mA. 1200 The DVDD18 supply powers all of the digital signal processing 1× INTERPOLATION 2× INTERPOLATION blocks of the device. The power consumption from this supply 4× INTERPOLATION 1000 8× INTERPOLATION is a function of which digital blocks are enabled and the frequency at which the device is operating. 800 The CVDD18 supply powers the clock receiver and clock distri- bution circuitry. The power consumption from this supply varies 600 directly with the operating frequency of the device. CVDD18 also powers the PLL. The power dissipation of the PLL is typically 400 80 mW when enabled. 200 Figure 76 through Figure 80 show the power dissipation of the AD9122 under a variety of operating conditions. All of 0 the graphs were taken with data being supplied to both the I 0 50 100 150 200 250 300 and Q DACs. The power consumption of the device does not f (MHz) DATA vary significantly with changes in the coarse modulation mode Figure 77. DVDD18 Power Dissipation vs. fDATA Without Fine NCO selected or the analog output frequency. Figure 76 through or Inverse Sinc Figure 80 show the total power dissipation, as well as the power dissipation of the DVDD18 and CVDD18 supplies. 250 1× INTERPOLATION 2× INTERPOLATION Maximum power dissipation can be estimated to be 20% higher 4× INTERPOLATION 8× INTERPOLATION than the typical power dissipation. 200 150 100 50 0 0 50 100 150 200 250 300 f (MHz) DATA Figure 78. CVDD18 Power Dissipation vs. fDATA with PLL Disabled Rev. B | Page 50 of 60 POWER (mW) POWER (mW) POWER (mW) 08281-046 08281-045 08281-044 AD9122 300 TEMPERATURE SENSOR The AD9122 has a band gap temperature sensor for monitoring 250 the temperature change of the AD9122. The temperature must be calibrated against a known temperature to remove the part- 200 to-part variation on the band gap circuit used to sense the temperature. The DACCLK must be running at a minimum 150 of 100 MHz to obtain a reliable temperature measurement. 100 To monitor temperature change, the user must take a reading at a known ambient temperature for a single-point calibration 50 of each AD9122 device. Tx = TREF + 7.7 × (Code_x − Code_ref)/1000 + 1 0 0 200 400 600 800 1000 1200 where: f (MHz) DAC Code_x is the readback code at the unknown temperature, Tx. Figure 79. DVDD18 Power Dissipation vs. f Due to Inverse Sinc Filter DAC Code_ref is the readback code at the calibrated temperature, T . REF To use the temperature sensor, it must be enabled by setting 300 Register 0x01, Bit 4, to 0. In addition, to obtain accurate read- 1× INTERPOLATION ings, the die temperature range control register (Register 0x48) 2×, 4×, 8× INTERPOLATION 250 should be set to 0x02. 200 150 100 50 0 50 100 150 200 250 300 f (MHz) DATA Figure 80. DVDD18 Power Dissipation vs. f Due to Fine NCO DATA Rev. B | Page 51 of 60 POWER (mW) POWER (mW) 08281-048 08281-047 AD9122 MULTICHIP SYNCHRONIZATION System demands may require that the outputs of multiple DACs SYNCHRONIZATION WITH CLOCK MULTIPLICATION be synchronized with each other or with a system clock. Systems When using the clock multiplier to generate the DAC sample rate that support transmit diversity or beamforming, where multiple clock, the REFCLK input signal acts as both the reference clock antennas are used to transmit a correlated signal, require multiple for the PLL-based clock multiplier and the synchronization signal. DAC outputs to be phase aligned with each other. Systems with To synchronize devices, distribute the REFCLK signal with low a time division multiplexing transmit chain may require one or skew to all the devices that need to be synchronized. Skew between more DACs to be synchronized with a system-level reference clock. the REFCLK signals of the different devices shows up directly as Multiple devices are considered synchronized to each other when a timing mismatch at the DAC outputs. the state of the clock generation state machines is identical for all Because two clocks are shared on the same signal, an appro- parts and when time-aligned data is being read from the FIFOs priate frequency must be chosen for the synchronization and of all parts simultaneously. Devices are considered synchronized REFCLK signals. The FRAME and DCI signals can be created to a system clock when there is a fixed and known relationship in the FPGA along with the data. A circuit diagram of a typical between the clock generation state machine and the data being configuration is shown in Figure 81. read from the FIFO and a particular clock edge of the system MATCHED LENGTH TRACES clock. The AD9122 has provisions for enabling multiple devices REFCLKP/ to be synchronized to each other or to a system clock. REFCLKN FRAMEP/ IOUT1P/ The AD9122 supports synchronization in two different modes: FRAMEN IOUT1N DCIP/ data rate mode and FIFO rate mode. In data rate mode, the input DCIN SYSTEM data rate represents the lowest synchronized clock rate. In FIFO CLOCK LOW SKEW CLOCK DRIVER rate mode, the FIFO rate, which is the data rate divided by the REFCLKP/ REFCLKN FIFO depth of 8, represents the lowest rate clock. IOUT2P/ FRAMEP/ FPGA IOUT2N The advantage of FIFO rate synchronization is increased time FRAMEN DCIP/ between the setup and hold time windows for DCI changes DCIN relative to the DACCLK or REFCLK input. When the synchro- Figure 81. Typical Circuit Diagram for Synchronizing Devices nization state machine is on in data rate mode, the elasticity of The Procedure for Synchronization When Using the PLL section the FIFO is not used to absorb timing variations between the data outlines the steps required to synchronize multiple devices. The source and the DAC, resulting in setup and hold time windows procedure assumes that the REFCLK signal is applied to all the repeating at the input data rate. devices and that the PLL of each device is phase locked to it. The The method chosen for providing the DAC sampling clock following procedure must be carried out on each individual device. directly affects the synchronization methods available. When Procedure for Synchronization When Using the PLL the device clock multiplier is used, only data rate mode is available. When the DAC sampling clock is sourced directly, In the initialization of the AD9122, all the clock signals (DACCLK, both data rate mode and FIFO rate mode synchronization are DCI, FRAME, synchronization, and REFCLK) must be present and available. The following sections describe the synchronization stable before the synchronization feature is turned on. Configure methods for enabling both clocking modes and querying the the AD9122 for data rate, periodic synchronization by writing status of the synchronization logic. 0xC8 to the sync control register (Register 0x10). Additional synchronization options are available (see the Additional The full synchronization methods described are used to align Synchronization Features section). multiple dual DACs within one DACCLK cycle. To achieve syn- chronization within one DACCLK cycle, both the REFCLK and Read the sync status register (Register 0x12) to verify that FRAME signals are required to perform back-end and front-end the sync locked bit (Bit 6) is set high, indicating that the device alignment. If synchronization does not need to be this accurate, achieved back-end synchronization, and that the sync lost bit other options can be used. In data rate mode or in FIFO rate mode, (Bit 7) is low. These levels indicate that the clocks are running using soft alignment of the FIFO for multiple DACs synchronizes with a constant and known phase relative to the synchroniza- the DAC outputs within two data clock cycles (see the Serial Port tion signal. Initiated FIFO Reset section). For more information about Reset the FIFO by strobing the FRAME signal high for the time synchronization, see the AN-1093 Application Note, “Synchro- interval required to write two complete input data words. Resetting nization of Multiple AD9122 TxDAC+ Converters.” the FIFO ensures that the correct data is being read from the FIFO. This completes the synchronization procedure; all devices should now be synchronized. Rev. B | Page 52 of 60 08281-049 AD9122 t SKEW REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) t t SDCI HDCI DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) Figure 82. Timing Diagram Required for Synchronizing Devices DACCLKP/ DACCLKN REFCLKP/ IOUT1P/ REFCLKN IOUT1N FRAMEP/ FRAMEN DCIP/ SAMPLE DCIN RATE CLOCK LOW SKEW MATCHED CLOCK DRIVER LENGTH TRACES DACCLKP/ DACCLKN REFCLKP/ REFCLKN IOUT2P/ SYNC IOUT2N FRAMEP/ CLOCK FRAMEN LOW SKEW CLOCK DRIVER DCIP/ DCIN FPGA Figure 83. Typical Circuit Diagram for Synchronizing Devices to a System Clock To maintain synchronization, the skew between the REFCLK master clock, use the master clock directly for generating the signals of the devices must be less than tSKEW ns. When resetting REFCLK input (see Figure 83). the FIFO, the FRAME signal must be held high for the time DATA RATE MODE SYNCHRONIZATION interval required to write two complete input data words. A The Procedure for Data Rate Synchronization When Directly timing diagram of the input signals is shown in Figure 82. Sourcing the DAC Sampling Clock section outlines the steps Figure 82 shows a REFCLK frequency equal to the data rate. required to synchronize multiple devices in data rate mode. The Although this is the most common situation, it is not strictly procedure assumes that the DACCLK and REFCLK signals are required for proper synchronization. Any REFCLK frequency applied to all the devices. The following procedure must be that satisfies the following equation is acceptable. (This carried out on each individual device. equation is valid only when the PLL is used because only data Procedure for Data Rate Synchronization When Directly rate mode is available with the PLL on.) Sourcing the DAC Sampling Clock N f = f /2 and f ≤ f SYNC_I DACCLK SYNC_I DATA Configure the AD9122 for data rate, periodic synchronization where N = 0, 1, 2, or 3. by writing 0xC8 to the sync control register (Register 0x10). Additional synchronization options are available (see the As an example, a configuration with 4× interpolation and clock Additional Synchronization Features section). frequencies of f = 1600 MHz, f = 800 MHz, f = VCO DACCLK DATA 200 MHz, and fSYNC_I = 100 MHz is a viable solution. Read the sync locked bit (Register 0x12, Bit 6) to verify that the device is back-end synchronized. A high level on this bit indicates SYNCHRONIZATION WITH DIRECT CLOCKING that the clocks are running with a constant and known phase When directly sourcing the DAC sample rate clock, a separate relative to the synchronization signal. REFCLK input signal is required for synchronization. To syn- Reset the FIFO by strobing the FRAME signal high for one chronize devices, the DACCLK signal and the REFCLK signal complete DCI period. Resetting the FIFO ensures that the must be distributed with low skew to all the devices being correct data is being read from the FIFO of each of the devices synchronized. If the devices need to be synchronized to a simultaneously. Rev. B | Page 53 of 60 08281-051 08281-050 AD9122 t DATA This completes the synchronization procedure; all devices should now be synchronized. DACCLK/ To ensure that each DAC is updated with the correct data on REFCLK the same CLK edge, two timing relationships must be met on SAMPLING each DAC. INTERVAL • DCIP/DCIN and D[15:0]P/D[15:0]N must meet the setup and hold times with respect to the rising edge of DACCLK. DCI • Synchronization (REFCLK) must also meet the setup and hold times with respect to the rising edge of DACCLK. t SDCI When these conditions are met, the outputs of the DACs are t HDCI updated within one DAC clock cycle of each other. The timing requirements of the input signals are shown in Figure 84. Figure 85. Timing Diagram for Input Data Port (Data Rate Mode) t SKEW FIFO RATE MODE SYNCHRONIZATION DACCLKP(1)/ The Procedure for FIFO Rate Synchronization When Directly DACCLKN(1) Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in FIFO rate mode. DACCLKP(2)/ DACCLKN(2) The procedure assumes that the DACCLK and REFCLK signals t t SUSYNC HSYNC are applied to all the devices. The procedure must be carried out REFCLKP(2)/ REFCLKN(2) on each individual device. t t SDCI HDCI Procedure for FIFO Rate Synchronization When Directly DCIP(2)/ DCIN(2) Sourcing the DAC Sampling Clock FRAMEP(2)/ Configure the AD9122 for FIFO rate, periodic synchronization FRAMEN(2) by writing 0x88 to the sync control register (Register 0x10). Addi- Figure 84. Data Rate Synchronization Signal Timing Requirements, tional synchronization options are available (see the Additional 2× Interpolation Synchronization Features section). Figure 84 shows the synchronization signal timing with 2× Read the sync locked bit (Register 0x12, Bit 6) to verify that the interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is device is back-end synchronized. A high level on this bit indicates shown to be equal to the data rate. The maximum frequency at that the clocks are running with a constant and known phase which the device can be resynchronized in data rate mode can relative to the synchronization signal. be expressed as Reset the FIFO by strobing the FRAME signal high for one com- N f = f /2 SYNC_I DATA plete DCI period. Resetting the FIFO ensures that the correct data where N is any non-negative integer. is being read from the FIFO of each of the devices simultaneously. Generally, for values of N greater than or equal to 3, select the This completes the synchronization procedure; all devices should FIFO rate synchronization mode. now be synchronized. When synchronization is used in data rate mode, the timing When these conditions are met, the outputs of the DACs are constraint between the DCI and DACCLK must be met according updated within one DAC clock cycle of each other. The timing to Table 25. In data rate mode, the allowed phase drift between requirements of the input signals are shown in Figure 86. the DCI and DACCLK is limited to one DCI cycle. The DCI to t SKEW DACCLK timing restriction is required to prevent corruption of the data transfer when the FIFO is constantly reset. The required DACCLKP(1)/ DACCLKN(1) timing between the DCI and DACCLK is shown in Figure 85. DACCLKP(2)/ Table 25. DCI to DACCLK Setup and Hold Times DACCLKN(2) t t DCI Delay SUSYNC HSYNC REFCLKP(2)/ Register 0x16, Minimum Setup Minimum Hold Sampling REFCLKN(2) Bits[1:0] Time, tSDCI (ns) Time, tHDCI (ns) Interval (ns) 00 −0.07 0.82 0.75 DCIP(2)/ DCIN(2) 01 −0.24 1.13 0.89 10 −0.39 1.40 1.01 FRAMEP(2)/ FRAMEN(2) 11 −0.49 1.55 1.06 Figure 86. FIFO Rate Synchronization Signal Timing Requirements, 2× Interpolation Rev. B | Page 54 of 60 08281-052 08281-147 08281-053 AD9122 Figure 86 shows the synchronization signal timing with 2× The sync phase readback bits (Register 0x13, Bits[7:0]) report interpolation; therefore, f = ½ × f . The REFCLK input is the current clock phase in a 6.2 format. Bits[7:2] report which of DCI CLK shown to be equal to the FIFO rate. The maximum frequency the 64 states (0 to 63) the clock is currently in. When averaging at which the device can be resynchronized in FIFO rate mode is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾). can be expressed as The lower two bits give an indication of the timing margin N issues that may exist. If the synchronization sampling is error fSYNC_I = fDATA/(8 × 2 ) free, the fractional clock state should be 00. where N is any non-negative integer. Timing Optimization ADDITIONAL SYNCHRONIZATION FEATURES The synchronization signal (REFCLK) is sampled by a version Table 26 shows the required timing between the DACCLK and the of the DACCLK. If sampling errors are detected, the opposite synchronization clock when synchronization is used. This timing sampling edge can be selected to improve the sampling point. restriction applies to both data rate mode and FIFO rate mode. The sampling edge can be selected by setting Register 0x10, Bit 3 (1 = rising and 0 = falling). Table 26. Synchronization Setup and Hold Times The synchronization logic resynchronizes when a phase change Parameter Min Max Unit between the synchronization signal (REFCLK) and the state of the tSKEW −tDACCLK/2 +tDACCLK/2 ps clock generation state machine exceeds a threshold. To mitigate tSUSYNC 100 ps the effects of jitter and prevent erroneous resynchronizations, the t 330 ps HSYNC relative phase can be averaged. The amount of averaging is set One-Time Synchronization by the sync averaging bits (Register 0x10, Bits[2:0]) and can be When implementing the full multichip synchronization feature set from 1 to 128. The higher the number of averages, the more (with the REFCLK and FRAME signals aligned within one DACCLK slowly the device recognizes and resynchronizes to a legitimate cycle), the user may experience difficulty meeting the DACCLK to phase correction. Generally, the averaging should be made as synchronization clock timing. In this case, a one-time synchroni- large as possible while still meeting the allotted resynchroniza- tion time interval. Note that, if the average synchronization zation method can be used. Before implementing the one-time synchronization, make sure that the synchronization signal is sampling result is in approximately the middle of the probability locked by checking both the sync signal locked and the sync signal curve, the synchronization engine can be unstable, resulting in lost flags (Bit 4 and Bit 5 in Register 0x06). It is also important corrupted output. that synchronization not be enabled before stable REFCLK signals The value of the Sync Phase Request[5:0] bits (Register 0x11, are present from the FPGA or ASIC. For more information and Bits[5:0]) is the state to which the clock generation state machine a detailed flowchart of the one-time synchronization feature, see resets upon initialization. By varying this value, the timing of the AN-1093 Application Note, “Synchronization of Multiple the internal clocks, with respect to the synchronization signal AD9122 TxDAC+ Converters.” (REFCLK), can be adjusted. Every increment of the Sync Phase Sync Status Bits Request[5:0] value advances the internal clocks by one DACCLK cycle. This offset can be used for two purposes: to skew the out- When the sync locked bit (Register 0x12, Bit 6) is set, it indicates puts of two synchronized DAC outputs in increments of the that the synchronization logic has reached alignment. This align- DACCLK cycle, and to change the relative timing between the ment is determined when the clock generation state machine DAC output and the SYNC input (REFCLK). This may allow phase is constant. for a more optimal placement of the DCI sampling point in data Alignment takes from (11 + averaging) × 64 to (11 + averaging) × rate synchronization mode. 128 DACCLK cycles. The sync locked bit can also trigger an IRQ, as described in the Interrupt Request Operation section. When the sync lost bit (Register 0x12, Bit 7) is set, it indicates that a previously synchronized device has lost alignment. This bit is latched and remains set until cleared by overwriting the IRQ register. This bit can also trigger an , as described in the Interrupt Request Operation section. Rev. B | Page 55 of 60 AD9122 INTERRUPT REQUEST OPERATION The AD9122 provides an interrupt request output signal on When an interrupt enable bit is set low, the event flag bit reflects Pin 7 (IRQ) that can be used to notify an external host processor the current status of the EVENT_FLAG_SOURCE signal, and the event flag has no effect on the external IRQ pin. of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that The latched version of an event flag (the INTERRUPT_SOURCE IRQ occurred. The pin is an open-drain, active low output. Pull signal) can be cleared in two ways. The recommended way is by IRQ the pin high external to the device. This pin can be tied to writing 1 to the corresponding event flag bit. A hardware or soft- the interrupt pins of other devices with open-drain outputs to ware reset also clears the INTERRUPT_SOURCE signal. wire-OR these pins together. INTERRUPT SERVICE ROUTINE The event flags provide visibility into the device. These flags Interrupt request management starts by selecting the set of are located in the two event flag registers, Register 0x06 and event flags that require host intervention or monitoring. The Register 0x07. The behavior of each event flag is independently events that require host action should be enabled so that the selected in the interrupt enable registers, Register 0x04 and host is notified when they occur. For events requiring host Register 0x05. When the flag interrupt enable is active, the event intervention upon IRQ activation, run the following routine flag latches and triggers an external interrupt. When the flag to clear an interrupt request: interrupt is disabled, the event flag monitors the source signal, 1. Read the status of the event flag bits that are being but the IRQ pin remains inactive. monitored. Figure 87 shows the IRQ-related circuitry and how the event flag 2. Set the interrupt enable bit low so that the unlatched signals propagate to the IRQ output. The INTERRUPT_ENABLE EVENT_FLAG_SOURCE signal can be monitored directly. signal represents one bit from the interrupt enable register. The 3. Perform any actions that may be required to clear the EVENT_FLAG_SOURCE signal represents one bit from the event EVENT_FLAG_SOURCE. In many cases, no specific flag register. The EVENT_FLAG_SOURCE signal represents actions may be required. one of the device signals that can be monitored, such as the 4. Read the event flag to verify that the actions taken have PLL_LOCKED signal from the PLL phase detector or the cleared the EVENT_FLAG_SOURCE. FIFO_WARNING_1 signal from the FIFO controller. 5. Clear the interrupt by writing 1 to the event flag bit. When an interrupt enable bit is set high, the corresponding 6. Set the interrupt enable bits of the events to be monitored. event flag bit reflects a positively tripped version of the Note that some EVENT_FLAG_SOURCE signals are latched EVENT_FLAG_SOURCE signal; that is, the event flag bit is signals. These signals are cleared by writing to the correspond- latched on the rising edge of the EVENT_FLAG_SOURCE ing event flag bit. For more information about each event flag, IRQ signal. This signal also asserts the external pin. see Register 0x06 and Register 0x07 in Table 11. 0 EVENT_FLAG 1 IRQ INTERRUPT_ SOURCE INTERRUPT_ENABLE OTHER INTERRUPT EVENT_FLAG_SOURCE SOURCES WRITE_1_TO_EVENT_FLAG DEVICE_RESET Figure 87. Simplified Schematic of IRQ Circuitry Rev. B | Page 56 of 60 08281-054 AD9122 INTERFACE TIMING VALIDATION The AD9122 provides on-chip sample error detection (SED) The SED has three flag bits (Register 0x67, Bit 5, Bit 1, and Bit 0) circuitry that simplifies verification of the input data interface. that indicate the results of the input sample comparisons. The The SED circuitry compares the input data samples captured sample error detected bit (Register 0x67, Bit 5) is set when an at the digital input pins with a set of comparison values. The error is detected and remains set until cleared. The SED also comparison values are loaded into registers through the SPI provides registers that indicate which input data bits experienced port. Differences between the captured values and the compar- errors (Register 0x70 through Register 0x73). These bits are ison values are detected and stored. Options are available for latched and indicate the accumulated errors detected until cleared. customizing SED test sequencing and error handling. Autosample error detection (AED) is an autoclear function in the SED. The autoclear mode has two effects: it activates the SED OPERATION compare fail bit and the compare pass bit (Register 0x67, Bit 1 The SED circuitry operates on a data set made up of four 16-bit and Bit 0) and changes the behavior of Register 0x70 through input words, denoted as I0, Q0, I1, and Q1. To properly align Register 0x73. The compare pass bit is set if the last comparison the input samples, the first I data-word (that is, I0) is indicated indicated that the sample was error free. The compare fail bit is by asserting FRAME for at least one complete input sample. set if an error is detected. The compare fail bit is automatically Figure 88 shows the input timing of the interface in word mode. cleared by the reception of eight consecutive error-free compar- The FRAME signal can be issued once at the start of the data isons. When autoclear mode is enabled, Register 0x70 through transmission, or it can be asserted repeatedly at intervals coinciding Register 0x73 accumulate errors as previously described but are with the I0 and Q0 data-words. reset to all 0s after eight consecutive error-free sample comparisons are made. FRAME If desired, the sample error detected, compare pass, and com- DATA[15:0] I0 Q0 I1 Q1 I0 Q0 IRQ pare fail flags can be configured to trigger the pin when active. This is done by enabling the appropriate bits in the event Figure 88. Timing Diagram of Extended FRAME Signal Required to Align Input Data for SED flag register (Register 0x07). Table 27 shows a progression of the input sample comparison results and the corresponding states of the error flags. Table 27. Progression of Input Sample Comparison Results and the Resulting SED Register Values Compare Results (Pass/Fail) P F F F P P P P P P P P P F P F Register 0x67, Bit 5 (Sample Error Detected) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Register 0x67, Bit 1 (Compare Fail) 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 Register 0x67, Bit 0 (Compare Pass) 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 2 Z N N N N N N N N N N N Z N N N Register 0x70 to Register 0x73 (Errors Detected x_BITS[15:0]) 1 Z = all 0s. 2 N = nonzero. Rev. B | Page 57 of 60 08281-056 AD9122 4. Write to Register 0x67 to enable the SED. SED EXAMPLE (Set Register 0x67 to 0x80.) Normal Operation 5. Clear the SED errors in Register 0x67 and Register 0x07. The following example illustrates the SED configuration for When the SED is first turned on, the FRAME signal may continuously monitoring the input data and assertion of the be detected immediately; therefore, the SED failure bit may IRQ pin when a single error is detected. be asserted due to the unknown initial FRAME status. For 1. Load the following comparison values. (Comparison values this reason, the SED compare fail status bit must be cleared can be chosen arbitrarily; however, choosing values that at least once immediately after enabling the SED. require frequent bit toggling provides the most robust test.) IRQ If is asserted, read Register 0x67 and Register 0x70 through Register 0x68: I0[7:0] Register 0x73 to verify that a SED error was detected and to deter- Register 0x69: I0[15:8] mine which input bits were in error. The bits in Register 0x70 Register 0x6A: Q0[7:0] through Register 0x73 are latched; therefore, the bits indicate Register 0x6B: Q0[15:8] any errors that occurred on those bits throughout the test (not Register 0x6C: I1[7:0] only the errors that caused the error detected flag to be set). Register 0x6D: I1[15:8] Note that the FRAME signal is not required during normal Register 0x6E: Q1[7:0] operation when the device is configured for word mode. Register 0x6F: Q1[15:8] Enabling the alignment of the I0 sample as described in the IRQ 2. Enable the SED error detect flag to assert the pin. SED Operation section requires the use of the FRAME signal. (Set Register 0x05 to 0x04.) The timing diagrams for byte and nibble modes are the same 3. Begin transmitting the input data pattern. as during normal operation and are shown in Figure 44 and Figure 45, respectively. Rev. B | Page 58 of 60 AD9122 EXAMPLE START-UP ROUTINE Device Configuration Register Write Sequence: To ensure reliable start-up of the AD9122, certain sequences should be followed. This section shows an example start-up 0x00 Æ 0x20 /* Issue Software Reset */ routine. This example uses the configuration described in the 0x00 Æ 0x00 Device Configuration section. DEVICE CONFIGURATION /* Start PLL */ 0x0D Æ 0xD9 The following device configuration is used for this example: 0x0A Æ 0xC0 • fDATA = 122.88 MSPS 0x0A Æ 0x80 • Interpolation is 4×, using HB1 = 10 and HB2 = 010010 • Input data is baseband data /* Verify PLL is Locked */ • fOUT = 140 MHz Read 0x0E /* Expect bit 7 = 1 */ • fREFCLK = 122.88 MHz • PLL is enabled • Fine NCO is enabled /* Configure Interpolation Filters */ • Inverse sinc filter is enabled 0x1B Æ 0x84 • Synchronization is enabled 0x1C Æ 0x04 • Silicon revision is R2 0x1D Æ 0x24 DERIVED PLL SETTINGS /* Configure NCO */ The following PLL settings can be derived from the device configuration: 0x1E Æ 0x01 0x30 Æ 0x55 • f = f × interpolation = 491.52 MHz DACCLK DATA 0x31 Æ 0x55 • f = 4 × f = 1966.08 MHz (1 GHz < f < 2 GHz) VCO DACCLK VCO 0x32 Æ 0xD5 • N1 = f /f = 4 DACCLK REFCLK • N2 = f /f = 4 0x33 Æ 0x11 VCO DACCLK DERIVED NCO SETTINGS /* Update Frequency Tuning Word */ The following NCO settings can be derived from the device 0x36 Æ 0x01 configuration: 0x36 Æ 0x00 • f = 2 × f NCO DATA • fCARRIER = fOUT − fMODHB1 = 140 − 122.88 = 17.12 MHz /* Choose Data Rate Mode */ 32 • FTW = 17.12/(2 × 122.8) × 2 = 0x11D55555 0x10 Æ 0x48 START-UP SEQUENCE The following sequence configures the power clock and register /* Issue Software FIFO Reset */ write sequencing for reliable device start-up in PLL ON mode: 0x17 Æ 0x04 Power up Device (no specific power supply 0x18 Æ 0x02 sequence is required) Apply stable REFCLK input signal. /* Verify FIFO Reset */ Apply stable DCI input signal. Read 0x18 /* Expect 0x07 */ Issue H/W RESET (Optional). 0x18 Æ 0x00 Read 0x19 /* Expect 0x1F or 0x0F or 0x07 */ Rev. B | Page 59 of 60 AD9122 OUTLINE DIMENSIONS 0.60 10.00 0.42 0.60 BSC SQ 0.24 0.42 0.24 PIN 1 55 72 INDICATOR 54 1 PIN 1 INDICATOR 0.50 9.75 BSC 6.15 BSC SQ TOP VIEW EXPOSED PAD 6.00 SQ (BOTTOM VIEW) 5.85 0.50 37 18 0.40 36 19 0.30 12° MAX 0.80 MAX 8.50 REF 1.00 0.65 TYP 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY 0.30 SEATING FUNCTION DESCRIPTIONS 0.08 PLANE 0.20 REF SECTION OF THIS DATA SHEET. 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 Figure 89. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-7) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9122BCPZ −40°C to +85°C 72-lead LFCSP_VQ CP-72-7 AD9122BCPZRL −40°C to +85°C 72-lead LFCSP_VQ CP-72-7 AD9122-M5372-EBZ Evaluation Board Connected to ADL5372 Modulator AD9122-M5375-EBZ Evaluation Board Connected to ADL5375 Modulator 1 Z = RoHS Compliant Part. ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08281-0-5/11(B) Rev. B | Page 60 of 60 052809-A