ANALOG DEVICES AD9059

Dual 8-Bit, 60 MSPS A/D Converter AD9059 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual 8-Bit ADCs on a Single Chip V PWRDN V D DD Low Power: 400 mW Typical On-Chip 2.5 V Reference and Track-and-Hold AD9059 1 V p-p Analog Input Range 8 Single 5 V Supply Operation AINA T/H ADC D7A–D0A A 5 V or 3 V Logic Interface VREF 120 MHz Analog Bandwidth ENCODE Power-Down Mode: <12 mW 2.5V APPLICATIONS 8 AINB T/H ADC Digital Communications (QAM Demodulators) B D7B–D0B RGB and YC/Composite Video Processing Digital Data Storage Read Channels GND Medical Imaging Digital Instrumentation PIN CONFIGURATION PRODUCT DESCRIPTION AINA 1 28 AINB The AD9059 is a dual 8-bit monolithic analog-to-digital converter VREF 2 27 GND optimized for low cost, low power, small size, and ease of use. PWRDN 3 26 ENCODE With a 60 MSPS encode rate capability and full-power analog V 4 25 V D D bandwidth of 120 MHz typical, the component is ideal for GND 5 24 GND AD9059 applications requiring multiple ADCs with excellent dynamic V 6 23 V DD DD TOP VIEW performance. (Not to Scale) D7A (MSB) 7 22 D7B (MSB) D6A 8 21 To minimize system cost and power dissipation, the AD9059 D6B D5A 9 D5B includes an internal 2.5 V reference and dual track-and-hold 20 D4A 10 19 D4B circuits. The ADC requires only a 5 V power supply and an D3A 11 18 D3B encode clock. No external reference or driver components are D2A 12 17 D2B required for many applications. D1A 13 16 D1B The AD9059’s single encode input is TTL/CMOS compatible D0A (LSB) 14 15 D0B (LSB) and simultaneously controls both internal ADC channels. The parallel 8-bit digital outputs can be operated from 5 V or 3 V supplies. A power-down function may be exercised to bring total consumption to <12 mW when ADC data is not required for lengthy periods of time. In power-down mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced BiCMOS process, the AD9059 is available in a space-saving 28-lead shrink small outline package (28-lead SSOP) and is specified over the industrial temperature range (–40°C to +85°C). Customers desiring single-channel digitization may consider the AD9057, a single 8-bit, 60 MSPS monolithic based on the AD9059 ADC core. The AD9057 is available in a 20-lead shrink small outline package (20-lead SSOP) and is specified over the industrial temperature range. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. AD9059–SPECIFICATIONS (V = 5 V, V = 3 V, external reference, ENCODE = 60 MSPS, unless otherwise noted.) D DD ELECTRICAL CHARACTERISTICS AD9059BRS Parameter Temp Test Level Min Typ Max Unit RESOLUTION 8 Bits DC ACCURACY Differential Nonlinearity 25°CI 0.75 2.0 LSB Full VI 2.5 LSB Integral Nonlinearity 25°CI 0.75 2.0 LSB Full VI 2.5 LSB No Missing Codes Full VI Guaranteed 1 Gain Error 25°CI –6 –2.5 +6 % FS Full VI –8 +8 % FS 1 Gain Temperature Coefficient Full V ±70 ppm/°C ANALOG INPUT Input Voltage Range (Centered at 2.5 V) 25°CV 1.0 V p-p Input Offset Voltage 25°CI –15 0 +15 mV Full VI –25 +25 mV Input Resistance 25°CV 150 kΩ Input Capacitance 25°CV 2 pF Input Bias Current 25°CI 6 16 µA Analog Bandwidth 25°CV 120 MHz CHANNEL MATCHING (A to B) Gain Delta 25°CV ±1% FS Input Offset Voltage Delta 25°CV ±4mV BAND GAP REFERENCE Output Voltage Full VI 2.4 2.5 2.6 V Temperature Coefficient Full V ±10 ppm/°C SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 60 MSPS Minimum Conversion Rate Full IV 5 MSPS Aperture Delay (t)25°CV 2.7 ns A Aperture Uncertainty (Jitter) 25°CV 5 ps, rms 2 Output Valid Time (t ) Full IV 4.0 6.6 ns V 2 Output Propagation Delay (t ) Full IV 9.5 14.2 ns PD 3 DYNAMIC PERFORMANCE Transient Response 25°CV 9 ns Overvoltage Recovery Time 25°CV 9 ns Signal-to-Noise Ratio (SINAD) (with Harmonics) f = 10.3 MHz 25°CI 4044.5 dB IN f = 76 MHz 25°CV 43.5 dB IN Effective Number of Bits (ENOB) f = 10.3 MHz 25°CI 6.35 7.1 Bits IN f = 76 MHz 25°CV 6.9 Bits IN Signal-to-Noise Ratio (SNR) (Without Harmonics) f = 10.3 MHz 25°CI 42 46 dB IN f = 76 MHz 25°CV 45 dB IN Second Harmonic Distortion f = 10.3 MHz 25°CI –50 –62 dBc IN f = 76 MHz 25°CV –54 dBc IN Third Harmonic Distortion f = 10.3 MHz 25°CI –46 –60 dBc IN f = 76 MHz 25°CV –54 dBc IN Two-Tone Intermodulation Distortion (IMD) 25°CV –52 dBc Channel Crosstalk Rejection 25°CV –50 dBc Differential Phase 25°CV 0.8 Degrees Differential Gain 25°CV 1.0 % –2– REV. A AD9059 SPECIFICATIONS (continued) AD9059BRS Parameter Temp Test Level Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage Full VI 2.0 V Logic 0 Voltage Full VI 0.8 V Logic 1 Current Full VI ±1 µA Logic 0 Current Full VI ±1 µA Input Capacitance 25°CV 4.5 pF Encode Pulsewidth High (t)25°CIV 6.7 166 ns EH Encode Pulsewidth Low (t)25°CIV 6.7 166 ns EL DIGITAL OUTPUTS Logic 1 Voltage (V = 3 V) Full VI 2.95 V DD Logic 1 Voltage (V = 5 V) Full IV 4.95 V DD Logic 0 Voltage (V = 3 V or 5 V) Full VI 0.05 V DD Output Coding Offset Binary Code POWER SUPPLY V Supply Current (V = 5 V) Full VI 72 92 mA D D 4 V Supply Current (V = 3 V) Full VI 13 15 mA DD DD 5, 6 Power Dissipation Full VI 400 505 mW Power-Down Dissipation Full VI 6 12 mW Power Supply Rejection Ratio (PSRR) 25°CI 3 mV/V NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference). 2 t and t are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed V PD an ac load of 10 pF or a dc current of ±40 µA. 3 SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range. 4 Digital supply current based on V = 3 V output drive with <10 pF loading under dynamic test conditions. DD 5 Power dissipation is based on 60 MSPS encode and 10.3 MHz analog input dynamic test conditions (V = 5 V ± 5%, V = 3 V ± 5%). D DD 6 Typical thermal impedance for the RS style (SSOP) 28-lead package: θ = 39°C/W, θ = 70°C/W, and θ = 109°C/W. JC CA JA Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS V , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Test Level D DD Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V D I– 100% production tested. Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V D II – 100% production tested at +25°C and sample tested at VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V D specified temperatures. Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA III – Sample tested only. Operating Temperature . . . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C IV – Parameter is guaranteed by design and characterization testing. *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device V– Parameter is a typical value only. at these or any other conditions above those indicated in the operational sections of VI – 100% production tested at +25°C; guaranteed by design this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. and characterization testing for industrial temperature range. ORDERING GUIDE Model Temperature Range Package Option AD9059BRS –40°C to +85°C RS-28 AD9059/PCB 25°C Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9059 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– AD9059 PIN FUNCTION DESCRIPTIONS NN + 3 N + 5 Pin No. Mnemonic Function AIN N + 1 1, 28 AINA, AINB Analog Inputs for ADC A and B. N + 2 N + 4 2 VREF Internal Voltage Reference (2.5 V t Typical); Bypass with 0.1 µF to A Ground or Overdrive with External t t ENCODE EH EL Voltage Reference. 3 PWRDN Power-Down Function Select; Logic t V HIGH for Power-Down Mode DIGITAL N – 3 N – 2 N – 1 N N + 1 N + 2 OUTPUTS (Digital Outputs Go to High- Impedance State). t PD 4, 25 V Analog 5 V Power Supply. D MIN TYP MAX 5, 24, 27 GND Ground. t 2.7ns A APERTURE DELAY t 6.7ns 166ns EH PULSEWIDTH HIGH 6, 23 V Digital Output Power Supply. DD t PULSEWIDTH LOW 6.7ns 166ns EL Nominally 3 V to 5 V. t OUTPUT VALID TIME 6.6n V 4.0ns 7–14 D7A–D0A Digital Outputs of ADC A. OUTPUT PROP DELAY t 9.5ns PD 14.2ns 22–15 D7B–D0B Digital Outputs of ADC B. Figure 1. Timing Diagram 26 ENCODE Encode Clock for ADCs A and B (ADCs Sample Simultaneously on PIN CONFIGURATION the Rising Edge of ENCODE). AINA 1 28 AINB Table I. Digital Coding (VREF = 2.5 V) VREF 2 27 GND PWRDN 3 26 ENCODE Analog Input (V) Voltage Level Digital Output V 4 25 V D D 3.0 Positive Full Scale 1111 1111 GND 5 24 GND AD9059 2.502 Midscale + 1/2 LSB 1000 0000 V 6 23 V DD DD TOP VIEW (Not to Scale) 2.498 Midscale – 1/2 LSB 0111 1111 D7A (MSB) 7 22 D7B (MSB) 2.0 Negative Full Scale 0000 0000 D6A 8 21 D6B D5A 9 D5B 20 D4A 10 19 D4B D3A 11 18 D3B D2A 12 17 D2B D1A 13 16 D1B D0A (LSB) 14 15 D0B (LSB) –4– REV. A Typical Performance Characteristics–AD9059 0 –30 ENCODE = 60MSPS ENCODE = 60MSPS –10 –35 ANALOG IN = 10.3MHz, –0.5dBFS AIN = –0.5dBFS SINAD = 43.9dB –20 –40 ENOB = 7.0 BITS SNR = 45.1dB –30 –45 –40 SECOND HARMONIC –50 –50 –55 –60 –60 –70 THIRD HARMONIC –65 –80 –90 –70 0 20 40 60 80 100 120 140 160 030 FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TPC 1. FFT Spectral Plot 60 MSPS, 10.3 MHz TPC 4. Harmonic Distortion vs. AIN Frequency 0 0 ENCODE = 60MSPS ENCODE = 60MSPS –10 –10 F1 IN = 9.5MHz @ –7.0dBFS ANALOG IN = 76MHz, –0.5dBFS F2 IN = 9.9MHz @ –7.0dBFS SINAD = 43.0dB 2F1 - F2 = –52.0dBc –20 –20 2F2 - F1 = –53.0dBc ENOB = 6.85 BITS –30 –30 SNR = 44.1dB –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 030 03 10 200 FREQUENCY (MHz) FREQUENCY (MHz) TPC 2. Spectral Plot 60 MSPS, 76 MHz TPC 5. Two-Tone IMD 46 54 SNR AIN = 10.3MHz, –0.5dBFS SNR 44 48 42 42 SINAD SINAD 40 36 38 30 ENCODE = 60MSPS AIN = –0.5dBFS 36 24 34 18 32 12 30 6 0 20 40 60 80 100 120 140 160 510 20 30405060708090 ANALOG INPUT FREQUENCY (MHz) ENCODE RATE (MSPS) TPC 3. SINAD/SNR vs. AIN Frequency TPC 6. SINAD/SNR vs. Encode Rate REV. A –5– dB dB dB dB dB dB AD9059 600 12 AIN = 10.3MHz, –0.5dBFS 11 550 10 V = 3V DD 500 9.5 9.0 450 V = 5V DD 8.5 400 8.0 7.5 V = 5V DD 350 7.0 V = 3V DD 300 6.5 250 6.0 510 20 3040506070 8090 –45 025 70 90 ENCODE RATE (MSPS) TEMPERATURE (°C) TPC 7. Power Dissipation vs. Encode Rate TPC 10. t vs. Temperature/Supply (3 V/5 V) PD 45.5 46.0 SNR 45.5 SNR 45.0 45.0 44.5 44.5 SINAD 44.0 44.0 43.5 SINAD 43.5 43.0 43.0 42.5 ENCODE = 60MSPS ENCODE = 60MSPS 42.5 42.0 AIN = 10.3MHz, –0.5dBFS AIN = 10.3MHz, –0.5dBFS 41.5 42.0 41.0 41.5 40.5 –45 025 70 90 5.8 6.7 7.5 8.4 9.2 10 10.9 TEMPERATURE (°C) ENCODE HIGH PULSEWIDTH (ns) TPC 8. SINAD/SNR vs. Temperature TPC 11. SINAD/SNR vs. Encode Pulsewidth 0 0 –1 –0.2 –2 –0.4 –3 –0.6 –4 –0.8 –5 –1.0 –6 –1.2 ENCODE = 60MSPS –7 AIN = –0.5dBFS –1.4 –8 –1.6 –9 –10 –1.8 1 25 10 20 50 100 200 500 –45 025 70 90 ANALOG FREQUENCY (MHz) TEMPERATURE (°C) TPC 12. ADC Frequency Response TPC 9. ADC Gain vs. Temperature (With External 2.5 V Reference) –6– REV. A dB GAIN ERROR (%) POWER (mW) t (ns) dB PD ADC GAIN (dB) AD9059 THEORY OF OPERATION Figure 3 shows typical connections for high performance dc The AD9059 combines Analog Devices’ proprietary MagAmp biasing using the ADC’s internal voltage reference. All compo- gray code conversion circuitry with flash converter technology to nents may be powered from a single 5 V supply (analog input provide dual high performance 8-bit ADCs in a single low cost signals are referenced to ground). monolithic device. The design architecture ensures low power, high speed, and 8-bit accuracy. 1k� +5V The AD9059 provides two linked ADC channels that are clocked +5V from a single ENCODE input (see Functional Block Diagram). 1k� AD8041 VIN The two ADC channels simultaneously sample the analog inputs A 1 AINA (AINA and AINB) and provide noninterleaved parallel digital 10k� outputs (D0A–D7A and D0B–D7B). The voltage reference 3 VREF (VREF) is internally connected to both ADCs so channel gains 10k� 0.1µF and offsets will track if external reference control is desired. AD9059 5V The analog input signal is buffered at the input of each ADC AD8041 channel and applied to a high speed track-and-hold. The track- 1k� 28 AINB and-hold circuit holds the analog input value during the VIN B (–0.5V TO +0.5V) conversion process (beginning with the rising edge of the 1k� ENCODE command). The track-and-hold’s output signal passes through the gray code and flash conversion stages to generate Figure 3. DC-Coupled AD9059 (VIN Inverted) coarse and fine digital representations of the held analog input level. Decode logic combines the multistage data and aligns the Voltage Reference 8-bit word for strobed outputs on the rising edge of the ENCODE A stable and accurate 2.5 V voltage reference is built into the command. The MagAmp/Flash architecture of the AD9059 AD9059 (VREF). The reference output is used to set the ADC results in three pipeline delays for the output data. gain/offset and can provide dc bias for the analog input signals. The internal reference is tied to the ADC circuitry through an USING THE AD9059 800 Ω internal impedance and is capable of providing 300 µA Analog Inputs external drive current (for dc biasing the analog input or other The AD9059 provides independent single-ended high impedance user circuitry). (150 kΩ) analog inputs for the dual ADCs. Each input requires a dc bias current of 6 µA (typical) centered near 2.5 V (±10%). The Some applications may require greater accuracy, improved dc bias may be provided by the user or may be derived from the temperature performance, or gain adjustments that cannot be ADC’s internal voltage reference. Figure 2 shows a low cost dc obtained using the internal reference. An external voltage may bias implementation that allows the user to capacitively couple be applied to the VREF pin to overdrive the internal voltage ac signals directly into the ADC without additional active cir- reference for gain adjustment of up to ±10% (the VREF pin is cuitry. For best dynamic performance, the VREF pin should internally tied directly to the ADC circuitry). ADC gain and be decoupled to ground with a 0.1 µF capacitor (to minimize offset will vary simultaneously with external reference adjust- modulation of the reference voltage), and the bias resistor should ment with a 1:1 ratio (a 2% or 50 mV adjustment to the 2.5 V be approximately 1 kΩ. reference varies ADC gain by 2% and ADC offset by 50 mV). Theoretical input voltage range versus reference input voltage 5V may be calculated using the following equations. 0.1µF Vp() −=p VREF 25. RANGE VIN 1 AINA A V =VREF MIDSCALE (1V p-p) 1k� V =+ VREF V 2 AD9059 TOP−− OF RANGE RANGE V =VREF – V 2 BOTTOM−− OF RANGE RANGE EXTERNAL V 3 VREF REF (OPTIONAL) 0.1µF The external reference should have a 1 mA minimum sink/ 1k� source current capability to ensure complete overdrive of the VIN 28 AINB internal voltage reference. B (1V p-p) 0.1µF Figure 2. Capacity Coupled AD9059 REV. A –7– AD9059 Digital Logic (5 V/3 V Systems) Applications The digital inputs and outputs of the AD9059 can easily be The wide analog bandwidth of the AD9059 makes it attractive for configured to interface directly with 3 V or 5 V logic systems. a variety of high performance receiver and encoder applications. The encode and power-down (PWRDN) inputs are CMOS Figure 4 shows the dual ADC in a typical low cost I and Q stages with TTL thresholds of 1.5 V, making the inputs compat- demodulator implementation for cable, satellite, or wireless ible with TTL, 5 V CMOS, and 3 V CMOS logic families. As LAN modem receivers. The excellent dynamic performance of with all high speed data converters, the encode signal should be the ADC at higher analog input frequencies and encode rates clean and jitter free to prevent degradation of ADC dynamic empowers users to employ direct IF sampling techniques (see performance. TPC 2). IF sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. The AD9059’s digital outputs will also interface directly with 5 V or 3 V CMOS logic systems. The voltage supply pins (V ) for DD these CMOS stages are isolated from the analog V voltage D AD9059 supply. By varying the voltage on these supply pins, the digital output high levels will change for 5 V or 3 V systems. The V ADC DD BPF pins are internally connected on the AD9059 die. Care should 90° IF IN be taken to isolate the V supply voltages from the 5 V analog DD ADC BPF supply to minimize noise coupling into the ADCs. The AD9059 provides high impedance digital output operation VCO VCO when the ADC is driven into power-down mode (PWRDN, logic high). A 200 ns (minimum) power-down time should be Figure 4. I and Q Digital Receiver provided before a high impedance characteristic is required. A 200 ns power-up period should be provided to ensure accurate The high sampling rate and analog bandwidth of the AD9059 ADC output data after reactivation (valid output data is avail- are ideal for computer RGB video digitizer applications. With a able three clock cycles after the 200 ns delay). full-power analog bandwidth of 2× the maximum sampling rate, the ADC provides sufficient pixel-to-pixel transient settling time Timing to ensure accurate 60 MSPS video digitization. Figure 5 shows The AD9059 is guaranteed to operate with conversion rates a typical RGB video digitizer implementation for the AD9059. from 5 MSPS to 60 MSPS. At 60 MSPS, the ADC is designed to operate with an encode duty cycle of 50%, but performance AD9059 is insensitive to moderate variations. Pulsewidth variations of up 8 RED ADC to ±10% (allowing the encode signal to meet the minimum/ maximum high/low specifications) will cause no degradation in 8 ADC GREEN ADC performance (see Figure 1). PIXEL CLOCK Due to the linked ENCODE architecture of the ADCs, the H-SYNC PLL AD9059 cannot be operated in a 2-channel ping-pong mode. 8 Power Dissipation BLUE ADC The power dissipation of the AD9059 is specified to reflect a ADC typical application setup under the following conditions: encode is 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, V is 5 V, D AD9059 V is 3 V, and digital outputs are loaded with 7 pF typical DD (10 pF maximum). The actual dissipation will vary as these conditions are modified in user applications. TPC 7 shows typi- Figure 5. RGB Video Encoder cal power consumption for the AD9059 versus ADC encode frequency and V supply voltage. DD A power-down function allows users to reduce power dissipation when ADC data is not required. A TTL/CMOS high signal (PWRDN) shuts down portions of the dual ADC and brings total power dissipation to less than 10 mW. The internal band gap voltage reference remains active during power-down mode to minimize ADC reactivation time. If the power-down function is not desired, Pin 3 should be tied to ground. Both ADC channels are controlled simultaneously by the PWRDN pin; they cannot be shut down or turned on independently. –8– REV. A AD9059 +V DD +V +V +V D 3V TO 5V D D 3k� 800� 500� ENCODE VREF AIN VREF D0–D7 PWRDN 2.5k� 2.5V DIGITAL INPUTS DIGITAL OUTPUTS VOLTAGE REFERENCE ANALOG INPUTS Figure 6. Equivalent Circuits Analog input signals to the board should be 1 V p-p into 50 Ω Evaluation Board for full-scale ADC drive. For ac-coupled operation, connect E7 The AD9059/PCB evaluation board provides an easy-to-use to E8 (analog input A to C12 feedthrough capacitor), E13 to analog/digital interface for the dual 8-bit, 60 MSPS ADC. The E15 (C12 to R15 termination resistor for Channel A), E4 to E6 board includes typical hardware configurations for a variety of high (analog input B to C11 feedthrough capacitor), and E10 to E12 speed digitization evaluations. On-board components include the (C11 to R14 termination resistor for Channel B) using the AD9059 (in the 28-lead SSOP package), optional analog input board jumper connectors. buffer amplifiers, digital output latches, board timing drivers, and configurable jumpers for ac coupling, dc coupling, and power- The on-board reference voltage may be used to drive the ADC or down function testing. The board is configured at shipment for an external reference may be applied. The standard configuration dc coupling using the AD9059’s internal reference. employs the internal voltage reference without any external connection requirements. An external voltage reference may be For dc-coupled analog input applications, amplifiers U3 and U4 applied at board connector input REF to overdrive the limited are configured to operate as unity gain inverters with adjustable current output of the AD9059’s internal voltage reference. The offset for the analog input signals. For full-scale ADC drive, external voltage reference should be 2.5 V typical. each analog input signal should be 1 V p-p into 50 Ω referenced to ground. Each amplifier offsets its analog signal by +VREF The power-down function of the AD9059 can be exercised (2.5 V typical) to center the voltage for proper ADC input drive. through a board jumper connection. Connect E2 to E1 (5 V to For dc-coupled operation, connect E7 to E9 (analog input A to PWRDN) for power-down mode operation. For normal operation, R11), E14 to E13 (amplifier output to analog input A of connect E3 to E1 (ground to PWRDN). AD9059), E4 to E5 (analog input B to R10), and E11 to E10 The encode signal source should be TTL/CMOS compatible (amplifier output to analog input B of AD9059) using the board and capable of driving a 50 Ω termination. The digital outputs jumper connectors. of the AD9059 are buffered through latches on the evaluation For ac-coupled analog input applications, amplifiers U3 and U4 board (U5 and U6) and are available for the user at connector are removed from the analog signal paths. The analog signals Pins 30–37 and Pins 22–29. Latch timing is derived from the are coupled through Capacitors C11 and C12, each terminated ADC ENCODE clock and a digital clocking signal is provided to the VREF voltage through separate 1 kΩ resistors (providing for the board user at connector Pins 2 and 21. bias current for the AD9059 analog inputs, AINA and AINB). REV. A –9– AD9059 J9, V DD ANALOG IN–A U4 C12 BNC AD8041Q 0.1µF E8 J5 C16 C9 8 E7 1 DIS NC 10µF 0.1µF P2 R5 U1 2 7 +V 5V S 10� C37DRPF AD9059RS E14 3 E9 6 R13 R11 E13 1 28 1 50� 4 5 1k� AINB –V AINA NC E15 S 2 27 2 GND VREF 3 3 26 R15 R7 ENC PWRDN U5 4 4 25 1k� 1k� V 5V 5V V D D 74ACQ574 5 5 24 GND GND C10 9 12 6 R8 C17 6 23 D0B 8D DB0 8Q V 10k� 0.1µF V DD 10µF DD 8 13 7 7 22 C8 D1B 7D 7Q DB1 D7A D7A D7B D7B 7 14 8 8 21 0.1µF D2B 6D 6Q DB2 R9 J1, REF D6A D6A D6B D6B 6 15 9 10k� 9 20 5D D3B 5Q DB3 D5A D5A D5B D5B 10 5 16 10 19 D4B 4D 4Q DB4 D4A D4A D4B D4B 11 4 17 11 18 D5B 3D 3Q DB5 D3A D3B D3B D3A 12 E2 3 18 12 17 5V 2Q D6B 2D DB6 E1 D2A D2B D2B R14 D2A 13 2 19 13 16 E3 D7B 1Q DB7 1k� D1A D1B D1B 1D D1A 14 PWRDN 14 15 CK D0A D0B D0B D0A OE 15 16 11 1 E12 17 R8 E10 1k� E11 18 U6 19 74ACQ574 R4 20 U3 10� 9 12 21 AD8041Q D7A 8D 8Q DA7 ANALOG IN–B 8 13 22 R10 D6A 7D 7Q DA6 1 8 DB0 BNC 7 14 DIS 1k� NC 23 6D DA5 E5 D5A 6Q J4 2 7 DB1 6 +V 5V 15 S 24 E4 D4A 5D 5Q DA4 6 DB2 3 5 16 E6 25 D3A 4D 4Q DA3 5 4 C11 DB3 4 R12 –V NC 17 S 26 3Q 0.1µF D2A 3D DA2 50� DB4 3 18 27 D1A 2Q DA1 2D DB5 2 19 28 DA0 1D 1Q D0A DB6 U7 29 CK DB7 OE 74AC00 30 BNC DA0 1 1 11 31 J10 3 DA1 2 32 J11, V D ENCODE C6 C7 C14 DA2 33 0.1µF 0.1µF 0.1µF U7 DA3 R15 34 74AC00 5V 50� DA4 4 35 C3 C4 C5 C13 C15 6 DA5 0.1µF 0.1µF 0.1µF 0.1µF 10µF 36 5 DA6 37 DA7 U7 DECOUPLING CAPS 74AC00 12 11 J12, GND 13 Figure 7. AD9059 Dual Evaluation Board Schematic –10– REV. A AD9059 Figure 8. Evaluation Board Layout (Top) Figure 9. Evaluation Board Layout (Bottom) REV. A –11– AD9059 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 8.20 5.30 7.80 5.00 7.40 1 14 1.85 1.75 0.10 1.65 COPLANARITY 2.00 MAX 0.25 0.09 8� 0.95 0.65 0.38 0.05 BSC 4� 0.75 0.22 SEATING MIN 0� PLANE 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH Revision History Location Page 4/03—Data Sheet changed from REV. 0 to REV. A. Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 –12– REV. A C00563–0–4/03(A)