ANALOG DEVICES AD9054A

8-Bit, 200 MSPS a A/D Converter AD9054A FEATURES FUNCTIONAL BLOCK DIAGRAM 200 MSPS Guaranteed Conversion Rate VREF IN VREF OUT 135 MSPS Low Cost Version Available 350 MHz Analog Bandwidth AD9054A 2.5V REFERENCE 1 V p-p Analog Input Range Internal 2.5 V Reference and T/H AIN 8 T/H QUANTIZER ENCODE DA –DA 7 0 Low Power: 500 mW AIN LOGIC 8 5 V Single Supply Operation DEMULTIPLEXER ENCODE DB –DB 7 0 TIMING TTL Output Interface ENCODE Single or Demultiplexed Output Ports V GND DS DEMUX DS DD APPLICATIONS RGB Graphics Processing High Resolution Video Digital Data Storage Read Channels Digital Communications Digital Instrumentation Medical Imaging GENERAL DESCRIPTION The AD9054A’s encode input interfaces directly to TTL, CMOS The AD9054A is an 8-bit monolithic analog-to-digital converter or positive-ECL logic and will operate with single-ended or optimized for high speed, low power, small size and ease of use. differential inputs. The user may select dual-channel or single- With a 200 MSPS encode rate capability and full-power analog channel digital outputs. The dual (demultiplexed) mode inter- bandwidth of 350 MHz, the component is ideal for applications leaves ADC data through two 8-bit channels at one-half the requiring the highest possible dynamic performance. clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces while allowing the ADC to To minimize system cost and power dissipation, the AD9054A be clocked to the full 200 MSPS conversion rate. In the single- includes an internal 2.5 V reference and track-and-hold circuit. channel (nondemultiplexed) mode, all data is piped at the full The user provides only a 5 V power supply and an encode clock. clock rate to the Channel A outputs. No external reference or driver components are required for many applications. Fabricated with an advanced BiCMOS process, the AD9054A is provided in a space-saving 44-lead LQFP surface mount plastic package (ST-44) and specified over the full industrial (–40°C to +85°C) temperature range. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD9054A–SPECIFICATIONS (V = 5 V, external reference, f = max unless otherwise noted.) ELECTRICAL CHARACTERISTICS DD S Test AD9054ABST-200 AD9054ABST-135 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25°CI ±0.9 +1.5/–1.0 ±0.9 +1.5/–1.0 LSB Full VI ±1.0 +2.0/–1.0 ±1.0 +2.0/–1.0 LSB Integral Nonlinearity 25°CI ±0.6 ±1.5 ±0.6 ±1.5 LSB Full VI ±0.9 ±2.0 ±0.9 ±2.0 LSB No Missing Codes Full VI Guaranteed Guaranteed 1 Gain Error 25°CI ± 2 ± 7 ± 2 ±7% FS 1 Gain Tempco Full V 160 160 ppm/°C ANALOG INPUT Input Voltage Range (With Respect to AIN) Full V ±512 ±512 mV p-p Compliance Range AIN or AIN Full V 1.8 3.2 1.8 3.2 V Input Offset Voltage 25°CI ± 4 ±16 ± 4 ±16 mV Full VI ± 8 ±19 ± 8 ±19 mV Input Resistance 25°C I 36 62 36 62 kΩ Full VI 23 23 kΩ Input Capacitance 25°CV 4 4 pF Input Bias Current 25°C I 25 50 25 50 µA Full VI 75 75 µA 2 Analog Bandwidth, Full Power 25°C V 350 350 MHz REFERENCE OUTPUT Output Voltage Full VI 2.4 2.5 2.6 2.4 2.5 2.6 V Temperature Coefficient Full V 110 110 ppm/°C SWITCHING PERFORMANCE Maximum Conversion Rate (f ) Full VI 200 135 MSPS S Minimum Conversion Rate (f ) Full IV 25 25 MSPS S Encode Pulsewidth High (t)25°C IV 2.0 22 3.0 22 ns EH Encode Pulsewidth Low (t)25°C IV 2.0 22 3.0 22 ns EL Aperture Delay (t)25°C V 0.5 0.5 ns A Aperture Uncertainty (Jitter) 25°C V 2.3 2.3 ps rms Data Sync Setup Time (t)25°CIV 0 0 ns SDS Data Sync Hold Time (t)25°C IV 0.5 0.5 ns HDS Data Sync Pulsewidth (t)25°C IV 2.0 2.0 ns PWDS 3 Output Valid Time (t ) Full VI 2.7 5.1 2.7 5.7 ns V 3 Output Propagation Delay (t ) Full VI 5.9 7.9 7.5 8.5 ns PD DIGITAL INPUTS 4 HIGH Level Current (I ) Full VI 500 625 500 625 µA IH 4 LOW Level Current (I ) Full VI 500 625 500 625 µA IL Input Capacitance 25°CV 3 3 pF DIFFERENTIAL INPUTS Differential Signal Amplitude (V ) Full IV 400 400 mV ID HIGH Input Voltage (V ) Full IV 1.5 V 1.5 V V IHD DD DD LOW Input Voltage (V ) Full IV 0 V – 0.4 0 V – 0.4 V ILD DD DD Common-Mode Input (V ) Full IV 1.5 1.5 V ICM DEMUX INPUT HIGH Input Voltage (V ) Full IV 2.0 V 2.0 V V IH DD DD LOW Input Voltage (V ) Full IV 0 0.8 0 0.8 V IL DIGITAL OUTPUTS HIGH Output Voltage (V ) Full VI 2.4 2.4 V OH LOW Output Voltage (V ) Full VI 0.4 0.4 V OL Output Coding Binary Binary –2– REV. D AD9054A Test AD9054ABST-200 AD9054ABST-135 Parameter Temp Level Min Typ Max Min Typ Max Unit POWER SUPPLY V Supply Current (I ) Full VI 128 156 120 140 mA DD DD 5, 6 Power Dissipation Full VI 640 781 600 700 mW 7 Power Supply Sensitivity 25°C I 0.005 0.015 0.005 0.015 V/V 8 DYNAMIC PERFORMANCE Transient Response 25°C V 1.5 1.5 ns Overvoltage Recovery Time 25°C V 1.5 1.5 ns Signal-to-Noise Ratio (SNR) (Without Harmonics) f = 19.7 MHz 25°CIV 42 45 42 45 dB IN Full V 45 45 dB f = 49.7 MHz 25°C I 42 45 42 45 dB IN Full V 45 45 dB f = 70.1 MHz 25°C I 42 45 dB IN Full V 45 dB Signal-to-Noise Ratio (SINAD) (With Harmonics) f = 19.7 MHz 25°CIV 40 43 40 43 dB IN Full V 43 43 dB f = 49.7 MHz 25°C I 40 43 40 43 dB IN Full V 43 43 dB f = 70.1 MHz 25°C I 39 42 dB IN Full V 42 dB Effective Number of Bits f = 19.7 MHz 25°C IV 6.35 6.85 6.35 6.85 Bits IN f = 49.7 MHz 25°C I 6.35 6.85 6.35 6.85 Bits IN f = 70.1 MHz 25°C I 6.18 6.85 Bits IN 2nd Harmonic Distortion f = 19.7 MHz 25°C IV 58 63 58 63 dBc IN f = 49.7 MHz 25°C I 54 59 54 59 dBc IN f = 70.1 MHz 25°C I 49 55 dBc IN 3rd Harmonic Distortion f = 19.7 MHz 25°C IV 48 56 48 56 dBc IN f = 49.7 MHz 25°C I 48 54 48 54 dBc IN f = 70.1 MHz 25°C I 43 50 dBc IN Two-Tone Intermod Distortion (IMD) f = 19.7 MHz 25°C V 60 60 dBc IN f = 49.7 MHz 25°C V 55 55 dBc IN f = 70.1 MHz 25°C V 50 dBc IN NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference). 2 3 dB bandwidth with full-power input signal. 3 t and t are measured from the threshold crossing of the ENCODE input to valid TTL levels of the digital outputs. The output ac load during test is 5 pF (Refer to V PD equivalent circuits Figures 5 and 6). 4 I and I are valid for differential input voltages of less than 1.5 V. At higher differential voltages, the input current will increase to a maximum of 1.5 mA. IH IL 5 Power dissipation is measured under the following conditions: analog input is –1 dBFS at 19.7 MHz. 6 Typical thermal impedance for the ST-44 (LQFP) 44-lead package (in still air): θ = 20°C/W, θ = 35°C/W, θ = 55°C/W. JC CA JA 7 A change in input offset voltage with respect to a change in V . DD 8 SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS IV. Parameter is guaranteed by design and characterization testing. Test Level V. Parameter is a typical value only. I. 100% production tested. VI. 100% production tested at 25°C; guaranteed by design and II. 100% production tested at 25°C and sample tested at speci- characterization testing for industrial temperature range. fied temperatures. III. Sample tested only. REV. D –3– AD9054A Table I. Output Coding ABSOLUTE MAXIMUM RATINGS* V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V DD Step AIN–AIN Code Binary Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . V to 0.0 V DD Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . V to 0.0 V DD 255 ≥0.512 V 255 1111 1111 VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . V to 0.0 V DD 254 0.508 V 254 1111 1110 Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA 253 0.504 V 253 1111 1101 Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C •• • • Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C •• • • Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C •• • • Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C 129 0.006 V 129 1000 0001 *Stresses above those listed under Absolute Maximum Ratings may cause perma- 128 0.002 V 128 1000 0000 nent damage to the device. This is a stress rating only; functional operation of the 127 –0.002 V 127 0111 1111 device at these or any other conditions outside of those indicated in the operation 126 –0.006 V 126 0111 1110 sections of this specification is not implied. Exposure to absolute maximum ratings •• • • for extended periods may affect device reliability. •• • • •• • • 2 –0.504 V 2 0000 0010 ORDERING GUIDE 1 –0.508 V 1 0000 0001 0 ≤–0.512 V 0 0000 0000 Temperature Package Model Range Option* AD9054ABST-200 –40°C to +85°C ST-44 AD9054ABST-135 –40°C to +85°C ST-44 AD9054A/PCB 25°C Evaluation Board *ST = Plastic Thin Quad Flatpack (LQFP). CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9054A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. D AD9054A PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION Pin Number Mnemonic Function 1 ENCODE Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE) 2 ENCODE Encode Clock Complement VREF IN DB 3 (ADC Samples on Falling Edge GND DB 2 of ENCODE) VDD DB 1 3, 5, 15, 18, 28, VDD Power Supply (5 V) GND DB (LSB) 0 30, 31, 36, 41 AIN VDD AD9054A 4, 6, 16, 17, 27, GND Ground AIN TOP VIEW GND (PINS DOWN) 29, 32, 35, 37, 40 GND GND 14–7 DA –DA Digital Outputs of ADC Channel VDD VDD 0 7 A. DA is the MSB, DA the LSB 7 0 DEMUX DA (LSB) 0 DS DA 19–26 DB –DB Digital Outputs of ADC Channel 1 0 7 PIN 1 DS DA B. DB is the MSB, DB the LSB IDENTIFIER 7 0 2 33 VREF OUT Internal Reference Output (2.5 V typical); Bypass with 0.1 µF to Ground 34 VREF IN Reference Input for ADC (2.5 V typical, ±4%) 38 AIN Analog Input—Complement. Connect to input signal midscale reference. 39 AIN Analog Input—True 42 DEMUX Format Select. LOW = Dual. Channel Mode, HIGH = Single. Channel Mode (Channel A Only) 43 DS Data Sync Complement 44 DS Data Sync—Aligns Output Chan- nels in Dual-Channel Mode SAMPLE N SAMPLE N+3 SAMPLE N+4 SAMPLE N–1 AIN SAMPLE N+1 SAMPLE N+2 t A 1/f t t EH EL S ENCODE ENCODE t PD t V DATA N–5 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N D –D 7 0 Figure 1. Timing—Single Channel Mode REV. D –5– ENCODE VREF OUT ENCODE GND VDD VDD GND VDD VDD GND VDD GND DA (MSB) GND 7 DA DB (MSB) 6 7 DB DA 5 6 DA DB 4 5 DA DB 3 4 AD9054A SAMPLE N SAMPLE N+3 SAMPLE N+4 SAMPLE N+5 SAMPLE N–1 AIN SAMPLE N–2 SAMPLE N+1 SAMPLE N+2 SAMPLE N+6 t A t t EH EL 1/f S ENCODE ENCODE t HDS t HDS t SDS t SDS DS DS t t PD t V PWDS PORT A DATA N–7 DATA N–7 INVALID IF OUT OF SYNC DATA N–2 DATA N OR N–8 D –D OR N–6 DATA N–4 IF IN SYNC 7 0 PORT B DATA N–8 DATA N–6 INVALID IF OUT OF SYNC DATA N–3 DATA N–1 DATA N+1 OR N–7 OR N–7 DATA N–5 IF IN SYNC D –D 7 0 Figure 2a. Timing—Dual Channel Mode (One-Shot Data Sync) SAMPLE N SAMPLE N+5 SAMPLE N+3 SAMPLE N+4 SAMPLE N–1 AIN SAMPLE N–2 SAMPLE N+1 SAMPLE N+2 SAMPLE N+6 t A t t EH EL 1/f S ENCODE ENCODE t t t t HDS SDS SDS HDS DS DS t PWDS t t PD V PORT A DATA N–7 INVALID IF OUT OF SYNC DATA N–7 DATA N–2 DATA N D –D OR N–8 OR N–6 DATA N–4 IF IN SYNC 7 0 PORT B DATA N–8 DATA N–6 INVALID IF OUT OF SYNC DATA N–3 DATA N–1 DATA N+1 OR N–7 OR N–7 DATA N–5 IF IN SYNC D –D 7 0 Figure 2b. Timing—Dual Channel Mode (Continuous Data Sync) –6– REV. D AD9054A EQUIVALENT CIRCUITS V DD V DD 17.5k� 300� 300� DEMUX AIN AIN 7.5k� Figure 3. Equivalent Analog Input Circuit Figure 6. Equivalent DEMUX Input Circuit V V DD DD VREF IN DIGITAL OUTPUTS Figure 4. Equivalent Reference Input Circuit Figure 7. Equivalent Digital Output Circuit V DD V DD 17.5k� 300� 300� ENCODE ENCODE OR DS OR DS VREF OUT 7.5k� Figure 5. Equivalent ENCODE and Data Select Input Circuit Figure 8. Equivalent Reference Output Circuit REV. D –7– AD9054A–Typical Performance Characteristics 55 45.4 45.2 50 45.0 SNR 50MHz 20MHz 45 44.8 SINAD 44.6 40 70MHz 44.4 NYQUIST FREQUENCY 35 (100MHz) 44.2 30 44.0 0 20 40 60 80 100 120 140 –45 0 25 70 90 f – MHz IN T – �C C TPC 1. SNR vs. f :f = 200 MSPS TPC 4. SNR vs. Temperature, f = 135 MSPS IN S S 50 46.0 49 45.8 48 45.6 20MHz 47 45.4 50MHz 46 45.2 SNR 70MHz 45 45.0 44 44.8 SINAD 43 44.6 42 44.4 41 44.2 40 44.0 25 50 75 100 125 150 175 200 225 250 270 300 –60 –40 –20 0 20 40 60 80 100 T – �C f – MSPS S C TPC 2. SNR vs. f : f = 19.7 MHz TPC 5. SNR vs. Temperature, f = 200 MSPS S IN S 50 50 f = 135MSPS S 48 SNR f = 10.3MHz IN 45 46 SINAD 44 40 42 SNR 35 40 38 SINAD 30 36 34 25 32 30 20 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 25 50 75 100 125 150 175 200 225 250 270 300 ENCODE PULSEWIDTH – ns f – MSPS S TPC 3. SNR vs. f :f = 70.1 MHz TPC 6. SNR vs. Clock Pulsewidth, (t ): f = 135 MSPS S IN PWH S –8– REV. D SNR – dB SNR – dB SNR – dB SNR – dB SNR – dB SNR – dB AD9054A 50 –70 f = 200MSPS –68 S 48 2ND HARMONIC f = 10.3MHz IN SNR –66 46 –64 44 –62 SINAD 42 –60 3RD HARMONIC –58 40 –56 38 –54 36 –52 34 –50 32 –48 30 –46 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 25 50 75 100 125 150 175 200 225 250 270 300 ENCODE PULSEWIDTH – ns f – MSPS S TPC 7. SNR vs. Clock Pulsewidth, (t ): f = 200 MSPS TPC 10. Harmonic Distortion vs. f :f = 19.7 MHz PWH S S IN 46 –60 2ND HARMONIC 45 –50 44 20MHz –40 43 3RD HARMONIC 42 70MHz –30 50MHz 41 –20 40 –10 39 38 0 25 50 75 100 125 150 175 200 225 250 270 300 –60 –40 –20 0 2040 6080 100 f – MSPS T – �C S C TPC 8. SINAD vs. Temperature: f = 135 MSPS TPC 11. Harmonic Distortion vs. f :f = 70.1 MHz S S IN 46 –40 45 –45 44 20MHz –50 43 50MHz 42 –55 70MHz 70MHz 41 –60 50MHz 40 –65 39 20MHz 38 –70 –60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 2040 6080 100 T – �C C T – �C C TPC 9. SINAD vs. Temperature: f = 200 MSPS TPC 12. 2nd Harmonic vs. Temperature: f = 135 MSPS S S REV. D –9– SNR – dB SINAD – dB SINAD – dB dB dBc dBc AD9054A –40 0 –45 –1 –2 –50 70MHz –55 –3 50MHz –60 –4 NYQUIST FREQUENCY 20MHz 100MHz –65 –5 –70 –6 –60 –40 –20 0 20 40 60 80 100 0 50 100 150 200 250 300 350 400 450 500 f – MHz T – �C C IN TPC 13. 2nd Harmonic vs. Temperature: f = 200 MSPS TPC 16. Frequency Response: f = 200 MSPS S S –40 0 FUNDAMENTAL = –0.5dBFS –10 SNR = 45.8dB –45 SINAD = 45.2dB 2ND HARMONIC = 69.8dB –20 3RD HARMONIC = 61.6dB –50 –30 70MHz 50MHz –40 –55 –50 20MHz –60 –60 –70 –65 –80 –70 –90 –60 –40 –20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100 MHz T – �C C TPC 14. 3rd Harmonic vs. Temperature: f = 135 MSPS TPC 17. Spectrum: f = 200 MSPS, f = 19.7 MHz S S IN –40 0 FUNDAMENTAL = –0.5dBFS –10 SNR = 44.6dB –45 SINAD = 37.6dB 2ND HARMONIC = –63.1dB –20 70MHz 3RD HARMONIC = –39.1dB –50 –30 50MHz –40 –55 –50 20MHz –60 –60 –70 –65 –80 –70 –90 –60 –40 –20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100 T – �C MHz C TPC 15. 3rd Harmonic vs. Temperature: f = 200 MSPS TPC 18. Spectrum: f = 200 MSPS, f = 70.1 MHz S S IN –10– REV. D dB dB dB dB dB dB AD9054A 7 0 F1 = 55.0MHz t –10 PD F2 = 56.0MHz 6 F1 = F2 = –7.0dBFS –20 t V 5 –30 –40 4 –50 3 –60 –70 2 –80 1 –90 0 –100 –60 –40 –20 0 2040 6080 100 0 10 20 30 40 50 60 70 80 90 100 T – �C MHz C TPC 19. Two-Tone Intermodulation Distortion TPC 22. Output Delay vs. Temperature 5.0 2.55 4.5 2.54 4.0 2.53 3.5 2.52 3.0 2.51 2.5 2.50 2.0 2.49 1.5 2.48 1.0 2.47 0.5 2.46 0.0 2.45 0.0 –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0 –9.0 –10.0 –20 –18 –16 –14 –12 –10 –8 –6 –4 –20 2 I – mA IREF OUT – mA OH TPC 23. Reference Voltage vs. Reference Load TPC 20. Output Voltage HIGH vs. Output Current 1.0 2.502 0.9 0.8 2.501 0.7 0.6 0.5 2.500 0.4 0.3 2.499 0.2 0.1 0.0 2.498 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 I – mA OL V – Volts DD TPC 21. Output Voltage LOW vs. Output Current TPC 24. Reference Voltage vs. Power Supply Voltage REV. D –11– V – Volts V – Volts OH dB OL VREF OUT – Volts VREF OUT – Volts ns AD9054A 2.502 These applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the A/D must settle 2.501 and sample the input in well under one pixel time. The architec- ture of the AD9054A is vastly superior to older flash architectures, that not only exhibit excessive input capacitance (which is very 2.500 hard to drive), but can make major errors when fed a very rap- idly slewing signal. The AD9054A’s extremely wide bandwidth Track/Hold circuit processes these signals without difficulty. 2.499 Using the AD9054A Good high speed design practices must be followed when using the AD9054A. To obtain maximum benefit, decoupling capaci- 2.498 tors should be physically as close to the chip as possible. We –40 –20 0 20 40 60 80 100 recommend placing a 0.1 µF capacitor at each power-ground T – �C AMB pin pair (9 total) for high frequency decoupling, and including TPC 25. Reference Voltage vs. Temperature one 10 µF capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0.1 µF capacitor. APPLICATION NOTES The part should be located on a solid ground plane and output THEORY OF OPERATION trace lengths should be short (<1 inch) to minimize transmis- The AD9054A combines Analog Devices’ patented MagAmp sion line effects. This avoids the need for termination resistors bit-per-stage architecture with flash converter technology to on the output bus and reduces the load capacitance that needs create a high performance, low power ADC. For ease of use the to be driven, which in turn minimizes on-chip noise due to part includes an on-board reference and input logic that accepts heavy current flow in the outputs. We have obtained optimum TTL, CMOS or PECL levels. performance on our evaluation board by tying all V pins to a DD quiet analog power supply system, and tying all GND pins to a The analog input signal is buffered by a high-speed differential quiet analog system ground. amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and Minimum Encode Rate maintains it for the duration of the conversion. The sampling The minimum sampling rate for the AD9054A is 25 MHz. and conversion process is initiated by a rising edge on the To achieve very high sampling rates, the track/hold circuit ENCODE input. Once the signal is captured by the T/H, the employs a very small hold capacitor. When operated below the four Most Significant Bits (MSBs) are sequentially encoded by minimum guaranteed sampling rate, the T/H droop becomes the MagAmp string. The residue signal is then encoded by a excessive. This is first observed as an increase in offset voltage, flash comparator string to generate the four Least Significant followed by degraded linearity at even lower frequencies. Bits (LSBs). The comparator outputs are decoded and com- Lower effective sampling rates may be easily supported by oper- bined into the 8-bit result. ating the converter in dual port output mode and using only If the user has selected Single Channel Mode (DEMUX = one output channel. A majority of the power dissipated by the HIGH), the 8-bit data word is directed to the Channel A out- AD9054A is static (not related to conversion rate) so the penalty put bank. Data are strobed to the output on the rising edge of for clocking at twice the desired rate is not high. the ENCODE input with four pipeline delays. If the user has Reference selected Dual Channel Mode (DEMUX = LOW) the data are The AD9054A internal reference, VREF, provides a simple, cost alternately directed between the A and B output banks and have effective reference for many applications. It exhibits reasonable five pipeline delays. At power-up, the N sample data can appear accuracy and excellent stability over power supply and tempera- at either the A or B port. To align the data in a known state the ture variations. The VREF OUT pin can simply be strapped to user must strobe DATA SYNC (DS, DS) per the conditions the VREF IN pin. The internal reference can be used to drive described in the Timing section. additional loads (up to several mA), including multiple A/D con- Graphics Applications verters as might be required in a triple video converter application. The high bandwidth and low power of the AD9054A make it very When an external reference is desired for accuracy or other attractive for applications that require the digitization of presampled requirements, the AD9054A should be driven directly by the waveforms, wherein the input signal rapidly slews from one external reference source connected to pin VREF IN (VREF level to another and is relatively stable for a period of time. OUT can be left floating). The external reference can be set to Examples of these include digitizing the output of computer 2.5 V ± 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the graphic display systems and very high speed solid state imagers. analog full-scale range will increase by 10% to 1.024 × 1.1 = 1.1264 V. The new input range will then be AIN ±0.5632 V. –12– REV. D VREF OUT – Volts AD9054A Digital Inputs When operating in Single-Channel Mode, the outputs at Port B SNR performance is directly related to the sampling clock sta- are held static in a random state. bility in A/D converters, particularly for high input frequencies Figure 10 shows the AD9054A used in single-channel output and wide bandwidths. A low jitter clock (<10 ps @ 100 MHz) is mode. The analog input (±0.5 V) is ac coupled and the ENCODE essential for optimum performance when digitizing signals that input is driven by a TTL level signal. The chip’s internal refer- are not presampled. ence is used. ENCODE and Data Select (DS) can be driven differentially or single-ended. For single-ended operation, the complement VREF OUT inputs (ENCODE, DS) are internally biased to V /3 (~1.5 V) DD 0.1�F VREF IN by a high impedance on-chip resistor divider (Figure 5), but A PORT they may be externally driven to establish an alternate threshold AIN if desired. A 0.1 µF decoupling capacitor to ground is sufficient 1k� AD9054A VIN AIN to maintain a threshold appropriate for TTL or CMOS logic. 0.1�F When driven differentially, ENCODE and DS will accommo- DEMUX 5V date differential signals centered between 1.5 V and 4.5 V with a total differential swing ≥800 mV (V ≥ 400 mV). ID DS DS ENC ENC Note the 6-diode clock input protection circuitry in Figure 5. 0.1�F This limits the differential input voltage to ~ ±2.1 V. When the NC diodes turn on, current is limited by the 300 Ω series resistor. CLOCK NC = NO CONNECT Exceeding 2.1 V across the differential inputs will have no impact on the performance of the converter, but be aware of the Figure 10. Single Port Mode—AC-Coupled Input—Single- clock signal distortion that may be produced by the nonlinear Ended Encode impedance at the converter. Dual Port Mode In Dual Port Mode (DEMUX = LOW), the conversion results V IH D are alternated between the two output ports (Figure 2). This CLOCK ENC limits the data output rate at either port to 1/2 the conversion V V IC M ID CLOCK ENC rate (ENCODE), and supports conversion at up to 200 MSPS V IL D with TTL/CMOS compatible interfaces. Dual Channel Mode is required for guaranteed operation above 100 MSPS, but may be a. Driving Differential Inputs Differentially enabled at any specified conversion rate. The multiplexing is controlled internally via a clock divider, V IH D CLOCK ENC which introduces a degree of ambiguity in the port assignments. V ID Figure 2 illustrates that, prior to synchronization, either Port A V IC M ENC or Port B may produce the even or odd samples. This is resolved 0.1�F V IL D by exercising the Data Sync (DS) control, a differential input (identical to the ENCODE input), which facilitates operation at b. Driving Differential Inputs Single-Endedly high speed. At least once after power-up, and prior to using the conversion Figure 9. Input Signal Level Definitions data, the part needs to be synchronized by a falling edge (or a positive-going pulse) on DS (observing setup and hold times Single Port Mode with respect to ENCODE). If the converter’s internal timing is When operated in a Single Port mode (DEMUX = HIGH), the in conflict with the DS signal when it is exercised, then two data timing of the AD9054A is similar to any high speed A/D Con- samples (one on each port) are corrupted as the converter is verter (Figure 1). resynchronized. The converter then produces data with a A sample is taken on every rising edge of ENCODE, and the known phase relationship from that point forward. resulting data is produced on the output pins following the Note that if the converter is already properly synchronized, the FOURTH rising edge of ENCODE after the sample was taken DS pulse has no effect on the output data. This allows the con- (four pipeline delays). The output data are valid t after the PD verter to be continuously resynchronized by a pulse at 1/2 the rising edge of ENCODE, and remain valid until at least t after V ENCODE rate. This signal is often available within a system, as the next rising edge of ENCODE. it represents the master clock rate for the demultiplexed output The maximum clock rate is specified as 100 MSPS. This is data. Of course, a single DS signal may be used to synchronize recommended because the guaranteed output data valid time multiple A/D converters in a multichannel system. equals the Clock Period (1/f ) minus the Output Propagation S Delay (t ) plus the Output Valid Time (t ), which comes to PD V 4.8 ns at 100 MHz. This is about as fast as standard logic is able to capture the data with reasonable design margins. The AD9054A will operate faster in single-channel mode if you are able to capture the data. REV. D –13– AD9054A Applications that call for the AD9054A to be synchronized at In Figure 11, the converter is operating in Dual Port Mode, power-up or only periodically during calibration/reset (i.e., valid with data coming alternately out of Port A and Port B. The data is not required prior to synchronization), need only be figure illustrates how the output data may be aligned with an concerned with the timing of the falling edge of DS. The falling output latch to produce a 16-bit output at 1/2 the conversion edge of DS must satisfy the setup time defined by Figure 2 and clock rate. The Data Sync input must be properly exercised to the specification table. In this case the DS hold time specifica- time the A Port with the synchronizing latch. tion on the rising edge can be ignored. Applications that will continuously update the synchronization VREF OUT 0.1�F command need to treat the DS signal as a pulse and satisfy VREF IN timing requirements on both rising and falling edges. It is easiest A PORT AIN to consider the DS signal in this case to be a pulse train at one '573 1k� AD9054A half the encode rate, the positive pulse nominally bracketing the AIN VIN ENCODE falling edge on alternate cycles as shown in the tim- 0.1�F ing diagram (Figure 2b). Both the falling and rising edges of DS B PORT must satisfy minimum setup (t ) and hold (t ) times with SDS HDS DEMUX respect to the falling edges of ENCODE. This timing require- ment produces a tight timing window at higher encode rates. Synchronization by a single reset edge results in a simpler timing DS DS ENC ENC solution in many applications. For example, synchronization 0.1�F may be provided at the beginning of each graphics line or frame. DS NC The data are presented at the output of the AD9054A in a ping- CLOCK pong (alternating) fashion to optimize the performance of the '74 converter. It may be aligned for presentation as sixteen bits in parallel by adding a register stage to the output. DIVIDE BY 2 NC = NO CONNECT In Dual Channel Mode, the converted data is produced five clock cycles after the rising edge of ENCODE on which the sample is taken (five pipeline delays). Figure 11. Dual Port Mode—Aligned Output Data –14– REV. D AD9054A EVALUATION BOARD Voltage Reference The AD9054A evaluation board offers an easy way to test the The AD9054A has an internal 2.5 V voltage reference. An AD9054A. It provides dc biasing for the analog input, generates external reference may be employed instead. The evaluation the latch clocks for both full speed and demuxed modes, and board is configured for the internal reference. To use an external includes a reconstruction DAC. The board has several different reference, connect it to the (VREF) pin on the power connector modes of operation, and is shipped in the following configuration: and move jumper S102. • DC-Coupled Analog Input Single Port Mode • Demuxed Outputs Single Port Mode sets the AD9054A to produce data on every • Differential Clocks clock cycle on output port A only. To test in this mode, jumper • Internal Voltage Reference. S104 should be set to single channel and S106 and S107 must be set to F (for Full). The maximum speed in single port mode VREF EXT DC BIAS is 100 MSPS. S102 AIN S103 Dual Port Mode VREF OUT Dual Port or half-speed output mode sets the ADC to produce B PORT VREF IN '574 data alternately on Port A and Port B. In this mode, the reset 50� AIN function should be implemented. To test in this mode, set AD9054A jumper S104 to Dual Channel, and set S106 and S107 to D (for AIN RESET Dual Port). The maximum speed in this mode is 200 MSPS. BUTTON A PORT 5V '574 RESET D DEMUX RESET drives the AD9054A’s Data Sync (DS) pins. When D FF S104 operating in Single Port Mode, RESET is not used. In Dual- C Channel Mode it is needed for two reasons: to synchronize the CLK A DS ENC ENC DS S105 timing of Port A data and Port B data with a known clock edge, as described in the data sheet, and to synchronize the evaluation board’s latch clocks with the data coming out of the AD9054A. CLK B DAC ENC Reset can be driven in two ways: by pushing the reset button on the board, or externally, with a TTL pulse through connector 50� J5 or J6. ENC CLK A ENC CLOCKING CLK B ENC DAC Out The DAC output is a representation of the data on output Port 50� A only. Output Port B is not reconstructed. Troubleshooting Figure 12. PCB Block Diagram If the board does not seem to be working correctly, try the Analog Input following: The evaluation board accepts a 1 V input signal centered at • Check that all jumpers are in the correct position for the ground. The board’s input circuitry then biases this signal to desired mode of operation. 2.5 V in one of two ways: • Push the reset button. This will align the AD9054A’s data 1. DC-coupled through an AD9631 op amp; this is the mode in output with the half speed latch clocks. which it is shipped. Potentiometer R7 provides adjustment of the bias voltage. • Switch the jumper S105 from A-R to R-B or vice-versa, then push the reset button. In demuxed mode, this will have the 2. AC-coupled through C1. effect of inverting the half speed latch clocks. These two modes are selected by jumpers S101 and S103. For • At high encode rates, the evaluation board’s clock generation dc coupling, the S101 jumper is connected between the two left circuitry is sensitive to the 5 V digital power supply. At high pins and the S103 jumper is connected between the two lower encode rates, the 5 V digital power should be kept below pins. For ac coupling, the S101 jumper is connected between 5.2 V. This is an evaluation board sensitivity and not an the two right pins and the S103 jumper is connected between AD9054A sensitivity. the two upper pins. The AD9054A Evaluation Board is provided as a design example ENCODE for customers of Analog Devices, Inc. ADI makes no warranties, The AD9054A ENCODE input can be driven two ways: express, statutory, or implied, regarding merchantability or 1. Differential TTL, CMOS, or PECL; it is shipped in this fitness for a particular purpose. mode. 2. Single-ended TTL or CMOS. To use in this mode, remove R11, the 50 Ω chip resistor located next to the ENCODE input, and insert a 0.1 µF ceramic capacitor into the C5 slot. C5 is located between the ENC connector and the ENCODE input to the DUT and is marked on the back side of the board. In this mode, ENCODE is biased with internal resis- tors to 1.5 V, but it can be externally driven to any dc voltage. REV. D –15– AD9054A Figure 13. Evaluation Board Schematic –16– REV. D R6 R7 R8 1k� 2k� 2k� VREF S102 C2 R3 JUMPER 0.1�F 100� C3 3 U4 10�F C37 DRPF R21–R39 2 74F574DW H20SM J6 C35 U1 J5 1 100� 9 S103 12 0.1�F AD9631R 1 20 1D 1Q RST RESET JUMPER 8 13 33 23 3 12 2D 2Q R21 GND 7 14 6 3 VREF 3D 3Q 11 29 6 15 2 B1B 2 OUT 4D 4Q S101 R5 34 22 5 10 28 16 1 VREF IN B2B 10� DB3 5D 5Q JUMPER R2 R4 9 27 BNC 35 21 4 17 B3B 140� 140� GND GND DB2 6D 6Q 3 J1 36 20 3 8 26 18 VDD 7D 7Q B4B +5VA DB1 2 7 25 37 19 2 19 AIN GND B5B GND (LSB) DB0 8D 8Q 1 38 18 6 24 R1 AIN +5VA CK OE B6B UA1 VDD 5 23 39 17 49.9� R9 B7B AIN GND GND C1 AD9054ABST 11 1 40 16 4 22 100� GND GND GND B8B 0.1�F GND 41 15 +5VA VDD VDD +5VA 42 14 C36, C37, AND R17–R20 DEMUX (LSB) DA0 2 2 S104 43 13 U5 DRB NOT INSTALLED FOR DA1 DS JUMPER 44 12 74F574DW STANDARD OPERATION DS DA2 3 9 12 13 30 GND 1D 1Q B8A 2 8 13 14 31 ENC ENC 2D 2Q B7A +5V GND +5V 1 7 14 15 32 3D 3Q B6A +5VA B1 1 11 6 15 16 33 C4 R12 4 4D 4Q B5A BUTTON 5 16 17 34 1k� 0.1�F 5D 5Q B4A PR 2 5 4 17 18 35 +5V D Q 6D 6Q B3A 3 18 19 36 RST 7D 7Q B2A 3 6 2 19 20 37 C B1A Q 8D 8Q S105 CL CK OE U2 JUMPER 1 74F74 11 1 3 21 DRA 3 +5V R39 BNC 2 J2 1 ENC R10 49.9� C5 5PB 510 RP1 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 AD96685R BNC U3 –5.2V GND J4 3 12 BNC 22 DAC A J3 U8 10H125 28 OUT I OUT CLK 4 AD9760AR U7 2 ENC R16 U6 B 4 11 R11 3 49.9� 6 10H131 21 5 49.9� R15 S1 7 2 10H125 49.9� D1 Q1 27 24 23 19 18 17 16 15 U7 6 5 +5V 7 6 Q1 C6 R14 C8 3 R1 S107 0.1�F 2k� 10H125 0.1�F TB1 JUMPER 4 U7 10 1 3 12 VREF VREF 11 C7 2 2 S106 +5VA +5V ANALOG 0.1�F 3 1 JUMPER 10H125 –5.2V –5.2V +5V 4 3 U7 14 GND GROUND 13 5 2 15 +5V +5V DIGITAL 1 +5V C28 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 10�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F +5VA –5.2V C23 C24 C25 C26 C27 C29 C30 C31 C32 C33 C34 10�F 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 10�F 0.1�F 0.1�F 0.1�F 0.1�F GND GND +5VA VDD +5VA VDD GND GND VDD +5VA +5VA VDD GND GND GND GND VDD +5VA GND GND DA7 DA6 DB7 DA5 DB6 DA4 DB5 DA3 DB4 DB9 DVDD DB8 AVDD DB7 COMP2 DB6 COMP1 DB5 DB4 FSADJ DB3 REFIO DB2 DB1 REFLO DB0 SLEEP (LSB) AD9054A Figure 14. Assembly—Top View Figure 16. Conductors—Top View Figure 15. Assembly—Bottom View Figure 17. Conductors—Bottom View REV. D –17– AD9054A BILL OF MATERIALS GS00104 REV. D ITEM QTY PART NUMBER REFERENCE DESCRIPTION MFG/DISTRIBUTOR 11 30 GRM40Z5U104M050BL C1, C2, C4, C6–C8, 0.1 µF CER CHIP CAP 0805 TTI C10–C22, C24–C29, C31–C35 12 1 P10FBK-ND R5 10 Ω SURFACE MT RES 1206 DIGI-KEY 13 21 P100FBK-ND R3, R9, R21–R39 100 Ω SURFACE MT RES 1206 DIGI-KEY 14 4 T491C106M016AS C3, C9, C23, C30 10 µF TANTALUM CHIP CAP TTI 15 2 P140FBK-ND R2, R4 140 Ω SURFACE MT RES 1206 DIGI-KEY 16 1 P1KFBK-ND R12 1 kΩ SURFACE MT RES 1206 DIGI-KEY 17 3 P2KFBK-ND R6, R8, R14 2 kΩ SURFACE MT RES 1206 DIGI-KEY 18 1 3296W-102-ND R7 1k TRIM POT TOP ADJ, 25 TURN DIGI-KEY 19 1 K44-C37S-QJ J6 37P D CONN RT ANG PCMT FEM CENTURY ELEC 10 5 P49.9FBK-ND R1, R10, R11, 49.9 Ω SURFACE MT RES 1206 DIGI-KEY R15, R16 11 1 CSC06A-01-511G RP1 510 Ω 6P BUSED RES NETWORK TTI 12 1 51F54113 TB1 8291Z 3-PIN TERMINAL BLOCK NEWARK 13 1 51F54112 TB1 8291Z 2-PIN TERMINAL BLOCK NEWARK 14 4 AMP-227699-2 J1–J4 BNC COAX CONN PCMT 5 LEAD TIME ELEC 15 1 MC10H131P U6 DIP-16 DUAL D FLIP-FLOP HAMILTON/HALLMARK 16 1 MC10H125P U7 DIP-16 QUAD ECL TO TTL TRANS HAMILTON/HALLMARK 17 1 74F74SC-ND U2 SO-14 FAST TTL DUAL D FLIP-FLOP DIGI-KEY 18 1 TSW-120-08-G-S J5 HEADER STRIP 20P GOLD MALE SAMTEC ALT: 1/2 90F3987 J5 40P HEADER NEWARK 19 1 AD96685BR U3 HIGH SPEED COMP SOIC-16 ANALOG DEVICES, INC. 20 7 S90F9280 S101–S107 SHORTING JUMPER NEWARK 21 8 89F4700 S101–S107, GND 3-PIN HEADER (DIVIDE 1 OF THE NEWARK 8 FOR 3 GND HOLES) 22 2 MC74F574DW U4, U5 SO-20 OCTAL D TYPE FLIP-FLOP HAMILTON/HALLMARK 23 1 AD9631AR U1 SOIC-8 OP AMP ANALOG DEVICES, INC. 24 1 AD9760AR U8 10-BIT CMOS DAC SOIC-28 ANALOG DEVICES, INC. 25 1 AD9054ABST UA1 8-BIT ADC IN 44-LEAD LQFP ANALOG DEVICES, INC. 26 1 P8002SCT-ND B1 SURFACE MOUNT MOMENTARY DIGI-KEY PUSHBUTTON 27 4 90F1533 – BUMPON PROTECTIVE BUMPER NEWARK PARTS NOT ON BILL OF MATERIALS, AND NOT TO BE INSTALLED: C5, C36, C37, R17–R20. –18– REV. D AD9054A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Thin Quad Flatpack (LQFP) (ST-44) 0.063 (1.60) MAX 0.472 (12.00) BSC SQ 0.030 (0.75) 33 23 0.018 (0.45) 34 22 SEATING PLANE 0.394 (10.0) TOP VIEW (PINS DOWN) BSC SQ 44 12 1 11 0.006 (0.15) 0.002 (0.05) 0.031 (0.80) 0.018 (0.45) 0.057 (1.45) BSC 0.012 (0.30) 0.053 (1.35) REV. D –19– AD9054A–Revision History Location Page Data Sheet changed from REV. C to REV. D. Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 –20– REV. D PRINTED IN U.S.A. C00560–0–7/01(D)