ANALOG DEVICES AD9051

10-Bit, 60 MSPS a A/D Converter AD9051 FEATURES FUNCTIONAL BLOCK DIAGRAM 60 MSPS Sampling Rate 9.3 Effective Number of Bits at f = 10.3 MHz IN BWSEL 5V GND IN OUT 250 mW Total Power at 60 MSPS 5V Selectable Input Bandwidth of 50 MHz or 130 MHz REFERENCE AD9051 CIRCUITS On-Chip T/H and Voltage Reference Single 5 V Supply Voltage AINB T/H ADC 5 V or 3 V Logic I/O Compatible AIN Input Range and Output Coding Options Available 10 DECODE DAC SUM LOGIC AMP APPLICATIONS Medical Imaging ADC ENCODE TIMING Digital Communications Professional Video Instrumentation Set-Top Box GENERAL DESCRIPTION A 2.5 V reference is included onboard, or the user can provide The AD9051 is a complete 10-bit monolithic sampling analog- an external reference voltage for gain control or matching of to-digital converter (ADC) with an onboard track-and-hold and multiple devices. Fabricated on a state-of-the-art BiCMOS reference. The unit is designed for low cost, high performance process, the AD9051 is packaged in a space saving surface applications and requires only 5 V and an encode clock to mount package (SSOP) and is specified over the industrial tem- achieve 60 MSPS sample rates with 10-bit resolution. perature range (–40°C to +85°C). The encode clock is TTL compatible and the digital outputs are CMOS; both can operate with 5 V/3 V logic. The two-step architecture used in the AD9051 is optimized to provide the best dynamic performance available while maintaining low power consumption. C REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise 781/461-3113 2010 under any patent or patent rights of Analog Devices. Fax: © Analog Devices, Inc., AD9051BRS/ AD9051BRS-2V/ AD9051BRSZ AD9051BRSZ-2V 9.3 9.1 8.76 9.0 8.59 8.8 8.8 8.6 56.5 56.5 53.5 56 52.5 55 54 53 55.5 56.5 54.5 56.5 53.5 55.5 55 54 REV. C AD9051BRS/ AD9051BRS-2V/ AD9051BRSZ AD9051BRSZ-2V REV. C AD9051 ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Test Level V , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V D DD I. 100% production tested. Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V D Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V D II. 100% production tested at 25°C and sample tested at VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V D specified temperatures. Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA III. Sample tested only. Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C IV. Parameter is guaranteed by design and characterization Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C testing. Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C V. Parameter is a typical value only. *Stresses above those listed under Absolute Maximum Ratings may cause perma- VI. 100% production tested at 25°C; guaranteed by design and nent damage to the device. This is a stress rating only; functional operation of the characterization testing for industrial temperature range. device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND) OR Digital Output Analog Input Voltage Level (Out of Range) MSB... LSB 3.126 (3.50)* Positive Full Scale + 1 LSB 1 1111111111 2.5 Midscale 0 0111111111 1.874 (1.50)* Negative Full Scale – 1 LSB 1 0000000000 *(BRS-2V Version) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9051 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. C –4– REV. AD9051 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1, 6, 7, 12, 21, 23 GND Ground 2, 8, 11 V Analog 5 V Power Supply D 3 VREFOUT Internal Bandgap Voltage Reference (Nominally 2.5 V) 4 VREFIN Input to Reference Amplifier. Voltage reference for ADC is connected here. 5 BWSEL Bandwidth Select. NC = 130 MHz nominal. +V = 50 MHz nominal. D 9 AINB Complementary Analog Input Pin (Analog Input Bar) 10 AIN Analog Input Pin 13 ENCODE Encode Clock Input to ADC. Internal T/H is placed in hold mode (ADC is encoding) on rising edge of encode signal. 14 OR Out of Range Signal. Logic “0” when analog input is in nominal range. Logic “1” when analog input is out of nominal range. 15 D9 (MSB) Most Significant Bit of ADC Output 16–19 D8–D5 Digital Output Bits of ADC 20, 22 V Digital Output Power Supply (Only Used by Digital Outputs) DD 24–27 D4–D1 Digital Output Bits of ADC 28 D0 (LSB) Least Significant Bit of ADC Output PIN CONFIGURATION N N + 1 N + 2 N + 3 N + 4 N + 5 AIN 1 28 D0 (LSB) GND t A 2 27 V D1 D 3 VREFOUT 26 D2 ENCODE t t EH EL 4 VREFIN 25 D3 t PD 5 D4 BWSEL 24 DIGITAL 6 GND 23 GND N – 5 N – 4 N – 3 N – 2 N – 1 N OUTPUTS AD9051 7 V GND 22 DD TOP VIEW 8 V 21 GND D (Not to Scale) Figure 1. Timing Diagram 9 AINB 20 V DD 19 AIN 10 D5 V V D D 18 D6 V 11 D 17 GND 12 D7 12k� 12k� INPUT ENCODE 13 16 D8 BUFFER ENCODE AINB (PIN 9) 14 D9 (MSB) OR 15 (PIN 13) AIN (PIN 10) 12k� 12k� Analog Input Encode V (PINS 20, 22) DD V D +3V TO +5V D0–D9, OR VREF OUT (PIN 3) Output Stage VREF Figure 2. Equivalent Circuits C REV. –5– AD9051 0 255 250 –1 245 BWSEL DISABLED 240 –2 235 –3 230 BWSEL ENABLED –4 225 220 –5 215 –6 210 15 15 20 25 30 35 40 45 50 55 60 1 40 52 80 118 141 201 CLOCK RATE – MSPS ANALOG INPUT FREQUENCY – MHz TPC 1. Power Dissipation vs. Clock Rate TPC 4. ADC Gain vs. AIN Frequency 60 59 AIN = 10.3MHz 59 58.5 SNR @ 40MSPS ENCODE = 40MSPS 58 58 57 SINAD @ 40MSPS 57.5 56 ENCODE = 60MSPS 57 55 SINAD @ 60MSPS 54 56.5 SNR @ 60MSPS 53 56 52 55.5 51 55 50 0 10 20 30 40 50 60 70 80 90 –40 –20 0 25 45 65 85 FREQUENCY – MHz TEMPERATURE – �C TPC 2. SNR/SINAD vs. AIN Frequency TPC 5. SNR vs. Temperature –50 60 AIN = 10.3MHz 59 –55 2ND @ 60MSPS 58 –60 3RD @ 40MSPS 57 –65 56 –70 2ND @ 40MSPS 55 –75 3RD @ 60MSPS 54 –80 53 –85 52 –90 51 –95 50 –100 0 10 20 30 40 50 60 70 80 90 5 10 20 30 40 50 60 70 FREQUENCY – MHz ENCODE – MSPS TPC 3. Harmonics vs. AIN Frequency TPC 6. SNR vs. Clock Rate C –6– REV. DISSIPATION – mW dB SNR/SINAD – dB SNR – dB SNR – dB ADC GAIN – dB AD9051 0 0 AIN = 15.2MHz –10 AIN = 10.3MHz –10 ENCODE = 60MSPS ENCODE = 40MSPS SNR = 58.29dB SNR = 58.6dB –20 –20 SINAD = 57.23dB SINAD = 57.69dB –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30 0 2.5 5.0 7.5 10 12.5 15 17.5 20 FREQUENCY – MHz FREQUENCY – MHz TPC 7. FFT Plot 40 MSPS, 10.3 MHz TPC 10. FFT Plot 60 MSPS, 15.2 MHz 0 0 AIN = 21.7MHz –10 AIN = 15.2MHz –10 ENCODE = 60MSPS ENCODE = 40MSPS SNR = 57.76dB SNR = 58.47dB –20 –20 SINAD = 56.27dB SINAD = 57.04dB –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30 0 2.5 5.0 7.5 10 12.5 15 17.5 20 FREQUENCY – MHz FREQUENCY – MHz TPC 8. FFT Plot 40 MSPS, 15.2 MHz TPC 11. FFT Plot 60 MSPS, 21.7 MHz 0 0 AIN = 10.3MHz –10 AIN1 = 9.5MHz, –7dBFS –10 ENCODE = 60MSPS AIN2 = 9.9MHz, –7dBFS SNR = 58.15dB IMD = –65dBc –20 –20 SINAD = 57.25dB ENCODE = 60MSPS –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30 0 3.8 7.5 11.3 15.0 18.8 22.5 26.3 30 FREQUENCY – MHz FREQUENCY – MHz TPC 9. FFT Plot 60 MSPS, 10.3 MHz TPC 12. Two-Tone IMD C REV. –7– dB dB dB dB dB dB AD9051 1.2 6.5 3V RISING 1.0 6 0.8 5.5 5V FALLING 0.6 5 3V FALLING 0.4 5V RISING 4.5 0.2 0 4 0 10 20 30 40 50 60 –40 –20 0 25 45 65 85 ENCODE – MSPS TEMPERATURE – �C TPC 13. Gain vs. Clock Rate TPC 16. t vs. Temperature 3 V/5 V PD 2.51 16 2.50 14 2.49 12 2.48 10 V OUT 2.47 8 2.46 6 2.45 4 2.44 2 2.43 0 2.42 0 0.1 0.25 0.4 0.55 0.7 0.85 1 1.15 1.3 1.45 1.6 1.75 1.9 2.0 10 20 30 40 50 60 ENCODE – MSPS SOURCE CURRENT – mA TPC 14. Offset vs. Clock Rate TPC 17. Reference Load Regulation 60 80 58 70 56 SNR @ 40MSPS 60 54 SNR @ 60MSPS 50 52 50 40 48 30 46 20 44 10 42 0 40 25 30 35 40 45 50 55 60 65 70 75 512 513 514 515 516 517 518 DUTY CYCLE – % CODE TPC 15. SNR vs. Duty Cycle TPC 18. Midscale Histogram (Inputs Tied) C –8– REV. % GAIN ERROR SNR – dB OFFSET – mV REF VOLTAGE t – ns PD % OCCURRANCE AD9051 THEORY OF OPERATION 140� Refer to the block diagram on the front page. 5V 5V 140� The AD9051 employs a subranging architecture with digital V IN 10 error correction. This combination of design techniques ensures –0.625V TO AD9631 AD9051 true 10-bit accuracy at the digital outputs of the converter. +0.625V 9 At the input, the analog signal is buffered by a high speed 0.1�F 5V differential buffer and applied to a track-and-hold (T/H) that AD820 holds the analog value present when the unit is strobed with 1k� 1k� 0.1�F an ENCODE command. The conversion process begins on the rising edge of this pulse. The two stage architecture completes a coarse and then a fine conversion of the T/H output signal. Error correction and decode logic correct and align data from Figure 3. Single Supply, Single-Ended, DC-Coupled the two conversions and present the result as a 10-bit parallel AD9051 digital word. Output data are strobed on the rising edge of the ENCODE command. The subranging architecture results in 140� five pipeline delays for the output data. Refer to the AD9051 +5V Timing Diagram. 5V 140� 0.1�F V IN 10 –0.625V USING THE AD9051 AD9051 TO AD9631 +0.625V 3 V System 9 –5V 0.1�F The digital input and outputs of the AD9051 can be easily configured to directly interface to 3 V logic systems. The encode input (Pin 13) is TTL compatible with a logic threshold of Figure 4. Single-Ended, Capacitively-Coupled AD9051 1.5 V. This input is actually a CMOS stage (refer to Equivalent Encode Input Stage) with a TTL threshold, allowing operation 140� with TTL, CMOS and 3 V CMOS logic families. Using 3 V CMOS logic allows the user to drive the encode directly without +5V 5V 140� the need to translate to 5 V. This saves the user power and 0.1�F V IN T1-1T 10 board space. As with all high speed data converters, the clock –0.625V TO AD9631 50� AD9051 signal must be clean and jitter free to prevent the degradation of +0.625V dynamic performance. –5V 9 The AD9051 outputs can also directly interface to 3 V logic systems. The digital outputs are standard CMOS stages (refer Figure 5. Differentially Driven AD9051 Using Trans- to AD9051 Output Stage) with isolated supply pins (Pins 20, former Coupling 22 V ). By varying the voltage on the V pins, the digital DD DD The AD830 provides a unique method of providing dc level output levels vary respectively. By connecting Pins 20 and 22 to shift for the analog input. Using the AD830 allows a great deal the 3 V logic supply, the AD9051 will supply 3 V output of flexibility for adjusting offset and gain. Figure 6 shows the levels. Care should be taken to filter and isolate the output AD830 configured to drive the AD9051. The offset is provided supply of the AD9051 as noise could be coupled into the by the internal biasing of the AD9051 differential input (Pin 9). ADC, limiting performance. For more information regarding the AD830, see the AD830 Analog Input data sheet. The analog input of the AD9051 is a differential input buffer (refer to AD9051 Equivalent Analog Input). The differential +5V +15V 1 inputs are internally biased at 2.5 V, obviating the need for V IN 2 7 10 external biasing. Excellent performance is achieved whether the –0.625V 3 AD830 TO analog inputs are driven single-endedly or differentially (for 4 +0.625V AD9051 best dynamic performance, impedances at AIN and AINB 9 –5V should match). 0.1�F Figure 3 shows typical connections for the analog inputs when using the AD9051 in a dc-coupled system with single-ended signals. All components are powered from a single 5 V supply. Figure 6. Level-Shifting with the AD830 The AD820 is used to offset the ground referenced input signal to the level required by the AD9051. AC coupling of the analog inputs of the AD9051 is easily accomplished. Figure 4 shows capacitive coupling of a single- ended signal while Figure 5 shows transformer coupling differentially into the AD9051. C REV. –9– AD9051 Overdrive of the Analog Input Some applications may require greater accuracy, improved Special care was taken in the design of the analog input section temperature performance, or adjustment of the gain of the of the AD9051 to prevent damage and corruption of data when AD9051, which cannot be obtained by using the internal refer- the input is overdriven. The nominal input range is 1.875 V to ence. For these applications, an external 2.5 V reference can be 3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range compara- used to connect to Pin 4 of the AD9051. The VREFIN requires tors detect when the analog input signal is out of this range and 2 µA of drive current. the input buffer is clamped. The digital outputs are locked at The input range can be adjusted by varying the reference their maximum or minimum value (i.e., all “0” or all “1”). This voltage applied to the AD9051. No appreciable degradation precludes the digital outputs changing to an invalid value when in performance occurs when the reference is adjusted ±5%. the analog input is out of range. The full-scale range of the ADC tracks reference voltage The input is protected to one volt outside the power supply changes linearly. rails. For nominal power (5 V and ground), the analog input will not be damaged with signals from +5.5 V to –0.5 V. Timing The performance of the AD9051 is very insensitive to the duty cycle of the clock. Pulsewidth variations of as much as ±15% for encode rates of 40 MSPS and ±10% for encode rates of 60 MSPS will cause no degradation in performance. (See Figure 17, SNR vs. Duty Cycle.) The AD9051 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (t ) PD after the rising edge of the encode command (refer to Figure 1, Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce tran- sients within the AD9051; these transients can detract from the converter’s dynamic performance. Power Dissipation The power dissipation specification in the parameter table is measured under the following conditions: encode is 60 MSPS, analog input is –FS. As shown in Figure 3, the actual power dissipation varies based on these conditions. For instance, reducing the clock rate will reduce power as expected for CMOS-type devices. The loading determines the power dissipated in the output stages. The analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. Power dissipation increases as more data bits switch at faster rates. For instance, if the input is a dc signal that is out of range, no output bits will switch. This minimizes power in the output stages, but is not realistic from a usage standpoint. The dissipation in the output stages can be minimized by inter- facing the outputs to 3 V logic (refer to Using the AD9051, 3 V System). The lower output swings minimize power consumption 2 as follows: (1/2 C × V × Update Rate). LOAD DD Voltage Reference A stable and accurate 2.5 V voltage reference is built into the AD9051 (Pin 3, VREFOUT). In normal operation the internal reference is used by strapping together Pins 3 and 4 of the AD9051. The internal reference has 500 µA of extra drive cur- rent that can be used for other circuits. C –10– REV. AD9051 OUTLINE DIMENSIONS 10.50 10.20 9.90 28 15 5.60 5.30 8.20 5.00 7.80 7.40 1 14 0.25 1.85 0.09 2.00 MAX 1.75 1.65 8° 0.95 0.38 0.05 MIN SEATING 4° 0.75 0.22 PLANE COPLANARITY 0° 0.65 BSC 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 7.28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD9051BRS −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRS-2V −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSRL −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSZ −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSZRL −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSRL-2V −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSZ-2V −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSZRL-2V −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 1 Z = RoHS Compliant Part. REVISION HISTORY 11/10—Rev. B to Rev. C Changes to Specifications Section ................................................... 2 Deleted Evaluation Board Section ................................................ 10 Updated Outline Dimensions ........................................................ 11 Changes to Ordering Guide ........................................................... 11 7/01—Rev. A to Rev. B Edits to ABSOLUTE MAXIMUM RATINGS ............................... 4 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00558-0-11/10(C) REV. C –11– 060106-A