ANALOG DEVICES AD8842

8-Bit Octal, 4-Quadrant a Multiplying, CMOS TrimDAC AD8842 FEATURES FUNCTIONAL BLOCK DIAGRAM Low Cost Replaces 8 Potentiometers V A IN DECODED 50 kHz 4-Quadrant Multiplying Bandwidth ADDRESS Low Zero Output Error G V DD 8 X 8 8 8 DAC A Eight Individual Channels DAC VOUTA R 3-Wire Serial Input LOGIC LD E AD8842 500 kHz Update Data Loading Rate DATA G I 4 8 ±3 V Output Swing S V H IN T Midscale Preset, Zero Volts Out G E SERIAL SDI 8 R DAC H REGISTER S APPLICATIONS V H OUT CLK Automatic Adjustment Trimmer Replacement GND V SDO PR SS Vertical Deflection Amplitude Adjustment Waveform Generation and Modulation GENERAL DESCRIPTION The AD8842 consumes only 95 mW from ±5 V power supplies. The AD8842 provides eight general purpose digitally controlled For single 5 V supply applications consult the DAC-8841. The voltage adjustment devices. The TrimDAC® capability allows AD8842 is pin compatible with the 1 MHz multiplying band- replacement of the mechanical trimmer function in new designs. width DAC8840. The AD8842 is available in 24-pin plastic The AD8842 is ideal for ac or dc gain control of up to 50 kHz DIP and surface mount SOL-24 packages. bandwidth signals. The four-quadrant multiplying capability is useful for signal inversion and modulation often found in video RR vertical deflection circuitry. V IN Internally the AD8842 contains eight voltage output digital-to- analog converters, each with separate voltage inputs. A new V OUT current conveyor amplifier design performs the four-quadrant multiplying function with a single amplifier at the output of the current steering digital-to-analog converter. This approach of- V = V • (D/128 – 1) fers an improved constant input resistance performance versus OUT IN previous voltage switched DACs used in TrimDAC circuits, eliminating the need for additional input buffer amplifiers. Figure 1. Functional Circuit of One 4-Quadrant Each DAC has its own DAC register that holds its output state. Multiplying Channel These DAC registers are updated from an internal serial-to- parallel shift register that is loaded from a standard 3-wire serial CURRENT CONVEYOR AMPLIFIER input digital interface. Twelve data bits make up the data word V IN REF V OUT clocked into the serial input register. This data word is decoded V D IN I1 = V (D/128–1) IN 256 R where the first 4 bits determine the address of the DAC register I2 V R (1- D) IN to be loaded with the last 8 bits of data. A serial data output pin 256 R at the opposite end of the serial register allows simple daisy R chaining in multiple DAC applications without additional exter- nal decoding logic. TrimDAC is a registered trademark of Analog Devices, Inc. Figure 2. Actual Current Conveyor Implementation of The current conveyor amplifier is a patented circuit belonging to Analog Multiplying DAC Channel Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: Fax: 781/329-4700 781/461-3113 AD8842–SPECIFICATIONS (V = +5 V, V = –5 V, All V x = +3 V, T = –40°C to +85°C, unless otherwise noted.) ELECTRICAL CHARACTERISTICS DD SS IN A Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H Resolution N 8 Bits Integral Nonlinearity Error INL ±0.2 ±1 LSB Differential Nonlinearity DNL All Devices Monotonic ±0.4 ±1 LSB Full-Scale Gain Error G 2 LSB FSE PR = 0, Sets D = 80 525 mV Output Offset V BZE H Output Offset Drift TCV PR = 0, Sets D = 80 5 μV/°C BZ H VOLTAGE INPUTS—Applies to All Inputs V x IN 1 Input Voltage Range IVR ±3 ±4V 12 19 kΩ Input Resistance R IN Input Capacitance C 9pF IN DAC OUTPUTS—Applies to All Outputs V x OUT 1 OVR R = 10 kΩ±3±4V Voltage Range L Output Current I ΔV < 1.5 LSB ±3mA OUT OUT Capacitive Load C No Oscillation 500 pF L DYNAMIC PERFORMANCE—Applies to All DACs 1 Full Power Gain Bandwidth GBW V x = ±3 V , R = 2 kΩ, C = 10 pF 10 50 kHz IN P L L Slew Rate Measured 10% to 90% Positive SR+ ΔV x = +5.5 V 0.5 1.0 V/μs OUT x = –5.5 V 1.0 1.8 V/μs Negative SR– ΔV OUT Total Harmonic Distortion THD V x = 4 V p-p, D = FF , f = 1 kHz, 0.01 % IN H = 80 kHz, R = 1 kΩ f LPF L Spot Noise Voltage e f = 1kHz, V = 0 V 78 nV/√Hz N IN ±1 LSB Error Band, D = 00 to FF 2.9 μs Output Settling Time t S H H D = FF to 00 5.4 μs H H Measured Between Adjacent Channel-to-Channel Crosstalk C T Channels, f = 100 kHz 72 dB Digital Feedthrough Q V x = 0 V, D = 0 to 255 5 nV-s IN 10 POWER SUPPLIES Positive Supply Current I PR = 0 V 10 14 mA DD Negative Supply Current I PR = 0 V 9 13 mA SS 2 P 95 135 mW Power Dissipation DISS Power Supply Rejection PSRR PR = 0 V, ΔV = ± 5% 0.0001 0.01 %/% DD Power Supply Range PSR V , |V | 4.75 5.00 5.25 V DD SS DIGITAL INPUTS Logic High V 2.4 V IH 0.8 V Logic Low V IL Input Current I ±10 μA L 7pF Input Capacitance C IL Input Coding Offset Binary DIGITAL OUTPUT Logic High V I = –0.4 mA 3.5 V OH OH Logic Low V I = 1.6 mA 0.4 V OL OL 1 TIMING SPECIFICATIONS Input Clock Pulse Width t , t 60 ns CH CL 40 ns Data Setup Time t DS Data Hold Time t 20 ns DH 80 ns CLK to SDO Propagation Delay t PD DAC Register Load Pulse Width t 70 ns LD 50 ns Preset Pulse Width t PR Clock Edge to Load Time t 30 ns CKLD Load Edge to Next Clock Edge t 60 ns LDCK NOTES 1 Guaranteed by design, not subject to production test. 2 Calculated limit = 5 V × (I + I ). DD SS Specifications subject to change without notice. –2– REV. A AD8842 1 SDI A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 CLK 0 DAC REGISTER LOAD 1 LD 0 +3V V OUT 0V DETAIL SERIAL DATA INPUT TIMING (PR = “1”) 1 SDI Ax or Dx (DATA IN) 0 t DS t DH 1 SDO (DATA OUT) 0 t t PD CH 1 CLK 0 t t t t CL CKLD LD LDCK 1 LD 0 t S –1 LSB +3V V OUT 0V–1 LSB ERROR BAND PRESET TIMING t PR 1 PR 0 t S –1 LSB +3V V OUT 0V–1 LSB ERROR BAND Figure 3. Timing Diagram ABSOLUTE MAXIMUM RATINGS (T = +25°C unless otherwise noted) A V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V DD V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V SS x to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V , V V IN DD SS V x to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V , V OUT DD SS Short Circuit I x to GND . . . . . . . . . . . . . . . . . Continuous OUT , 0 V Digital Input & Output Voltage to GND . . . . . . . . . . V DD Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Max) . . . . . . . . . +150°C Maximum Junction Temperature (T J Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Max–T )/θ Package Power Dissipation . . . . . . . . . . . . . . . (T J A JA Thermal Resistance θ JA, SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8842 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– V C 1 24 V D OUT OUT V B 2 23 V C OUT IN V A 3 22 V D OUT IN V B IN 4 21 V DD 5 20 SDI V A IN AD8842 GND 6 19 V SS TOP VIEW 7 18 SDO PR (Not to Scale) V E 8 17 CLK IN V F 9 16 LD IN V E 10 15 V H OUT IN V F 1 11 1 14 V G OUT IN V G 12 13 V H OUT OUT AD8842 Table I. Serial Input Decode Table LAST FIRST LSB MSB LSB MSB D1 D2 D3 D4 D5 D6 A1 A2 D0 D7 A0 A3 DATA ADDRESS MSB LSB A3 A2 A1 A0 DAC UPDATED 0 0 0 0 NO OPERATION 0 0 0 1 DAC A 0 0 1 0 DAC B 0 0 1 1 DAC C 0 1 0 0 DAC D • • • 1 0 0 0 DAC H 1 0 0 1 NO OPERATION • • • 1 1 1 1 NO OPERATION MSB LSB DAC OUTPUT VOLTAGE D7 D6 D5 D4 D3 D2 D1 D0 V = (D/128 –1) x V OUT IN 0 0 0 0 0 0 0 0 –V IN 0 0 0 0 0 0 0 1 (1/128–1) x V IN • • • 0 1 1 1 1 1 1 1 (127/128–1) x V IN 1 0 0 0 0 0 0 0 (128/128–1) x V = 0V; (PRESET VALUE) IN 1 0 0 0 0 0 0 1 (129/128–1) x V IN • • • 1 1 1 1 1 1 1 0 (254/128–1) x V IN 1 1 1 1 1 1 1 1 (255/128–1) x V » V IN IN Table II. Input Logic Control Truth Table CLK LD PR Input Shift Register Operation L L H No Operation ↑ L H Shift One Bit in from SDI (Pin 20), Shift One Bit* Out from SDO (Pin 18) X L L All DAC Registers = 80 H X Η H Load Serial Register Data into DAC(X) Register X H X Serial Data Input Register Loading Disabled *Data shifted into the SDI pin appears twelve clocks later at the SDO pin. REV. A –5– AD8842–Typical Performance Characteristics 0.4 8 +1/2 DACs A, B, C, D SUPERIMPOSED 0.3 V X = +3V IN T = +125 °C A 6 0 0.2 TA = +25 °C 4 0.1 –1/2 T = +25°C 2 A V = +5V DD 0 0 V = – 5V SS V X = +3V –2 IN +1/2 –0.1 VINX = –3V –4 –0.2 T = –55 °C V = +5V 0 A DD –8 V = –5V SS DACs E, F, G, H SUPERIMPOSED V = +4.75V DD –0.3 –1/2 DAC A V X = +3V IN –10 VSS = –4.75V –0.4 0 64 128 192 256 0 64 128 192 256 –75 –50 –25 0 25 50 75 100 125 DIGITAL INPUT CODE – Decimal DIGITAL INPUT CODE – Decimal TEMPERATURE – °C Figure 4. Linearity Error vs. Figure 5. Linearity Error vs. Figure 6. V Half Scale (80 ) OUT H Digital Code Digital Code vs. Temperature vs. Temperature 21 100 4 W V = +3V V = +4Vp-p IN IN V = +4.75V DD f = 80kHz LPF V = –4.75V SS 20 10 CODE = FF H AVG +2s DV = –3VmIN 3 19 1 AVG SR+ 2 18 0.1 AVG –2s SR– 1 17 0.01 R = 2kW L V = +4.75V DD V = –4.75V SS 0.001 16 0 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 10 100 1k 10k 100k 25 50 75 100 125 TEMPERATURE – °C FREQUENCY – Hz TEMPERATURE – °C Figure 9. V Slew Rate Figure 8. Total Harmonic Distortion OUT Figure 7. Input Resistance (V ) IN vs. Temperature vs. Frequency vs. Temperature 1 GAIN T = +25°C A –FS INPUT A 0 0 dB V = 0V V A = 100mV IN OUTPUT B IN pp –10 15 V B = 0V 0.8 0 IN +FS T = +25°C A PHASE –20 30 –45m CODE = ALL ONES –30 45 0.6 –90 –40 60 –135 75 0.4 –180 PHASE 90 –225 CODE = ALL ZEROS 0.2 105 –270 V = – 100mV IN 120 –315 T = +25°C A 135 0 –360 10k 100k 1M 10M 10k 10M 1k 10 100k 1M 100 1k 10k 100k FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz Figure 11. DAC Crosstalk Figure 12. Voltage Noise Density Figure 10. Gain and Phase vs. Frequency (Code = 00 or FF ) vs. Frequency vs. Frequency H H A –6– REV. PHASE – Degrees LINEARITY ERROR – LSB REFERENCE INPUT RESISTANCE – k GAIN – dB TOTAL HARMONIC DISTORTION – % LINEARITY ERROR – LSB CROSSTALK – dB e – NOISE VOLTAGE ( V/√Hz) V HALF SCALE – mV n OUT V – SLEW RATE – V/ s OUT AD8842 5ms 5ms 5V 100 100 100 90 90 90 10 10 10 0% 0% 0% 2V 2V 5mm5 s S 2V 5ms Figure 16. Settling Time—Upper Trace LD @ 5 V/Div, Figure 13. Pulse Response—Upper Trace V @ 2 V/Div IN @ 2 V/Div Lower Trace V Lower Trace V @2 V/Div OUT OUT 10mV 5V 5ms 5ms 100 100 100 90 90 90 10 10 10 0% 0% 0% 50mV 2V 500ns 50ns 5mS to 7F , Figure 17. Digital Feedthrough—V @ 10 mV/Div, Figure 14. Worst Case 1 LSB Step Change Code 80 H H OUT Upper Trace LD @ 5 V/Div, Lower Trace V @ 50 mV/Div V = 0 V; Code 7F to 80 OUT IN H H 5V 5ms 5ms 100 100 100 90 90 90 10 10 10 0% 0% 0% 5mV 2V 5m50ns S 5mV 2ms Figure 15. Crosstalk—V @ 5 mV/Div Figure 18. Clock Feedthrough—V @ 5 mV/Div OUT OUT REV. A –7– AD8842 80 2V –3dB FREQUENCY 60 100 90 40 20 0 –20 10 0% –40 2V 20ms 100 mVp-p INPUT AMPLITUDE –80 –100 0 1 2 3 4 5 FREQUENCY – MHz Figure 19. 10 kHz Sawtooth Waveform, Figure 20. AC Sweep Frequency 100 mV p-p Amplitude Upper Trace V , Lower Trace V IN OUT Response 12 –3dB FREQUENCY + PSRR 300 40 I @ V = +6V DD DD 11 AND V = –5V SS 200 30 100 10 I @ V = +4V DD DD 0 AND V = –5V SS 20 –PSRR 9 –100 –I @ V = +5V SS DD + PSRR: V = +5V–250mV –200 AND V = –4V OR –6V DD SS 10 –PSRR: V = –5V–250mV 8 SS 500 mVp-p INPUT AMPLITUDE –300 V X = +3V IN –400 0 7 0 1 2 3 4 5 100 1k 10k 100k 1M –75 –50 –25 0 25 50 75 100 125 FREQUENCY – MHz FREQUENCY – Hz TEMPERATURE – °C Figure 21. AC Sweep Frequency Figure 23. PSRR vs. Frequency Figure 22. Supply Current vs. 500 mV p-p Amplitude Response Voltage and Temperature 6 24 V = 100mV V = +3V IN AC 5 IN T = +25°C A 15 12 V = +5V DD 4 SHORT CIRCUIT DATA = ŞŞ V = –5V H SS 10 3 0 CURRENT CŞ CODE = 80 H H LIMITING 2 AŞ H 5 –12 9Ş H 1 c 88 + 2sH 0 0 –24 84 H c–1 82 H –36 –5 81 H –2 c– 2s 80 H –3 –48 –10 T = +25°C A SHORT CIRCUIT –4 V = +5V DD –60 CURRENT –15 V = –5V –5 SS LIMITING –72 –6 –4 –3 –2 –1 0 1 2 3 4 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 V X – Volts OUT FREQUENCY – Hz T = HOURS OF OPERATION AT 150°C Figure 24. Gain (V /V ) and Figure 26. Output Voltage Drift Figure 25. Short Circuit Limit OUT IN Feedthrough vs. Frequency Accelerated by Burn-In Output Current vs. Voltage –8– REV. A GAIN – dB OUTPUT AMPLITUDE – mV I – mA OUT SUPPLY CURRENT – mA OUTPUT AMPLITUDE – mV POWER SUPPLY REJECTION – dB HALF SCALE OFFSET – mV AD8842 CIRCUIT OPERATION can be activated at any time to force the DAC registers to the The AD8842 is a general purpose 8-channel ac or dc signal- half-scale code 80 . This is generally the most convenient place H to start general purpose adjustment procedures. level adjustment device designed to replace potentiometers used in the three-terminal connection mode. Eight independent Achieving 4-Quadrant Multiplying with a Current Conveyor channels of programmable signal level control are available in Amplifier this 24-pin package device. The outputs are completely buffered The traditional current output CMOS digital-to-analog con- providing up to 3 mA of output drive-current to drive external verter requires two amplifiers to perform the current-to-voltage loads. The functional equivalent DAC and amplifier combina- translation and the half-scale offset to achieve four-quadrant tion shown in Figure 27 produces four-quadrant multiplication multiplying capability. The circuit shown in Figure 28 shows times the digital input control of the signal inputs applied to V IN one such traditional connection. word. In addition the AD8842 provides a 50 kHz full power R/2 bandwidth in each four-quadrant multiplying channel. Operat- ing from plus and minus 5 V power supplies, analog inputs and A1 outputs of ±3 V are easily accommodated. I 1 RR REF R/2 V IN V IN CURRENT OUT R DAC V OUT GND A2 V V DAC I O 2 V = D/256 · V DAC IN V = 2 · V – V OUT DAC IN Figure 28. One Traditional Technique to Achieve Four- = 2 (D/256) · V – V IN IN Quadrant Multiplying with a Complementary Current = (D/128 – 1) · V IN Output DAC AD8842 INPUT-OUTPUT VOLTAGE RANGE A single new current conveyor amplifier design emulates ampli- fiers A1 and A2 shown in Figure 28. Figure 29 shows the con- nection and equations that define this new circuit that achieves 4 D = FFH four-quadrant multiplication with only one amplifier. 2 D = C0H D = 80H 0 CURRENT CONVEYOR V IN AMPLIFIER REF D = 40H V D REF I 1 V X 256 OUT –2 R D = 00H I V (1- D) 2 R REF V 256 R OUT = V (D/128–1) –4 IN R –4 –2 0 24 V – Volts IN V = V (D/128 – 1), WHERE D = 0 TO 255 OUT IN Figure 29. Current Conveyor Amplifier Figure 27. Functional Equivalent Circuit to the AD8842 Results in a 4-Quadrant Multiplying Channel Using the equations given in Figure 29 one can calculate the final output equation as follows: In order to simplify use with a controlling microprocessor a PCB space saving three-wire serial data interface was chosen. This interface can be easily adapted to almost all microcom-  V   V   D  ±D IN IN V =±1± ×   × × R ± × R O     puter and microprocessor systems. A clock (CLK), serial data  256  R 256 R     input (SDI) and a load (LD) strobe pins make up the three-wire interface. The 12-bit input data word used to change the value of the internal DAC registers contains a 4-bit address and 8-bits   D D of data. Using this word combination any DAC register can be ±1 V + ×V   IN IN  256  256 changed at a given time without disturbing the other channels. A serial data output SDO pin simplifies cascading multiple  2D  = ±1 V   IN AD8842s without adding address decoder chips to the system.   256 PR pin forces During system power up a logic low on the preset  D  = ±1 V   which in turn forces all the buffer am- IN all DAC registers to 80 H  128  PR plifier outputs to zero volts. This asynchronous input pin REV. A –9– V – Volts OUT AD8842 tance. The amplifier output stage can handle shorts to GND; ADJUSTING AC OR DC SIGNAL LEVELS however, care should be taken to avoid continuous short circuit The four-quadrant multiplication operation of the AD8842 is operation. shown in Figure 27. For dc operation the equation describing the relationship between V , digital inputs and V is: IN OUT The low output impedance of the buffers minimizes crosstalk between analog input channels. A graph (Figure 11) of analog V (D) = (D/128-1) × V (1) OUT IN crosstalk between channels is provided in the typical perfor- where D is a decimal number between 0 and 255 mance characteristics section. At 100 kHz 70 dB of channel-to- The actual output voltages generated with a fixed 3 V dc input channel isolation exists. It is recommended to use good circuit applied to V are summarized in this table. IN layout practice such as guard traces between analog channels and power supply bypass capacitors. A 0.01 μF ceramic in paral- Table III. lel with a 1 μF–10 μF tantalum capacitor provides a good power supply bypass for most frequencies encountered. Decimal Comments Input (D) V (D) (V = 3 V) OUT IN DIGITAL INTERFACING The four digital input pins (CLK, SDI, LD, PR) of the AD8842 0 –3.00 V Inverted FS were designed for TTL and 5 V CMOS logic compatibility. The 1 –2.98 SDO output pin offers good fanout in CMOS logic applications 127 –0.02 and can easily drive several AD8842s. 128 0.00 Zero Output 129 0.02 The Logic Contro Input Truth Table II describes how to shift 254 2.95 data into the internal 12-bit serial input register. Note that the 255 2.98 Full Scale (FS) CLK is a positive-edge sensitive input. If mechanical switches are used for breadboard evaluation, they should be debounced Notice that the output polarity is the same as the input polarity by a flipflop or other suitable means. The basic three-wire serial when the DAC register is loaded with 255 (in binary = all ones). data interface setup is shown in Figure 30. Also note that the output does not exactly equal the input volt- age. This is a result of the R-2R ladder DAC architecture cho- ZERO VOLTAGE 7 21 +5V PR sen. When the DAC register is loaded with 0, the output OUTPUT PRESET polarity is inverted and exactly equals the magnitude of the in- AD8842 . The actual voltage measured when setting up a put voltage V IN 20 SDI DAC in this example will vary within the ±1 LSB linearity error SERIAL DATA specification of the AD8842. The calculated voltage error would 6 be ±0.023 V (= ±3 V/128). CLOCK 17 CLK is an ac signal such as a sine wave, then we can use Equa- If V IN tion 2 to describe circuit performance. (t, D) = (D/128-1) × A sin (ωt) (2) 16 19 V –5V OUT LOAD STROBE LD ω = 2 πf, A = sine wave amplitude, and D = decimal where input code. Figure 30. Basic Three-Wire Serial Interface This transfer characteristic Equation 2 lends itself to amplitude The required address plus data input format is defined in the se- . When the DAC is and phase control of the incoming signal V IN rial input decode Table I. Note there are 8 address states that loaded with all zeros, the output sine wave is shifted by 180° result in no operation (NOP) or activity in the AD8842 when with respect to the input sine wave. This powerful multiplying the positive edge triggered load-strobe (LD) is activated. This capability can be used for a wide variety of modulation, wave- NOP can be used in cascaded applications where only one DAC form adjustment and amplitude control. out of several packages needs updating. The packages not re- quiring data changes would receive the NOP address, that is, all SIGNAL INPUTS (V A, B, C, D, E, F, G, H) IN zeros. It takes 12 clocks on the CLK pin to fully load the serial- The eight independent V inputs have a constant input- IN input shift-register. Data on the SDI input pin is subject to the resistance nominal value of 19 kΩ as specified in the electrical timing diagram (Figure 3) data setup and data hold time re- characteristics table. These signal-inputs are designed to receive quirements. After the twelfth clock pulse the processor needs to not only dc, but ac input voltages. The signal-input voltage activate the LD strobe to have the AD8842 decode the serial- range can operate to within one volt of either supply. That is, register contents and update the target DAC register with the 8- the operating input-voltage-range is: bit data word. This needs to be done before the thirteenth + 1 V < V x < (V – 1 V) (3) V SS IN DD positive clock edge. The timing requirements are provided in the electrical characteristic table and in the Figure 3 timing dia- DAC OUTPUTS (V A, B, C, D, E, F, G, H) OUT gram. After twelve clock edges, data initially loaded into the The eight D/A converter outputs are fully buffered by the shift register at SDI appears at the shift register output SDO. A AD8842’s internal amplifier. This amplifier is designed to drive multiple package interface circuit is shown in Figure 31. In this up to 1 kΩ loads in parallel with 100 pF. However, in order to topology all the devices are clocked with the new data; however, minimize internal device power consumption, it is recom- only the decoded package address signal updates the target mended whenever possible to use larger values of load resis- package LD strobe which is being used as a chip select. –10– REV. A AD8842 CLOCK Figure 32 shows a three-wire interface for a single AD8842 that LD easily cascades for multiple packages. This circuit topology often AD8842 CLK called daisy chaining requires preformating all the serial data for #1 DATA SDI each package in the chain. In the case of the 3 packages shown a 36 bit data word must be completely clocked into all the ADDRESSS CODED AD8842 serial data input registers then the LD strobe would DECODE PACKAGE LD transfer the data bits into the DAC registers updating one DAC ADDRESS • AD8842 • in each package. CLK • #2 EN SDI mC • WR DATA • PA0 • CLOCK LD PA1 LD AD8842 CLK PA2 #N SDI SDI DAC A V OU CLK ANALOG CONNECTIONS OMITTED FOR CLARITY • AD8842 #1 • • Figure 31. Addressing Multiple AD8842 Packages V LD O SDO DAC H There is some digital feedthrough from the digital input pins. Operating the clock only when the DAC registers require updat- SDI DAC A ing minimizes the effect of the digital feedthrough on the analog CLK signal channels. Measurements of DAC switch feedthrough AD8842 #2 shown in the electrical characteristics table were accomplished • by grounding the V x inputs and cycling the data codes be- IN LD tween all zeros and all ones. Under this condition 5 nV-s of SDO DAC H feedthrough was measured on the output of the switched DAC channel. An adjacent channel measured less than 1 nV-s of digi- SDI DAC A tal crosstalk. The digital feedthrough and crosstalk photographs CLK shown in the typical performance characteristics section display AD8842 #3 • these characteristics (Figures 15 and 17). LD SDO DAC H Figure 32. Three-Wire Interface Updates Multiple AD8842s REV. A –11– AD8842 OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 12 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) MAX 0.210 (5.33) 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) MIN 0.130 (3.30) GAUGE PLANE 0.014 (0.36) 0.115 (2.92) SEATING 0.010 (0.25) PLANE 0.008 (0.20) 0.022 (0.56) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 33. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 12 10.00 (0.3937) 45° 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 1.27 (0.0500) 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 34. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) –12– REV. A 0.75 (0.0295) 5 (0.0 0.2 098) 071006-A 12-09-2010-A AD8842 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8842AN −40°C to +85°C 24-Lead PDIP N-24-1 AD8842ANZ −40°C to +85°C 24-Lead PDIP N-24-1 AD8842AR −40°C to +85°C 24-Lead SOIC_W RW-24 AD8842AR-REEL −40°C to +85°C 24-Lead SOIC_W RW-24 AD8842ARZ −40°C to +85°C 24-Lead SOIC_W RW-24 AD8842ARZ-REEL −40°C to +85°C 24-Lead SOIC_W RW-24 1 Z = RoHS Compliant Part. REVISION HISTORY 10/11—Rev. 0 to Rev. A Changes to Pin 13 Mnemonic ......................................................... 4 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 13 4/94—Revision 0: Initial Version ©1994–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01904-0-10/11(A) REV. A –13–