ANALOG DEVICES AD8801

Octal 8-Bit TrimDAC a with Power Shutdown AD8801/AD8803 FEATURES FUNCTIONAL BLOCK DIAGRAM Low Cost (DACs 2–7 Omitted for Clarity) Replaces Eight Potentiometers V V REFH REFL Eight Individually Programmable Outputs Three-Wire Serial Input AD8801/AD8803 V Power Shutdown ≤ 25 mW Including I and I REFH DD REF 8 8-BIT V VDD DAC 1 OUT O1 LATCH Midscale Preset, AD8801 V REFL Separate V Range Setting, AD8803 REFL CK RS GND 8 +3 V to +5 V Single Supply Operation 1 DAC SELECT . APPLICATIONS 8 . ADDRESS Automatic Adjustment 3 Trimmer Potentiometer Replacement . Video and Audio Equipment Gain and Offset Adjustment 11-BIT . SERIAL 8 Portable and Battery Operated Equipment LATCH . SDI D . RS CK CLK V 8-BIT REFH 88 CS V LATCH DAC 8 OUT O8 GENERAL DESCRIPTION V REFL CK RS The AD8801/AD8803 provides eight digitally controlled dc 8 ® voltage outputs. This potentiometer divider TrimDAC allows replacement of the mechanical trimmer function in new designs. RS SHDN The AD8801/AD8803 is ideal for dc voltage adjustment applications. Easily programmed by serial interfaced microcontroller ports, the AD8801 with its midscale preset is ideal for potentiometer Internally the AD8801/AD8803 contain eight voltage output replacement where adjustments start at a nominal value. Appli- digital-to-analog converters, sharing a common reference volt- cations such as gain control of video amplifiers, voltage con- age input. trolled frequencies and bandwidths in video equipment, Each DAC has its own DAC register that holds its output state. geometric correction and automatic adjustment in CRT com- These DAC registers are updated from an internal serial-to-par- puter graphic displays are a few of the many applications ideally allel shift register that is loaded from a standard three-wire serial suited for these parts. The AD8803 provides independent con- input digital interface. Eleven data bits make up the data word trol of both the top and bottom end of the potentiometer divider clocked into the serial input register. This data word is decoded allowing a separate zero-scale voltage setting determined by the where the first 3 bits determine the address of the DAC register V pin. This is helpful for maximizing the resolution of de- REFL to be loaded with the last 8 bits of data. The AD8801/AD8803 vices with a limited allowable voltage control range. consumes only 5 μA from 5 V power supplies. In addition, in shutdown mode reference input current consumption is also re- duced to 5 μA while saving the DAC latch settings for use after return to normal operation. The AD8801/AD8803 is available in 16-pin plastic DIP and the 1.5 mm height SO-16 surface mount packages. See the AD8802/AD8804 for a twelve channel version of this product. TrimDAC is a registered trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1995 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 (V = +3 V 6 10% or +5 V 6 10%, V = +V , V = 0 V, –408C DD REFH DD REFL ≤ T ≤ +858C unless otherwise noted) A AD8801/AD8803–SPECIFICATIONS 1 Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACY Specifications Apply to All DACs Resolution N 8 Bits Integral Nonlinearity Error INL –1.5 ±1/2 +1.5 LSB Differential Nonlinearity DNL Guaranteed Monotonic –1 ±1/4 +1 LSB Full-Scale Error G –4 –2.8 +0.5 LSB FSE Zero-Code Error V –0.5 ±0.1 +0.5 LSB ZSE DAC Output Resistance R 35 8 kΩ OUT Output Resistance Match ΔR/R 1% O REFERENCE INPUT 2 Voltage Range V 0V V REFH DD V Pin Available on AD8803 Only 0 V V REFL DD Input Resistance R Digital Inputs = 55 , V = V 2kΩ REFH H REFH DD 3 Reference Input Capacitance C Digital Inputs All Zeros 25 pF REF0 C Digital Inputs All Ones 25 pF REF1 DIGITAL INPUTS Logic High V V = +5 V 2.4 V IH DD Logic Low V V = +5 V 0.8 V IL DD Logic High V V = +3 V 2.1 V IH DD Logic Low V V = +3 V 0.6 V IL DD Input Current I V = 0 V or +5 V ±1 μA IL IN 3 Input Capacitance C 5pF IL 4 POWER SUPPLIES Power Supply Range V Range 2.7 5.5 V DD Supply Current (CMOS) I V = V or V = 0 V 0.01 5 μA DD IH DD IL Supply Current (TTL) I V = 2.4 V or V = 0.8 V, V = +5.5 V 1 4 mA DD IH IL DD Shutdown Current I SHDN = 0 0.01 5 μA REFH Power Dissipation P V = V or V = 0 V, V = +5.5 V 27.5 μW DISS IH DD IL DD Power Supply Sensitivity PSRR V = 5 V ± 10%, V = +4.5 V 0.001 0.002 %/% DD REFH Power Supply Sensitivity PSRR V = 3 V ± 10%, V = +2.7 V 0.01 %/% DD REFH 3 DYNAMIC PERFORMANCE V Settling Time (Positive or Negative) t ±1/2 LSB Error Band 0.6 μs OUT S Crosstalk CT See Note 5, f = 100 kHz 50 dB 3, 6 SWITCHING CHARACTERISTICS Input Clock Pulse Width t , t Clock Level High or Low 15 ns CH CL Data Setup Time t 5ns DS Data Hold Time t 5ns DH CS Setup Time t 10 ns CSS CS High Pulse Width t 10 ns CSW Reset Pulse Width t 60 ns RS CLK Rise to CS Rise Hold Time t 15 ns CSH CS Rise to Next Rising Clock t 10 ns CS1 NOTES 1 Typical values represent average readings measured at +25°C. 2 V can be any value between GND and V , for the AD8803 V can be any value between GND and V . REFH DD REFL DD 3 Guaranteed by design and not subject to production test. 4 Digital Input voltages V = 0 V or V for CMOS condition. DAC outputs unloaded. P is calculated from (I × V ). IN DD DISS DD DD 5 Measured at a V pin where an adjacent V pin is making a full-scale voltage change. OUT OUT 6 See timing diagram for location of measured values. All input control voltages are specified with t = t = 2 ns (10% to 90% of V ) and timed from a voltage R F DD level of 1.6 V. Specifications subject to change without notice. –2– REV. A AD8801/AD8803 ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS (T = +25°C, unless otherwise noted) A Package Package V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +8 V DD Model FTN Temperature Description Option V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V REFX DD Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V DD AD8801AN RS –40°C to +85°C PDIP-16 N-16 Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, V DD AD8801AR RS –40°C to +85°C SO-16 R-16A Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C AD8803AN REFL –40°C to +85°C PDIP-16 N-16 Maximum Junction Temperature (T MAX) . . . . . . . . +150°C J AD8803AR REFL –40°C to +85°C SO-16 R-16A Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . .(T MAX – T )/θ AD8803 PIN DESCRIPTIONS J A JA Thermal Resistance θ JA, Pin Name Description SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W P-DIP (N-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W 1V Common High-Side DAC Reference Input REFH 2 O1 DAC Output #1, Addr = 000 2 AD8801 PIN DESCRIPTIONS 3 O2 DAC Output #2, Addr = 001 2 Pin Name Description 4 O3 DAC Output #3, Addr = 010 2 1V Common DAC Reference Input REFH 5 O4 DAC Output #4, Addr = 011 2 2 O1 DAC Output #1, Addr = 000 2 6 SHDN Reference inputs open circuit, active low, all 3 O2 DAC Output #2, Addr = 001 DAC outputs open circuit. DAC latch settings 2 maintained. 4 O3 DAC Output #3, Addr = 010 2 7 CS Chip Select Input, active low. When CS returns 5 O4 DAC Output #4, Addr = 011 2 high, data in the serial input register is decoded 6 SHDN Reference input open circuit, active low, all based on the address bits and loaded into the tar- DAC outputs open circuit. DAC latch settings get DAC register. maintained. 8 GND Ground 7 CS Chip Select Input, active low. When CS returns 9V Common Low-Side DAC Reference Input high, data in the serial input register is decoded REFL based on the address bits and loaded into the tar- 10 CLK Serial Clock Input, Positive Edge Triggered get DAC register. 11 SDI Serial Data Input 8 GND Ground 12 O5 DAC Output #5, Addr = 100 2 9 CLK Serial Clock Input, Positive Edge Triggered 13 O6 DAC Output #6, Addr = 101 2 10 SDI Serial Data Input 14 O7 DAC Output #7, Addr = 110 2 11 O5 DAC Output #5, Addr = 100 2 15 O8 DAC Output #8, Addr = 111 2 12 O6 DAC Output #6, Addr = 101 2 16 V Positive power supply, specified for operation at DD 13 O7 DAC Output #7, Addr = 110 both +3 V and +5 V. 2 14 O8 DAC Output #8, Addr = 111 2 15 RS Asynchronous preset to midscale output setting, PIN CONFIGURATIONS active low. Loads all DAC latches with 80 . H 16 V Positive power supply, specified for operation at 16 16 V 1 V V 1 V DD REFH DD REFH DD both +3 V and +5 V. O1 2 15 O1 2 15 O8 RS 3 14 3 14 O2 O8 O2 O7 AD8801 AD8803 O3 4 13 O7 O3 4 13 O6 TOP VIEW TOP VIEW 5 12 O6 5 12 O5 O4 O4 (Not to Scale) (Not to Scale) 6 11 O5 6 11 SDI SHDN SHDN 7 10 SDI 7 10 CLK CS CS GND89 CLK GND89 V REFL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– AD8801/AD8803 OCTAL 8-BIT TRIMDAC, WITH SHUTDOWN following address assignments for the ADDR decode which de- 1 termines the location of DAC register receiving the serial regis- SDI A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ter data in bits B7 through B0: 0 1 DAC # = A2 × 4 + A1 × 2 + A0 + 1 CLK 0 DAC outputs can be changed one at a time in random se- 1 quence. The fast serial-data loading of 33 MHz makes it possible DAC REGISTER LOAD CS to load all eight DACs in as little time as 3 μs (12 × 8 × 30 ns). 0 +5V The exact timing requirements are shown in Figure 2. VOUT 0V The AD8801 offers a midscale preset activated by the RS pin simplifying initial setting conditions at first power up. The Figure 2a. Timing Diagram AD8803 has both a V and a V pin to establish indepen- REFH REFL dent positive full-scale and zero-scale settings to optimize reso- DETAIL SERIAL DATA INPUT TIMING (RS = "1") lution. Both parts offer a power shutdown SHDN that places SDI 1 the DAC structure in a zero power consumption state resulting (DATA A OR D A OR D X X X X in only leakage currents being consumed from the power supply, 0 IN) t DS V inputs, and all 8 outputs. In shutdown mode the DACx REF t DH t CH t latch settings are maintained. When returning to operational CS1 1 CLK mode from power shutdown the DAC outputs return to their 0 previous voltage settings. t t CL CSH t CSS 1 TO OTHER DACS CS t CSW 0 P CH t S V REFH +5V ±1 LSB N CH MSB V OUT O 2R X 0V ±1 LSB ERROR BAND R Figure 2b. Detail Timing Diagram DAC REGISTER RESET TIMING D7 2R t RS 1 D6 RS R D0 0 t S . . . +5V V . . . OUT ±1 LSB . . . 2.5V ±1 LSB ERROR BAND 2R LSB Figure 2c. Reset Timing Diagram 2R GND Table I. Serial-Data Word Format V REFL ADDR DATA Figure 3. AD8801/AD8803 Equivalent TrimDAC Circuit B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 PROGRAMMING THE OUTPUT VOLTAGE MSB LSB MSB LSB The output voltage range is determined by the external refer- 10 9 8 7 6 5 4 3 2 1 0 2 2 2 2 2 2 2 2 2 2 2 ence connected to V and V pins. See Figure 3 for a REFH REFL simplified diagram of the equivalent DAC circuit. In the case of the AD8801, its V is internally connected to GND and REFL OPERATION therefore cannot be offset. V can be tied to V and V REFH DD REFL The AD8801/AD8803 provides eight channels of programmable can be tied to GND establishing a basic rail-to-rail voltage out- voltage output adjustment capability. Changing the programmed put programming range. Other output ranges are established by output voltage of each TrimDAC is accomplished by clocking in the use of different external voltage references. The general an 11-bit serial data word into the SDI (Serial Data Input) pin. transfer equation that determines the programmed output The format of this data word is three address bits, MSB first, voltage is: followed by eight data bits, MSB first. Table I provides the se- V (Dx) = (Dx)/256 × (V – V ) + V (1) O REFH REFL REFL rial register data word format. The AD8801/AD8803 has the where Dx is the data contained in the 8-bit DACx latch. REV. A –4– AD8801/AD8803 For example, when V = +5 V and V = 0 V the follow- DIGITAL INTERFACING REFH REFL ing output voltages will be generated for the following codes: The AD8801/AD8803 contains a standard three-wire serial in- put control interface. The three inputs are clock (CLK), CS and DV Output State OX serial data input (SDI). The positive-edge sensitive CLK input (V = +5 V, V = 0 V) REFH REFL requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If 255 4.98 V Full-Scale mechanical switches are used for product evaluation, they 128 2.50 V Half-Scale (Midscale Reset Value) should be debounced by a flip-flop or other suitable means. Fig- 1 0.02 V 1 LSB ure 4 block diagram shows more detail of the internal digital cir- 0 0.00 V Zero-Scale cuitry. When CS is taken active low, the clock can load data into the serial register on each positive clock edge, see Table II. REFERENCE INPUTS (V , V ) REFH REFL The reference input pins set the output voltage range of all eight Table II. Input Logic Control Truth Table DACs. In the case of the AD8801 only the V pin is avail- REFH CS CLK Register Activity able to establish a user designed full-scale output voltage. The external reference voltage can be any value between 0 and V DD 1 X No effect. but must not exceed the V supply voltage. In the case of the DD 0 P Shifts Serial Register one bit loading the AD8803, which has access to the V which establishes the REFL next bit in from the SDI pin. zero-scale output voltage, any voltage can be applied between P X Data is transferred from the serial register 0 V and V . V can be smaller or larger in voltage than DD REFL to the decoded DAC register. See Figure 5. V since the DAC design uses fully bidirectional switches as REFH NOTE: P = positive edge, X = don’t care. shown in Figure 3. The input resistance to the DAC has a code dependent variation that has a nominal worst case measured at The data setup and data hold times in the specification table 55 , which is approximately 2 kΩ. When V is greater than H REFH determine the data valid time requirements. The last 11 bits of V , the REFL reference must be able to sink current out of REFL the data word entered into the serial register are held when CS the DAC ladder, while the REFH reference is sourcing current returns high. At the same time CS goes high it gates the address into the DAC ladder. The DAC design minimizes reference decoder which enables one of the eight positive edge triggered glitch current maintaining minimum interference between DAC DAC registers, see Figure 5 detail. channels during code changes. DAC 1 DAC OUTPUTS (O1–O8) DAC 2 CS . ADDR . The eight DAC outputs present a constant output resistance of DECODE . approximately 5 kΩ independent of code setting. The distribu- DAC 8 tion of R from DAC to DAC typically matches within ±1%. OUT However, device to device matching is process lot dependent SERIAL CLK REGISTER having a ±20% variation. The change in R with temperature OUT SDI has a 500 ppm/°C temperature coefficient. During power shut- down all eight outputs are open circuited. Figure 5. Equivalent Control Logic The target DAC register is loaded with the last eight bits of the se- rial data word completing one DAC update. Eight separate 11-bit CS AD8801/AD8803 V DD data words must be clocked in to change all eight output settings. V REFH All digital inputs are protected with a series input resistor and CLK DAC D7 O1 DAC parallel Zener ESD structure shown in Figure 6. This applies to 1 DAC digital input pins CS, SDI, RS, SHDN, CLK. O2 EN REG #1 D10 ADDR O3 DEC D9 D0 100Ω R D8 O4 LOGIC D7 O5 ... .. SER ... .. REG . ... .. O6 . . O7 D7 Figure 6. Equivalent ESD Protection Circuit SDI D D0 DAC O8 DAC 8 Digital inputs can be driven by voltages exceeding the AD8801/ REG #8 AD8803 V value. This allows 5 V logic to interface directly to DD 8 D0 the part when it is operated at 3 V. R SHDN V GND RS REFL (AD8801 ONLY) (AD8803 ONLY) Figure 4. Block Diagram REV. A –5– AD8801/AD8803–Typical Performance Characteristics 1 200 V = +5V DD V = +5V DD T = +85°C A VREFH = +2V V = +5V 0.75 REFH T = +25°C A V = 0V REFL V = 0V REFL T = –40°C A ALL OTHER DACS SET 0.5 150 TO ZERO SCALE T = +25°C A 0.25 0 100 –0.25 –0.5 50 –0.75 –1 0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE – Decimal CODE – Decimal Figure 7. INL vs. Code Figure 10. Input Reference Current vs. Code 1 10k V = +5V V = +5.5V DD DD 0.75 V = +5V V = 0V REFH REF T = –40°C, +25°C, +85°C V = 0V A REFL 0.5 1k 0.25 V = +5.5V DD 100 0 V = +5.5V REF –0.25 –0.5 10 –0.75 –1 0 0 64 128 192 256 –55 –35 –15 5 25 45 65 85 105 125 CODE – Decimal TEMPERATURE – °C Figure 11. Shutdown Current vs. Temperature Figure 8. Differential Nonlinearity Error vs. Code 1200 100k V = +5.5V DD V = +4.5V 1080 DD LOGIC = +2.4V 10k V = +4.5V ALL DIGITAL PINS REF 960 V = 0V TIED TOGETHER REFL 1k T = +25°C A 840 SS = 2446 PCS 100 720 600 10 V = +5.5V DD 480 1 LOGIC = +5.5V 260 ALL DIGITAL PINS 0.1 TIED TOGETHER 240 0.01 120 0.001 0 –55 –35 –15 5 25 45 65 85 105 125 –3.4 –3.3 –3.2 –3.1 –3.0 –2.9 –2.8 –2.7 –2.6 –2.5 TEMPERATURE – °C TOTAL UNADJUSTED ERROR – LSB Figure 12. Supply Current vs. Temperature Figure 9. Total Unadjusted Error Histogram REV. A –6– INL – LSB DNL – LSB FREQUENCY I SHUTDOWN CURRENT – nA REF I SUPPLY CURRENT – µA I CURRENT – µA DD REF AD8801/AD8803 100 T = +25°C A ALL DIGITAL INPUTS OUTPUT1: OO → FF H H 10 TIED TOGETHER V = +5V DD 100 V = +2V REF 90 f = 500kHz 1.0 V = +5V DD 0.1 10 0.01 0% V = +3V DD 0.001 TIME – 0.2µs/DIV 0.0001 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 LOGIC INPUT VOLTAGE – Volts Figure 13. Supply Current vs. Logic Input Voltage Figure 16. Adjacent Channel Clock Feedthrough 80 OUTPUT1: 7F → 80 H H V = +5V ±0.5V DD P V = +5V DD 60 100 V = +2V REFH 90 V = +2V REF CODE = 80 H OUT1 T = +25°C A 10mV/DIV 40 CS 5V/DIV 10 0% 20 TIME – 0.2µs/DIV 0 10 100 1k 10k 100k FREQUENCY – Hz Figure 17. Midscale Transition Figure 14. Power Supply Rejection vs. Frequency 0.01 V = +4.5V DD V = +5V DD V = +4.5V REF V = +2V REF SS = 162 PCS 100 0.005 V = 0V REFL 2V 90 OUT1 0V 0 5V 10 0% 0% CS 0V –0.005 TIME – 1µs/DIV –0.01 0 150 300 450 600 HOURS OF OPERATION AT 150°C Figure 18. Zero-Scale Error Accelerated by Burn-In Figure 15. Large-Signal Settling Time REV. A –7– I SUPPLY CURRENT – mA DD PSRR – dB CHANGE IN ZERO-SCALE ERROR – LSB OUTPUT2 – 10mV/DIV AD8801/AD8803 1.0 0.04 V = +4.5V V = +4.5V DD DD V = +4.5V V = +4.5V REF REF CODE = 55 SS = 162 PCS H x + 2σ SS = 162 PCS 0.5 0.02 x + 2σ x x 0 0 x – 2σ x – 2σ –0.5 –0.02 –1.0 –0.04 0 150 300 450 600 0 150 300 450 600 HOURS OF OPERATION AT 150°C HOURS OF OPERATION AT 150°C Figure 20. REF Input Resistance Accelerated by Burn-In Figure 19. Full-Scale Error Accelerated by Burn-In +5V APPLICATIONS Supply Bypassing Precision analog products, such as the AD8801/AD8803, re- V DD quire a well filtered power source. Since the AD8801/AD8803 operate from a single +3 V to +5 V supply, it seems convenient AD8801/ + 10µF 0.1µF AD8803 to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates DGND noise in the 20 kHz to 1 MHz range. In addition, fast logic gates can generate glitches hundred of millivolts in amplitude due to wiring resistances and inductances. If possible, the AD8801/AD8803 should be powered directly from the system power supply. This arrangement, shown in Fig- Figure 22. Recommended Supply Bypassing for the ure 21, will isolate the analog section from the logic switching AD8801/AD8803 transients. Even if a separate power supply trace is not available, Buffering the AD8801/AD8803 Output however, generous supply bypassing will reduce supply-line in- In many cases, the nominal 5 kΩ output impedance of the duced errors. Local supply bypassing consisting of a 10 μF tan- AD8801/AD8803 is sufficient to drive succeeding circuitry. If a talum electrolytic in parallel with a 0.1 μF ceramic capacitor is lower output impedance is required, an external amplifier can recommended (Figure 22). be added. Several examples are shown in Figure 23. One ampli- fier of an OP291 is used as a simple buffer to reduce the output TTL/CMOS resistance of DAC A. The OP291 was chosen primarily for its LOGIC CIRCUITS rail-to-rail input and output operation, but it also offers opera- + tion to less than 3 V, low offset voltage, and low supply current. 10µF AD8801/ 0.1µF AD8803 TANT The next two DACs, B and C, are configured in a summing ar- rangement where DAC C provides the coarse output voltage +5V setting and DAC B can be used for fine adjustment. The inser- POWER SUPPLY tion of R1 in series with DAC B attenuates its contribution to the voltage sum node at the DAC C output. Figure 21. Use Separate Traces to Reduce Power Supply Noise REV. A –8– CHANGE IN FULL-SCALE ERROR – LSB INPUT RESISTANCE DRIFT – kΩ AD8801/AD8803 +5V Microcomputer Interfaces The AD8801/AD8803 serial data input provides an easy inter- V V REFH DD face to a variety of single-chip microcomputers (μCs). Many μCs OP291 have a built-in serial data capability that can be used for com- V H SIMPLE BUFFER municating with the DAC. In cases where no serial port is pro- V L 0V TO 5V vided, or it is being used for some other purpose (such as an RS-232 communications interface), the AD8801/AD8803 can V H easily be addressed in software. V L R1 Eleven data bits are required to load a value into the AD8801/ 100kΩ V SUMMER CIRCUIT H AD8803 (3 bits for the DAC address and 8 bits for the DAC WITH FINE TRIM V L ADJUSTMENT value). If more than 11 bits are transmitted before the Chip Se- lect input goes high, the extra (i.e., the most-significant) bits are AD8801/ AD8803 ignored. This feature is valuable because most μCs only transmit VREFL GND data in 8-bit increments. Thus, the μC will send 16 bits to the DAC instead of 11 bits. The AD8801/AD8803 will only re- DIGITAL INTERFACING OMITTED FOR CLARITY spond to the last 11 bits clocked into the SDI input, however, so the serial data interface is not affected. Figure 23. Buffering the AD8801/AD8803 Output An 8051 μC Interface Increasing Output Voltage Swing A typical interface between the AD8801/AD8803 and an 8051 An external amplifier can also be used to extend the output volt- μC is shown in Figure 25. This interface uses the 8051’s internal age swing beyond the power supply rails of the AD8801/AD8803. serial port. The serial port is programmed for Mode 0 opera- This technique permits an easy digital interface for the DAC, tion, which functions as a simple 8-bit shift register. The 8051’s while expanding the output swing to take advantage of higher Port3.0 pin functions as the serial data output, while Port3.1 voltage external power supplies. For example, DAC A of Fig- serves as the serial clock. ure 24 is configured to swing from –5 V to +5 V. The actual +5V output voltage is given by: + 0.1µF 10µF R   D F V = 1+ × × 5V ±5V OUT ()   R 256 S V V DD REFH AD8801 Where D is the DAC input value (i.e., 0 to 255). This circuit RxD P3.0 SDI SBUF SERIAL DATA SHIFT REGISTER O1 can be combined with the “fine/coarse” circuit of Figure 23 if, TxD P3.1 O2 SHIFT CLOCK SCLK for example, a very accurate adjustment around 0 V is desired. O3 P1.3 RESET 8051 µC O4 +5V R R S F O5 P1.2 100kΩ 100kΩ SHDN O6 P1.1 O7 +5V CS O8 V V DD REFH 1.3 1.2 1.1 PORT 1 –5V TO +4.98V GND A OP191 –5V AD8801/ AD8803 Figure 25. Interfacing the 8051 μC to an AD8801/AD8803, +12V Using the Serial Port OP193 B When data is written to the Serial Buffer Register (SBUF, at 0V TO +10V Special Function Register location 99 ), the data is automati- H V GND REFL cally converted to serial format and clocked out via Port3.0 and Port3.1. After 8 bits have been transmitted, the Transmit Inter- 100kΩ rupt flag (SCON.1) is set and the next 8 bits can be transmitted. 100kΩ The AD8801 and AD8803 require the Chip Select to go low at the beginning of the serial data transfer. In addition, the SCLK input must be high when the Chip Select input goes high at the Figure 24. Increasing Output Voltage Swing end of the transfer. The 8051’s serial clock meets this require- DAC B of Figure 24 is in a noninverting gain of two configura- ment, since Port3.1 both begins and ends the serial data in the tion, which increases the available output swing to +10 V. The high state. feedback resistors can be adjusted to provide any scaling of the Software for the 8051 Interface output voltage, within the limits of the external op amp power A software routine for the AD8801/AD8803 to 8051 interface is supplies. shown in Listing 1. The routine transfers the 8-bit data stored at data memory location DAC_VALUE to the AD8801/AD8803 DAC addressed by the contents of location DAC_ADDR. REV. A –9– AD8801/AD8803 ; ; This subroutine loads an AD8801/AD8803 DAC from an 8051 microcomputer, ; using the 8051’s serial port in MODE 0 (Shift Register Mode). ; The DAC value is stored at location DAC_VAL ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations ; PORT1 DATA 90H ;SFR register for port 1 DAC_VALUE DATA 40H ;DAC Value DAC_ADDR DATA 41H ;DAC Address SHIFT1 DATA 042H ;high byte of 16-bit answer SHIFT2 DATA 043H ;low byte of answer SHIFT_COUNT DATA 44H ; ; ORG 100H ;arbitrary start DO_8801: CLR SCON.7 ;set serial CLR SCON.6 ; data mode 0 CLR SCON.5 CLR SCON.1 ;clr transmit flag ORL PORT1.1,#00001110B ;/RS, /SHDN, /CS high CLR PORT1.1 ;set the /CS low MOV SHIFT1,DAC_ADDR ;put DAC value in shift register ACALL BYTESWAP ; MOV SBUF,SHIFT2 ;send the address byte ADDR_WAIT: JNB SCON.1,ADDR_WAIT ;wait until 8 bits are sent CLR SCON.1 ;clear the serial transmit flag MOV SHIFT1,DAC_VALUE ;send the DAC value ACALL BYTESWAP ; MOV SBUF,SHIFT2 ; VALU_WAIT: JNB SCON.1,VALU_WAIT ;wait again CLR SCON.1 ;clear serial flag SETB PORT1.1 ;/CS high, latch data RET ; into AD8801 ; BYTESWAP: MOV SHIFT_COUNT,#8 ;Shift 8 bits SWAP_LOOP: MOV A,SHIFT1 ;Get source byte RLC A ;Rotate MSB to carry MOV SHIFT1,A ;Save new source byte MOV A,SHIFT2 ;Get destination byte RRC A ;Move carry to MSB MOV SHIFT2,A ;Save DJNZ SHIFT_COUNT,SWAP_LOOP ;Done? RET END Listing 1. Software for the 8051 to AD8801/AD8803 Serial Port Interface REV. A –10– AD8801/AD8803 The subroutine begins by setting appropriate bits in the Serial The BYTESWAP routine in Listing 1 is convenient because the Control register to configure the serial port for Mode 0 opera- DAC data can be calculated in normal LSB form. For example, tion. Next the DAC’s Chip Select input is set low to enable the producing a ramp voltage on a DAC is simply a matter of re- AD8801/AD8803. The DAC address is obtained from memory peatedly incrementing the DAC_VALUE location and calling location DAC_ADDR, adjusted to compensate for the 8051’s the LD_8801 subroutine. serial data format, and moved to the serial buffer register. At If the μC’s hardware serial port is being used for other purposes, this point, serial data transmission begins automatically. When the AD8801/AD8803 can be loaded by using the parallel port. all 8 bits have been sent, the Transmit Interrupt bit is set, and A typical parallel interface is shown in Figure 26. The serial data the subroutine then proceeds to send the DAC value stored at is transmitted to the DAC via the 8051’s Port1.7 output, while location DAC_VALUE. Finally the Chip Select input is re- Port1.6 acts as the serial clock. turned high, causing the appropriate AD8801/AD8803 output Software for the interface of Figure 26 is contained in Listing 2. The voltage to change, and the subroutine ends. subroutine will send the value stored at location DAC_VALUE to The 8051 sends data out of its shift register LSB first, while the the AD8801/AD8803 DAC addressed by location DAC_ADDR. AD8801/AD8803 require data MSB first. The subroutine there- The program begins by setting the AD8801/AD8803’s Serial fore includes a BYTESWAP subroutine to reformat the data. Clock and Chip Select inputs high, then setting Chip Select low This routine transfers the MSB-first byte at location SHIFT1 to to start the serial interface process. The DAC address is loaded an LSB-first byte at location SHIFT2. The routine rotates the into the accumulator and three Rotate Right shifts are per- MSB of the first byte into the carry with a Rotate Left Carry in- formed. This places the DAC address in the 3 MSBs of the ac- struction, then rotates the carry into the MSB of the second byte cumulator. The address is then sent to the AD8801/AD8803 via with a Rotate Right Carry instruction. After 8 loops, SHIFT2 the SEND_SERIAL subroutine. Next, the DAC value is loaded contains the data in the proper format. into the accumulator and sent to the AD8801/AD8803. Finally, the Chip Select input is set high to complete the data transfer. ; This 8051 μC subroutine loads an AD8801 or AD8803 DAC with an 8-bit value, ; using the 8051’s parallel port #1. ; The DAC value is stored at location DAC_VALUE ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations PORT1 DATA 90H ;SFR register for port 1 DAC_VALUE DATA 40H ;DAC Value DAC_ADDR DATA 41H ;DAC Address (0 through 7) LOOPCOUNT DATA 43H ;COUNT LOOPS ; ORG 100H ;arbitrary start LD_8803: ORL PORT1,#11110000B ;set CLK, /CS and /SHDN high, CLR PORT1.5 ;Set Chip Select low MOV LOOPCOUNT,#3 ;Address is 3 bits MOV A,DAC_ADDR ; Get DAC address RR A ; Rotate the DAC RR A ;address to the Most RR A ;Significant Bits (MSBs) ACALL SEND_SERIAL ;Send the address MOV LOOPCOUNT,#8 ;Do 8 bits of data MOV A,DAC_VALUE ACALL SEND_SERIAL ;Send the data SETB PORT1.5 ;Set /CS high RET ;DONE SEND_SERIAL: RLC A ;Move next bit to carry MOV PORT1.7,C ;Move data to SDI CLR PORT1.6 ;Pulse the SETB PORT1.6 ; CLK input DJNZ LOOPCOUNT,SEND_SERIAL ;Loop if not done RET; END Listing 2. Software for the 8051 to AD8801/AD8803 Parallel Port Interface REV. A –11– AD8801/AD8803 +5V MC68HC11* AD8801/ AD8803* MOSI (PD3) SDI V V DD REFH 8051 µC CLK (PD4) SCK AD8803 O1 P1.7 CS SDI (PD5) SS O2 P1.6 O3 CLK PC0 SHDN O4 P1.5 CS O5 PC1 RS (AD8801 ONLY) O6 P1.4 SHDN O7 *ADDITIONAL PINS OMITTED FOR CLARITY PORT 1 1.7 1.6 1.5 1.4 O8 GND VREFL Figure 27. An AD8801/AD8803-to-MC68HC11 Interface A software routine for loading the AD8801/AD8803 from a 68HC11 evaluation board is shown in Listing 3. First, the MC68HC11 is configured for SPI operation. Bits CPHA and Figure 26. An AD8801/AD8803-8051 μC Interface Using CPOL define the SPI mode wherein the serial clock (SCK) is Parallel Port 1 high at the beginning and end of transmission, and data is valid Unlike the serial port interface of Figure 25, the parallel port in- on the rising edge of SCK. This mode matches the requirements terface only transmits 11 bits to the AD8801/AD8803. Also, the of the AD8801/AD8803. After the registers are saved on the BYTESWAP subroutine is not required for the parallel inter- stack, the DAC value and address are transferred to RAM and face, because data can be shifted out MSB first. However, the the AD8801/AD8803’s CS is driven low. Next, the DAC’s ad- results of the two interface methods are exactly identical. In dress byte is transferred to the SPDR register, which automati- most cases, the decision on which method to use will be deter- cally initiates the SPI data transfer. The program tests the SPIF mined by whether or not the serial data port is available for bit and loops until the data transfer is complete. Then the DAC communication with the AD8801/AD8803. value is sent to the SPI. When transmission of the second byte is An MC68HC11-to-AD8801/AD8803 Interface complete, CS is driven high to load the new data and address Like the 8051, the MC68HC11 includes a dedicated serial data into the AD8801/AD8803. port (labeled SPI). The SPI port provides an easy interface to the AD8801/AD8803 (Figure 27). The interface uses three lines of Port D for the serial data, and one or two lines from Port C to control the SHDN and RS (AD8801 only) inputs. REV. A –12– AD8801/AD8803 * * AD8801/AD8803 to M68HC11 Interface Assembly Program * * M68HC11 Register definitions * PORTC EQU $1003 Port C control register * “0,0,0,0;0,0,RS/, SHDN/” DDRC EQU $1007 Port C data direction PORTD EQU $1008 Port D data register * “0,0,/CS,CLK;SDI,0,0,0” DDRD EQU $1009 Port D data direction SPCR EQU $1028 SPI control register * “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0” SPSR EQU $1029 SPI status register * “SPIF,WCOL,0,MODF;0,0,0,0” SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * SDI RAM variables: SDI1 is encoded from 0 (Hex) to 7 (Hex) * SDI2 is encoded from 00 (Hex) to FF (Hex) * AD8801/3 requires two 8-bit loads; upper 5 bits * of SDI1 are ignored. AD8801/3 address bits in last * three LSBs of SDI1. * SDI1 EQU $00 SDI packed byte 1 “0,0,0,0;0,A2,A1,A0” SDI2 EQU $01 SDI packed byte 2 “DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0” * * Main Program * ORG $C000 Start of user’s RAM in EVB INIT LDS #$CFFF Top of C page RAM * * Initialize Port C Outputs * LDAA #$03 0,0,0,0;0,0,1,1 * /RS-Hi, /SHDN-Hi STAA PORTC Initialize Port C Outputs LDAA #$03 0,0,0,0;0,0,1,1 STAA DDRC /RS and /SHDN are now enabled as outputs * * Initialize Port D Outputs * LDAA #$20 0,0,1,0;0,0,0,0 * /CS-Hi,/CLK-Lo,SDI-Lo STAA PORTD Initialize Port D Outputs LDAA #$38 0,0,1,1;1,0,0,0 STAA DDRD /CS,CLK, and SDI are now enabled as outputs * * Initialize SPI Interface * LDAA #$53 STAA SPCR SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32 * * Call update subroutine * BSR UPDATE Xfer 2 8-bit words to AD8402 JMP $E000 Restart BUFFALO * * Subroutine UPDATE * UPDATE PSHX Save registers X, Y, and A REV. A –13– AD8801/AD8803 PSHY PSHA * * Enter Contents of SDI1 Data Register * LDAA $0000 Hi-byte data loaded from memory STAA SDI1 SDI1 = data in location 0000H * * Enter Contents of SDI2 Data Register * LDAA $0001 Low-byte data loaded from memory STAA SDI2 SDI2 = Data in location 0001H * LDX #SDI1 Stack pointer at 1st byte to send via SDI LDY #$1000 Stack pointer at on-chip registers * * Reset AD8801 to one-half scale (AD8803 does not have a Reset input) * BCLR PORTC,Y $02 Assert /RS BSET PORTC,Y $02 De-assert /RS * * Get AD8801/03 ready for data input * BCLR PORTD,Y $20 Assert /CS * TFRLP LDAA 0,X Get a byte to transfer via SPI STAA SPDR Write SDI data reg to start xfer * WAIT LDAA SPSR Loop to wait for SPIF BPL WAIT SPIF is the MSB of SPSR * (when SPIF is set, SPSR is negated) INX Increment counter to next byte for xfer CPX #SDI2+1 Are we done yet ? BNE TFRLP If not, xfer the second byte * * Update AD8801 output * BSET PORTD,Y $20 Latch register & update AD8801 * PULA When done, restore registers X, Y & A PULY PULX RTS ** Return to Main Program ** Listing 3. AD8801/AD8803 to MC68HC11 Interface Program Source Code REV. A –14– AD8801/AD8803 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Plastic DIP Package (N-16) 0.840 (21.33) 0.745 (18.93) 16 9 0.280 (7.11) 0.240 (6.10) 18 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) 0.060 (1.52) 0.115 (2.93) PIN 1 0.015 (0.38) 0.210 (5.33) MAX 0.130 0.160 (4.06) (3.30) 0.115 (2.93) MIN 0.015 (0.381) 0.070 (1.77) SEATING 0.008 (0.204) 0.022 (0.558) 0.100 0.045 (1.15) PLANE 0.014 (0.356) (2.54) BSC 16-Pin Narrow Body SOIC Package (R-16A) 16 9 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.2440 (6.20) 1 8 0.2284 (5.80) 0.3937 (10.00) 0.0196 (0.50) x 45° 0.3859 (9.80) 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35) 8° 0.0098 (0.25) 0° 0.0500 (1.27) 0.0500 0.0192 (0.49) 0.0099 (0.25) 0.0040 (0.10) (1.27) 0.0160 (0.41) 0.0138 (0.35) 0.0075 (0.19) BSC REV. A –15– –16– PRINTED IN U.S.A. C2026–18–4/95