ANALOG DEVICES AD876

10-Bit 20 MSPS 160 mW a CMOS A/D Converter AD876 FEATURES FUNCTIONAL BLOCK DIAGRAM CMOS 10-Bit 20 MSPS Sampling A/D Converter Pin-Compatible 8-Bit Option AV DV CLK DRV DD DD DD Power Dissipation: 160 mW +5 V Single Supply Operation SHA SHA GAIN SHA GAIN SHA GAIN STBY Differential Nonlinearity: 0.5 LSB AIN A/D Guaranteed No Missing Codes A/D D/A A/D D/A A/D D/A THREE- Power Down (Standby) Mode REFTF STATE Three-State Outputs REFTS CORRECTION LOGIC Digital I/Os Compatible with +5 V or +3.3 V Logic REFBS Adjustable Reference Input OUTPUT BUFFERS (MSB) REFBF Small Size: 28-Lead SOIC, 28-Lead SSOP, or 48-Lead AD876 D9 Thin Quad Flatpack (TQFP) D0 (LSB) CML AV DV DRV SS SS SS PRODUCT DESCRIPTION The AD876 comes in a space saving 28-lead SOIC and 48-lead The AD876 is a CMOS, 160 mW, 10-bit, 20 MSPS analog-to- thin quad flatpack (TQFP) and is specified over the commercial digital converter (ADC). The AD876 has an on-chip input (0°C to +70°C) temperature range. sample-and-hold amplifier. By implementing a multistage pipe- lined architecture with output error correction logic, the AD876 PRODUCT HIGHLIGHTS offers accurate performance and guarantees no missing codes Low Power over the full operating temperature range. Force and sense con- The AD876 at 160 mW consumes a fraction of the power of nections to the reference inputs minimize external voltage drops. presently available 8- or 10-bit, video speed converters. Power- down mode and single-supply operation further enhance its The AD876 can be placed into a standby mode of operation desirability in low power, battery operated applications such reducing the power below 50 mW. The AD876’s digital I/O as electronic still cameras, camcorders and communication interfaces to either +5 V or +3.3 V logic. Digital output pins systems. can be placed in a high impedance state; the format of the out- put is straight binary coding. Very Small Package The AD876 comes in a 28-lead SOIC, 28-lead SSOP, and 48- The AD876’s speed, resolution and single-supply operation lead surface mount, thin quad flat package. The TQFP package ideally suit a variety of applications in video, multimedia, imag- is ideal for very tight, low headroom designs. ing, high speed data acquisition and communications. The AD876’s low power and single-supply operation satisfy require- Digital I/O Functionality ments for high speed portable applications. Its speed and reso- The AD876 offers three-state output control. lution ideally suit charge coupled device (CCD) input systems Pin Compatible Upgrade Path such as color scanners, digital copiers, electronic still cameras The AD876 offers the option of laying out designs for eight and camcorders. bits and migrating to 10-bit resolution if prototype results warrant. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or Fax: 781/326-8703 © Analog Devices, Inc., 1998 otherwise under any patent or patent rights of Analog Devices. (T to T with AV = +5.0 V, DV = +5.0 V, DRV = +3.3 V, V = +4.0 V, V = MIN MAX DD DD DD REFB REFB +2.0 V, f = 20 MSPS, unless otherwise noted) AD876–SPECIFICATIONS CLOCK AD876JR-8 AD876 Parameter Min Typ Max Min Typ Max Units RESOLUTION 8 10 Bits DC ACCURACY Integral Nonlinearity (INL) ±0.3 ±1.0 ±1.0 LSB Differential Nonlinearity (DNL) ±0.1 ±0.75 ±0.5 ±1 LSB No Missing Codes GUARANTEED GUARANTEED Offset Error 0.1 0.4 % FSR Gain Error 0.1 0.2 % FSR ANALOG INPUT Input Range 2 2 V p-p Input Capacitance 5.0 5.0 pF REFERENCE INPUT Reference Top Voltage 3.5 4.0 4.5 3.5 4.0 4.5 V Reference Bottom Voltage 1.6 2.0 2.5 1.6 2.0 2.5 V Reference Input Resistance 250 250 Ω Reference Input Current 8.0 8.0 mA Reference Top Offset 35 35 mV Reference Bottom Offset 35 35 mV DYNAMIC PERFORMANCE Effective Number of Bits f = 1 MHz 7.8 9.0 Bits IN f = 3.58 MHz 7.4 7.8 8.2 9.0 Bits IN f = 10 MHz 7.5 8.2 Bits IN Signal-to-Noise and Distortion (S/N+D) Ratio f = 1 MHz 49 56 dB IN = 3.58 MHz 46 49 51 56 dB f IN = 10 MHz 47 51 dB f IN Total Harmonic Distortion (THD) =1 MHz –62 –62 dB f IN = 3.58 MHz –62 –56 –62 –56 dB f IN =10 MHz –60 –60 dB f IN 2 –65 –65 dB Spurious Free Dynamic Range Full Power Bandwidth 150 150 MHz Differential Phase 0.5 0.5 Degree Differential Gain 1 1 % POWER SUPPLIES Operating Voltage 1 AV +4.5 +5.25 +4.5 +5.25 Volts DD 1 +4.5 +5.25 +4.5 +5.25 Volts DV DD +3.0 +5.25 +3.0 +5.25 Volts DRV DD Operating Current 20 25 20 25 mA IAV DD 12 16 12 16 mA IDV DD IDRV 0.1 1 0.1 1 mA DD POWER CONSUMPTION 160 190 160 190 mW TEMPERATURE RANGE Specified 0 +70 0 +70 °C NOTES 1 AV and DV must be within 0.5 V of each other to maintain specified performance levels. DD DD 2 3.58 MHz Input Frequency. Specifications subject to change without notice. See Definition of Specifications for additional information. –2– REV. B AD876 (T to T with AV = +5.0 V, DV = +5.0 V, DRV = +3.3 V, V = +4.0 V, V = +2.0 V, MIN MAX DD DD DD REFT REFB DIGITAL SPECIFICATIONS f = 20 MSPS, C = 20 pF unless otherwise noted) CLOCK L AD876 Parameter Symbol DRV Min Typ Max Units DD LOGIC INPUT High Level Input Voltage V 3.0 2.4 V IH 5.0 4.0 V 5.25 4.2 V Low Level Input Voltage V 3.0 0.6 V IL 5.0 1.0 V 5.25 1.05 V High Level Input Current I 5.0 –10 +10 μA IH Low Level Input Current I 5.0 –50 +50 μA IL Low Level Input Current (CLK Only) I 5.0 –10 +10 μA IL Input Capacitance C 5pF IN LOGIC OUTPUTS High Level Output Voltage V OH (I = 50 μA) 3.0 2.4 V OH 5.0 3.8 V = 0.5 mA) 5.0 2.4 V (I OH Low Level Output Voltage V OL (I = 50 μA) 3.6 0.7 V OL 5.25 1.05 V = 0.6 mA) 5.25 0.4 V (I OL 5pF Output Capacitance C OUT Output Leakage Current I –10 10 μA OZ Specifications subject to change without notice. TIMING SPECIFICATIONS Symbol Min Typ Max Units 1 Maximum Conversion Rate 20 MHz 50 ns Clock Period t C 23 25 ns Clock High t CH 23 25 ns Clock Low t CL 10 20 ns Output Delay t OD Pipeline Delay (Latency) 3.5 Clock Cycles Aperture Delay Time 4 ns Aperture Jitter 22 ps NOTE 1 Conversion rate is operational down to 10 kHz without degradation in specified performance. SAMPLE N SAMPLE N+1 SAMPLE N+2 AIN t t CH CL CLK t t OD C OUT DATA N-4 DATA N-3 DATA N-2 DATA N-1 DATA N Figure 1. Timing Diagram REV. B –3– AD876 PIN FUNCTION DESCRIPTIONS SOIC TQFP Symbol Pin No. Pin No. Type Name and Function D0 (LSB) 3 1 DO Least Significant Bit. D1–D4 4–7 2–5 DO Data Bits 1 through 4. D5–D8 8–11 8–11 Data Bits 5 through 8. D9 (MSB) 12 12 DO Most Significant Bit. THREE- 16 23 DI THREE-STATE = LOW THREE-STATE = HIGH STATE or N/C Normal Operating Mode High Impedance Outputs STBY 17 24 DI STBY = LOW or N/C STBY = HIGH Normal Operating Mode Standby Mode CLK 15 22 DI Clock Input. CML 26 38 AO Bypass Pin for an Internal Bias Point. REFTF 22 30 AI Reference Top Force. REFBF 24 34 AI Reference Bottom Force. REFTS 21 29 AI Reference Top Sense. REFBS 25 35 AI Reference Bottom Sense. AIN 27 39 AI Analog Input. AV 28 42 P +5 V Analog Supply. DD AV 1 44 P Analog Ground. SS DV 18 26 P +5 V Digital Supply. DD DV 14, 19, 20 17, 27, 28 P Digital Ground. SS DRV 2 45 P +3.3 V/+5 V Digital Supply. Supply for digital DD input and output buffers. DRV 13 16 P +3.3 V/+5 V Digital Ground. Ground for digital SS input and output buffers. Type: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power. PIN CONFIGURATIONS SOIC/SSOP TQFP AV 1 28 AV SS DD 47 46 45 43 42 48 44 41 40 39 38 37 DRV 2 27 AIN DD 26 3 CML 1 36 D0 *D0 4 25 REFBS 35 2 *D1 D1 REFBS 5 24 REFBF D2 3 34 D2 REFBF D3 6 23 33 NC 4 D3 AD876 D4 7 22 REFTF 5 32 D4 TOP VIEW D5 8 21 REFTS AD876 31 (Not to Scale) 6 TOP VIEW D6 9 20 DV 7 30 SS (Not to Scale) REFTF 19 DV 29 D7 10 8 SS D5 REFTS D8 11 18 DV 9 28 DD DV D6 SS D9 12 17 STBY 10 27 D7 DV SS DRV 13 16 THREE-STATE 26 SS 11 D8 DV DD DV 14 CLK 15 12 25 SS D9 13 14 15 16 17 18 19 20 21 22 23 24 * PINS D0 AND D1 ARE LEFT OPEN FOR THE AD876JR-8 NC = NO CONNECT –4– REV. B DRV DRV SS DD DV AV SS SS AV DD AIN CLK THREE-STATE CML STBY AD876 ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE Parameter With Respect to Min Max Units Temperature Package Package Model Range Description Options AV AV –0.5 +6.5 Volts DD SS DV , DRV DV , DRV –0.5 +6.5 Volts DD DD SS SS AD876JR 0°C to +70°C 28-Lead SOIC R-28 AV DV , DRV –0.5 +0.5 Volts SS SS SS AD876JST-Reel 0°C to +70°C 48-Lead TQFP ST-48 AIN AV –0.5 +6.5 Volts SS (Tape and Reel 13") REFTS, REFTF AD876JR-8 0°C to +70°C 28-Lead SOIC R-28 REFBS, REFBF AV –0.5 +6.5 Volts SS AD876AR –40°C to +85°C 28-Lead SOIC R-28 Digital Inputs, CLK DV , DRV –0.5 +6.5 Volts SS SS AD876ARS –40°C to +85°C 28-Lead SSOP RS-28 Junction Temperature +150 °C AD876JRS 0°C to +70°C 28-Lead SSOP RS-28 Storage Temperature –65 +150 °C AD876JRS-8 0°C to +70°C 28-Lead SSOP RS-28 Lead Temperature (10 sec) +300 °C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. DV DD DV DD DRV DD DRV DD DV DRV DD DD DV SS DRV SS DV SS DV SS DRV SS DRV SS DV SS a) D0–D9 b) Three-State, Standby c) CLK AV DD REFTF AV SS AV DD AV DD INTERNAL REFTS REFERENCE VOLTAGE AV SS AV SS AV DD d) AIN INTERNAL REFERENCE REFBS VOLTAGE AV SS AV DD REFBF AV SS Figure 2. Equivalent Circuits CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD876 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– AD876–Typical Performance Characteristics 1 0 –10 –20 0.5 –30 –40 0 –50 THD –60 2ND –0.5 –70 3RD –80 –1 –90 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 10 1 CODE OFFSET FREQUENCY – MHz Figure 3. AD876 Typical DNL Figure 6. THD vs. Input Frequency 2nd, 3rd Harmonics 2 60 0 55 –2 50 –4 45 –6 40 –8 35 –10 30 1 10 100 1000 53 10 15 20 250 FREQUENCY – MHz CLOCK FREQUENCY – MHz Figure 4. Full Power Bandwidth Figure 7. SINAD vs. CLK Frequency (AIN = –0.5 dB) 180 60 170 55 160 50 150 140 45 130 40 120 35 110 100 30 02 510 15 205 0 1 2 10 10 10 CLOCK FREQUENCY – MHz INPUT FREQUENCY – MHz Figure 8. Power Consumption vs. Sample Rate Figure 5. SINAD vs. Input Frequency (f = 20 MSPS, AIN = –0.5 dB) CLK –6– REV. B GAIN – dB dB DNL – LSBs dB mW dB AD876 1 PIPELINE DELAY (LATENCY) The number of clock cycles between conversion initiation and HARMONICS (dBc) 2ND –68.02 6TH –77.74 the associated output data being made available. New output 3RD –72.85 7TH –75.62 data is provided every clock cycle. 4TH –70.68 8TH –75.98 5TH –78.09 9TH –81.20 REFERENCE TOP/BOTTOM OFFSET THD = –64.12 Resistance between the reference input and comparator input SNR = 48.73 SINAD = 48.61 tap points causes offset errors. These errors can be nulled out SFDR = –68.02 by using the force-sense connection as shown in the Reference Input section. 2 4 3 6 7 8 5 9 THEORY OF OPERATION The AD876 implements a pipelined multistage architecture to achieve high sample rate with low power. The AD876 distrib- utes the conversion over several smaller A/D subblocks, refining Figure 9. AD876JR-8 Typical FFT (f = 3.58 MHz, IN the conversion with progressively higher accuracy as it passes AIN = –0.5 dB, f = 20 MSPS) CLOCK the results from stage to stage. As a consequence of the distrib- uted conversion, the AD876 requires a small fraction of the 1023 1 comparators used in a traditional flash type A/D. A sample-and- HARMONICS (dBc) hold function within each of the stages permits the first stage to 2ND –68.91 6TH –80.55 3RD –73.92 7TH –82.02 operate on a new input sample while the second and third stages 4TH –68.67 8TH –81.02 operate on the two preceding samples. 5TH –73.26 9TH –88.94 THD = –64.24 APPLYING THE AD876 SNR = 55.71 SINAD = 55.14 DRIVING THE ANALOG INPUT SFDR = –68.67 Figure 11 shows the equivalent analog input of the AD876, a 2 4 sample-and-hold amplifier (SHA). Bringing CLK to a logic low 5 3 level closes Switches 1 and 2 and opens Switch 3. The input 6 7 8 source connected to AIN must charge capacitor C during this H 9 time. When CLK transitions from logic “low” to logic “high,” Switch 1 opens first, placing the SHA in hold mode. Switch 2 opens subsequently. Switch 3 then closes, connects the feed- Figure 10. AD876 Typical FFT (f = 3.58 MHz, AIN = –0.5 dB, IN back loop around the op amp, and forces the output of the op f = 20 MSPS) CLOCK amp to equal the voltage stored on C . When CLK transitions H from logic “high” to logic “low”, Switch 3 opens first. Switch 2 DEFINITIONS OF SPECIFICATIONS closes and reconnects the input to C . Finally, Switch 1 closes H INTEGRAL NONLINEARITY (INL) and places the SHA in track mode. Integral nonlinearity refers to the deviation of each individual The structure of the input SHA places certain requirements on code from a line drawn from “zero” through “full scale”. The the input drive source. The combination of the pin capacitance, point used as “zero” occurs 1/2 LSB before the first code transi- C , and the hold capacitance, C , is typically less than 5 pF. P H tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last The input source must be able to charge or discharge this ca- code transition. The deviation is measured from the center of pacitance to 10-bit accuracy in one half of a clock cycle. When each particular code to the true straight line. the SHA goes into track mode, the input source must charge or discharge capacitor C from the voltage already stored on C DIFFERENTIAL NONLINEARITY (DNL, NO MISSING H H (the previously captured sample) to the new voltage. In the CODES) worst case, a full-scale voltage step on the input, the input An ideal ADC exhibits code transitions that are exactly 1 LSB source must provide the charging current through the R (50 Ω) apart. DNL is the deviation from this ideal value. It is often ON of Switch 2 and quickly settle (within 1/2 CLK period). This specified in terms of the resolution for which no missing codes situation corresponds to driving a low input impedance. On the (NMC) are guaranteed. other hand, when the source voltage equals the value previously OFFSET ERROR stored on C , the hold capacitor requires no input current and H The first transition should occur at a level 1/2 LSB above the equivalent input impedance is extremely high. “zero.” Offset is defined as the deviation of the actual first code Adding series resistance between the output of the source and transition from that point. the AIN pin reduces the drive requirements placed on the source. Figure 12 shows this configuration. The bandwidth of GAIN ERROR the particular application limits the size of this resistor. To The first code transition should occur for an analog value 1/2 LSB maintain the performance outlined in the data sheet specifica- above nominal negative full scale. The last transition should tions, the resistor should be limited to 200 Ω or less. For appli- occur for an analog value 1 1/2 LSB below the nominal positive cations with signal bandwidths less than 10 MHz, the user may full scale. Gain error is the deviation of the actual difference increase the size of the series resistor proportionally. Alterna- between first and last code transitions and the ideal difference tively, adding a shunt capacitance between the AIN pin and between the first and last code transitions. REV. B –7– AD876 analog ground can lower the ac source impedance. The value 20 kHz. At a sample clock frequency of 20 MHz, the dc bias of this capacitance will depend on the source resistance and the current at 3 V dc is approximately 30 μA. If we choose R2 equal required signal bandwidth. to 1 kΩ and R1 equal to 50 Ω, the parallel capacitance should be a minimum of 0.008 μF to avoid attenuating signals close to The input span of the AD876 is a function of the reference 20 kHz. Note that the bias current will cause a 31.5 mV offset voltages. For more information regarding the input range, see from the 3 V bias. the DRIVING THE REFERENCE TERMINALS section of the data sheet. In systems that must use dc-coupling, use an op amp to level- shift a ground-referenced signal to comply with the input requirements of the AD876. Figure 14 shows an AD817 3 AD876 configured in inverting mode with ac signal gain of –1. The dc 1 voltage at the noninverting input of the op amp controls the AIN amount of dc level shifting. A resistive voltage divider attenu- 2 C H C P ates the REFBF signal. The op amp then multiplies the attenu- ated signal by 2. In the case where REFBF = 1.6 V, the dc output level will be 2.6 V. The AD817 is a low cost, fast settling, Figure 11. AD876 Equivalent Input Structure single supply op amp with a G = –1 bandwidth of 29 MHz. The AD818 is similar to the AD817 but has a 50 MHz bandwidth. < < 200V Other appropriate op amps include the AD8011, AD812 (a dual), AIN and the AD8001. V S R = 4.99kV f +V CC 0.1mF Figure 12. Simple AD876 Drive Requirements AD876 NC In many cases, particularly in single-supply operation, ac- 2V p-p coupling offers a convenient way of biasing the analog input 0Vdc R = 4.99kV IN AD817 OR signal at the proper signal range. Figure 13 shows a typical AIN AD818 3kV configuration for ac-coupling the analog input signal to the REFBF AD876. Maintaining the specifications outlined in the data 14.7kV NC sheet requires careful selection of the component values. The most important concern is the f high-pass corner that is a -3 dB function of R2, and the parallel combination of C1 and C2. Figure 14. Bipolar Level Shift The f point can be approximated by the equation -3 dB An integrated difference amplifier such as the AD830 is an alternate means of providing dc level shifting. The AD830 1 f = −3 dB provides a great deal of flexibility with control over offset and [2×π×(R2) Ceq] gain. Figure 15 shows the AD830 precisely level-shifting a where Ceq is the parallel combination of C1 and C2. Note that unipolar, ground-referenced signal. The reference voltage, C1 is typically a large electrolytic or tantalum capacitor that REFBS, determines the amount of level-shifting. The ac gain becomes inductive at high frequencies. Adding a small ceramic is 1. The AD830 offers the advantages of high CMRR, precise or polystyrene capacitor on the order of 0.01 μF that does not gain, offset, and high-impedance inputs when compared with a become inductive until negligibly higher frequencies maintains discrete implementation. For more information regarding the AD830, see the AD830 data sheet. a low impedance over a wide frequency range. +12V AD876 0.1 C1 R1 2V V +2V V B AIN IN 0 AD876 R2 V I B B C2 AD830 AIN 3V V BIAS V B 0.1 Figure 13. AC-Coupled Inputs –12V There are additional considerations when choosing the resistor REFBS values. The ac-coupling capacitors integrate the switching transients present at the input of the AD876 and cause a net dc Figure 15. Level Shifting with the AD830 , to flow into the input. The magnitude of this bias current, I B bias current increases with increasing dc signal level and also REFERENCE INPUT DRIVING THE REFERENCE increases with sample frequency. This bias current will result in TERMINALS . If it is necessary to compen- an offset error of (R1 + R2) × I B The AD876 requires an external reference on pins REFTF and sate this error, consider making R2 negligibly small or modify- REFBF. The AD876 provides reference sense pins, REFTS to account for the resultant offset. ing V BIAS and REFBS, to minimize voltage drops caused by external and internal wiring resistance. A resistor ladder, nominally 250 Ω, As an example, assume that the input to the AD876 must have connects pins REFTF and REFBF. a dc bias of 3 V and the minimum expected signal frequency is –8– REV. B AD876 ance changes associated with the reference inputs. The simpli- Figure 16 shows the equivalent input structure for the AD876 fied diagram of Figure 16 shows that the reference pins connect reference pins. There is approximately 5 Ω of resistance between to a capacitor for one-half of the clock period. The size of the both the REFTF and REFBT pins and the reference ladder. If capacitor is a function of the analog input voltage. the force-sense connections are not used, the voltage drop across the 5 Ω resistors will result in a reduced voltage appear- The external reference must be able to maintain a low imped- ing across the ladder resistance. This reduces the input span of ance over all frequencies of interest in order to provide the charge the converter. Applying a slightly larger span between the REFTF required by the capacitance. By supplying the requisite charge, and REFBF pins compensates this error. Note that the tem- the reference voltages will be relatively constant and perfor- perature coefficients of the 5 Ω resistors are 1350 ppm. The mance will not degrade. For some reference configurations, user should consider the effects of temperature when not using voltage transients will be present on the reference lines; this a force-sense reference configuration. is particularly true during the falling edge of CLK. It is impor- tant that the reference recovers from the transients and settles to AD876 5V the desired level of accuracy prior to the rising edges of CLK. REFTF There are several reference configurations suitable for the CLK REFTS V1 AD876 depending on the application, desired level of accuracy, R LADDER C (V ) and cost trade-offs. The simplest configuration, shown in Fig- DACS IN 250V ure 18, utilizes a resistor string to generate the reference volt- REFBS V2 CLK ages from the converter’s analog power supply. The 0.1 μF 5V bypass capacitors effectively reduce high-frequency transients. REFBF The 10 μF capacitors act to reduce the impedances at the REFTF and REFBF pins at lower frequencies. As input fre- Figure 16. AD876 Equivalent Reference Structure quencies approach dc, the capacitors become ineffective, and Do not connect the REFTS and REFBS pins in configurations small voltage deviations will appear across the biasing resistors. that do not use a force-sense reference. Connecting the force This application can maintain 10-bit accuracy for input frequen- and sense lines together allows current to flow in the sense lines. cies above approximately 200 Hz. 8-bit applications can use this Any current allowed to flow through these lines must be negligi- circuit for input frequencies above approximately 50 Hz. bly small. Current flow causes voltage drops across the resis- tance in the sense lines. Because the internal D/As of the AD876 AD876 tap different points along the sense lines, each D/A REFTS NC would receive a slightly different reference voltage if current were flowing in these wires. To avoid this undesirable condition, 140V (61%) 4V REFTF leave the sense lines unconnected. Any current allowed to flow +5V 10mF 0.1mF through these lines must be negligibly small (<100 μA). 250V 10mF (615%) The voltage drop across the internal resistor ladder determines 250V (61%) 2V the input span of the AD876. The driving voltages required at REFBF the V1 and V2 points are respectively +4 V and +2 V. Calculate 0.1mF 10mF the full-scale input span from the equation NC REFBS Input Span (V ) = REFTS ± REFBS NC = NO CONNECT This results in a full-scale input span of approximately +2 V Figure 18. Low Cost Reference Circuit when REFTS = +4 V and REFBS = +2 V In order to maintain This reference configuration provides the lowest cost but has the requisite 2 V drop across the internal ladder, the external several disadvantages. These disadvantages include poor dc reference must be capable of providing approximately 8.0 mA. power supply rejection and poor accuracy due to the variability The user has flexibility in determining both the full-scale span of of the internal and external resistors. the analog input and where to center this voltage. Figure 17 The AD876 offers force-sense reference connections to elimi- shows the range over which the AD876 can operate without nate the voltage drops associated with the internal connections degrading the typical performance. to the reference ladder. Figure 19 shows a suggested circuit (2.5, 4.5) (1.6, 4.5) using an AD826 dual, high speed op amp. This configuration 4.5 uses 3.6 V and 1.6 V reference voltages for REFT and REFB, 4.0 respectively. The connections shown in Figure 19 configure the 3.5 op amps as voltage followers. (1.6, 3.5) (2.5, 3.5) 3.0 2.5 1.0 1.5 2.0 2.5 3.0 REFBF, REFBS Figure 17. AD876 Reference Ranges While the previous issues address the dc aspects of the AD876 reference, the user must also be aware of the dynamic imped- REV. B –9– REFTF, REFTS AD876 C3 common ground, are effectively removed by the AD876’s high 0.1mF common-mode rejection. AD876 High frequency noise sources, V and V , are shunted to N1 N2 REFTS ground by decoupling capacitors. Any voltage drops between +5V C4 the analog input ground and the reference bypassing points will 6 0.1mF 8 7 be treated as input signals by the converter via the reference REFTF 5 REFT 1/2 C2 inputs. Consequently, the reference decoupling capacitors AD826 0.1mF should be connected to the same analog ground point used to REFBS C5 define the analog input voltage. (For further suggestions, see 2 6 0.1mF the “Grounding and Layout Rules” section of the data sheet.) REFBF 3 REFB C1 4 0.1mF 1/2 AD826 V 4V N1 REFTF AD876 Figure 19. Kelvin Connected Reference Using the AD826 REFBF By connecting the op amp feedback through the sense connec- V 2V N2 AIN tions of the AD876, the outputs of the op amps automatically adjust to compensate for the voltage drops that occur within the converter. The AD826 has the advantage of being able to maintain stability while driving unlimited capacitive loads. As a result, 0.1 μF capacitors C1, C2, and C3 can connect directly to the outputs of the op amps. These decoupling capacitors Figure 21. Recommended Bypassing for the Reference reduce high frequency transients. Capacitors C4 and C5 shunt Inputs across the internal resistors of the force sense connections and prevent instability. CLOCK INPUT This configuration provides excellent performance and a mini- The AD876 clock input is buffered internally with an inverter mal number of components. The circuit also offers the advan- powered from the DRV pin. This feature allows the AD876 DD tage of operating from a single +5 V supply. While alternative to accommodate either +5 V or +3.3 V CMOS logic input sig- op amps may also be suitable, consider the stability of these op nal swings with the input threshold for the CLK pin nominally amps while driving capacitive loads. at DRV /2. DD The circuit shown in Figure 20 allows a wider selection of op The AD876’s pipelined architecture operates on both rising and amps when compared with the previous configuration. An falling edges of the input clock. To minimize duty cycle varia- tions the recommended logic family to drive the clock input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. AD876 CMOS logic provides both symmetrical voltage threshold levels 20kV REFTS and sufficient rise and fall times to support 20 MSPS operation. 47nF The AD876 is designed to support a conversion rate of 20 MSPS; 22mF 10V running the part at slightly faster clock rates may be possible, REFTF although at reduced performance levels. Conversely, some REFT 1/2 10mF 0.1mF OP-295 slight performance improvements might be realized by clocking 20kV the AD876 at slower clock rates. REFBS 47nF The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency; running at reduced 10V REFBF clock rates provides a reduction in power consumption. Figure REFB 1/2 0.1mF 10mF 8 illustrates this trade-off. OP-295 DIGITAL INPUTS AND OUTPUTS Figure 20. Kelvin Connected Reference Using the OP295 Each of the AD876 digital control inputs, THREE-STATE and OP295 dual, single-supply op amp provides stable 3.6 V and STBY, has an input buffer powered from the DRV supply DD 1.6 V reference voltages. The AD822 dual op amp is also suit- pins. With DRV set to +5 V, all digital inputs readily inter- DD able for single-supply applications. Each half of the OP295 is face with +5 V CMOS logic. For interfacing with lower voltage compensated to drive the 10 μF and 0.1 μF decoupling capaci- CMOS logic, DRV can be set to 3.3 V, effectively lowering DD tors at the REFTF and REFBF pins and maintain stability. the nominal input threshold of all digital inputs to 3.3 V/2 = 1.65 V. Like any high resolution converter, the layout and decoupling of the reference is critical. The actual voltage digitized by the The format of the digital output is straight binary. Table I shows AD876 is relative to the reference voltages. In Figure 21, for the output format for the case where REFTS = 4 V and REFBS example, the reference return and the bypass capacitors are = 2 V. connected to the shield of the incoming analog signal. Distur- bances in the ground of the analog input, that will be common- mode to the REFT, REFB, and AIN pins because of the –10– REV. B AD876 Table I. Output Data Format For DRV = 5 V, the AD876 output signal swing is compat- DD ible with both high speed CMOS and TTL logic families. For Approx. THREE- DATA TTL, the AD876 on-chip, output drivers were designed to AIN (V) STATE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 20 MSPS, other TTL >4 0 1111111111 families may be appropriate. For interfacing with lower voltage 4 0 1111111111 CMOS logic, the AD876 sustains 20 MSPS operation with 3 0 1000000000 DRV = 3.3 V. In all cases, check your logic family data DD 2 0 0000000000 sheets for compatibility with the AD876 Digital Specification <2 0 0000000000 table. X 1 ZZZZZZZZZZ THREE-STATE OUTPUTS A low power mode feature is provided such that for STBY = The digital outputs of the AD876 can be placed in a high im- HIGH and the clock disabled, the static power of the AD876 pedance state by setting the THREE-STATE pin to HIGH. will drop below 50 mW. This feature is provided to facilitate in-circuit testing or evaluation. Note that this function is not intended for enabling/ GROUNDING AND LAYOUT RULES disabling the ADC outputs from a bus at 20 MSPS. Also, to As is the case for any high performance device, proper ground- avoid corruption of the sampled analog signal during conversion ing and layout techniques are essential in achieving optimal (3.5 clock cycles), it is highly recommended that the AD876 performance. The analog and digital grounds on the AD876 outputs be enabled on the bus prior to the first sampling. For have been separated to optimize the management of return the purpose of budgetary timing, the maximum access and float currents in a system. It is recommended that a printed circuit delay times (t , t shown in Figure 15) for the AD876 are DD HL board (PCB) of at least 4 layers employing a ground plane and 150 ns. power planes be used with the AD876. The use of ground and power planes offers distinct advantages: THREE-STATE 1. The minimization of the loop area encompassed by a signal t and its return path. t DD HL D0–D9 2. The minimization of the impedance associated with ground HIGH IMPEDANCE ACTIVE and power paths. 3. The inherent distributed capacitor formed by the power Figure 22. High-Impedance Output Timing Diagram plane, PCB insulation, and ground plane. These characteristics result in both a reduction of electro- magnetic interference (EMI) and an overall improvement in performance. It is important to design a layout which prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD876. A solid ground plane under the AD876 is also acceptable if the power and ground return currents are managed carefully. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. For further layout suggestions, see the AD876 Evaluation Board data sheet. DIGITAL OUTPUTS Each of the on-chip buffers for the AD876 output bits (D0–D9) supply pins, separate from AV or is powered from the DRV DD DD . The output drivers are sized to handle a variety of logic DV DD families while minimizing the amount of glitch energy gener- ated. In all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level. REV. B –11– AD876 TP3 TP4 1 2 U4 CLK_IN U4 74F04 TP1 74F04 J1 4 3 3ST STBY +5VD +5VD VP6 VP5 R1 C50 JP4 51V JP1 10mF U1 P1 1 P1 2 U2 + AD876 74ALS541 P1 3 P1 4 1 15 14 G1 D9 R2* JP2 CLK DV 19 SS 11 P1 5 P1 6 G2 VP8 13 Y7 16 9 3_STATE 12 D8 R3* DRV A7 C62 SS Y6 P1 7 P1 8 8 17 12 9 0.1mF A6 13 STBY DB9 Y5 D7 R4* 7 A5 14 P1 9 P1 10 D5 18 11 8 Y4 DV DD DB8 D6 5 6 A4 R5* 15 Y3 D6 P1 11 P1 12 10 19 SUBST 7 DB7 5 A3 6 Y2 16 D7 REFTS D5 R6* A2 7 4 P1 13 P1 14 VP3 20 NC DB6 9 6 Y1 17 D8 A1 D4 R7* 8 3 Y0 18 REFTS DB5 D9 8 5 P1 15 P1 16 21 A0 2 REFTS 9 D3 R8* REFTF DB4 P1 17 P1 18 22 7 4 REFTF D2 NC R9* DB3 U3 23 6 3 P1 19 P1 20 REFBF DB2 1 D1 R10* G1 5 2 24 P1 21 P1 22 19 11 REFBF REFBS DB1 G2 D0 Y7 R11* 25 4 1 9 12 P1 23 P1 24 A7 CML DB0 Y6 REFBS 8 A6 13 26 3 0 Y5 AIN P1 25 P1 26 DRV DD 7 A5 14 D0 Y4 2 27 VP4 AV DD AV 0 A4 P1 27 P1 28 SS 6 15 Y3 D1 REFBS 1 A3 28 1 5 Y2 16 D2 P1 29 P1 30 A2 C64 2 4 Y1 17 D3 A1 0.1mF P1 31 P1 32 REFTF 3 Y0 REFBF 3 18 D4 R12* A0 VP1 4 VP2 2 P1 33 P1 34 P1 35 P1 36 74ALS541 C56 P1 37 P1 38 0.1mF P1 39 P1 40 C4 10mF + + C49 C2 +5VD 10mF 10mF R16 R17 +5VA *R2–R12 = 20V 1kV 1.13kV C54 DC_IN R18 0.1mF R14 1kV 100V EXT_CM23 INT_CM JP5 1 AIN TP18 C1 J2 0.1mF TP2 R15 51V C3 47mF Figure 23. AD876 Evaluation Board Schematic –12– REV. B + + AD876 Figure 24. Silkscreen Layer, Component Side PCXB Layout Figure 25. Silkscreen Layer, Circuit Side PCB Layout REV. B –13– AD876 Figure 26. Component Side PCB Layout Figure 27. Circuit Side PCB Layout –14– REV. B AD876 Figure 28. Ground Layer PCB Layout Figure 29. Power Layer PCB Layout REV. B –15– AD876 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). R-28 28-Lead Wide Body (SOIC) 0.7125 (18.10) 0.6969 (17.70) 28 15 1 14 0.1043 (2.65) PIN 1 0.0291 (0.74) x 45° 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0500 0.0192 (0.49) 0° 0.0118 (0.30) 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) 0.0040 (0.10) PLANE BSC 0.0091 (0.23) ST-48 28-Lead Plastic Thin Quad Flatpack (TQFP) 0.059 +0.008 –0.004 (1.50 +0.2 –0.1) 0.354 ± 0.008 (9.00 ± 0.2) SQ 0.055 ± 0.002 0.039 (1.00) 0.02 ± 0.008 (1.40 ± 0.05) REF (0.5 ± 0.2) 36 25 37 24 SEATING PLANE 0.276 ± 0.004 TOP VIEW (7.0 ± 0.1) (PINS DOWN) SQ 48 13 0.004 ± 0.002 1 12 (0.1 ± 0.05) 0° MIN (3.5° ± 3.5°) 0.02 ± 0.003 0.007 +0.003 –0.001 0.005 +0.002 –0.0008 (0.50 ± 0.08) (0.18 +0.08 –0.03) (0.127 +0.05 –0.02) RS-28 28-Lead Shrink Small Outline Package (SSOP) 0.407 (10.34) 0.397 (10.08) 28 15 1 14 0.07 (1.79) 0.078 (1.98) PIN 1 0.066 (1.67) 0.068 (1.73) 0.03 (0.762) 8° 0.0256 0.015 (0.38) 0° 0.022 (0.558) 0.008 (0.203) SEATING 0.009 (0.229) (0.65) 0.010 (0.25) PLANE 0.002 (0.050) BSC 0.005 (0.127) –16– REV. B 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.2992 (7.60) 0.205 (5.21) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PRINTED IN U.S.A. C1991a–0–1/98