ANALOG DEVICES AD8682

Dual/Quad Low Power, High Speed JFET Operational Amplifiers AD8682/AD8684 FEATURES PIN CONFIGURATIONS Low supply current: 250 μA/amp maximum OUT A 1 8 V+ AD8682 High slew rate: 9 V/μs –IN A 2 7 OUT B TOP VIEW +IN A 3 6 –IN B Bandwidth: 3.5 MHz typical (Not to Scale) V– 4 5 +IN B Low offset voltage: 1 mV maximum @ 25°C Low input bias current: 20 pA maximum @ 25°C Figure 1. 8-Lead SOIC_N and 8-Lead MSOP CMRR: 90 dB typical Fast settling time 14 OUT D Unity-gain stable OUT A 1 –IN A 2 13 –IN D APPLICATIONS +IN A 3 12 +IN D V+ 4 11 V– AD8684 Portable telecommunications +IN B 5 10 +IN C Low power industrial and instrumentation –IN B 6 9 –IN C Loop filters OUT B 7 8 OUT C Active and precision filters TOP VIEW (Not to Scale) Integrators Figure 2. 14-Lead SOIC_N and 14-Lead TSSOP Strain gauge amplifiers Portable medical instrumentation Supply current monitoring GENERAL DESCRIPTION The AD8682 and AD8684 are dual and quad low power, precision The devices are ideal for portable, low power applications, (1 mV) JFET amplifiers featuring excellent speed at low supply especially with high source impedance. The devices are unity-gain currents. The slew rate is typically 9 V/μs with a supply current stable and can drive higher capacity loads (G = 1, noninverting), under 250 μA per amplifier. These unity-gain stable amplifiers as an example of their excellent dynamic response over a wide have a typical gain bandwidth of 3.5 MHz. The JFET input stage range of conditions, delivering dc precision performance at low ensures bias current is typically a few picoamps and below quiescent currents. 125 pA maximum over the full temperature operating range. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06278-002 06278-001 AD8682/AD8684 TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution...................................................................................4  Applications ....................................................................................... 1  Typical Performance Characteristics ..............................................5  Pin Configurations ........................................................................... 1  Applications Information .............................................................. 10  General Description ......................................................................... 1  High-Side Signal Conditioning ................................................ 10  Revision History ............................................................................... 2  Phase Inversion ........................................................................... 10  Specif ica t ions ..................................................................................... 3  Active Filters ............................................................................... 10  Electrical Characteristics ............................................................. 3  Programmable State Variable Filter ......................................... 11  Absolute Maximum Ratings ............................................................ 4  Outline Dimensions ....................................................................... 12  Thermal Resistance ...................................................................... 4  Ordering Guide .......................................................................... 14  REVISION HISTORY 7/08—Rev. A to Rev. B Changes to Phase Inversion Section ............................................ 10 Deleted Figure 33 ............................................................................ 10 Added Figure 33 and Figure 34..................................................... 10 Updated Outline Dimensions ....................................................... 12 7/07—Rev. 0 to Rev. A Change to Figure 21 ......................................................................... 8 Change to Figure 31 ......................................................................... 9 10/06—Revision 0: Initial Version Rev. B | Page 2 of 16 AD8682/AD8684 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = ±15.0 V, T = 25°C, V = 0 V, unless otherwise noted. S A CM Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 0.35 1 mV AD8682 +25°C ≤ T ≤ +85°C 2.5 mV A −40°C ≤ T ≤ +25°C 3 mV A AD8684 +25°C ≤ TA ≤ +85°C 3.5 mV −40°C ≤ TA ≤ +25°C 4 mV Input Bias Current IB 6 20 pA −40°C ≤ T ≤ +85°C 125 pA A Input Offset Current I 20 pA OS −40°C ≤ T ≤ +85°C 100 pA A Input Voltage Range −11 +15 V Common-Mode Rejection Ratio CMRR −11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C 70 90 dB Large Signal Voltage Gain AVO RL = 10 kΩ 20 V/mV R = 10 kΩ, −40°C ≤ T ≤ +85°C 15 V/mV L A Offset Voltage Drift ΔV/ΔT 10 μV/°C OS Bias Current Drift ΔIB/ΔT 8 pA/°C OUTPUT CHARACTERISTICS Output Voltage High V R = 10 kΩ 13.5 13.9 V OH L Output Voltage Low VOL RL = 10 kΩ −13.9 −13.5 V Short-Circuit Limit ISC Source 3 10 mA Sink −12 −8 mA Open-Loop Output Impedance Z f = 1 MHz 200 Ω OUT POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C 92 114 dB Supply Current/Amplifier I V = 0 V, −40°C ≤ T ≤ +85°C 210 250 μA SY O A Supply Voltage Range V ±4.5 ±18 V S DYNAMIC PERFORMANCE Slew Rate SR R = 10 kΩ 7 9 V/μs L Full-Power Bandwidth BW 1% distortion 125 kHz P Settling Time tS To 0.01% 1.6 μs Gain Bandwidth Product GBP 3.5 MHz Phase Margin ØM 55 Degrees NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 1.3 μV p-p Voltage Noise Density en f = 1 kHz 36 nV/√Hz Current Noise Density i 0.01 pA/√Hz n Rev. B | Page 3 of 16 AD8682/AD8684 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Rating Table 3. Supply Voltage ±18 V Package Type θ θ Unit JA JC Input Voltage ±18 V 8-Lead MSOP [RM-8] 210 45 °C/W 1 Differential Input Voltage 36 V 8-Lead SOIC_N [R-8] 158 43 °C/W Output Short-Circuit Duration Indefinite 14-Lead TSSOP [RU-14] 180 35 °C/W Storage Temperature Range −65°C to +150°C 14-Lead SOIC_N [R-14] 120 36 °C/W Operating Temperature Range −40°C to +85°C Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C ESD CAUTION 1 For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 4 of 16 AD8682/AD8684 TYPICAL PERFORMANCE CHARACTERISTICS 80 180 70 V = ±15V V = ±15V S S T = 25°C T = 25°C A 60 A 60 135 50 A = 100 VCL 40 40 90 30 A = 10 VCL 20 45 20 10 A = 1 0 0 VCL 0 –10 –20 –45 –20 –90 –40 –30 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 3. AD8682 Open-Loop Gain and Phase vs. Frequency Figure 6. AD8682 Closed-Loop Gain vs. Frequency 45 30 V = ±15V S V = ±15V S R = 10kΩ L 40 R = 10kΩ L C = 50pF L 25 –SR 35 30 20 25 15 20 15 10 +SR 10 5 5 0 0 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 4. AD8682 Open-Loop Gain vs. Temperature Figure 7. Slew Rate vs. Temperature 80 1000 V = ±15V V = ±15V S S V = 0V R = 2kΩ CM L 70 V = 100mV p-p IN A = 1 VCL T = 25°C 60 A 100 +OS 50 –OS 40 10 30 20 1 10 0 0.1 0 100 200 300 400 500 –75 –50 –25 0 25 50 75 100 125 LOAD CAPACITANCE (pF) TEMPERATURE (°C) Figure 5. Small Signal Overshoot vs. Load Capacitance Figure 8. AD8682 Input Bias Current vs. Temperature Rev. B | Page 5 of 16 OPEN-LOOP GAIN (dB) OVERSHOOT (%) OPEN-LOOP GAIN (V/mV) 06278-005 06278-004 PHASE (Degree) 06278-003 CLOSED-LOOP GAIN (dB) INPUT BIAS CURRENT (pA) SLEW RATE (V/µs) 06278-007 06278-008 06278-006 AD8682/AD8684 1000 20 V = ±15V T = 25°C A S R = 10kΩ T = 25°C L A 15 V OH 10 100 5 0 –5 10 –10 V OL –15 1 –20 0 ±5 ±10 ±15 ±20 10 100 1k 10k FREQUENCY (Hz) SUPPLY VOLTAGE (V) Figure 9. Voltage Noise Density vs. Frequency Figure 12. Output Voltage Swing vs. Supply Voltage 1000 1000 V = ±15V S V = ±15V S T = 25°C A T = 25°C A 100 100 A = 100 VCL 10 10 A = 10 VCL 1 1 A = 1 VCL 0.1 0.1 –15 –10 –5 0 5 10 15 100 1k 10k 100k 1M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 10. Input Bias Current vs. Common-Mode Voltage Figure 13. Closed-Loop Output Impedance vs. Frequency 480 480 T = 25°C A 475 475 470 470 465 465 460 460 455 455 450 450 0 ±5 ±10 ±15 ±20 –50 –25 0 50 75 100 25 125 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 11. AD8682 Supply Current vs. Supply Voltage Figure 14. AD8682 Supply Current vs. Temperature Rev. B | Page 6 of 16 VOLTAGE NOISE DENSITY (nV/√Hz) SUPPLY CURRENT (µA) INPUT BIAS CURRENT (pA) 06278-010 06278-011 06278-009 OUTPUT IMPEDANCE (Ω) SUPPLY CURRENT (µA) OUTPUT VOLTAGE SWING (V) 06278-014 06278-012 06278-013 AD8682/AD8684 30 16 V = ±15V V = ±15V S S T = 25°C T = 25°C A A 14 R = 10kΩ L 25 V = 1 OL A VCL 12 20 10 V OH 15 8 6 10 4 5 2 0 0 100 1k 10k 100 1k 10k 100k 1M FREQUENCY (Hz) LOAD RESISTANCE (Ω) Figure 15. Absolute Output Voltage vs. Load Resistance Figure 18. Maximum Output Swing vs. Frequency 140 140 V = ±15V S V = ±15V S T = 25°C 120 A T = 25°C 120 A 100 100 +PSRR 80 80 60 60 40 40 20 –PSRR 20 0 0 –20 –20 –40 –40 –60 –60 100 1k 10k 100k 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. AD8682 PSRR vs. Frequency Figure 19. AD8682 CMRR vs. Frequency 14 20 V = ±15V S V =±15V S T = 25°C A 18 T = 25°C A 12 100 × AD8682 16 (200 OP AMPS) SINK 10 14 12 8 10 SOURCE 6 8 6 4 4 2 2 0 0 –50 –25 0 25 50 75 100 125 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 V (µV) OS TEMPERATURE (°C) Figure 20. AD8682 VOS Distribution Figure 17. AD8682 Short-Circuit Current vs. Temperature Rev. B | Page 7 of 16 SHORT-CIRCUIT CURRENT (mA) ABSOLUTE OUTPUT VOLTAGE (V) PSRR (dB) 06278-016 06278-015 06278-017 MAXIMUM OUTPUT SWING (V p-p) CMRR (dB) UNITS 06278-020 06278-019 06278-018 AD8682/AD8684 400 1000 V = ±15V S 360 300 × AD8682 (600 OP AMPS) 320 100 280 240 200 10 160 120 1 80 40 0 0.1 –75 –50 –25 0 25 50 75 100 125 041 82 16 20 24 28 32 36 TEMPERATURE (°C) TCV (µV/°C) OS Figure 21. AD8682 TCVOS Distribution SOIC_N Package Figure 24. AD8684 Input Bias Current vs. Temperature 50 950 45 945 40 940 35 935 30 25 930 20 925 15 920 10 915 5 0 910 –50 –25 0 25 50 75 100 125 010 20 30 40 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 22. AD8684 Open-Loop Gain vs. Temperature Figure 25. AD8684 Relative Supply Current vs. Supply Voltage 60 950 V = ±15V S T = 25°C A 945 50 A = 100 VCL 40 940 935 30 A = 10 VCL 20 930 925 10 A = 1 VCL 920 0 915 –10 910 –20 –50 –25 0 25 50 75 100 125 1k 10k 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 26. AD8684 Supply Current vs. Temperature Figure 23. AD8684 Closed-Loop Gain vs. Frequency Rev. B | Page 8 of 16 CLOSED-LOOP GAIN (dB) UNITS OPEN-LOOP GAIN (V/mV) 06278-022 06278-021 06278-023 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) INPUT BIAS CURRENT (pA) 06278-026 06278-025 06278-024 AD8682/AD8684 140 40 V = ±15V S V = ±15V S T = 25°C A 35 120 100 × AD8684 (400 OP AMPS) 30 100 PSRR+ 25 80 PSRR– 20 60 15 40 10 20 5 0 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 1k 10k 100k 1M 10M V (µV) FREQUENCY (Hz) OS Figure 27. AD8684 PSRR vs. Frequency Figure 30. AD8684 VOS Distribution Package 14 800 V = ±15V S 300 × AD8684 700 12 (1200 OP AMPS) SINK 600 10 SOURCE 500 8 400 6 300 4 200 2 100 0 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 –50 –25 0 25 50 75 100 125 TCV (µV/°C) TEMPERATURE (°C) OS Figure 28. AD8684 Short-Circuit Current vs. Temperature Figure 31. AD8684 TCVOS Distribution Package 140 V = ±15V S 120 100 80 60 40 20 0 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 29. AD8684 CMRR vs. Frequency Rev. B | Page 9 of 16 CMRR (dB) PSRR (dB) SHORT-CIRCUIT CURRENT (mA) 06278-028 06278-029 06278-027 UNITS UNITS 06278-031 06278-030 AD8682/AD8684 APPLICATIONS INFORMATION The AD8682 and AD8684 are dual and quad JFET op amps that current when the input exceeds the supply rail. The resistor are optimized for high speed at low power. This combination should be selected to limit the amount of input current below makes these amplifiers excellent choices for battery-powered or the absolute maximum rating. low power applications that require above average performance. V+ Applications benefiting from this performance combination D2 include telecommunications, geophysical exploration, portable R1 AD8682/ IN5711 10kΩ AD8684 medical equipment, and navigational instrumentation. V IN D1 V+ V OUT IN5711 V– HIGH-SIDE SIGNAL CONDITIONING D3 IN5711 There are many applications requiring the sensing of signals near the positive rail. The AD8682 and the AD8684 were tested and V– are guaranteed over a common-mode range (−11 V ≤ V ≤ CM Figure 33. Phase Reversal Solution Circuit +15 V) that includes the positive supply. The AD8682/AD8684 are commonly used in the sensing of power supply currents and in current sensing applications, such V = ±15V S as the partial circuit shown in Figure 32. In this circuit, the voltage drop across a low value resistor, such as the 0.1 Ω shown here, is amplified and compared to 7.5 V. The output can then be used for current limiting. 0.1Ω 15V 2 500kΩ R L 100kΩ 100kΩ V OUT 1/2 AD8682 V IN 500kΩ TIME (200µs/DIV) Figure 34. No Phase Reversal Figure 32. High-Side Signal Conditioning ACTIVE FILTERS PHASE INVERSION Most JFET input amplifiers invert the phase of the input signal The wide bandwidth and high slew rates of the AD8682/AD8684 if either input exceeds the input common-mode range. For the make either one an excellent choice for many filter applications. AD8682/AD8684, a negative signal in excess of 11 V causes There are many active filter configurations, but the four most phase inversion. This is caused by saturation of the input stage popular configurations are: Butterworth, elliptic, Bessel, and leading to the forward-biasing of a gate-drain diode. Phase Chebyshev. Each type has a response that is optimized for a reversal in AD8682/AD8684 can be prevented by using Schottky given characteristic, as shown in Table 4. diodes to clamp the input terminals to each other and to the supplies. In the simple buffer circuit below, D1 protects the op amp against phase reversal. R1, D2, and D3 limit the input Table 4. Type Selectivity Overshoot Phase Amplitude (Pass Band) Amplitude (Stop Band) Butterworth Moderate Good Maximum flat Chebyshev Good Moderate Nonlinear Equal ripple Elliptic Best Poor Equal ripple Equal ripple Bessel (Thompson) Poor Best Linear Rev. B | Page 10 of 16 06278-032 VOLTAGE (5V/DIV) 06278-033 06278-034 AD8682/AD8684 PROGRAMMABLE STATE VARIABLE FILTER The circuit shown in Figure 35 can be used to accurately program This cutoff frequency can be expressed as the Q factor; the cutoff frequency (fC); and the gain of a two- 1 D1 ⎛ ⎞ f = pole state variable filter. The AD8684 has been used in this ⎜ ⎟ C 2πR1C1⎝ 256⎠ design because of its high bandwidth, low power, and low noise. where D1 is the digital code for the DAC. This circuit takes only three packages to build because of the quad configuration of the op amps and DACs. DAC 3 is used to set the gain. The gain equation is The DACs shown are used in voltage mode; therefore, many R4 D3 ⎛ ⎞ Gain= ⎜ ⎟ values are dependent on the accuracy of the DAC only and not R5⎝ 256⎠ on the absolute values of the DAC resistive ladders. As a result, this DAC 2 is used to set the Q of the circuit. Adjusting this DAC makes the circuit unusually accurate for a programmable filter. controls the amount of feedback from the band-pass node to Adjusting DAC 1 changes the signal amplitude across R1; therefore, the input summing node. Note that the digital value of the the DAC attenuation × R1 determines the amount of signal current DAC is in the numerator; therefore, zero code is not a valid that charges the integrating capacitor, C1. operating point. R2 256 ⎛ ⎞ Q= ⎜ ⎟ R3⎝ D2⎠ R7 2kΩ R4 DAC 3 2kΩ V IN R5 C1 1/4 2kΩ 1000pF DAC 1 1/4 AD8684 1/4 DAC8408 R1 AD8684 C1 1/4 2kΩ 1000pF DAC 4 1/4 AD8684 1/4 DAC8408 R1 AD8684 1/4 2kΩ 1/4 AD8684 HIGH PASS 1/4 DAC8408 AD8684 LOW PASS R6 2kΩ BAND PASS R3 2kΩ DAC 2 R2 1/4 2kΩ 1/4 AD8684 1/4 DAC8408 AD8684 Figure 35. Programmable State Variable Filter Rev. B | Page 11 of 16 06278-035 AD8682/AD8684 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 36. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.38 0.60 0.23 0° 0.00 0.22 0.40 0.08 SEATING COPLANARITY PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 37. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. B | Page 12 of 16 012407-A AD8682/AD8684 8.75 (0.3445) 8.55 (0.3366) 8 14 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 38. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 MAX 0.20 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 39. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. B | Page 13 of 16 061908-A 060606-A AD8682/AD8684 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD8682ARZ −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8682ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8682ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8682ARMZ-R2 −40°C to +85°C 8-Lead MSOP RM-8 A1K 1 AD8682ARMZ-REEL −40°C to +85°C 8-Lead MSOP RM-8 A1K 1 AD8684ARZ −40°C to +85°C 14-Lead SOIC_N R-14 1 AD8684ARZ-REEL −40°C to +85°C 14-Lead SOIC_N R-14 1 AD8684ARZ-REEL7 −40°C to +85°C 14-Lead SOIC_N R-14 1 AD8684ARUZ −40°C to +85°C 14-Lead TSSOP RU-14 1 AD8684ARUZ-REEL −40°C to +85°C 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part. Rev. B | Page 14 of 16 AD8682/AD8684 NOTES Rev. B | Page 15 of 16 AD8682/AD8684 NOTES ©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06278-0-7/08(B) Rev. B | Page 16 of 16