ANALOG DEVICES AD8651

50 MHz, Precision, Low Distortion, Low Noise CMOS Amplifiers AD8651/AD8652 FEATURES PIN CONFIGURATIONS Bandwidth: 50 MHz @ 5 V Low noise: 4.5 nV/√Hz + OUT A 1 8 V NC 1 8 NC Offset voltage: 100 μV typical, specified over AD8652 –IN A 2 7 OUT B AD8651 + –IN 2 7 V entire common-mode range +IN A 3 TOP VIEW 6 –IN B +IN 3 TOP VIEW 6 OUT (Not to Scale) – (Not to Scale) V 4 5 +IN B Slew rate: 41 V/μs – V 4 5 NC Rail-to-rail input and output swing NC = NO CONNECT Input bias current: 1 pA Figure 1. 8-Lead MSOP (RM-8) Figure 2. 8-Lead MSOP (RM-8) Single-supply operation: 2.7 V to 5.5 V Space-saving MSOP and SOIC_N packaging NC 1 8 NC + OUT A 1 8 V + –IN 2 AD8651 7 V AD8652 –IN A 2 7 OUT B +IN 3 6 OUT TOP VIEW APPLICATIONS +IN A 3 6 –IN B TOP VIEW (Not to Scale) – V 4 5 NC (Not to Scale) – V 4 5 +IN B Optical communications NC = NO CONNECT Laser source drivers/controllers Figure 3. 8-Lead SOIC_N (R-8) Figure 4. 8-Lead SOIC_N (R-8) Broadband communications High speed ADCs and DACs Microwave link interface Cell phone PA control Video line drivers Audio GENERAL DESCRIPTION The AD865x family features the newest generation of DigiTrim® in-package trimming. This new generation measures and The AD865x family consists of high precision, low noise, low corrects the offset over the entire input common-mode range, distortion, rail-to-rail CMOS operational amplifiers that run providing less distortion from V variation than is typical of OS from a single-supply voltage of 2.7 V to 5.5 V. other rail-to-rail amplifiers. Offset voltage and CMRR are both The AD865x family is made up of rail-to-rail input and output specified and guaranteed over the entire common-mode range amplifiers with a gain bandwidth of 50 MHz and a typical as well as over the extended industrial temperature range. voltage offset of 100 μV across common mode from a 5 V The AD865x family is offered in the narrow 8-lead SOIC supply. It also features low noise—4.5 nV/√Hz. package and the 8-lead MSOP package. The amplifiers are The AD865x family can be used in communications specified over the extended industrial temperature range applications, such as cell phone transmission power control, fiber (−40°C to +125°C). optic networking, wireless networking, and video line drivers. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03301-002 03301-001 03301-004 03301-003 AD8651/AD8652 TABLE OF CONTENTS Features .............................................................................................. 1 Input Protection ..................................................................... 15 Applications....................................................................................... 1 Overdrive Recovery ............................................................... 15 Pin Configurations ........................................................................... 1 Layout, Grounding, and Bypassing Considerations.............. 15 General Description ......................................................................... 1 Power Supply Bypassing........................................................ 15 Specifications..................................................................................... 3 Grounding............................................................................... 15 Electrical Characteristics............................................................. 3 Leakage Currents.................................................................... 15 Absolute Maximum Ratings............................................................ 5 Input Capacitance .................................................................. 16 Thermal Resistance ...................................................................... 5 Output Capacitance ............................................................... 16 ESD Caution.................................................................................. 5 Settling Time........................................................................... 16 Typical Performance Characteristics ............................................. 6 THD Readings vs. Common-Mode Voltage ...................... 16 Applications..................................................................................... 14 Driving a 16-Bit ADC............................................................ 17 Theory of Operation .................................................................. 14 Outline Dimensions ....................................................................... 18 Rail-to-Rail Output Stage...................................................... 14 Ordering Guide .......................................................................... 19 Rail-to-Rail Input Stage......................................................... 14 REVISION HISTORY Change to Input Protection section .............................................. 15 8/06—Rev. B. to Rev. C Changes to Ordering Guide ........................................................... 20 Changes to Figure 1 to Figure 4...................................................... 1 Changes to Figure 7 and Figure 9................................................... 6 6/04—Rev. 0 to Rev. A Changes to Figure 23........................................................................ 9 Change to Figure 18 .............................................................................8 Changes to Figure 53...................................................................... 14 Change to Figure 21 .............................................................................9 Updated Outline Dimensions ....................................................... 18 Change to Figure 29 .............................................................................10 Changes to Ordering Guide .......................................................... 19 Change to Figure 30 .............................................................................10 Change to Figure 43 .............................................................................12 9/04—Rev. A to Rev. B Change to Figure 44 .............................................................................12 Added AD8652 ....................................................................Universal Change to Figure 47 .............................................................................13 Change to General Description ....................................................... 1 Change to Figure 57 .............................................................................17 Changes to Electrical Characteristics ............................................. 3 Changes to Absolute Maximum Ratings ........................................ 5 10/03 Revision 0: Initial Version Change to Figure 23 .......................................................................... 9 Change to Figure 26 .......................................................................... 9 Change to Figure 36 ........................................................................ 11 Change to Figure 42 ........................................................................ 12 Change to Figure 49 ........................................................................ 13 Change to Figure 51 ........................................................................ 13 Inserted Figure 52............................................................................ 13 Change to Theory of Operation section....................................... 14 Rev. C | Page 2 of 20 AD8651/AD8652 SPECIFICATIONS ELECTRICAL CHARACTERISTICS + – + V = 2.7 V, V = 0 V, V = V /2, T = 25°C, unless otherwise specified. CM A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS AD8651 0 V ≤ VCM ≤ 2.7 V 100 350 μV –40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 2.7 V 1.4 mV –40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V 1.6 mV AD8652 0 V ≤ VCM ≤ 2.7 V 90 300 μV –40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V 0.4 1.3 mV Offset Voltage Drift TCVOS 4 μV/°C Input Bias Current IB 1 10 pA –40°C ≤ TA ≤ +125°C 600 pA Input Offset Current IOS 1 10 pA –40°C ≤ T ≤ +85°C 30 pA A –40°C ≤ T ≤ +125°C 600 pA A Input Voltage Range V –0.1 +2.8 V CM Common-Mode Rejection Ratio CMRR + AD8651 V = 2.7 V, –0.1 V < V < +2.8 V 75 95 dB CM –40°C ≤ T ≤ +85°C, –0.1 V < V < +2.8 V 70 88 dB A CM –40°C ≤ T ≤ +125°C, –0.1 V < V < +2.8 V 65 85 dB A CM + AD8652 V = 2.7 V, –0.1 V < V < +2.8 V 77 95 dB CM –40°C ≤ T ≤ +125°C, –0.1 V < V < +2.8 V 73 90 dB A CM Large Signal Voltage Gain A R = 1 kΩ, 200 mV < V < 2.5 V 100 115 dB VO L O RL = 1 kΩ, 200 mV < VO < 2.5 V, TA = 85°C 100 114 dB RL = 1 kΩ, 200 mV < VO < 2.5 V, TA = 125°C 95 108 dB OUTPUT CHARACTERISTICS Output Voltage High V I = 250 μA, –40°C ≤ T ≤ +125°C 2.67 V OH L A Output Voltage Low V I = 250 μA, –40°C ≤ T ≤ +125°C 30 mV OL L A Short-Circuit Limit ISourcing 80 mA SC Sinking 80 mA Output Current I 40 mA O POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V, VCM = 0 V 76 94 dB –40°C ≤ TA ≤ +125°C 74 93 dB Supply Current I SY AD8651 I = 0 9 12 mA O –40°C ≤ T ≤ +125°C 14.5 mA A AD8652 I = 0 17.5 19.5 mA O –40°C ≤ T ≤ +125°C 22.5 mA A INPUT CAPACITANCE CIN Differential 6 pF Common Mode 9 pF DYNAMIC PERFORMANCE Slew Rate SR G = 1, R = 10 kΩ 41 V/μs L Gain Bandwidth Product GBP G = 1 50 MHz Settling Time, 0.01% G = ±1, 2 V step 0.2 μs + Overload Recovery Time VIN × G = 1.48 V 0.1 μs Total Harmonic Distortion + Noise THD + N G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p 0.0006 % NOISE PERFORMANCE Voltage Noise Density e f = 10 kHz 5 nV/√Hz n f = 100 kHz 4.5 nV/√Hz Current Noise Density i f = 10 kHz 4 fA/√Hz n Rev. C | Page 3 of 20 AD8651/AD8652 + – + V = 5 V, V = 0 V, V = V /2, T = 25°C, unless otherwise specified. CM A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS AD8651 0 V ≤ VCM ≤ 5 V 100 350 μV –40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 5 V 1.4 mV –40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V 1.7 mV AD8652 0 V ≤ VCM ≤ 5 V 90 300 μV –40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V 0.4 1.4 mV Offset Voltage Drift TCVOS 4 μV/°C Input Bias Current IB 1 10 pA –40°C ≤ TA ≤ +85°C 30 pA –40°C ≤ TA ≤ +125°C 600 pA Input Offset Current I 1 10 pA OS –40°C ≤ T ≤ +85°C 30 pA A –40°C ≤ T ≤ +125°C 600 pA A Input Voltage Range V –0.1 +5.1 V CM Common-Mode Rejection Ratio CMRR AD8651 0.1 V < V < 5.1 V 80 95 dB CM –40°C ≤ T ≤ +85°C, 0.1 V < V < 5.1 V 75 94 dB A CM –40°C ≤ T ≤ +125°C, 0.1 V < V < 5.1 V 70 90 dB A CM AD8652 0.1 V < V < 5.1 V 84 100 dB CM –40°C ≤ T ≤ +125°C, 0.1 V < V < 5.1 V 76 95 dB A CM Large Signal Voltage Gain A R = 1 kΩ, 200 mV < V < 4.8 V 100 115 dB VO L O RL = 1 kΩ, 200 mV < VO < 4.8 V, TA = 85°C 98 114 dB RL = 1 kΩ, 200 mV < VO < 4.8 V, TA = 125°C 95 111 dB OUTPUT CHARACTERISTICS Output Voltage High V I = 250 μA, –40°C ≤ T ≤ +125°C 4.97 V OH L A Output Voltage Low V I = 250 μA, –40°C ≤ T ≤ +125°C 30 mV OL L A Short-Circuit Limit ISourcing 80 mA SC Sinking 80 mA Output Current I 40 mA O POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V, VCM = 0 V 76 94 dB –40°C ≤ TA ≤ +125°C 74 93 dB Supply Current I SY AD8651 I = 0 9.5 14.0 mA O –40°C ≤ T ≤ +125°C 15 mA A AD8652 I = 0 17.5 20.0 mA O –40°C ≤ T ≤ +125°C 23.5 mA A INPUT CAPACITANCE CIN Differential 6 pF Common Mode 9 pF DYNAMIC PERFORMANCE Slew Rate SR G = 1, R = 10 kΩ 41 V/μs L Gain Bandwidth Product GBP G = 1 50 MHz Settling Time, 0.01% G = ±1, 2 V step 0.2 μs + Overload Recovery Time VIN × G = 1.2 V 0.1 μs Total Harmonic Distortion + Noise THD + N G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p 0.0006 % NOISE PERFORMANCE Voltage Noise Density e f = 10 kHz 5 nV/√Hz n f = 100 kHz 4.5 nV/√Hz Current Noise Density i f = 10 kHz 4 fA/√Hz n Rev. C | Page 4 of 20 AD8651/AD8652 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 3. THERMAL RESISTANCE Parameter Rating JA is specified for the worst-case conditions, that is, a device Supply Voltage 6.0 V soldered in a circuit board for surface-mount packages. Input Voltage GND to V + 0.3 V S Table 4. Thermal Resistance Differential Input Voltage ±6.0 V Package Type θ θ Unit JA JC Output Short-Circuit Duration to GND Indefinite 8-Lead MSOP (RM) 210 45 °C/W Electrostatic Discharge (HBM) 4000 V 8-Lead SOIC_N (R) 158 43 °C/W Storage Temperature Range RM, R Package −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range RM, R Package −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 5 of 20 AD8651/AD8652 TYPICAL PERFORMANCE CHARACTERISTICS 60 100 V = 5V V = ±2.5V S S V = 0V CM 50 80 40 60 30 40 20 20 10 0 0 –20 01 23 4 5 6 COMMON-MODE VOLTAGE (V) V (µV) OS Figure 5. Input Offset Voltage Distribution Figure 8. Input Offset Voltage vs. Common-Mode Voltage 300 500 V = ±2.5V V = ±2.5V S S V = 0V CM 200 400 100 300 0 200 –100 100 –200 –300 0 –50 0 50 100 150 04 200 60 80 100 120140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. Input Offset Voltage vs. Temperature Figure 9. Input Bias Current vs. Temperature 60 10 V = ±2.5V S V =0V CM T : –40°C TO +125°C A 50 8 40 6 30 4 20 2 10 0 0 01 2 34 5 67 8 9 10 11 02 1 3 4 56 TCV (µV/°C) SUPPLY VOLTAGE (V) OS Figure 7. TCVOS Distribution Figure 10. Supply Current vs. Supply Voltage Rev. C | Page 6 of 20 V (µV) OS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS –200 –160 –120 –80 –40 0 40 80 120 160 200 03301-007 03301-005 03301-006 INPUT BIAS CURRENT (pA) SUPPLY CURRENT (mA) V (µV) OS 03301-010 03301-008 03301-009 AD8651/AD8652 12 2.50 V = ±2.5V V = 5V S S I = 250µA L 11 2.00 10 1.50 9 1.00 8 0.50 7 6 0 –50 0 50 100 150 –50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Supply Current vs. Temperature Figure 14. Output Voltage Swing Low vs. Temperature 500 100 V =±2.5V S V = ±2.5V S 400 80 300 60 V OH 200 40 V OL 100 20 0 0 020 40 60 80 100 10 100 1k 10k 100k 1M 10M CURRENT LOAD (mA) FREQUENCY (Hz) Figure 12. Output Voltage to Supply Rail vs. Load Current Figure 15. CMRR vs. Frequency 4.997 110 V = 5V V = ±2.5V S S I = 250µA L 4.996 105 4.995 4.994 100 4.993 4.992 95 4.991 4.990 90 –50 0 50 100 150 –50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Output Voltage Swing High vs. Temperature Figure 16. CMRR vs. Temperature Rev. C | Page 7 of 20 OUTPUT SWING HIGH (V) (V – V ) (mV) SUPPLY CURRENT (mA) SY OUT 03301-013 03301-012 03301-011 CMRR (dB) CMRR (dB) OUTPUT SWING LOW (mV) 03301-016 03301-015 03301-014 AD8651/AD8652 100 100 V = ±2.5V S 97 94 91 10 88 85 82 1 –50 0 50 100 150 10 100 1k 10k 100k TEMPERATURE (°C) FREQUENCY (Hz) Figure 17. CMRR vs. Temperature Figure 20. Voltage Noise Density vs. Frequency 100 80 V = ±2.5V V = ±2.5V S S 80 60 +PSRR 60 –PSRR 40 40 20 20 0 0 1 10 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 18. PSRR vs. Frequency Figure 21. Current Noise Density vs. Frequency 100 V = ±2.5V S V = ±2.5V S V = 6.4V IN V IN 95 V OUT 0 90 85 80 –50 0 50 100 150 TIME (200µs/DIV) TEMPERATURE (°C) Figure 19. PSRR vs. Temperature Figure 22. No Phase Reversal Rev. C | Page 8 of 20 PSRR (dB) PSRR (dB) CMRR (dB) 03301-019 03301-017 03301-018 CURRENT NOISE DENSITY (fA/√Hz) VOLTAGE NOISE DENSITY (nV/√Hz) VOLTAGE (1V/DIV) 03301-022 03301-021 03301-020 AD8651/AD8652 140 0 60 V = ±2.5V V = ±2.5V S S R = 1MΩ L 120 C = 47pF L 40 G = 100 100 –45 80 20 G = 10 60 –90 0 40 G = 1 20 –135 –20 0 –20 –180 –40 10 100 1k 10k 100k 1M 10M 100M 5k 50k 500k 5M 50M 300M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Open-Loop Gain and Phase vs. Frequency Figure 26. Closed-Loop Gain vs. Frequency 117 6 V = ±2.5V S R = 1kΩ L 5 116 V = 5V S 4 115 3 114 V = 2.7V S 2 113 1 112 0 –50 0 50 100 150 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 24. Open-Loop Gain vs. Temperature Figure 27. Maximum Output Swing vs. Frequency 140 V = ±2.5V V =±2.5V S S C = 47pF L I =250µA 130 L A = 1 V I =2.5mA L 120 I =4.2mA L 110 100 90 80 70 60 0 50 100 150 200 250 TIME (100µs/DIV) OUTPUT VOLTAGE SWING FROM THE RAILS (mV) Figure 25. Open-Loop Gain vs. Output Voltage Swing Figure 28. Large Signal Response Rev. C | Page 9 of 20 OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) 03301-025 03301-024 PHASE (Degrees) 03301-023 MAXIMUM OUTPUT SWING (V) CLOSED-LOOP GAIN (dB) VOLTAGE (1V/DIV) 03301-028 03301-027 03301-026 AD8651/AD8652 V = ±2.5V S V = ±2.5V S V = 200mV IN V = 200mV IN A = 1 V GAIN = –15 0V OUTPUT –2.5V 200mV INPUT 0V TIME (10µs/DIV) TIME (200ns/DIV) Figure 29. Small Signal Response Figure 32. Positive Overload Recovery Time 30 40 V = ±2.5V V = ±2.5V S S V = 200mV IN A = 1 25 V 30 20 –OS 20 15 GAIN = 10 +OS 10 GAIN = 1 10 5 GAIN = 100 0 0 02 100 30 40 50 6070 10 100 1k 10k 100k CAPACITANCE (pF) FREQUENCY (Hz) Figure 30. Small Signal Overshoot vs. Load Capacitance Figure 33. Output Impedance vs. Frequency 60 V = ±2.5V S V = ±1.35V S 2.5V V = 200mV IN V = 0V CM GAIN = –15 50 40 0V 30 0V 20 –200mV 10 0 TIME (200ns/DIV) V (µV) OS Figure 31. Negative Overload Recovery Time Figure 34. Input Offset Voltage Distribution Rev. C | Page 10 of 20 SMALL SIGNAL OVERSHOOT (%) VOLTAGE (100mV/DIV) 03301-031 03301-029 03301-030 OUTPUT IMPEDANCE (Ω) NUMBER OF AMPLIFIERS –200 –160 –120 –80 –40 0 40 80 120 160 200 03301-032 03301-034 03301-033 AD8651/AD8652 300 500 V = ±1.35V V = ±1.35V S S = 0V V CM 200 400 100 300 V OH 0 200 V –100 OL 100 –200 –300 0 –50 0 50 100 150 020 40 60 80 100 TEMPERATURE (°C) CURRENT LOAD (mA) Figure 35. Input Offset Voltage vs. Temperature Figure 38. Output Voltage to Supply Rail vs. Load Current 80 2.697 V = 2.7V V = 2.7V S S I = 250µA L 2.696 60 2.695 40 2.694 2.693 20 2.692 0 2.691 –20 2.690 012 3 –50 0 50 100 150 INPUT COMMON-MODE VOLTAGE (V) TEMPERATURE (°C) Figure 36. Input Offset Voltage vs. Common-Mode Voltage Figure 39. Output Voltage Swing High vs. Temperature 11 3.00 V = ±1.35V V = 2.7V S S I = 250µA L 2.50 10 2.00 9 1.50 8 1.00 7 0.50 6 0 –50 0 50 100 150 –50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 37. Supply Current vs. Temperature Figure 40. Output Voltage Swing Low vs. Temperature Rev. C | Page 11 of 20 SUPPLY CURRENT (mA) V (µV) INPUT OFFSET VOLTAGE (µV) OS 03301-036 03301-037 03301-035 OUTPUT SWING LOW (mV) OUTPUT SWING HIGH (V) (V – V ) (mV) SY OUT 03301-040 03301-039 03301-038 AD8651/AD8652 30 V = ±1.35V V = ±1.35V S S A = 1 V = 200mV V IN 25 20 15 –OS 10 +OS 5 0 02 100 30 40 50 6070 TIME (200µs/DIV) CAPACITANCE (pF) Figure 41. No Phase Reversal Figure 44. Small Signal Overshoot vs. Load Capacitance V = ±1.35V S V = ±1.35V S C = 47pF V = 200mV L IN A = 1 GAIN = –10 V 1.35V 0V 0V –200mV TIME (100µs/DIV) TIME (200ns/DIV) Figure 42. Large Signal Response Figure 45. Negative Overload Recovery Time V = ±1.35V S V = ±1.35V S V = 200mV IN V = 200mV IN C = 47pF L GAIN = –10 A = 1 0V V –1.35V 200mV 0V TIME (10µs/DIV) TIME (200ns/DIV) Figure 43. Small Signal Response Figure 46. Positive Overload Recovery Time Rev. C | Page 12 of 20 VOLTAGE (1V/DIV) VOLTAGE (100mV/DIV) VOLTAGE (500mV/DIV) 03301-043 03301-042 03301-041 SMALL SIGNAL OVERSHOOT (%) 03301-046 03301-045 03301-044 AD8651/AD8652 100 120 V = ±1.35V V = ±1.35V S S R = 1kΩ L 118 80 116 60 114 40 112 20 110 0 108 10 100 1k 10k 100k 1M 10M –50 0 50 100 150 FREQUENCY (Hz) TEMPERATURE (°C) Figure 47. CMRR vs. Frequency Figure 50. Open-Loop Gain vs. Temperature 100 60 V = ±1.35V V = ±1.35V S S R = 1MΩ L C = 47pF L 40 80 G = 100 +PSRR 20 60 –PSRR G = 10 40 0 G = 1 –20 20 0 –40 1 10 100 1k 10k 100k 1M 10M 5k 50k 500k 5M 50M 300M FREQUENCY (Hz) FREQUENCY (Hz) Figure 48. PSRR vs. Frequency Figure 51. Closed-Loop Gain vs. Frequency 0 140 0 R1 V = ±1.35V S 10kΩ +2.5V 120 R2 –20 100Ω V+ V– V IN 100 –45 –40 28mV p-p V OUT V– V+ 80 –60 –2.5V 60 –90 –80 40 –100 20 –135 –120 0 V = ±2.5V S –140 –20 –180 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 49. Open-Loop Gain and Phase vs. Frequency Figure 52. Channel Separation vs. Frequency. Rev. C | Page 13 of 20 OPEN-LOOP GAIN (dB) PSRR (dB) CMRR (dB) 03301-047 03301-048 PHASE (Degrees) 03301-049 CHANNEL SEPARATION (dB) CLOSED-LOOP GAIN (dB) A (dB) VO 03301-052 03301-050 03301-051 AD8651/AD8652 APPLICATIONS THEORY OF OPERATION The NMOS and PMOS input stages are separately trimmed using DigiTrim to minimize the offset voltage in both differen- The AD865x family consists of voltage feedback, rail-to-rail tial pairs. Both NMOS and PMOS input differential pairs are input and output precision CMOS amplifiers that operate from active in a 500 mV transition region when the input common- 2.7 V to 5.5 V of power supply voltage. These amplifiers use mode voltage is approximately 1.5 V below the positive supply Analog Devices, Inc. DigiTrim technology to achieve a higher voltage. A special design technique improves the input offset degree of precision than is available from most CMOS voltage in the transition region that traditionally exhibits a amplifiers. DigiTrim technology, used in a number of Analog slight V variation. As a result, the common-mode rejection OS Devices amplifiers, is a method of trimming the offset voltage of ratio is improved within this transition band. Compared to the the amplifier after it has been assembled. The advantage of Burr Brown OPA350 amplifier, shown in Figure 53, the post-package trimming is that it corrects any offset voltages AD865x, shown in Figure 54, exhibits much lower offset voltage caused by the mechanical stresses of assembly. shift across the entire input common-mode range, including the The AD865x family is available in standard op amp pinouts, transition region. making DigiTrim completely transparent to the user. The input 600 stage of the amplifiers is a true rail-to-rail architecture, allowing the input common-mode voltage range of the op amp to extend 400 to both positive and negative supply rails. The open-loop gain of the AD865x with a load of 1 kΩ is typically 115 dB. 200 The AD865x can be used in any precision op amp application. 0 The amplifiers do not exhibit phase reversal for common-mode voltages within the power supply. With voltage noise of –200 4.5 nV/√Hz and –105 dB distortion for 10 kHz, 2 V p-p signals, the AD865x is a great choice for high resolution data –400 acquisition systems. Their low noise, sub-pA input bias current, precision offset, and high speed make them superb preamps for –600 fast photodiode applications. The speed and output drive 014 2356 COMMON-MODE VOLTAGE (V) capabilities of the AD865x also make the amplifiers useful in Figure 53. Input Offset Distribution over Common-Mode video applications. Voltage for the OPA350 Rail-to-Rail Output Stage The voltage swing of the output stage is rail-to-rail and is 600 achieved by using an NMOS and PMOS transistor pair con- nected in a common source configuration. The maximum 400 output voltage swing is proportional to the output current, and larger currents will limit how close the output voltage can get to 200 the proximity of the output voltage to the supply rail. This is a characteristic of all rail-to-rail output amplifiers. With 40 mA of 0 output current, the output voltage can reach within 5 mV of the positive and negative rails. At light loads of >100 kΩ, the output –200 swings within ~1 mV of the supplies. –400 Rail-to-Rail Input Stage The input common-mode voltage range of the AD865x extends –600 to both positive and negative supply voltages. This maximizes 014 2356 COMMON-MODE VOLTAGE (V) the usable voltage range of the amplifier, an important feature Figure 54. Input Offset Distribution over Common-Mode for single-supply and low voltage applications. This rail-to-rail Input Protection for the AD865x input range is achieved by using two input differential pairs, one NMOS and one PMOS, placed in parallel. The NMOS pair is active at the upper end of the common-mode voltage range, and the PMOS pair is active at the lower end of the common-mode range. Rev. C | Page 14 of 20 V (µV) V (µV) OS OS 03301-061 03301-053 AD8651/AD8652 Input Protection Bypassing schemes are designed to minimize the supply impedance at all frequencies with a parallel combination of As with any semiconductor device, if a condition exists for the capacitors of 0.1 μF and 4.7 μF. Chip capacitors of 0.1 μF (X7R input voltage to exceed the power supply, the device input or NPO) are critical and should be as close as possible to the overvoltage characteristic must be considered. The inputs of the amplifier package. The 4.7 μF tantalum capacitor is less critical AD865x family are protected with ESD diodes to either power for high frequency bypassing, and, in most cases, only one is supply. Excess input voltage energizes internal PN junctions in needed per board at the supply inputs. the AD865x, allowing current to flow from the input to the supplies. This results in an input stage with picoamps of input Grounding current that can withstand up to 4000 V ESD events (human A ground plane layer is important for densely packed PC body model) with no degradation. boards to spread the current-minimizing parasitic inductances. However, an understanding of where the current flows in a Excessive power dissipation through the protection devices circuit is critical to implementing effective high speed circuit destroys or degrades the performance of any amplifier. Differential design. The length of the current path is directly proportional to voltages greater than 7 V result in an input current of approximately the magnitude of parasitic inductances and, therefore, the high (| V – V | – 0.7 V)/R , where R is the resistance in series with CC EE I I frequency impedance of the path. High speed currents in an the inputs. For input voltages beyond the positive supply, the inductive ground return create an unwanted voltage noise. input current is approximately (V – V – 0.7)/R . For input IN CC I voltages beyond the negative supply, the input current is about The length of the high frequency bypass capacitor leads is (VIN – VEE + 0.7)/RI. If the inputs of the amplifier sustain critical. A parasitic inductance in the bypass grounding works differential voltages greater than 7 V or input voltages beyond against the low impedance created by the bypass capacitor. the amplifier power supply, limit the input current to 10 mA by Place the ground leads of the bypass capacitors at the same using an appropriately sized input resistor (RI), as shown in physical location. Because load currents also flow from the Figure 55. supplies, the ground for the load impedance should be at the (V –V –0.7V) same physical location as the bypass capacitor grounds. For the (| V –V |–0.7V) CC EE IN EE R > R > I I 30mA 30mA larger value capacitors, intended to be effective at lower (V –V +0.7V) IN EE frequencies, the current return path distance is less critical. R > FOR LARGE | V –V | I CC EE 30mA + FOR V BEYOND IN AD865x Leakage Currents SUPPLY VOLTAGES +V O –V + – IN Poor PC board layout, contaminants, and the board insulator R I material can create leakage currents that are much larger than the input bias current of the AD865x family. Any voltage differential Figure 55. Input Protection Method between the inputs and nearby traces sets up leakage currents through the PC board insulator, for example 1 V/100 G = 10 pA. Overdrive Recovery Similarly, any contaminants on the board can create significant Overdrive recovery is defined as the time it takes for the output leakage (skin oils are a common problem). of an amplifier to come off the supply rail after an overload signal is To significantly reduce leakages, put a guard ring (shield) initiated. This is usually tested by placing the amplifier in a closed- around the inputs and the input leads that are driven to the loop gain of 15 with an input square wave of 200 mV p-p while the same voltage potential as the inputs. This ensures that there is amplifier is powered from either 5 V or 3 V. The AD865x family no voltage potential between the inputs and the surrounding has excellent recovery time from overload conditions (see Figure 31 area to set up any leakage currents. To be effective, the guard and Figure 32). The output recovers from the positive supply rail ring must be driven by a relatively low impedance source and within 200 ns at all supply voltages. Recovery from the negative rail should completely surround the input leads on all sides, above is within 100 ns at 5 V supply. and below, using a multilayer board. LAYOUT, GROUNDING, AND BYPASSING Another effect that can cause leakage currents is the charge CONSIDERATIONS absorption of the insulator material itself. Minimizing the Power Supply Bypassing amount of material between the input leads and the guard Power supply pins can act as inputs for noise, so care must be ring helps to reduce the absorption. Also, low absorption taken that a noise-free, stable dc voltage is applied. The purpose materials, such as Teflon® or ceramic, may be necessary in of bypass capacitors is to create low impedances from the supply some instances. to ground at all frequencies, thereby shunting or filtering most of the noise. Rev. C | Page 15 of 20 03301-054 AD8651/AD8652 Input Capacitance • Another way to stabilize an op amp driving a large capacitive load is to use a snubber network, as shown in Figure 57. Because Along with bypassing and grounding, high speed amplifiers can be there is not any isolation resistor in the signal path, this method sensitive to parasitic capacitance between the inputs and ground. A has the significant advantage of not reducing the output swing. few picofarads of capacitance reduces the input impedance at high The exact values of RS and CS are derived experimentally. In frequencies, which in turn increases the amplifier gain, causing Figure 57, an optimum RS and CS combination for a capacitive peaking in the frequency response or oscillations. With the load drive ranging from 50 pF to 1 nF was chosen. For this, AD865x, additional input damping is required for stability with RS = 3 Ω and CS = 10 nF were chosen. capacitive loads greater than 47 pF with direct input to output feedback (see the Output Capacitance section). + V Output Capacitance + + V When using high speed amplifiers, it is important to consider V OUT AD865x R – S the effects of the capacitive loading on amplifier stability. V – C R L L C 200mV S Capacitive loading interacts with the output impedance of the – V amplifier, causing reduction of the BW as well as peaking and Figure 57. Snubber Network ringing of the frequency response. To reduce the effects of the capacitive loading and allow higher capacitive loads, there are Settling Time two commonly used methods. The settling time of an amplifier is defined as the time it takes • As shown in Figure 56, place a small value resistor (RS) in for the output to respond to a step change of input and enter series with the output to isolate the load capacitor from the and remain within a defined error band, as measured relative to amplifier output. Heavy capacitive loads can reduce the the 50% point of the input pulse. This parameter is especially phase margin of an amplifier and cause the amplifier important in measurements and control circuits where amplifi- response to peak or become unstable. The AD865x is able ers are used to buffer A/D inputs or DAC outputs. The design of to drive up to 47 pF in a unity gain buffer configuration the AD865x family combines a high slew rate and a wide gain bandwidth product to produce an amplifier with very fast without oscillation or external compensation. However, if settling time. The AD865x is configured in the noninverting an application requires a higher capacitive load drive when the AD865x is in unity gain, the use of external isolation gain of 1 with a 2 V p-p step applied to its input. The AD865x networks can be used. The effect produced by this resistor family has a settling time of about 130 ns to 0.01% (2 mV). The is to isolate the op amp output from the capacitive load. output is monitored with a 10×, 10 M, 11.2 pF scope probe. The required amount of series resistance has been THD Readings vs. Common-Mode Voltage tabulated in Table 5 for different capacitive loads. While Total harmonic distortion of the AD865x family is well below this technique improves the overall capacitive load drive 0.0004% with any load down to 600 Ω. The distortion is a for the amplifier, its biggest drawback is that it reduces the function of the circuit configuration, the voltage applied, and output swing of the overall circuit. the layout, in addition to other factors. The AD865x family V CC outperforms its competitor for distortion, especially at U1 3 frequencies below 20 kHz, as shown in Figure 58. V + IN + V V R OUT S 0.1 AD865x 2 V = +3.5V/–1.5V SY – V 0.05 V = 2.0V p-p – OUT C R L L 0.02 0 0 0.01 0 Figure 56. Driving Large Capacitive Loads 0.005 0.002 OPA350 0.001 Table 5. Optimum Values for Driving Large Capacitive Loads C R L S 0.0005 100 pF 50 Ω AD8651 0.0002 500 pF 35 Ω 0.0001 1.0 nF 25 Ω 20 50 100 500 1k 2k 5k 20k FREQUENCY (Hz) Figure 58. Total Harmonic Distortion Rev. C | Page 16 of 20 03301-055 THD + NOISE (%) 03301-056 03301-057 AD8651/AD8652 5V +3.5V + 10kΩ U1 3 V AD865x OUT + + V V CC 33Ω 10kΩ 600Ω IN – 47pF AD865x 1µF AD7685 – 2 V V – IN 2.7nF –1.5V 2V p-p 1kΩ V IN 0V TO 5V f = 45kHz IN Figure 59. THD + N Test Circuit 1kΩ Figure 61. AD865x Driving a 16-Bit ADC Driving a 16-Bit ADC The AD865x family is an excellent choice for driving high speed, high precision ADCs. The driver amplifier for this type Table 6. Data Acquisition Solution of Figure 60 of application needs low THD + N as well as quick settling time. Parameter Reading (dB) Figure 61 shows a complete single-supply data acquisition THD + N 105.2 solution. The AD865x family drives the AD7685, a 250 kSPS, SFDR 106.6 1 16-bit data converter. 2nd Harmonics 107.7 3rd Harmonics 113.6 The AD865x is configured in an inverting gain of 1 with a 5 V single supply. Input of 45 kHz is applied, and the ADC samples at 250 kSPS. The results of this solution are listed in Table 6. The advantage of this circuit is that the amplifier and ADC can be powered with the same power supply. For the case of a noninverting gain of 1, the input common-mode voltage encompasses both supplies. 1 For more information about the AD7685 data converter, go to http://www.analog.com/Analog_Root/productPage/productHome/0%2C21 21%2CAD7685%2C00.html 0 f = 250kSPS SAMPLE f = 45kHz IN –20 INPUT RANGE = 0V TO 5V –40 –60 –80 –100 –120 –140 –160 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY (kHz) Figure 60. Frequency Response of AD865x Driving a 16-Bit ADC Rev. C | Page 17 of 20 AMPLITUDE (dB of Full Scale) 03301-058 03301-059 03301-060 AD8651/AD8652 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.38 0.60 0.23 0° 0.00 0.22 0.40 0.08 SEATING COPLANARITY PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 62. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 85 4.00 (0.1574) 6.20 (0.2440) 1 3.80 (0.1497) 5.80 (0.2284) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 63. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. C | Page 18 of 20 060506-A AD8651/AD8652 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8651ARM-REEL –40°C to +125°C 8-Lead MSOP RM-8 BEA AD8651ARM-R2 –40°C to +125°C 8-Lead MSOP RM-8 BEA 1 AD8651ARMZ-REEL –40°C to +125°C 8-Lead MSOP RM-8 BEA# 1 AD8651ARMZ-R2 –40°C to +125°C 8-Lead MSOP RM-8 BEA# AD8651AR –40°C to +125°C 8-Lead SOIC_N R-8 AD8651AR-REEL –40°C to +125°C 8-Lead SOIC_N R-8 AD8651AR-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8 1 AD8651ARZ –40°C to +125°C 8-Lead SOIC_N R-8 1 AD8651ARZ-REEL –40°C to +125°C 8-Lead SOIC_N R-8 1 AD8651ARZ-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8 1 AD8652ARMZ-R2 –40°C to +125°C 8-Lead MSOP RM-8 A05 1 AD8652ARMZ-REEL –40°C to +125°C 8-Lead MSOP RM-8 A05 1 AD8652ARZ –40°C to +125°C 8-Lead SOIC_N R-8 1 AD8652ARZ-REEL –40°C to +125°C 8-Lead SOIC_N R-8 1 AD8652ARZ-REEL7 –40°C to +125°C 8-Lead SOIC_N R-8 1 Z = Pb-free part; # denotes lead-free product may be top or bottom marked. Rev. C | Page 19 of 20 AD8651/AD8652 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03301-0-8/06(C) Rev. C | Page 20 of 20