ANALOG DEVICES AD8643

Low Power, Rail-to-Rail Output, Precision JFET Amplifiers Data Sheet AD8641/AD8642/AD8643 FEATURES PIN CONFIGURATIONS Low supply current: 250 μA max OUT 1 5 VCC Very low input bias current: 1 pA max AD8641 VEE 2 TOP VIEW Low offset voltage: 750 μV max (Not to Scale) +IN 3 Single-supply operation: 5 V to 26 V 4 –IN Dual-supply operation: ±2.5 V to ±13 V Figure 1. 5-Lead SC70 (KS-5) Rail-to-rail output Unity-gain stable NC 1 8 NC AD8641 No phase reversal –IN 2 7 VCC SC70 package +IN 3 6 OUT TOP VIEW (Not to Scale) VEE 4 5 NC NC = NO CONNECT APPLICATIONS Figure 2. 8-Lead SOIC (R-8) Line-/battery-powered instruments Photodiode amplifiers OUT A 1 8 V+ AD8642 Precision current sensing –IN A 2 7 OUT B Medical instrumentation +IN A 3 6 –IN B TOP VIEW (Not to Scale) V– 4 5 +IN B Industrial controls Precision filters Figure 3. 8-Lead SOIC (R-8) Portable audio OUT A 1 8 V+ ATE AD8642 –IN A 2 7 OUT B TOP VIEW +IN A 3 6 –IN B (Not to Scale) GENERAL DESCRIPTION V– 4 5 +IN B The AD8641/AD8642/AD8643 are low power, precision JFET Figure 4. 8-Lead MSOP (RM-8) input amplifiers featuring extremely low input bias current and rail-to-rail output. The ability to swing nearly rail-to-rail at the OUT A 1 14 OUT D –IN A 2 13 –IN D input and rail-to-rail at the output enables designers to buffer +IN A 3 12 +IN D AD8643 CMOS DACs, ASICs, and other wide output swing devices in V+ 4 TOP VIEW 11 V– single-supply systems. The outputs remain stable with (Not to Scale) 5 10 +IN B +IN C capacitive loads of more than 500 pF. –IN B 6 9 –IN C The AD8641/AD8642/AD8643 are suitable for applications OUT B 7 8 OUT C utilizing multichannel boards that require low power to manage Figure 5. 14-Lead SOIC (R-14) heat. Other applications include photodiodes, ATE reference level drivers, battery management, and industrial controls. The AD8641/AD8642/AD8643 are fully specified over the extended industrial temperature range of –40°C to +125°C. The –IN A 1 12 –IN D PIN 1 AD8641 is available in 5-lead SC70 and 8-lead SOIC lead-free INDICATOR 11 +IN D +IN A 2 packages. The AD8642 is available in 8-lead MSOP and 8-lead AD8643 V+ 3 10 V– TOP VIEW SOIC lead-free packages. The AD8643 is available in 14-lead +IN B 4 9 +IN C SOIC and 16-lead, 3 mm × 3 mm, LFCSP lead-free packages. NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD SHOULD BE CONNECTED TO V+. Figure 6. 16-Lead LFCSP (CP-16) (Not Drawn to Scale) Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. –IN B 5 16 NC OUT B 6 15 OUT A OUT C 7 14 OUT D –IN C 8 13 NC 05072-101 05072-102 05072-064 05072-103 05072-105 05072-104 AD8641/AD8642/AD8643 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Absolute Maximum Ratings ............................................................5  Applications....................................................................................... 1  Thermal Resistance.......................................................................5  General Description ......................................................................... 1  ESD Caution...................................................................................5  Pin Configurations ........................................................................... 1  Typical Performance Characteristics ..............................................6  Revision History ............................................................................... 2  Outline Dimensions....................................................................... 13  Specifications..................................................................................... 3  Ordering Guide .......................................................................... 15  Electrical Characteristics............................................................. 3  REVISION HISTORY 9/11—Rev. D to Rev. E 3/05—Rev. 0 to Rev. A Changes to Thermal Resistance Section........................................ 5 Added AD8642 ...................................................................Universal Changes to General Description .....................................................1 7/11—Rev. C to Rev. D Added Figure 3 and Figure 4............................................................1 Changes to Figure 6.......................................................................... 1 Changes to Specifications.................................................................3 Changes to Absolute Maximum Ratings........................................5 11/10—Rev. B to Rev. C Changes to Figure 22.........................................................................8 Changes to Figure 6.......................................................................... 1 Changes to Figure 23.........................................................................9 Added Thermal Resistance Section and Table 4 .......................... 5 Changes to Figure 41...................................................................... 12 Updated Outline Dimensions ....................................................... 13 Updated Outline Dimensions....................................................... 13 Changes to Ordering Guide .......................................................... 14 Changes to Ordering Guide .......................................................... 15 4/05—Rev. A to Rev. B 10/04—Initial Version: Revision 0 Added AD8643 ...................................................................Universal Added 14-Lead SOIC .........................................................Universal Added 16-Lead LFCSP.......................................................Universal Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 Rev. E | Page 2 of 16 Data Sheet AD8641/AD8642/AD8643 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 5.0 V, V = 2.5 V, T = 25°C, unless otherwise noted. S CM A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 50 750 μV AD8643 LFCSP only 1 mV –40°C < T < +85°C 1.5 mV A +85°C < TA < +125°C, VCM = 1.5 V 1.6 mV Input Bias Current IB 0.25 1 pA –40°C < TA < +125°C 180 pA Input Offset Current I 0.5 pA OS –40°C < T < +125°C 60 pA A Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.5 V 74 93 dB Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.5 to 4.5 V 80 140 V/mV Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C 2.5 μV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH 4.95 V I = 1 mA, –40°C to +125°C 4.94 V L Output Voltage Low V 0.05 V OL I = 1 mA, –40°C to +125°C 0.01 0.05 V L Output Current IOUT ±6 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V = 5 V to 26 V 90 107 dB S Supply Current/Amplifier ISY 195 250 μA –40°C < TA < +125°C 270 μA DYNAMIC PERFORMANCE Slew Rate SR 2 V/μs Gain Bandwidth Product GBP AD8641, AD8642 3 MHz AD8643 2.5 MHz Phase Margin Ø 50 Degrees m NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz 4.0 μV p-p N Voltage Noise Density e f = 1 kHz 28.5 nV/√Hz N Current Noise Density i f = 1 kHz 0.5 fA/√Hz N Rev. E | Page 3 of 16 AD8641/AD8642/AD8643 Data Sheet V = ±13 V, V = 0 V, T =25°C, unless otherwise noted. S CM A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 70 750 μV OS AD8643 LFCSP only 1 mV –40° < T < +125°C 1.5 mV A Input Bias Current IB 0.25 1 pA –40°C < TA < +125°C 260 pA Input Offset Current IOS 0.5 pA –40°C < T < +125°C 65 pA A Input Voltage Range –13 +10 V Common-Mode Rejection Ratio CMRR V = −13 V to +10 V 90 107 dB CM Large Signal Voltage Gain AVO RL = 10 kΩ, VO = –11 V to +11 V 215 290 V/mV Offset Voltage Drift ∆VOS/∆T –40°C < TA < +125°C 2.5 μV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH +12.95 V IL = 1 mA, –40°C to +125°C +12.94 V Output Voltage Low V –12.95 V OL I = 1 mA, –40°C to +125°C –12.94 V L Output Current I ±12 mA OUT POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±2.5 V to ±13 V 90 107 dB S Supply Current/Amplifier I 200 290 μA SY –40°C < TA < +125°C 330 μA DYNAMIC PERFORMANCE Slew Rate SR 3 V/μs Gain Bandwidth Product GBP 3.5 MHz Phase Margin Øm 60 Degrees NOISE PERFORMANCE Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4.2 μV p-p Voltage Noise Density eN f = 1 kHz 27.5 nV/√Hz Current Noise Density i f = 1 kHz 0.5 fA/√Hz N Rev. E | Page 4 of 16 Data Sheet AD8641/AD8642/AD8643 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Absolute maximum ratings apply at 25°C, unless otherwise noted. θ is specified for the worst-case conditions, that is, a device JA Table 3. soldered in a circuit board for surface-mount packages. This Parameter Rating was measured using a standard 4-layer board. For the LFCSP Supply Voltage 27.3 V package, solder the exposed pad to a copper plane, which Input Voltage VS− to VS+ should be connected to V+. Differential Input Voltage ±Supply Voltage Table 4. Output Short-Circuit Duration Indefinite Storage Temperature Range Package Type θJA θJC Unit KS-5, R-8, RM-8, R-14, CP-16 Packages −65°C to +150°C 5-Lead SC70 (KS) 430 149 °C/W Operating Temperature Range −40°C to +125°C 8-Lead SOIC (R) 121 43 °C/W Junction Temperature Range 8-Lead MSOP (RM) 142 45 °C/W KS-5, R-8, RM-8, R-14, CP-16 Packages −65°C to +150°C 14-Lead SOIC (R) 110 36 °C/W Lead Temperature (Soldering, 60 sec) 300°C 16-Lead LFCSP (CP) 81 16 °C/W Stresses above those listed under Absolute Maximum Ratings ESD CAUTION may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. E | Page 5 of 16 AD8641/AD8642/AD8643 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 20 80 V = 5V V =±13V SY SY 18 V = 1.5V CM 70 16 60 14 50 12 10 40 8 30 6 20 4 10 2 0 0 T V (μV/°C) V (mV) C OS OS Figure 7. Input Offset Voltage Figure 10. Offset Voltage Drift 16 4.5 V =±13V SY V =±13V SY 4.0 14 T = 25°C A 3.5 12 3.0 10 2.5 8 2.0 1.5 6 1.0 4 0.5 2 0 0 –0.5 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 OFFSET VOLTAGE (μV/°C) V (V) CM Figure 11. Input Bias Current vs. V CM Figure 8. Offset Voltage Drift 0.5 70 V =±2.5V SY V =±13V 0.4 SY T = 25°C 60 A 0.3 50 0.2 0.1 40 0 30 –0.1 –0.2 20 –0.3 10 –0.4 –0.5 0 –15.0 –12.5 –10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0 12.5 15.0 V (V) V (mV) CM OS Figure 12. Input Bias Current vs. V Figure 9. Input Offset Voltage CM Rev. E | Page 6 of 16 FREQUENCY NUMBER OF AMPLIFIERS FREQUENCY –0.60 –0.60 0 –0.55 –0.55 0.5 –0.50 –0.50 1.0 –0.45 –0.45 1.5 –0.40 –0.40 –0.35 2.0 –0.35 –0.30 –0.30 2.5 –0.25 –0.25 3.0 –0.20 –0.20 3.5 –0.15 –0.15 4.0 –0.10 –0.10 4.5 –0.05 –0.05 0 5.0 0 0.05 0.05 5.5 0.10 0.10 6.0 0.15 0.15 6.5 0.20 0.20 7.0 0.25 0.25 0.30 7.5 0.30 0.35 0.35 8.0 0.40 0.40 8.5 0.45 0.45 9.0 0.50 0.50 9.5 0.55 0.55 10.0 0.60 0.60 05072-004 05072-003 05072-002 INPUT BIAS (pA) INPUT BIAS (pA) NUMBER OF AMPLIFIERS 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 05072-006 05072-007 05072-005 Data Sheet AD8641/AD8642/AD8643 1000 500 V = 5V V =±13V SY SY 400 300 100 200 100 10 0 –100 –200 1 –300 –400 0.1 –500 0 25 50 75 100 125 150 0 0.5 1.0 1.5 2.0 2.5 TEMPERATURE (°C) V (V) CM Figure 16. Input Offset Voltage vs. V Figure 13. Input Bias Current vs. Temperature CM 10M 1.0 V = +5V OR±5V SY 0.8 0.6 0.4 1M 0.2 V =±13V SY 0 –0.2 100k V =±2.5V SY –0.4 –0.6 –0.8 –1.0 10k 0.1 1 10 100 –5 –4 –3 –2 –1 0 1 2 3 4 5 V (V) LOAD RESISTANCE (kΩ) CM Figure 14. Input Bias Current vs. V CM Figure 17. Open-Loop Gain vs. Load Resistance 1000 1000 V =±13V SY 900 A B 800 C 700 100 600 D 500 E 400 300 10 200 A. V =±13V, V =±11V, R = 10kΩ SY O L B. V =±13V, V =±11V, R = 2kΩ SY O L 100 C. V = +5V, V = +0.5V/+4.5V, R = 10kΩ SY O L D. V = +5V, V = +0.5V/+4.5V, R = 2kΩ SY O L 0 E. V = +5V, V = +0.5V/+4.5V, R = 600Ω SY O L –100 1 0 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 –50 –30 –10 10 30 50 70 90 110 130 150 V (V) TEMPERATURE (°C) CM Figure 15. Input Offset Voltage vs. VCM Figure 18. Open-Loop Gain vs. Temperature Rev. E | Page 7 of 16 V (μV) INPUT BIAS (pA) INPUT BIAS CURRENT (pA) OS 05072-010 05072-009 05072-008 A (V/mV) VO OPEN-LOOP GAIN (V/V) V (μV) OS 05072-013 05072-012 05072-011 AD8641/AD8642/AD8643 Data Sheet 10000 600 V =±13V V =±13V SY SY 500 400 V – V SY OH 1000 300 200 100 100 0 100kΩ –V – V SY OL –100 –200 10 –300 10kΩ 1kΩ –400 –500 1 –600 –15 –10 –5 0 5 10 15 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) OUTPUT VOLTAGE (V) Figure 19. Input Error Voltage vs. Output Voltage for Resistive Loads Figure 22. Output Saturation Voltage vs. Load Current 10000 250 V =5V V =±5V SY 200 SY POS RAIL V –V SY OH 150 R = 1kΩ 100 1000 L 50 R = 2kΩ L V OL 0 R = 10kΩ L R = 100kΩ L –50 100 –100 –150 –200 10 R = 1kΩ R = 100kΩ L L –250 R = 10kΩ L –300 NEG RAIL R = 2kΩ L –350 1 0.001 0.01 0.1 1 10 100 0 50 100 150 200 250 300 350 LOAD CURRENT (mA) OUTPUT VOLTAGE FROM SUPPLY RAIL (mV) Figure 20. Input Error Voltage vs. Output Voltage Figure 23. Output Saturation Voltage vs. Load Current Within 300 mV of Supply Rails 800 70 315 V =±13V SY 700 60 270 R = 2kΩ L C = 40pF L 50 225 600 40 180 500 GAIN 30 135 400 20 90 PHASE 300 +25°C 10 45 +125°C 0 0 200 –55°C –10 –45 100 –20 –90 0 –30 –135 4 8 12 16 20 24 28 10k 100k 1M 10M V (V) SY FREQUENCY (Hz) Figure 21. Quiescent Current vs. Supply Voltage at Different Temperatures Figure 24. Open-Loop Gain and Phase Margin vs. Frequency Rev. E | Page 8 of 16 I (μA) OFFSET VOLTAGE (μV) SY INPUT VOLTAGE (μV) 05072-016 05072-014 05072-015 GAIN (dB) SATURATION VOLTAGE (mV) SATURATION VOLTAGE (mV) PHASE (Degrees) 05072-018 05072-017 05072-019 Data Sheet AD8641/AD8642/AD8643 70 140 315 V =±13V V = 5V SY SY 60 270 120 R = 2kΩ L C = 40pF L 50 100 225 40 180 80 GAIN 30 135 60 20 40 90 PHASE 10 45 20 0 0 0 –10 –45 –20 –20 –90 –40 –30 –135 –60 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 25. Open-Loop Gain and Phase Margin vs. Frequency Figure 28. CMRR vs. Frequency 70 140 V =5V SY V =±13V SY 120 60 R = 2kΩ L C = 40pF L 50 100 80 40 G = +100 30 60 40 20 G = +10 20 10 0 0 G = +1 –20 –10 –20 –40 –60 –30 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. Closed-Loop Gain vs. Frequency Figure 29. CMRR vs. Frequency 70 140 V =±13V SY V = 5V SY 60 120 R = 2kΩ L C = 40pF L 50 100 +PSRR 40 80 G = +100 30 60 20 40 –PSRR G = +10 10 20 0 0 G = +1 –10 –20 –20 –40 –30 –60 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 27. Closed-Loop Gain vs. Frequency Figure 30. PSRR vs. Frequency Rev. E | Page 9 of 16 GAIN (dB) GAIN (dB) GAIN (dB) PHASE (Degrees) 05072-022 05072-021 05072-020 PSRR (dB) CMRR (dB) CMRR (dB) 05072-025 05072-024 05072-023 AD8641/AD8642/AD8643 Data Sheet 140 1.0 T V =±13V V =5V SY SY 120 0.8 100 0.6 +PSRR 1 V IN 80 0.4 60 0.2 40 0 –PSRR 20 –0.2 0 –0.4 2 –20 –0.6 V OUT –40 –0.8 –60 –1.0 1k 10k 100k 1M 10M –5 CH1 10.0V –4 –3CH2 10.0V –2 –1 0 M400μ1 s 2 A CH1 1.00V 3 4 5 T 0.00000s FREQUENCY (Hz) V (V) CM Figure 34. No Phase Reversal Figure 31. PSRR vs. Frequency 15 1000 V =±13V V =±13V SY S GAIN = +5 G = +100 10 100 TS + (1%) 5 TS + (0.1%) 10 0 G = +10 1 –5 G = +1 TS – (0.1%) 0.1 –10 TS – (1%) –15 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1k 10k 100k 1M 10M 100M SETTLING TIME (μs) FREQUENCY (Hz) Figure 32. Output Impedance vs. Frequency Figure 35. Output Swing and Error vs. Settling Time 1000 70 V =5V SY V =±13V S R = 10kΩ L G = +100 60 V = 100mV p-p IN 100 A = +1 V 50 10 40 G = +10 OS– 30 1 G = +1 OS+ 20 0.1 10 0 0.01 1k 10k 100k 1M 10M 100M 1 10 100 1000 FREQUENCY (Hz) CAPACITANCE (pF) Figure 33. Output Impedance vs. Frequency Figure 36. Small Signal Overshoot vs. Load Capacitance Rev. E | Page 10 of 16 PSRR (dB) Z (Ω) Z (Ω) OUT OUT 05072-026 05072-028 05072-027 OVERSHOOT (%) OUTPUT SWING (V) INPUT BIAS (pA) 05072-029 05072-031 05072-030 05072-009 Data Sheet AD8641/AD8642/AD8643 70 1k V =±13V SY V =±2.5V S R = 10kΩ L 60 V = 100mV p-p IN A = +1 V 50 100 40 OS– 30 10 OS+ 20 10 0 1 1 10 100 1000 10 100 1k 10k CAPACITANCE (pF) FREQUENCY (Hz) Figure 37. Small Signal Overshoot vs. Load Capacitance Figure 40. Voltage Noise Density 1.0 1k V =±13V V = 5V SY S G = +1M 0.8 CH1 p-p = 4.26V 0.6 0.4 100 0.2 10 –0.2 10 –0.4 –0.6 –0.8 –1.0 1 10 100 1k 10k –5 CH1 1.00V –4 –3 –2 –1 0 M1.00s 1 2 A CH1 3 4 –20.0V 5 V (V) FREQUENCY (Hz) CM Figure 38. 0.1 Hz to 10 Hz Noise Figure 41. Voltage Noise Density 0.004 1.0 V =±2.5V V =±13V SY S 8V p-p INPUT 0.8 G = +1M LOAD = 100kΩ CH1 p-p = 4.06V GAIN = +1 0.001 0.6 0.4 1V p-p INPUT 0.2 2V p-p INPUT 0.0001 10 4V p-p INPUT –0.2 –0.4 0.00001 –0.6 –0.8 0.000001 –1.0 12 100 1k 10k0k –5 CH1 1.00V –4 –3 –2 –1 0 M1.00s 1 2 A CH1 3 4 –20.0V 5 FREQUENCY (Hz) V (V) CM Figure 39. 0.1 Hz to 10 Hz Noise Figure 42. Total Harmonic Distortion + Noise vs. Frequency Rev. E | Page 11 of 16 INPUT BIAS (pA) INPUT BIAS (pA) OVERSHOOT (%) 05072-034 05072-033 05072-009 05072-009 05072-032 THD + NOISE (%) VOLTAGE NOISE DENSITY (nV/ Hz) VOLTAGE NOISE DENSITY (nV/ Hz) 05072-037 05072-036 05072-035 AD8641/AD8642/AD8643 Data Sheet –40 20kΩ –50 2kΩ – –60 + –70 2kΩ 2kΩ V IN –80 –90 V = 18V p-p IN –100 –110 V = 4.5V p-p IN –120 –130 –140 V = 9V p-p IN –150 –160 20 100 1k 10k 100k FREQUENCY (Hz) Figure 43. Channel Separation Rev. E | Page 12 of 16 (dB) 05072-041 + – Data Sheet AD8641/AD8642/AD8643 OUTLINE DIMENSIONS 2.20 2.00 1.80 5 4 2.40 1.35 2.10 1.25 12 3 1.80 1.15 0.65 BSC 1.00 0.40 1.10 0.90 0.10 0.80 0.70 0.46 0.22 SEATING 0.10 MAX 0.36 0.30 0.08 PLANE COPLANARITY 0.26 0.15 0.10 COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 44. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 45. 8-Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches) Rev. E | Page 13 of 16 012407-A 072809-A AD8641/AD8642/AD8643 Data Sheet 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 46. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 8 14 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 47. 14-Lead Standard Small Outline Package [SOIC_N] (R-14) Dimensions shown in millimeters and (inches) 0.50 0.40 0.60 MAX 0.30 3.00 BSC SQ BOTTOM VIEW * 1.65 0.45 13 16 12 1 1.50 SQ PIN 1 2.75 1.35 TOP INDICATOR EXPOSED BSC SQ VIEW PAD 9 4 0.50 8 5 BSC 0.25 MIN 1.50 REF 0.80 MAX 12° MAX 0.65 TYP 0.90 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.85 THE PIN CONFIGURATION AND 0.05 MAX 0.80 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.23 0.18 * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters Rev. E | Page 14 of 16 PIN 1 INDICATOR 10-07-2009-B 060606-A 07-17-2008-A Data Sheet AD8641/AD8642/AD8643 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8641AKSZ-R2 −40°C to +125°C 5-Lead SC70 KS-5 A07 AD8641AKSZ-REEL7 −40°C to +125°C 5-Lead SC70 KS-5 A07 AD8641AKSZ-REEL −40°C to +125°C 5-Lead SC70 KS-5 A07 AD8641ARZ −40°C to +125°C 8-lead SOIC_N R-8 AD8641ARZ-REEL7 −40°C to +125°C 8-lead SOIC_N R-8 AD8641ARZ-REEL −40°C to +125°C 8-lead SOIC_N R-8 AD8642ARMZ −40°C to +125°C 8-lead MSOP RM-8 A0A AD8642ARMZ-REEL −40°C to +125°C 8-lead MSOP RM-8 A0A AD8642ARZ −40°C to +125°C 8-lead SOIC_N R-8 AD8642ARZ-REEL7 −40°C to +125°C 8-lead SOIC_N R-8 AD8642ARZ-REEL −40°C to +125°C 8-lead SOIC_N R-8 AD8643ARZ −40°C to +125°C 14-lead SOIC_N R-14 AD8643ARZ-REEL7 −40°C to +125°C 14-lead SOIC_N R-14 AD8643ARZ-REEL −40°C to +125°C 14-lead SOIC_N R-14 AD8643ACPZ-R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA AD8643ACPZ-REEL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA AD8643ACPZ-REEL −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 AUA 1 Z = RoHS Compliant Part. Rev. E | Page 15 of 16 AD8641/AD8642/AD8643 Data Sheet NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05072-0-9/11(E) Rev. E | Page 16 of 16