ANALOG DEVICES AD8627

Precision Low Power Single-Supply JFET Amplifiers AD8625/AD8626/AD8627 FEATURES PIN CONFIGURATIONS 8-Lead SOIC 5-Lead SC70 SC70 package (R-8 Suffix) (KS Suffix) Very low IB: 1 pA max OUT A 1 5 V+ Single-supply operation: 5 V to 26 V NC 1 8 NC V– 2 AD8627 Dual-supply operation: ±2.5 V to ±13 V 2 7 –IN V+ Rail-to-rail output AD8627 +IN 3 4 –IN 3 6 +IN OUT Low supply current: 630 μA/amp typ V– 4 5 NC Low offset voltage: 500 μV max Unity gain stable NC = NO CONNECT No phase reversal 8-Lead SOIC 8-Lead MSOP (R-8 Suffix) (RM-Suffix) APPLICATIONS OUT A 1 8 V+ OUT A 1 8 V+ Photodiode amplifiers –IN A OUT B AD8626 2 7 –IN A OUT B +IN A –IN B ATEs AD8626 V– 4 5 +IN B 3 6 +IN A –IN B Line-powered/battery-powered instrumentation Industrial controls V– 4 5 +IN B Automotive sensors Precision filters 14-Lead SOIC 14-Lead TSSOP Audio (R-Suffix) (RU-Suffix) OUT A114 OUT D OUT A 1 14 OUT D –IN A –IN D –IN A213 –IN D +IN A +IN D +IN A312 +IN D V+ AD8625 V– AD8625 +IN B +IN C V+411 V– –IN B –IN C +IN B510 +IN C OUT B 7 8 OUT C –IN B69 –IN C OUT B78 OUT C Figure 1. GENERAL DESCRIPTION The 5 MHz bandwidth and low offset are ideal for precision filters. The AD862x is a precision JFET input amplifier. It features true single-supply operation, low power consumption, and The AD862x is fully specified over the industrial temperature rail-to-rail output. The outputs remain stable with capacitive range. (−40°C to +85°C). The AD8627 is available in both loads of over 500 pF; the supply current is less than 630 μA/amp. 5-lead SC70 and 8-lead SOIC surface-mount packages (SC70 Applications for the AD862x include photodiode transimpedance packaged parts are available in tape and reel only). The AD8626 amplification, ATE reference level drivers, battery management, is available in MSOP and SOIC packages, while the AD8625 is both line powered and portable instrumentation, and remote available in TSSOP and SOIC packages. sensor signal conditioning, which includes automotive sensors. The AD862x’s ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables it to be used to buffer CMOS DACs, ASICs, and other wide output swing devices in single-supply systems. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03023-001 AD8625/AD8626/AD8627 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ..............................................6  Applications ....................................................................................... 1  Applications Information .............................................................. 13  Pin Configurations ........................................................................... 1  Minimizing Input Current ........................................................ 15  General Description ......................................................................... 1  Photodiode Preamplifier Application ...................................... 15  Revision History ............................................................................... 2  Output Amplifier for DACs ...................................................... 16  Specif ica t ions ..................................................................................... 3  Eight-Pole Sallen Key Low-Pass Filter ..................................... 17  Electrical Characteristics ............................................................. 3  Outline Dimensions ....................................................................... 18  Absolute Maximum Ratings ............................................................ 5  Ordering Guide .......................................................................... 20  ESD Caution .................................................................................. 5  REVISION HISTORY 12/10—Rev. D to Rev. E 1/04—Rev. A to Rev. B Removed Table Summary Conditions Above Table 3 ................. 5 Change to General Description ....................................................... 1 Updated Outline Dimensions ....................................................... 18 Change to Figure 10 .......................................................................... 7 Change to Figure13 ........................................................................... 7 3/09—Rev. C to Rev. D Change to Figure 37 ....................................................................... 11 Updated Outline Dimensions ....................................................... 18 Changes to Figure 38 ...................................................................... 12 Changes to Ordering Guide .......................................................... 19 Change to Output Amplifier for DACs Section ......................... 15 Updated Outline Dimensions ....................................................... 19 11/04—Rev. B to Rev. C Updated Figure Codes ....................................................... Universal 10/03—Rev. 0 to Rev. A Changes to Figure 17 and 18 ........................................................... 8 Addition of Two New Parts ............................................... Universal Changes to Figure 33 and Figure 37 ............................................. 11 Change to General Description ....................................................... 1 Changes to Figure 38 ...................................................................... 12 Changes to Pin Configurations ....................................................... 1 Changes to Figure 39 and Figure 40 ............................................. 13 Change to Specifications Table ........................................................ 3 Changes to Figure 41 to Figure 44 ................................................ 14 Changes to Figure 31 ...................................................................... 10 Changes to Figure 32 ...................................................................... 11 Changes to Figure 38 ...................................................................... 12 Changes to Figure 46 ...................................................................... 16 Changes to Figure 47 ...................................................................... 16 Changes to Figure 49 ...................................................................... 17 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 Rev. E | Page 2 of 20 AD8625/AD8626/AD8627 SPECIFICATIONS ELECTRICAL CHARACTERISTICS @V = 5 V, V = 1.5 V, T = 25°C, unless otherwise noted. S CM A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 0.05 0.5 mV −40°C < T < +85°C 1.2 mV A Input Bias Current I 0.25 1 pA B –40°C < TA < +85°C 60 pA Input Offset Current IOS 0.5 pA –40°C < TA < +85°C 25 pA Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR V = 0 V to 2.5 V 66 87 dB CM Large Signal Voltage Gain A R = 10 kΩ, V = 0.5 V to 4.5 V 100 230 V/mV VO L O Offset Voltage Drift ∆VOS/∆T –40°C < TA < +85°C 2.5 μV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH 4.92 V IL = 2 mA, –40°C < TA < +85°C 4.90 V Output Voltage Low VOL 0.075 V I = 2 mA, –40°C < T < +85°C 0.08 V L A Output Current I ±10 mA OUT POWER SUPPLY Power-Supply Rejection Ratio PSRR V = 5 V to 26 V 80 104 dB S Supply Current/Amplifier I 630 785 μA SY –40°C < T < +85°C 800 μA A DYNAMIC PERFORMANCE Slew Rate SR 5 V/μs Gain Bandwidth Product GBP 5 MHz Phase Margin ØM 60 Degrees NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 1.9 μV p-p n Voltage Noise Density en f = 1 kHz 17.5 nV/√Hz Current Noise Density in f = 1 kHz 0.4 fA/√Hz Channel Separation C f = 1 kHz 104 dB s Rev. E | Page 3 of 20 AD8625/AD8626/AD8627 @V = ±13 V; V = 0 V; T = 25°C, unless otherwise noted. S CM A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 0.35 0.75 mV OS –40°C < T < +85°C 1.35 mV A Input Bias Current I 0.25 1 pA B –40°C < TA < +85°C 60 pA Input Offset Current IOS 0.5 pA –40°C < TA < +85°C 25 pA Input Voltage Range –13 +11 V Common-Mode Rejection Ratio CMRR V = –13 V to +10 V 76 105 dB CM Large Signal Voltage Gain A R = 10 kΩ, V = –11 V to +11 V 150 310 V/mV VO L O Offset Voltage Drift ∆VOS/∆T –40°C < TA < +85°C 2.5 μV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH +12.92 V VOH IL = 2 mA, –40°C < TA < +85°C +12.91 V Output Voltage Low VOL –12.92 V V I = 2 mA, –40°C < T < +85°C –12.91 V OL L A Output Current I ±15 mA OUT POWER SUPPLY Power-Supply Rejection Ratio PSRR V = ±2.5 V to ±13 V 80 104 dB S Supply Current/Amplifier I 710 850 μA SY –40°C < T < +85°C 900 μA A DYNAMIC PERFORMANCE Slew Rate SR 5 V/μs Gain Bandwidth Product GBP 5 MHz Phase Margin ØM 60 Degrees NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2.5 μV p-p n Voltage Noise Density en f = 1 kHz 16 nV/√Hz Current Noise Density in f = 1 kHz 0.5 fA/√Hz Channel Separation Cs f = 1 kHz 105 dB Rev. E | Page 4 of 20 AD8625/AD8626/AD8627 ABSOLUTE MAXIMUM RATINGS θJA is specified for worst-case conditions when devices are Table 3. soldered in circuit boards for surface-mount packages. Parameter Ratings Table 4. Supply Voltage 27 V Input Voltage V to V Package Type θJA θJC Unit S– S+ Differential Input Voltage ± Supply Voltage 5-Lead SC70 (KS) 376 126 °C/W Output Short-Circuit Duration Indefinite 8-Lead MSOP (RM) 210 45 °C/W Storage Temperature Range, R Package −65°C to +125°C 8-Lead SOIC (R) 158 43 °C/W 14-Lead SOIC (R) 120 36 °C/W Operating Temperature Range −40°C to +85°C 14-Lead TSSOP (RU) 180 35 °C/W Junction Temperature Range, R Package −65°C to +150°C Lead Temperature Range (Soldering, 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings ESD CAUTION may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. E | Page 5 of 20 AD8625/AD8626/AD8627 TYPICAL PERFORMANCE CHARACTERISTICS 25 16 V =±12V SY V = +3.5V/–1.5V SY T = 25°C A 14 20 12 10 15 8 10 6 4 5 2 0 0 –600 –400 –200 0 200 400 600 0 123 4567 89 10 VOLTAGE (μV) OFFSET VOLTAGE (μV/°C) Figure 2. Input Offset Voltage Figure 5. Offset Voltage Drift 12 50 V =±13V SY V =±13V SY 40 T = 25°C A 10 30 20 8 10 6 0 –10 4 –20 –30 2 –40 0 –50 01 23 45 678 9 10 –15.0–12.5–10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0 12.5 15.0 OFFSET VOLTAGE (μV/°C) V (V) CM Figure 6. Input Bias Current vs. V Figure 3. Offset Voltage Drift CM 18 0 V = +3.5V/–1.5V SY V =±13V SY 16 –0.1 T = 25°C A 14 –0.2 12 –0.3 10 –0.4 8 –0.5 6 –0.6 4 –0.7 2 –0.8 0 –0.9 –400 –300 –200 –100 0 100 200 300 –15.0–12.5–10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0 12.5 15.0 VOLTAGE (μV) V (V) CM Figure 4. Input Offset Voltage Figure 7. Input Bias Current vs. V CM Rev. E | Page 6 of 20 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 03023-004 03023-003 03023-002 INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (pA) NUMBER OF AMPLIFIERS 03023-005 03023-006 03023-007 AD8625/AD8626/AD8627 100 500 V = 5V V =±13V SY SY 400 V = 0V CM 300 200 10 100 0 –100 1 –200 –300 –400 0.1 –500 –50 –25 0 25 50 75 100 125 150 –1 0123 4 TEMPERATURE (°C) V (V) CM Figure 8. Input Bias Current vs. Temperature Figure 11. Input Offset Voltage vs. V CM 2.0 10M V = +5V OR±5V SY 1.5 1.0 1M 0.5 V =±13V SY 0 V = +5V SY –0.5 100k –1.0 –1.5 –2.0 10k –5 –4 –3 –2 –1 01234 5 0.1 1 10 100 V (V) LOAD RESISTANCE (kΩ) CM Figure 9. Input Bias Current vs. V Figure 12. Open-Loop Gain vs. Load Resistance CM 1000 1000 V =±13V SY 900 a 800 d 700 b 100 600 c 500 e 400 300 10 200 a. V =±13V, V =±11V, R = 10kΩ SY O L b. V =±13V, V =±11V, R = 2kΩ SY O L 100 c. V = +5V, V = +0.5V/+4.5V, R = 2kΩ SY O L d. V = +5V, V = +0.5V/+4.5V, R = 10kΩ SY O L 0 e. V = +5V, V = +0.5V/+4.5V, R = 600Ω SY O L –100 1 –15–12 –9 –6 –3 0369 12 15 –4025 95125 V (V) TEMPERATURE (°C) CM Figure 10. Input Offset Voltage vs. VCM Figure 13. Open-Loop Gain vs. Temperature Rev. E | Page 7 of 20 INPUT BIAS CURRENT (pA) INPUT OFFSET VOLTAGE (μV) INPUT BIAS CURRENT (pA) 03023-008 03023-009 03023-010 OPEN-LOOP GAIN (V/mV) OPEN-LOOP GAIN (V/V) INPUT OFFSET VOLTAGE (μV) 03023-012 03023-013 03023-011 AD8625/AD8626/AD8627 600 10k V =±13V SY V =±13V SY 500 400 1k R = 10kΩ L 300 200 R = 100kΩ L 100 100 0 V R = 600Ω L OL –100 10 V –200 OH –300 –400 1 –15 –10 –5 0 5 10 15 0.001 0.01 0.1 1 10 100 OUTPUT VOLTAGE (V) LOAD CURRENT (mA) Figure 14. Input Error Voltage vs. Output Voltage for Resistive Loads Figure 17. Output Saturation Voltage vs. Load Current 250 10k V =±5V R = 1kΩ SY L V = 5V SY 200 POS RAIL 150 R = 10kΩ R = 100kΩ 1k L L 100 50 0 100 R = 10kΩ L –50 R = 1kΩ L V OL –100 10 NEG RAIL –150 V OH –200 –250 1 0 50 100 150 200 250 300 0.001 0.01 0.1 1 10 100 OUTPUT VOLTAGE FROM SUPPLY RAILS (mV) LOAD CURRENT (mA) Figure 15. Input Error Voltage vs. Output Voltage within 300 mV of Figure 18. Output Saturation Voltage vs. Load Current Supply Rails 800 70 315 V =±13V SY 60 270 R = 2kΩ L 700 C = 40pF L +125°C 50 225 600 40 –55°C 180 +25°C GAIN 500 30 135 400 20 90 PHASE 10 45 300 0 –0 200 –10 –45 100 –20 –90 0 –30 –135 0 4 8 12 16 20 24 28 10k 100k 1M 10M 50M TOTAL SUPPLY VOLTAGE (V) FREQUENCY (Hz) Figure 16. Quiescent Current vs. Supply Voltage at Different Temperatures Figure 19. Open-Loop Gain and Phase Margin vs. Frequency Rev. E | Page 8 of 20 QUIESCENT CURRENT (μA) INPUT VOLTAGE (μV) OFFSET VOLTAGE (μV) 03023-016 03023-015 03023-014 GAIN (dB) V – OUTPUT VOLTAGE (mV) V – OUTPUT VOLTAGE (mV) SY SY 03023-018 03023-017 PHASE (Degrees) 03023-019 AD8625/AD8626/AD8627 70 140 315 V = 5V V =±13V SY SY 60 120 R = 2kΩ 270 L C = 40pF L 50 225 100 40 80 180 GAIN 30 135 60 20 90 40 PHASE 10 20 45 0 –0 0 –10 –45 –20 –20 –90 –40 –30 –135 –60 10k 100k 1M 10M 50M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 20. Open-Loop Gain and Phase Margin vs. Frequency Figure 23. CMRR vs. Frequency 70 140 V =±13V V =5V SY SY 60 R = 2kΩ 120 L C = 40pF L 50 100 40 80 G = +100 30 60 20 40 G = +10 10 20 0 0 G = +1 –10 –20 –20 –40 –30 –60 1k 10k 100k 1M 10M 50M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 21. Closed-Loop Gain vs. Frequency Figure 24. CMRR vs. Frequency 70 140 V =±13V V = 5V SY SY 60 120 R = 2kΩ L C = 40pF L 50 100 40 80 G = +100 +PSRR 30 60 20 40 G = +10 –PSRR 10 20 0 0 G = +1 –10 –20 –20 –40 –30 –60 1k 10k 100k 1M 10M 50M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. Closed-Loop Gain vs. Frequency Figure 25. PSRR vs. Frequency Rev. E | Page 9 of 20 GAIN (dB) GAIN (dB) GAIN (dB) 03023-022 03023-021 PHASE (Degrees) 03023-020 PSRR (dB) CMRR (dB) CMRR (dB) 03023-025 03023-024 03023-023 AD8625/AD8626/AD8627 140 V =±13V INPUT SY V =5V SY 120 100 80 60 40 OUTPUT +PSRR 20 –PSRR 0 –20 –40 –60 TIME (400μs/DIV) 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 26. PSRR vs. Frequency Figure 29. No Phase Reversal 15 300 V =±13V SY 270 10 240 TS + (1%) 210 5 TS + (0.1%) 180 0 150 120 TS – (0.1%) –5 90 G = +10 G = +1 TS – (1%) 60 –10 G = +100 30 –15 0 1k 10k 100k 1M 10M 100M 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (Hz) SETTLING TIME (μs) Figure 27. Output Impedance vs. Frequency Figure 30. Output Swing and Error vs. Settling Time 300 70 V =±13V V =5V S SY R = 10kΩ 270 L 60 V = 100mV p-p IN A = +1 240 V 50 210 180 40 OS– 150 30 OS+ 120 90 20 G = +10 G = +1 60 G = +100 10 30 0 0 1k 10k 100k 1M 10M 100M 10 100 1k CAPACITANCE (pF) FREQUENCY (Hz) Figure 28. Output Impedance vs. Frequency Figure 31. Small-Signal Overshoot vs. Load Capacitance Rev. E | Page 10 of 20 Z (Ω) Z (Ω) PSRR (dB) OUT OUT 03023-026 03023-028 03023-027 OVERSHOOT (%) OUTPUT SWING (V) VOLTAGE (10V/DIV) 03023-029 03023-031 03023-030 AD8625/AD8626/AD8627 70 56 V =±2.5V S V =±13V SY R = 10kΩ L 49 60 V = 100mV p-p IN A = +1 V 42 50 35 40 19.7nV/ Hz 28 30 21 OS+ 20 14 OS– 10 7 0 0 10 100 1k 012 34 567 89 10 CAPACITANCE (pF) FREQUENCY (kHz) Figure 32. Small-Signal Overshoot vs. Load Capacitance Figure 35. Voltage Noise Density 56 V =±13V SY V = 5V SY A = 100,000V/V VO 49 42 35 16.7nV/ Hz 0 28 21 14 7 0 TIME (1s/DIV) 012 34 567 89 10 FREQUENCY (kHz) Figure 36. Voltage Noise Density Figure 33. 0.1 Hz to 10 Hz Noise –40 V =±2.5V SY A = 100,000V/V VO –50 –60 –70 V =±5V, V = 9V p-p SY IN 0 –80 V =±13V, V = 18V p-p SY IN –90 V =±2.5V, V = 4.5V p-p SY IN –100 –110 TIME (1s/DIV) 10 100 1k 10k 100k FREQUENCY (Hz) Figure 37. Total Harmonic Distortion + Noise vs. Frequency Figure 34. 0.1 Hz to 10 Hz Noise Rev. E | Page 11 of 20 OVERSHOOT (%) VOLTAGE (50mV/DIV) VOLTAGE (50mV/DIV) 03023-034 03023-033 03023-032 THD + NOISE (dB) VOLTAGE (nV) VOLTAGE (nV) 03023-036 03023-035 03023-037 AD8625/AD8626/AD8627 20kΩ 2kΩ 2kΩ 2kΩ V IN –80 –90 –100 V = 9V p-p IN –110 V = 4.5V p-p IN V = 18V p-p IN –120 –130 –140 –150 –160 10 100 1k 10k 100k FREQUENCY (Hz) Figure 38. Channel Separation Rev. E | Page 12 of 20 CHANNEL SEPARATION (dB) 03023-049 AD8625/AD8626/AD8627 APPLICATIONS INFORMATION The AD862x is one of the smallest and most economical V = 5V SY JFETs offered. It has true single-supply capability and has INPUT an input voltage range that extends below the negative rail, 4V allowing the part to accommodate input signals below ground. The rail-to-rail output of the AD862x provides the maximum dynamic range in many applications. To provide a low offset, 0V low noise, high impedance input stage, the AD862x uses 4V n-channel JFETs. The input common-mode voltage extends OUTPUT from 0.2 V below –VS to 2 V below +VS. Driving the input of the amplifier, configured in the unity gain buffer, closer than 0V 2 V to the positive rail causes an increase in common-mode voltage error, as illustrated in Figure 15, and a loss of amplifier bandwidth. This loss of bandwidth causes the rounding of the TIME (2μs/DIV) output waveforms shown in Figure 39 and Figure 40, which Figure 39. Unity Gain Follower Response to 0 V to 4 V Step have inputs that are 1 V and 0 V from +V , respectively. S The AD862x does not experience phase reversal with input V = 5V SY signals close to the positive rail, as shown in Figure 29. For 5V input voltages greater than +VSY, a resistor in series with the INPUT AD862x’s noninverting input prevents phase reversal at the expense of greater input voltage noise. This current-limiting resistor should also be used if there is a possibility of the input 0V voltage exceeding the positive supply by more than 300 mV, or if an input voltage is applied to the AD862x when ±V = 0. SY 4V OUTPUT Either of these conditions damages the amplifier if the condition exists for more than 10 seconds. A 100 kΩ resistor allows the amplifier to withstand up to 10 V of continuous 0V overvoltage, while increasing the input voltage noise by a negligible amount. TIME (2μs/DIV) Figure 40. Unity Gain Follower Response to 0 V to 5 V Step Rev. E | Page 13 of 20 VOLTAGE (2V/DIV) VOLTAGE (2V/DIV) 03023-039 03023-038 AD8625/AD8626/AD8627 20kΩ The AD862x can safely withstand input voltages 15 V below V if the total voltage between the positive supply and the input SY +5V 10kΩ terminal is less than 26 V. Figure 41 through Figure 43 show the 0V AD862x in different configurations accommodating signals –10mV close to the negative rail. The amplifier input stage typically –30mV maintains picoamp-level input currents across that input voltage range. V = 5V SY 20kΩ +5V 10kΩ 0V –2.5V V = 5V, 0V SY 5V 0V TIME (2μs/DIV) Figure 43. Gain-of-Two Inverter Response to 20 mV Step, Centered 20 mV below Ground The AD862x is designed for 16 nV/√Hz wideband input voltage noise and maintains low noise performance to low frequencies, 0V as shown in Figure 35. This noise performance, along with the AD862x’s low input current and current noise, means that the TIME (2μs/DIV) AD862x contributes negligible noise for applications with large Figure 41. Gain-of-Two Inverter Response to 2.5 V Step, source resistances. Centered 1.25 V below Ground The AD862x has a unique bipolar rail-to-rail output stage that 60mV swings within 5 mV of the rail when up to 2 mA of current is 5V 20mV drawn. At larger loads, the drop-out voltage increases, as shown 0V in Figure 17 and Figure 18. The AD862x’s wide bandwidth and fast slew rate allows it to be used with faster signals than older 600Ω single-supply JFETs. Figure 44 shows the response of the AD862x, configured in unity gain, to a V of 20 V p-p at IN 50 kHz. The full-power bandwidth (FPBW) of the part is close to 100 kHz. V =±13V SY R = 600Ω L 0V V = 5V SY R = 600Ω L 0V TIME (2μs/DIV) Figure 42. Unity Gain Follower Response to 40 mV Step, Centered 40 mV above Ground TIME (5μs/DIV) Figure 44. Unity Gain Follower Response to 20 V, 50 kHz Input Signal Rev. E | Page 14 of 20 VOLTAGE (10mV/DIV) VOLTAGE (1V/DIV) 03023-041 03023-040 VOLTAGE (5V/DIV) VOLTAGE (10mV/DIV) 03023-043 03023-042 AD8625/AD8626/AD8627 MINIMIZING INPUT CURRENT PHOTODIODE PREAMPLIFIER APPLICATION The AD862x is guaranteed to 1 pA maximum input current The low input current and offset voltage levels of the AD862x, with a ±13 V supply voltage at room temperature. Careful together with its low voltage noise, make this amplifier an attention to how the amplifier is used maintains or possibly excellent choice for preamplifiers used in sensitive photodiode betters this performance. The amplifier’s operating temperature applications. In a typical photovoltaic preamp circuit, shown in should be kept as low as possible. Like other JFET input ampli- Figure 45, the output of the amplifier is equal to fiers, the AD862x’s input current doubles for every 10°C rise in V =−ID(R )=−R (P)R OUT f p f junction temperature, as illustrated in Figure 8. On-chip power where: dissipation raises the device operating temperature, causing an increase in input current. Reducing supply voltage to cut power ID = photodiode signal current (A). dissipation reduces the AD862x’s input current. Heavy output Rp = photodiode sensitivity (A/W). loads can also increase chip temperature; maintaining a Rf = value of the feedback resistor, in Ω. minimum load resistance of 1 kΩ is recommended. P = light power incident to photodiode surface, in W. The AD862x is designed for mounting on PC boards. Main- The amplifier’s input current, I , contributes an output voltage B taining picoampere resolution in those environments requires error proportional to the value of the feedback resistor. The offset voltage error, V , causes a small current error due to the a lot of care. Both the board and the amplifier’s package have OS finite resistance. Voltage differences between the input pins and photodiode’s finite shunt resistance, RD. other pins, as well as PC board metal traces may cause parasitic The resulting output voltage error, VE, is equal to currents larger than the AD862x’s input current, unless special R ⎛ ⎞ precautions are taken. To ensure the best result, refer to the ADI f ⎜ ⎟ V = 1+ V + R (I ) E OS f B ⎜ ⎟ website for proper board layout seminar materials. Two R ⎝ D⎠ common methods of minimizing parasitic leakages that should A shunt resistance on the order of 100 MΩ is typical for a small be used are guarding of the input lines and maintaining photodiode. Resistance R is a junction resistance that typically D adequate insulation resistance. drops by a factor of two for every 10°C rise in temperature. In Contaminants, such as solder flux on the board’s surface and the AD862x, both the offset voltage and drift are low, which the amplifier’s package, can greatly reduce the insulation helps minimize these errors. With I values of 1 pA and V of B OS resistance between the input pin and traces with supply or 50 mV, VE for Figure 45 is very negligible. Also, the circuit in signal voltages. Both the package and the board must be kept Figure 45 results in an SNR value of 95 dB for a signal bandwidth clean and dry. of 30 kHz. C F 5pF R F PHOTODIODE 1.5MΩ V OS OUTPUT C4 R I I D B B 15pF AD8627 100MΩ Figure 45. A Photodiode Model Showing DC Error Rev. E | Page 15 of 20 03023-044 AD8625/AD8626/AD8627 OUTPUT AMPLIFIER FOR DACs 5V 2.5V Many system designers use amplifiers as buffers on the output 10μF of amplifiers to increase the DAC’s output driving capability. 0.1μF 0.1μF The high resolution current output DACs need high precision 5V amplifiers on their output as current-to-voltage converters SERIAL (I/V). Additionally, many DACs operate with a single supply of V V *V * DD REFF REFS INTERFACE 5 V. In a single-supply application, selection of a suitable op CS AD8627 DIN UNIPOLAR amp may be more difficult because the output swing of the OUT AD5551/AD5552 OUTPUT SCLK amplifier does not usually include the negative rail, in this case LDAC* AGND. This can result in some degradation of the DAC’s DGND AGND specified performance, unless the application does not use *AD5552 ONLY codes near zero. The selected op amp needs to have very low Figure 46. Unipolar Output offset voltage—for a 14-bit DAC, the DAC LSB is 300 μV with a 5 V reference—to eliminate the need for output offset trims. 10kΩ Input bias current should also be very low because the bias 10kΩ +13V current multiplied by the DAC output impedance (about 10 kΩ in some cases) adds to the zero-code error. Rail-to-rail input and 10V output performance is desired. For fast settling, the slew rate of 1/2 VREF V OUT AD8626 5kΩ the op amp should not impede the settling time of the DAC. ADR01 –10V < V < +10V Output impedance of the DAC is constant and code OUT independent, but in order to minimize gain errors, the input –13V impedance of the output amplifier should be as high as possible. V V XR X DD REF FB The AD862x, with a very high input impedance, I B of 1 pA, and a fast slew rate, is an ideal amplifier for these types of ONE CHANNEL AD5544 applications. A typical configuration with a popular DAC is 1/2 AD8626 shown in Figure 46. In these situations, the amplifier adds V A FA X SS GND GND another time constant to the system, increasing the settling time DIGITAL INTERFACE CONNECTIONS of the output. The AD862x, with 5 MHz of BW, helps in OMITTED FOR CLARITY achieving a faster effective settling time of the combined DAC Figure 47. 4-Quadrant Multiplying Application Circuit and amplifier. In applications with full 4-quadrant multiplying capability or a bipolar output swing, the circuit in Figure 47 can be used. In this circuit, the first and second amplifiers provide a total gain of 2, which increases the output voltage span to 20 V. Biasing the external amplifier with a 10 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. Rev. E | Page 16 of 20 03023-045 03023-046 AD8625/AD8626/AD8627 1.2 EIGHT-POLE SALLEN KEY LOW-PASS FILTER V4 The AD862x’s high input impedance and dc precision make it a great selection for active filters. Due to the very low bias current V2 V3 of the AD862x, high value resistors can be used to construct low 0.8 frequency filters. The AD862x’s picoamp-level input currents V1 contribute minimal dc errors. Figure 49 shows an example of a 10 Hz, 8-pole Sallen Key filter constructed using the AD862x. Different numbers of the AD862x can be used depending on 0.4 the desired response, which is shown in Figure 48. The high value used for R1 minimizes interaction with signal source resistance. Pole placement in this version of the filter minimizes the Q associated with the lower pole section of the filter. This 0 0.1 1 10 100 1k eliminates any peaking of the noise contribution of resistors in FREQUENCY (Hz) the preceding sections, minimizing the inherent output voltage Figure 48. Frequency Response Output at Different Stages noise of the filter. of the Low-Pass Filter C1 100μF R1 162.3kΩ V V3 DD R2 V 162.3kΩ U1 C3 IN R10 4 3 100μF 191.4kΩ V1 1 2 D 1/4 R5 C2 R11 AD8625 11 191.4kΩ U2 C5 96.19μF 286.5kΩ V 100μF V2 EE D 1/4 R3 C4 R7 AD8625 25kΩ C7 69.14μF 286.5kΩ R12 100μF U3 815.8kΩ D V3 R4 R9 25kΩ 815.8kΩ U4 1/4 C6 AD8625 30.86μF V4 D 1/4 C8 AD8625 R6 3.805μF 25kΩ D R8 25kΩ Figure 49. 10 Hz, 8-Pole Sallen Key Low-Pass Filter Rev. E | Page 17 of 20 VOLTAGE (V) 03023-048 03023-047 AD8625/AD8626/AD8627 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 5 4 2.40 1.25 2.10 1.15 12 3 1.80 0.65 BSC 1.00 0.40 1.10 0.90 0.10 0.80 0.70 0.46 0.22 SEATING 0.10 MAX 0.36 0.30 0.08 PLANE COPLANARITY 0.26 0.15 0.10 COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 50. 5-Lead Plastic Surface-Mount Package [SC70] (KS-5) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 51. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. E | Page 18 of 20 012407-A 072809-A AD8625/AD8626/AD8627 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 52. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 8 14 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 53. 14-Lead Standard Small Outline Package [SOIC_N] (R-14) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 54. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. E | Page 19 of 20 10-07-2009-B 061908-A 060606-A AD8625/AD8626/AD8627 ORDERING GUIDE 1, 2 Model Temperature Range Package Description Package Option Branding AD8625ARUZ –40°C to +85°C 14-Lead TSSOP RU-14 AD8625ARUZ-REEL –40°C to +85°C 14-Lead TSSOP RU-14 AD8625AR –40°C to +85°C 14-Lead SOIC_N R-14 AD8625AR-REEL –40°C to +85°C 14-Lead SOIC_N R-14 AD8625AR-REEL7 –40°C to +85°C 14-Lead SOIC_N R-14 AD8625ARZ –40°C to +85°C 14-Lead SOIC_N R-14 AD8625ARZ-REEL –40°C to +85°C 14-Lead SOIC_N R-14 AD8625ARZ-REEL7 –40°C to +85°C 14-Lead SOIC_N R-14 AD8626ARMZ-REEL –40°C to +85°C 8-Lead MSOP RM-8 BJA AD8626ARMZ –40°C to +85°C 8-Lead MSOP RM-8 BJA AD8626ARZ –40°C to +85°C 8-Lead SOIC_N R-8 AD8626ARZ-REEL –40°C to +85°C 8-Lead SOIC_N R-8 AD8626ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8 AD8627AKSZ-REEL –40°C to +85°C 5-Lead SC70 KS-5 B9B AD8627AKSZ-REEL7 –40°C to +85°C 5-Lead SC70 KS-5 B9B AD8627AKSZ-R2 –40°C to +85°C 5-Lead SC70 KS-5 B9B AD8627ARZ –40°C to +85°C 8-Lead SOIC_N R-8 AD8627ARZ-REEL –40°C to +85°C 8-Lead SOIC_N R-8 AD8627ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8 1 Z = RoHS Compliant Part; # denotes product may be top or bottom marked. 2 For the AD8627AKS models, pre-0542 parts were branded with B9A without #. ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03023-0-12/10(E) Rev. E | Page 20 of 20