ANALOG DEVICES AD8614

Single and Quad 18 V Operational Amplifiers AD8614/AD8644 FEATURES PIN CONFIGURATIONS Unity-gain bandwidth: 5.5 MHz OUT A 1 5 V+ Low voltage offset: 1.0 mV AD8614 Slew rate: 7.5 V/μs V– 2 TOP VIEW (Not to Scale) Single-supply operation: 5 V to 18 V +IN 3 4 –IN High output current: 70 mA Low supply current: 800 μA/amplifier Figure 1. 5-Lead SOT-23 Stable with large capacitive loads (RJ-5) Rail-to-rail inputs and outputs OUT A 1 14 OUT D APPLICATIONS 2 –IN A 13 –IN D LCD gamma and VCOM drivers 3 +IN A AD8644 12 +IN D TOP VIEW Modems 4 11 V+ V– (Not to Scale) Portable instrumentation 5 10 +IN B +IN C Direct access arrangement 6 9 –IN B –IN C 7 8 OUT B OUT C GENERAL DESCRIPTION Figure 2. 14-Lead TSSOP The AD8614 (single) and AD8644 (quad) are single-supply, (RU-14) 5.5 MHz bandwidth, rail-to-rail amplifiers optimized for LCD monitor applications. OUT A 1 14 OUT D –IN A 2 13 –IN D They are processed using the Analog Devices, Inc. high voltage, +IN A 3 12 +IN D AD8644 extra fast complementary bipolar (HV XFCB) process. This TOP VIEW V+ 4 11 V– (Not to Scale) proprietary process includes trench-isolated transistors that 5 10 +IN B +IN C lower internal parasitic capacitance, which improves gain –IN B 6 9 –IN C bandwidth, phase margin, and capacitive load drive. The low OUT B 7 8 OUT C supply current of 800 μA (typical) per amplifier is critical for Figure 3. 14-Lead Narrow Body SOIC portable or densely packed designs. In addition, the rail-to-rail (R-14) output swing provides greater dynamic range and control than standard video amplifiers provide. These products operate from supplies of 5 V to as high as 18 V. The unique combination of an output drive of 70 mA, high slew rates, and high capacitive drive capability makes the AD8614/AD8644 an ideal choice for LCD applications. The AD8614 and AD8644 are specified over the temperature range of –20°C to +85°C. They are available in 5-lead SOT-23, 14-lead TSSOP, and 14-lead SOIC surface-mount packages in tape and reel. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06485-001 06485-003 06485-002 AD8614/AD8644 TABLE OF CONTENTS Features .............................................................................................. 1 Output Short-Circuit Protection.................................................9 Applications....................................................................................... 1 Input Overvoltage Protection ................................................... 10 General Description ......................................................................... 1 Output Phase Reversal............................................................... 10 Pin Configurations ........................................................................... 1 Power Dissipation....................................................................... 10 Revision History ............................................................................... 2 Unused Amplifiers ..................................................................... 10 Specifications..................................................................................... 3 Capacitive Load Drive ............................................................... 11 Electrical Characteristics............................................................. 3 Direct Access Arrangement ...................................................... 11 Absolute Maximum Ratings............................................................ 4 A One-Chip Headphone/Microphone Preamplifier Solution........................................................................................ 11 Thermal Resistance ...................................................................... 4 Outline Dimensions....................................................................... 13 ESD Caution.................................................................................. 4 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 5 Theory of Operation ........................................................................ 9 REVISION HISTORY 9/07—Rev. A to Rev B Change to Current Noise Density in Table 1 ................................ 3 12/06—Rev. 0 to Rev. A Updated Format..................................................................Universal Deleted SPICE Model Availability Section.................................. 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 10/99—Revision 0: Initial Version Rev. B | Page 2 of 16 AD8614/AD8644 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 1 5 V ≤ V ≤ 18 V, V = V /2, T = 25°C, unless otherwise noted. S CM S A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 1.0 2.5 mV OS −20°C ≤ T ≤ +85°C 3 mV A Input Bias Current I 80 400 nA B −20°C ≤ TA ≤ +85°C 500 nA Input Offset Current IOS 5 100 nA −20°C ≤ TA ≤ +85°C 200 nA Input Voltage Range 0 V V S Common-Mode Rejection Ratio CMRR V = 0 V to V 60 75 dB CM S Voltage Gain A V = 0.5 V to V – 0.5 V, R = 10 kΩ 10 150 V/mV VO OUT S L OUTPUT CHARACTERISTICS Output Voltage High V I = 10 mA V − 0.15 V OH LOAD S Output Voltage Low V I = 10 mA 65 150 mV OL LOAD Output Short-Circuit Current ISC 35 70 mA −20°C ≤ TA ≤ +85°C 30 mA POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±2.25 V to ±9.25 V 80 110 dB Supply Current/Amplifier ISY 0.8 1.1 mA −20°C ≤ T ≤ +85°C 1.5 mA A DYNAMIC PERFORMANCE Slew Rate SR CL = 200 pF 7.5 V/μs Gain Bandwidth Product GBP 5.5 MHz Phase Margin Φo 65 Degrees Settling Time t 0.01%, 10 V step 3 μs S NOISE PERFORMANCE Voltage Noise Density e f = 1 kHz 12 nV/√Hz n en f = 10 kHz 11 nV/√Hz Current Noise Density in f = 10 kHz 1 pA/√Hz 1 All typical values are for VS = 18 V. Rev. B | Page 3 of 16 AD8614/AD8644 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. θ is specified for the worst-case conditions, that is, a device JA Parameter Rating soldered in a circuit board for surface-mount packages. Supply Voltage 20 V Input Voltage GND to V S Table 3. Thermal Resistance Storage Temperature Range −65°C to +150°C Package Type θ θ Unit JA JC Operating Temperature Range −20°C to +85°C 5-Lead SOT-23 (RJ) 230 140 °C/W Junction Temperature Range −65°C to +150°C 14-Lead TSSOP (RU) 180 35 °C/W Lead Temperature Range (Soldering, 60 sec) 300°C 14-Lead SOIC (R) 120 56 °C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ESD CAUTION rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 4 of 16 AD8614/AD8644 TYPICAL PERFORMANCE CHARACTERISTICS 50 7.5 V =18V V =5V S S R =2kΩ R =2kΩ 45 6.5 L L T =25°C C =200pF L A A =1 40 5.5 V T =25°C A 35 4.5 30 3.5 25 2.5 20 1.5 15 0.5 +OS 10 –0.5 –OS 5 –1.5 0 –2.5 10 100 1k 10k TIME (1µs/DIV) CAPACITANCE (pF) Figure 7. Large Signal Transient Response, V = 5 V Figure 4. Small Signal Overshoot vs. Load Capacitance S 12 29 V =18V S R =2kΩ 25 L C =200pF L 8 A =1 V 21 T = 25°C A 0.1% 0.01% 17 4 13 0 9 5 –4 0.1% 1 0.01% –3 –8 –7 –12 –11 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TIME (1µs/DIV) SETTLING TIME (µs) Figure 8. Large Signal Transient Response, V = 18 V Figure 5. Output Swing vs. Settling Time S 80 45 60 40 90 5V≤ V ≤ 18V S 20 R =1MΩ 135 L =40pF C L V S T = 25°C 0 A 180 2 V =5V≤ V ≤ 18V S S R =2kΩ L C = 200pF L A =1 V T = 25°C A TIME (500ns/DIV) 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 9. Small Signal Transient Response Figure 6. Open-Loop Gain and Phase Shift vs. Frequency Rev. B | Page 5 of 16 GAIN (dB) OUTPUT SWING FROM 0 TO ±V SMALL SIGNAL OVERSHOOT (%) 06485-006 06485-005 06485-004 PHASE SHIFT (Degrees) VOLTAGE (50mV/DIV) VOLTAGE (4V/DIV) VOLTAGE (1V/DIV) 06485-009 06485-008 06485-007 AD8614/AD8644 10k 400 5V≤ V ≤ 18V S V =±9V S T =25°C A 300 200 1k 100 0 100 –100 SINK 10 SOURCE –200 –300 1 –400 0.001 0.01 0.1 1 10 100 –9 –7 –5 –3 –1 013579 LOAD CURRENT (mA) COMMON-MODE VOLTAGE (V) Figure 10. Output Voltage to Supply Rail vs. Load Current Figure 13. Input Bias Current vs. Common-Mode Voltage, VS = ±9 V 1000 180 T = 25°C 2.5V≤ V ≤ 9V A S T = 25°C 900 A 160 800 140 700 120 600 100 500 80 400 60 300 40 200 20 100 0 0 0 1234 567 89 10 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 SUPPLY VOLTAGE (±V) INPUT OFFSET VOLTAGE (mV) Figure 11. Supply Current vs. Supply Voltage Figure 14. Input Offset Voltage Distribution 400 1.0 V = ±2.5V S 300 0.9 V =18V 200 S 100 0.8 0 0.7 –100 V =5V S –200 0.6 –300 –400 0.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 –35 –15 5 25 45 65 85 COMMON-MODE VOLTAGE (V) TEMPERATURE (°C) Figure 12. Input Bias Current vs. Common-Mode Voltage, VS = ±2.5 V Figure 15. Supply Current vs. Temperature Rev. B | Page 6 of 16 INPUT BIAS CURRENT (nA) SUPPLY CURRENT/AMPLIFIER (µA) ΔOUTPUT VOLTAGE (mV) 06485-012 06485-011 06485-010 SUPPLY CURRENT/AMPLIFIER (mA) QUANTITY (Amplifiers) INPUT BIAS CURRENT (nA) 06485-015 06485-014 06485-013 AD8614/AD8644 6 5V≤ V ≤ 18V S T =25°C A 5 40 V =5V S A =1 VCL R =2kΩ L 4 T = 25°C A 20 3 0 2 1 0 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. Maximum Output Swing vs. Frequency, V = 5 V Figure 19. Closed-Loop Gain vs. Frequency S 20 140 5V≤ V ≤ 18V S 18 T =25°C A 120 V = 18V S 16 A =1 VCL R =2kΩ L 100 14 T = 25°C A 12 80 10 60 8 6 40 4 20 2 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Maximum Output Swing vs. Frequency, V = 18 V Figure 20. Common-Mode Rejection vs. Frequency S 300 100 V = 18V 5V≤ V ≤ 18V S S T = 25°C T =25°C A A 240 80 180 60 PSRR+ 120 40 PSRR– 60 20 A =1 V A =10 V A =100 V 0 0 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 18. Closed-Loop Output Impedance vs. Frequency Figure 21. Power Supply Rejection vs. Frequency Rev. B | Page 7 of 16 IMPEDANCE (Ω) OUTPUT SWING (V p-p) OUTPUT SWING (V p-p) 06485-018 06485-017 06485-016 GAIN (dB) POWER SUPPLY REJECTION (dB) COMMON-MODE REJECTION (dB) 06485-021 06485-020 06485-019 AD8614/AD8644 100 9 V = 18V S T = 25°C A 8 SR+ 7 6 SR– 5 10 4 3 2 A =1 V R =2kΩ L 1 C = 200pF L T = 25°C A 0 1 02468 10 12 14 16 18 20 10 100 1k 10k SUPPLY VOLTAGE (V) FREQUENCY (Hz) Figure 22. Slew Rate vs. Supply Voltage Figure 24. Voltage Noise Density vs. Frequency, V = 18 V S 100 V =5V S T =25°C A 10 1 10 100 1k 10k FREQUENCY (Hz) Figure 23. Voltage Noise Density vs. Frequency, V = 5 V S Rev. B | Page 8 of 16 VOLTAGE NOISE DENSITY (nV/ Hz) SLEW RATE (V/µs) 06485-023 06485-022 VOLTAGE NOISE DENSITY (nV/ Hz) 06485-024 AD8614/AD8644 THEORY OF OPERATION The AD8614/AD8644 are processed using Analog Devices high OUTPUT SHORT-CIRCUIT PROTECTION voltage, extra fast complementary bipolar (HV XFCB) process. To achieve a wide bandwidth and high slew rate, the output of This process includes trench-isolated transistors that lower the AD8614/AD8644 is not short-circuit protected. Shorting parasitic capacitance. the output directly to ground or to a supply rail can destroy the Figure 26 shows a simplified schematic of the AD8614/AD8644. device. The typical maximum safe output current is 70 mA. The input stage is rail-to-rail, consisting of two complementary In applications where some output current protection is needed, differential pairs, one NPN pair and one PNP pair. The input but not at the expense of reduced output voltage headroom, a stage is protected against avalanche breakdown by two back-to- low value resistor in series with the output can be used. This is back diodes. Each input has a 1.5 kΩ resistor that limits input shown in Figure 25. The resistor is connected within the current during overvoltage events and furnishes phase reversal feedback loop of the amplifier so that if V is shorted to OUT protection if the inputs are exceeded. The two differential pairs ground and V swings up to 18 V, the output current does not IN are connected to a double-folded cascode. This is the stage in exceed 70 mA. the amplifier with the most gain. The double-folded cascode For 18 V single-supply applications, resistors less than 261 Ω are differentially feeds the output stage circuitry. Two complemen- not recommended. tary common emitter transistors are used as the output stage. 18V This allows the output to swing to within 125 mV from each rail with a 10 mA load. The gain of the output stage, and thus the V open-loop gain of the op amp, depends on the load resistance. IN 261Ω V OUT AD86x4 The AD8614/AD8644 have no built-in short-circuit protection. The short-circuit limit is a function of high current roll-off of the output stage transistors and the voltage drop over the resistor shown on the schematic at the output stage. The voltage over this resistor is clamped to one diode during short-circuit Figure 25. Output Short-Circuit Protection voltage events. V CC – 1.5kΩ 1.5kΩ + V OUT V V CC CC V EE Figure 26. Simplified Schematic Rev. B | Page 9 of 16 06485-025 06485-026 AD8614/AD8644 To calculate the internal junction temperature of the INPUT OVERVOLTAGE PROTECTION AD8614/AD8644, the following formula can be used: As with any semiconductor device, whenever the condition T = P × θ + T J DISS JA A exists for the input to exceed either supply voltage, attention needs to be paid to the input overvoltage characteristic. As an where: overvoltage occurs, the amplifier can be damaged, depending TJ is the AD8614/AD8644 junction temperature. on the voltage level and the magnitude of the fault current. PDISS is the AD8614/AD8644 power dissipation. When the input voltage exceeds either supply by more than θJA is the AD8614/AD8644 junction-to-ambient package thermal 0.6 V, internal pin junctions energize, allowing current to flow resistance. from the input to the supplies. Observing Figure 26, the T is the ambient temperature of the circuit. A AD8614/AD8644 have 1.5 kΩ resistors in series with each The power dissipated by the device can be calculated as: input, which helps to limit the current. This input current is not inherently damaging to the device as long as it is limited to PDISS = ILOAD × (VS – VOUT) 5 mA or less. If the voltage is large enough to cause more than where: 5 mA of current to flow, an external series resistor should be ILOAD is the AD8614/AD8644 output load current. added. The size of this resistor is calculated by dividing the VS is the AD8614/AD8644 supply voltage. maximum overvoltage by 5 mA and subtracting the internal V is the AD8614/AD8644 output voltage. OUT 1.5 kΩ resistor. For example, if the input voltage could reach 100 V, the external resistor should be (100 V ÷ 5 mA) – 1.5 kΩ = 18.5 kΩ. Figure 27 provides a convenient way to determine if the device This resistance should be placed in series with either or both is being overheated. The maximum safe power dissipation can inputs if they are subjected to the overvoltages. be found graphically, based on the package type and the ambient temperature around the package. By using the previous equation, it OUTPUT PHASE REVERSAL is a simple matter to see if PDISS exceeds the device’s power derating The AD8614/AD8644 are immune to phase reversal as long as curve. To ensure proper operation, it is important to observe the the input voltage is limited to within the supply rails. Although recommended derating curves shown in Figure 27. the device’s output does not change phase, large currents due to 1.5 input overvoltage can result, damaging the device. In applica- tions where the possibility of an input voltage exceeding the 14-LEAD SOIC PACKAGE θ = 120°C/W supply voltage exists, overvoltage protection should be used, as JA described in the previous section. 1.0 14-LEAD TSSOP PACKAGE POWER DISSIPATION θ = 180°C/W JA The maximum power that can be safely dissipated by the AD8614/AD8644 is limited by the associated rise in junction 0.5 5-LEAD SOT-23 PACKAGE temperature. The maximum safe junction temperature is 150°C, θ = 230°C/W JA and should not be exceeded or device performance could suffer. If this maximum is momentarily exceeded, proper circuit operation is restored as soon as the die temperature is reduced. 0 –35 –15 5 254565 85 Leaving the device in an overheated condition for an extended AMBIENT TEMPERATURE (°C) period can result in permanent damage to the device. Figure 27. Maximum Power Dissipation vs. Temperature (5-Lead and 14-Lead Package Types) UNUSED AMPLIFIERS It is recommended that any unused amplifiers in the quad package be configured as a unity-gain follower with a 1 kΩ feedback resistor connected from the inverting input to the output, and the noninverting input tied to the ground plane. Rev. B | Page 10 of 16 MAXIMUM POWER DISSIPATION (W) 06485-027 AD8614/AD8644 P1 CAPACITIVE LOAD DRIVE Tx GAIN ADJUST R2 9.09kΩ The AD8614/AD8644 exhibit excellent capacitive load driving C1 TRANSMIT R1 TO TELEPHONE 2kΩ 0.1µF TxA capabilities. Although the device is stable with large capacitive 10kΩ LINE R3 2 360Ω 1 1:1 loads, there is a decrease in amplifier bandwidth as the A1 3 R5 6.2V capacitive load increases. ZO 10kΩ 600Ω 6.2V When driving heavy capacitive loads directly from the 5V DC T1 R6 AD8614/AD8644 output, a snubber network can be used to MIDCOM 6 10kΩ 671-8005 R7 7 A2 10kΩ improve the transient response. This network consists of a 5 series R-C connected from the amplifier’s output to ground, R8 10µF 10kΩ placing it in parallel with the capacitive load. The configuration R9 R10 is shown in Figure 28. Although this network does not increase 10kΩ 10kΩ P2 Rx GAIN the bandwidth of the amplifier, it does significantly reduce the ADJUST RECEIVE 2 R13 R14 RxA 10kΩ 14.3kΩ R11 1 amount of overshoot. A3 10kΩ 3 2kΩ C2 6 R12 0.1µF 7 5V A4 10kΩ 5 A1, A2 = 1/2 AD8644 A3, A4 = 1/2 AD8644 Figure 29. A Single-Supply Direct Access Arrangement for Modems V OUT AD86x4 A ONE-CHIP HEADPHONE/MICROPHONE C V R L IN X PREAMPLIFIER SOLUTION C X Because of its high output current performance, the AD8644 makes an excellent amplifier for driving an audio output jack in Figure 28. Snubber Network Compensation for Capacitive Loads a computer application. Figure 30 shows how the AD8644 can The optimum values for the snubber network should be be interfaced with an ac codec to drive headphones or speakers. determined empirically based on the size of the capacitive load. 5V Table 4 shows a few sample snubber network values for a given load capacitance. 5V AV 25 DD1 C1 R3 10 100µF Table 4. Snubber Networks for Large Capacitive Loads VREFOUT 28 2 20Ω + U1-A 1 Load Capacitance (C ) Snubber Network (R , C ) L X X 4 LINE_OUT_L 35 R1 3 2kΩ 0.47 nF 300 Ω, 0.1 μF 5 4.7 nF 30 Ω, 1 μF AD1881A (AC'97) 47 nF 5 Ω, 10 μF DIRECT ACCESS ARRANGEMENT 6 C2 Figure 29 shows a schematic for a 5 V single-supply transmit/ 36 R4 LINE_OUT_R 100µF 7 20Ω + U1-B receive telephone line interface for 600 Ω transmission systems. It AV 26 SS1 9 R2 allows full duplex transmission of signals on a transformer- 8 2kΩ coupled 600 Ω line. Amplifier A1 provides gain that can be adjusted to meet the modem’s output drive requirements. Both U1 = AD8644 NOTES A1 and A2 are configured to apply the largest possible differential 1. ADDITIONAL PINS OMITTED FOR CLARITY. signal to the transformer. The largest signal available on a single Figure 30. A PC-99-Compliant Headphone/Line Out Amplifier 5 V supply is approximately 4.0 V p-p into a 600 Ω transmission system. Amplifier A3 is configured as a difference amplifier to extract the receive information from the transmission line for amplification by A4. A3 also prevents the transmit signal from interfering with the receive signal. The gain of A4 can be adjusted in the same manner as A1 to meet the modem input signal requirements. Standard resistor values permit the use of single in-line package (SIP) format resistor arrays. Couple this with the AD8644 14-lead SOIC or TSSOP package and this circuit can offer a compact solution. Rev. B | Page 11 of 16 06485-028 06485-030 06485-029 AD8614/AD8644 If gain is required from the output amplifier, four additional current from the headphones and create a high-pass filter with a resistors should be added as shown in Figure 31. corner frequency of 5V 1 R6 f = 20kΩ −3 dB 2πC1() R4+ R 25 AV L DD1 5V 38 AV DD2 where RL is the resistance of the headphones. C1 35 R3 10 LINE_OUT_L 100µF 2 20Ω R5 + The remaining two amplifiers can be used as low voltage 10kΩ U1-A 1 microphone preamplifiers. A single AD8614 can be used as a 4 R1 3 2kΩ standalone microphone preamplifier. Figure 32 shows this 5 implementation. 27 VREF 10kΩ 5V A = 20dB 2.2kΩ V 6 AD1881A 1µF 1kΩ C2 + (AC'97) R4 100µF 7 20Ω + R5 21 MIC1 U1-B 9 10kΩ MIC 1 LINE_OUT_R 36 R2 8 2kΩ 26 AV SS1 10kΩ 5V AD1881A R6 (AC'97) 20kΩ U1 = AD8644 A = 20dB 2.2kΩ V 1µF 1kΩ + R6 A = = +6dB WITH VALUES SHOWN V R5 22 MIC2 NOTES MIC 2 1. ADDITIONAL PINS OMITTED FOR CLARITY. Figure 31. A PC-99-Compliant Headphone/Speaker Amplifier with Gain VREF 27 The gain of the AD8644 can be set as Figure 32. Microphone Preamplifier R6 A = V R5 Input coupling capacitors are not required for either circuit as the reference voltage is supplied from the AD1881A. The resistors R4 and R5 help protect the AD8644 output in case the output jack or headphone wires are accidentally shorted to ground. The output coupling capacitors C1 and C2 block dc Rev. B | Page 12 of 16 06485-031 06485-032 AD8614/AD8644 OUTLINE DIMENSIONS 5.10 2.90 BSC 5.00 4.90 5 4 14 8 1.60 BSC 2.80 BSC 4.50 12 3 6.40 4.40 BSC 4.30 PIN 1 0.95 BSC 1 7 1.90 1.30 BSC PIN 1 1.15 0.90 1.05 0.65 BSC 1.00 0.20 1.45 MAX 1.20 0.22 0.80 0.75 0.09 MAX 0.08 8° 0.60 0.15 0.30 10° 0° 0.45 SEATING 0.15 MAX 0.05 5° 0.19 0.50 0.60 COPLANARITY SEATING PLANE 0° 0.10 0.30 0.45 PLANE 0.30 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 33. 5-Lead Small Outline Transistor Package [SOT-23] Figure 34. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RJ-5) (RU-14) Dimensions shown in millimeters Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 14 8 6.20 (0.2441) 4.00 (0.1575) 1 3.80 (0.1496) 5.80 (0.2283) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 35. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. B | Page 13 of 16 060606-A AD8614/AD8644 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8614ART-R2 –20°C to +85°C 5-Lead SOT-23 RJ-5 A6A AD8614ART-REEL –20°C to +85°C 5-Lead SOT-23 RJ-5 A6A AD8614ART-REEL7 –20°C to +85°C 5-Lead SOT-23 RJ-5 A6A 1 AD8614ARTZ-REEL –20°C to +85°C 5-Lead SOT-23 RJ-5 A0Z 1 AD8614ARTZ-REEL7 –20°C to +85°C 5-Lead SOT-23 RJ-5 A0Z AD8644AR –20°C to +85°C 14-Lead SOIC_N R-14 AD8644AR-REEL –20°C to +85°C 14-Lead SOIC_N R-14 AD8644AR-REEL7 –20°C to +85°C 14-Lead SOIC_N R-14 1 AD8644ARZ –20°C to +85°C 14-Lead SOIC_N R-14 1 AD8644ARZ-REEL –20°C to +85°C 14-Lead SOIC_N R-14 1 AD8644ARZ-REEL7 –20°C to +85°C 14-Lead SOIC_N R-14 AD8644ARU –20°C to +85°C 14-Lead TSSOP RU-14 AD8644ARU-REEL –20°C to +85°C 14-Lead TSSOP RU-14 1 AD8644ARUZ –20°C to +85°C 14-Lead TSSOP RU-14 1 AD8644ARUZ-REEL –20°C to +85°C 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part. Rev. B | Page 14 of 16 AD8614/AD8644 NOTES Rev. B | Page 15 of 16 AD8614/AD8644 NOTES ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06485-0-9/07(B) Rev. B | Page 16 of 16