ANALOG DEVICES AD8608

Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers Data Sheet AD8605/AD8606/AD8608 FEATURES PIN CONFIGURATIONS BALL A1 Low offset voltage: 65 µV maximum CORNER Low input bias currents: 1 pA maximum Low noise: 8 nV/√Hz OUTA V+ OUTB Wide bandwidth: 10 MH Z A1 A2 A3 High open-loop gain: 1000 V/mV –INA –INB Unity gain stable B1 B3 Single-supply operation: 2.7 V to 5.5 V +INA V– +INB 5-ball WLCSP for single (AD8605) and 8-ball WLCSP for C1 C2 C3 V+ OUT 1 5 dual (AD8606) AD8605 TOP VIEW V– 2 (Not to Scale) AD8606 APPLICATIONS +IN 3 4 –IN TOP VIEW (BALL SIDE DOWN) Photodiode amplification Figure 1. 5-Lead SOT-23 (RJ Suffix) Figure 2. 8-Ball WLCSP (CB Suffix) Battery-powered instrumentation Multipole filters TOP VIEW (BUMP SIDE DOWN) OUT A 1 14 OUT D Sensors OUT V+ –IN A 2 13 –IN D Barcode scanners 1 5 3 12 +IN A +IN D AD8608 Audio V– TOP VIEW V+ 4 11 V– 2 (Not to Scale) GENERAL DESCRIPTION +IN B 5 10 +IN C +IN –IN 1 3 4 –IN B 6 9 –IN C The AD8605, AD8606, and AD8608 are single, dual, and quad OUT B 7 8 OUT C rail-to-rail input and output, single-supply amplifiers. They AD8605 ONLY feature very low offset voltage, low input voltage and current Figure 3. 5-Ball WLCSP (CB Suffix) Figure 4. 14-Lead SOIC_N (R Suffix) noise, and wide signal bandwidth. They use the Analog Devices, Inc. patented DigiTrim® trimming technique, which achieves OUT A 1 14 OUT D –IN A –IN D superior precision without laser trimming. OUT A 1 8 AD8608 V+ +IN A +IN D AD8606 TOP VIEW –IN A OUT B V+ V– TOP VIEW The combination of low offsets, low noise, very low input bias (Not to Scale) +IN B +IN C +IN A –IN B (Not to Scale) –IN B –IN C 4 5 currents, and high speed makes these amplifiers useful in a V– +IN B 7 8 OUT B OUT C wide variety of applications. Filters, integrators, photodiode Figure 5. 8-Lead MSOP (RM Suffix), Figure 6. 14-Lead TSSOP (RU Suffix) amplifiers, and high impedance sensors all benefit from the 8-Lead SOIC_N (R Suffix) combination of performance features. Audio and other ac applications benefit from the wide bandwidth and low distortion. Applications for these amplifiers include optical control loops, portable and loop-powered instrumentation, and audio amplification for portable devices. The AD8605, AD8606, and AD8608 are specified over the extended industrial temperature range (−40°C to +125°C). The AD8605 single is available in 5-lead SOT-23 and 5-ball WLCSP packages. The AD8606 dual is available in an 8-lead MSOP, an 8-ball WLSCP, and a narrow SOIC surface-mounted package. The AD8608 quad is available in a 14-lead TSSOP package and a narrow 14-lead SOIC package. The 5-ball and 8-ball WLCSP offer the smallest available footprint for any surface-mounted operational amplifier. The WLCSP, SOT-23, MSOP, and TSSOP versions are available in tape-and-reel only. 1 Protected by U.S. Patent No. 5,969,657. Rev. L Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02731-006 02731-001 02731-003 02731-057 02731-004 02731-002 AD8605/AD8606/AD8608 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 THD + Noise ............................................................................... 16 Applications ....................................................................................... 1 Total Noise Including Source Resistors ................................... 17 General Description ......................................................................... 1 Channel Separation .................................................................... 17 Pin Configurations ........................................................................... 1 Capacitive Load Drive ............................................................... 17 Revision History ............................................................................... 3 Light Sensitivity .......................................................................... 18 5 V Electrical Specifications ............................................................ 4 WLCSP Assembly Considerations ........................................... 18 2.7 V Electrical Specifications ......................................................... 6 I-V Conversion Applications ........................................................ 19 Absolute Maximum Ratings ............................................................ 8 Photodiode Preamplifier Applications .................................... 19 ESD Caution .................................................................................. 8 Audio and PDA Applications ................................................... 19 Typical Performance Characteristics ............................................. 9 Instrumentation Amplifiers ...................................................... 20 Applications Information .............................................................. 16 DAC Conversion ........................................................................ 20 Output Phase Reversal ............................................................... 16 Outline Dimensions ....................................................................... 21 Maximum Power Dissipation ................................................... 16 Ordering Guide .......................................................................... 24 Input Overvoltage Protection ................................................... 16 Rev. L | Page 2 of 24 Data Sheet AD8605/AD8606/AD8608 REVISION HISTORY Changes to Table 4 ........................................................................ 6 2/12—Rev. K to Rev. L Changes to Figure 12 Caption ..................................................... 8 Changed Functional Block Diagrams Section to Pin Changes to Figure 26 and Figure 27 Captions ....................... 11 Configuration Section ................................................................. 1 Changes to Figure 33 Caption .................................................. 12 Changes to Figure 11 ................................................................... 9 Changes to Figure 44 ................................................................. 14 Added Figure 33 ......................................................................... 13 Updated Outline Dimensions ................................................... 19 8/11—Rev. J to Rev. K Changes to Ordering Guide ...................................................... 20 Changes to Figure 20 ................................................................... 2 5/04—Rev. C to Rev. D Updated Outline Dimensions ................................................... 20 Updated Format ............................................................. Universal Changes to Ordering Guide ...................................................... 23 Edit to Light Sensitivity Section ............................................... 16 8/10—Rev. I to Rev. J Updated Outline Dimensions ................................................... 19 Changes to Figure 10 and Figure 11 .......................................... 9 Changes to Ordering Guide ...................................................... 20 Changes to Figure 15 ................................................................. 10 7/03—Rev. B to Rev. C Changes to Figure 36 ................................................................. 13 Changes to Features ....................................................................... 1 Changes to Figure 42 ................................................................. 14 Change to General Description .................................................... 1 Updated Outline Dimensions ................................................... 20 Addition to Functional Block Diagrams ..................................... 1 Changes to Ordering Guide ...................................................... 23 Addition to Absolute Maximum Ratings .................................... 4 9/08—Rev. H to Rev. I Addition to Ordering Guide ......................................................... 4 Changes to Input Overvoltage Protection Section ................ 15 Change to Equation in Maximum Power Dissipation Changes to Ordering Guide ...................................................... 22 Section .......................................................................................... 11 2/08—Rev. G to Rev. H Added Light Sensitivity Section ................................................ 12 Changes to Features ..................................................................... 1 Added New Figure 8; Renumbered Subsequently .................. 13 Changes to Table 1 ....................................................................... 4 Added New MicroCSP Assembly Considerations Section .... 13 Changes to Table 2 ....................................................................... 6 Changes to Figure 9 .................................................................... 13 Changes to Figure 11 ................................................................... 9 Change to Equation in Photodiode Preamplifier Changes to Figure 13, Figure 14, and Figure 16 Captions .... 10 Applications Section .................................................................. 13 Changes to Figure 15, Figure 17, and Figure 18 ..................... 10 Changes to Figure 12 .................................................................. 14 Changes to Figure 34 and Figure 35 Captions ........................ 13 Change to Equation in D/A Conversion Section .................... 14 Changes to Figure 36 ................................................................. 13 Updated Outline Dimensions ................................................... 15 Changes to Figure 37 Caption .................................................. 14 3/03—Rev. A to Rev. B Changes to Figure 38 and Figure 41 ........................................ 14 Changes to Functional Block Diagram ....................................... 1 Changes to Figure 45 ................................................................. 15 Changes to Absolute Maximum Ratings..................................... 4 Changes to Audio and PDA Applications Section ................. 18 Changes to Ordering Guide ........................................................ 4 Changes to Figure 52 ................................................................. 18 Changes to Figure 9 ................................................................... 13 Changes to Ordering Guide ...................................................... 22 Updated Outline Dimensions .................................................... 15 10/07—Rev. F to Rev. G 11/02—Rev. 0 to Rev. A Changes to Figure 2 ...................................................................... 1 Change to Electrical Characteristics ............................................ 2 Updated Outline Dimensions ................................................... 20 Changes to Absolute Maximum Ratings..................................... 4 8/07—Rev. E to Rev. F Changes to Ordering Guide ......................................................... 4 Added 8-Ball WLCSP Package ..................................... Universal Change to TPC 6 ........................................................................... 5 Changes to Features ..................................................................... 1 Updated Outline Dimensions .................................................... 15 Changes to Table 1 ....................................................................... 3 5/02—Revision 0: Initial Version Changes to Table 2 ....................................................................... 5 Changes to Table 4 ....................................................................... 7 Updated Outline Dimensions ................................................... 19 Changes to Ordering Guide ...................................................... 21 1/06—Rev. D to Rev. E Changes to Table 1 ....................................................................... 3 Changes to Table 2 ....................................................................... 5 Rev. L | Page 3 of 24 AD8605/AD8606/AD8608 Data Sheet 5 V ELECTRICAL SPECIFICATIONS VS = 5 V, VCM = VS/2, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS AD8605/AD8606 (Except WLCSP) VS = 3.5 V, VCM = 3 V 20 65 µV AD8608 VS = 3.5 V, VCM = 2.7 V 20 75 µV AD8605/AD8606/AD8608 VS = 5 V, VCM = 0 V to 5 V 80 300 µV −40°C < T < +125°C 750 µV A Input Bias Current I 0.2 1 pA B AD8605/AD8606 −40°C < T < +85°C 50 pA A AD8605/AD8606 −40°C < TA < +125°C 250 pA AD8608 −40°C < TA < +85°C 100 pA AD8608 −40°C < T < +125°C 300 pA A Input Offset Current I 0.1 0.5 pA OS −40°C < T < +85°C 20 pA A −40°C < TA < +125°C 75 pA Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 85 100 dB −40°C < T < +125°C 75 90 dB A Large Signal Voltage Gain A R = 2 kΩ, V = 0.5 V to 4.5 V 300 1000 V/mV VO L O Offset Voltage Drift AD8605/AD8606 ΔVOS/ΔT −40°C < TA < +125°C 1 4.5 µV/°C AD8608 ΔVOS/ΔT −40°C < TA < +125°C 1.5 6.0 µV/°C INPUT CAPACITANCE Common-Mode Input Capacitance CCOM 8.8 pF Differential Input Capacitance CDIFF 2.6 pF OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 1 mA 4.96 4.98 V IL = 10 mA 4.7 4.79 V −40°C < T < +125°C 4.6 V A Output Voltage Low V I = 1 mA 20 40 mV OL L I = 10 mA 170 210 mV L −40°C < TA < +125°C 290 mV Output Current IOUT ±80 mA Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 1 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR AD8605/AD8606 V = 2.7 V to 5.5 V 80 95 dB S AD8605/AD8606 WLCSP V = 2.7 V to 5.5 V 75 92 dB S AD8608 V = 2.7 V to 5.5 V 77 92 dB S −40°C < TA < +125°C 70 90 dB Supply Current/Amplifier ISY IOUT = 0 mA 1 1.2 mA −40°C < TA < +125°C 1.4 mA DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ, CL = 16 pF 5 V/µs Settling Time tS To 0.01%, 0 V to 2 V step, AV = 1 <1 µs Unity Gain Bandwidth Product GBP 10 MHz Phase Margin Φ 65 Degrees M Rev. L | Page 4 of 24 Data Sheet AD8605/AD8606/AD8608 Parameter Symbol Conditions Min Typ Max Unit NOISE PERFORMANCE Peak-to-Peak Noise en p-p f = 0.1 Hz to 10 Hz 2.3 3.5 µV p-p Voltage Noise Density en f = 1 kHz 8 12 nV/√Hz e f = 10 kHz 6.5 nV/√Hz n Current Noise Density i f = 1 kHz 0.01 pA/√Hz n Rev. L | Page 5 of 24 AD8605/AD8606/AD8608 Data Sheet 2.7 V ELECTRICAL SPECIFICATIONS VS = 2.7 V, VCM = VS/2, TA = 25°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS AD8605/AD8606 (Except WLCSP) VS = 3.5 V, VCM = 3 V 20 65 µV AD8608 VS = 3.5 V, VCM = 2.7 V 20 75 µV AD8605/AD8606/AD8608 VS = 2.7 V, VCM = 0 V to 2.7 V 80 300 µV −40°C < T < +125°C 750 µV A Input Bias Current I 0.2 1 pA B AD8605/AD8606 −40°C < T < +85°C 50 pA A AD8605/AD8606 −40°C < TA < +125°C 250 pA AD8608 −40°C < TA < +85°C 100 pA AD8608 −40°C < T < +125°C 300 pA A Input Offset Current I 0.1 0.5 pA OS −40°C < T < +85°C 20 pA A −40°C < TA < +125°C 75 pA Input Voltage Range 0 2.7 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 80 95 dB −40°C < T < +125°C 70 85 dB A Large Signal Voltage Gain A R = 2 kΩ, V = 0.5 V to 2.2 V 110 350 V/mV VO L O Offset Voltage Drift AD8605/AD8606 ΔVOS/ΔT −40°C < TA < +125°C 1 4.5 µV/°C AD8608 ΔVOS/ΔT −40°C < TA < +125°C 1.5 6.0 µV/°C INPUT CAPACITANCE Common-Mode Input Capacitance CCOM 8.8 pF Differential Input Capacitance CDIFF 2.6 pF OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 1 mA 2.6 2.66 V −40°C < TA < +125°C 2.6 V Output Voltage Low V I = 1 mA 25 40 mV OL L −40°C < T < +125°C 50 mV A Output Current I ±30 mA OUT Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 1.2 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR AD8605/AD8606 VS = 2.7 V to 5.5 V 80 95 dB AD8605/AD8606 WLCSP VS = 2.7 V to 5.5 V 75 92 dB AD8608 V = 2.7 V to 5.5 V 77 92 dB S −40°C < T < +125°C 70 90 dB A Supply Current/Amplifier I I = 0 mA 1.15 1.4 mA SY OUT −40°C < TA < +125°C 1.5 mA DYNAMIC PERFORMANCE Slew Rate SR R = 2 kΩ, C = 16 pF 5 V/µs L L Settling Time tS To 0.01%, 0 V to 1 V step, AV = 1 <0.5 µs Unity Gain Bandwidth Product GBP 9 MHz Phase Margin ΦM 50 Degrees Rev. L | Page 6 of 24 Data Sheet AD8605/AD8606/AD8608 Parameter Symbol Conditions Min Typ Max Unit NOISE PERFORMANCE Peak-to-Peak Noise en p-p f = 0.1 Hz to 10 Hz 2.3 3.5 µV p-p Voltage Noise Density en f = 1 kHz 8 12 nV/√Hz e f = 10 kHz 6.5 nV/√Hz n Current Noise Density i f = 1 kHz 0.01 pA/√Hz n Rev. L | Page 7 of 24 AD8605/AD8606/AD8608 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Table 4. 1 Parameter Rating Package Type θJA θJC Unit Supply Voltage 6 V 5-Ball WLCSP (CB) 170 °C/W Input Voltage GND to V 5-Lead SOT-23 (RJ) 240 92 °C/W S Differential Input Voltage 6 V 8-Ball WLCSP (CB) 115 °C/W Output Short-Circuit Duration to GND Observe Derating Curves 8-Lead MSOP (RM) 206 44 °C/W Storage Temperature Range 8-Lead SOIC_N (R) 157 56 °C/W All Packages −65°C to +150°C 14-Lead SOIC_N (R) 105 36 °C/W 14-Lead TSSOP (RU) 148 23 °C/W Operating Temperature Range 1 All Packages −40°C to +125°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Junction Temperature Range All Packages −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. L | Page 8 of 24 Data Sheet AD8605/AD8606/AD8608 TYPICAL PERFORMANCE CHARACTERISTICS 4500 0.30 V = 5V V = 5V S S 0.25 T = 25°C 4000 A V = 0V TO 5V 0.20 CM 3500 0.15 3000 0.10 0.05 2500 0 2000 –0.05 1500 –0.10 –0.15 1000 –0.20 500 –0.25 0 –0.30 –200 –100 0 100 200 300 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –300 OFFSET VOLTAGE (µV) V (V) CM Figure 7. Input Offset Voltage Distribution Figure 10. Input Offset Voltage vs. Common-Mode Voltage (200 Units, 5 Wafer Lots, Including Process Skews) 24 250 V = 5V S V = 5V SY T = –40°C TO +125°C A V = V /2 CM SY 200 V = 2.5V 20 CM 150 16 100 12 50 0 8 –50 4 AD8605 –100 AD8606 AD8608 0 –150 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 –50 –25 0 25 50 75 100 125 TCVOS (µV/°C) TEMPERATURE (°C) Figure 11. Input Bias Current vs. Temperature Figure 8. AD8608 Input Offset Voltage Drift Distribution 1k 20 V = 5V V = 5V S S T = 25°C T = –40°C TO +125°C A 18 A V = 2.5V CM 16 100 14 12 10 10 8 SOURCE SINK 6 1 4 2 0.1 0 0.001 0.01 0.1 1 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 LOAD CURRENT (mA) TCVOS (µV/°C) Figure 12. Output Saturation Voltage vs. Load Current Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution Rev. L | Page 9 of 24 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 02731-009 02731-007 INPUT BIAS CURRENT (pA) V (mV) OS OUTPUT SATURATION VOLTAGE (mV) 02731-010 02731-012 02731-011 02731-008 AD8605/AD8606/AD8608 Data Sheet 6 5.00 V @ 1mA LOAD OH 5 4.95 V = 5V S V = 5V S 4 4.90 V = 4.9V p-p IN T = 25°C A R = 2kΩ L 4.85 3 A = 1 V 4.80 2 V @ 10mA LOAD OH 4.75 1 4.70 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 1k 10k 100k 1M 10M FREQUENCY (Hz) TEMPERATURE (°C) Figure 16. Closed-Loop Output Voltage Swing (FPBW) Figure 13. Output Voltage Swing High vs. Temperature 100 0.25 V = 5V S V = 5V S 90 V @ 10mA LOAD OL 0.20 80 70 A = 100 V 60 0.15 50 A = 10 A = 1 V V 40 0.10 30 0.05 20 V @ 1mA LOAD OL 10 0 0 1k 10k 100k 1M 10M 100M –40 –25 –10 5 20 35 50 65 80 95 110 125 FREQUENCY (Hz) TEMPERATURE (°C) Figure 17. Output Impedance vs. Frequency Figure 14. Output Voltage Swing Low vs. Temperature 120 100 225 V = 5V V = ±2.5V S S 80 180 110 R = 2kΩ L C = 20pF L 60 135 100 Φ = 64° M PHASE 90 40 90 20 45 80 0 0 70 GAIN 60 –20 –45 50 –40 –90 40 –60 –135 30 –80 –180 –100 –225 20 10k 100k 1M 10M 40M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. Open-Loop Gain and Phase vs. Frequency Figure 18. Common-Mode Rejection Ratio (CMRR) vs. Frequency Rev. L | Page 10 of 24 GAIN (dB) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 02731-014 02731-013 PHASE (Degrees) 02731-015 OUTPUT IMPEDANCE (Ω) CMRR (dB) OUTPUT SWING (V p-p) 02731-016 02731-018 02731-017 Data Sheet AD8605/AD8606/AD8608 140 1.0 V = 5V S 120 0.9 100 0.8 80 0.7 60 0.6 40 0.5 20 0.4 0 0.3 –20 0.2 –40 0.1 –60 0 1k 10k 100k 1M 10M 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (Hz) SUPPLY VOLTAGE (V) Figure 19. PSRR vs. Frequency Figure 22. Supply Current/Amplifier vs. Supply Voltage 45 V = 5V S V = 5V S 40 R = ∞ L T = 25°C A 35 A = –1 V 30 25 +OS 20 –OS 15 10 5 0 10 100 1k TIME (1s/DIV) CAPACITANCE (pF) Figure 20. Small Signal Overshoot vs. Load Capacitance Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise 2.0 V = ±2.5V S R = 10kΩ L C = 200pF L A = 1 V 1.5 V = 2.7V S 1.0 V = 5V S 0.5 0 TIME (200ns/DIV) –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 24. Small Signal Transient Response Figure 21. Supply Current/Amplifier vs. Temperature Rev. L | Page 11 of 24 SUPPLY CURRENT/AMPLIFIER (mA) SMALL SIGNAL OVERSHOOT (%) PSRR (dB) 02731-020 02731-019 02731-021 SUPPLY CURRENT/AMPLIFIER (mA) VOLTAGE (50mV/DIV) VOLTAGE NOISE (1µV/DIV) 02731-024 02731-023 02731-022 AD8605/AD8606/AD8608 Data Sheet 36 V = ±2.5V S V = ±2.5V S R = 10kΩ L 32 C = 200pF L A = 1 V 28 24 20 16 12 8 4 TIME (400ns/DIV) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (kHz) Figure 25. Large Signal Transient Response Figure 28. Voltage Noise Density vs. Frequency 53.6 V = ±2.5V S V = ±2.5V S R = 10kΩ L 2.5V 46.9 A = –100 V V OUT V = 50mV IN 40.2 0V 33.5 0V 26.8 20.1 V IN 13.4 –50mV 6.7 0 TIME (400ns/DIV) 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (kHz) Figure 26. Positive Overload Recovery Figure 29. Voltage Noise Density vs. Frequency 119.2 V = ±2.5V S V = ±2.5V S R = 10kΩ L 104.3 A = –100 V 0V V = 50mV IN 89.4 –2.5V 74.5 50mV 59.6 44.7 0V 29.8 14.9 0 TIME (1µs/DIV) 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz) Figure 27. Negative Overload Recovery Figure 30. Voltage Noise Density vs. Frequency Rev. L | Page 12 of 24 VOLTAGE (1V/DIV) 02731-025 02731-027 02731-026 VOLTAGE NOISE DENSITY (nV/ Hz) VOLTAGE NOISE DENSITY (nV/ Hz) VOLTAGE NOISE DENSITY (nV/ Hz) 02731-028 02731-029 02731-030 Data Sheet AD8605/AD8606/AD8608 1k 1800 V = 2.7V V = 2.7V S S T = 25°C 1600 T = 25°C A A V = 0V TO 2.7V CM 1400 100 1200 SOURCE 1000 10 800 SINK 600 1 400 200 0.1 0 0.1 –200 –100 0 100 200 300 0.001 0.01 10 –300 1 LOAD CURRENT (mA) OFFSET VOLTAGE (µV) Figure 34. Output Saturation Voltage vs. Load Current Figure 31. Input Offset Voltage Distribution 300 2.680 V = 2.7V S V = 2.7V S T = 25°C A 200 2.675 2.670 100 2.665 0 V @ 1mA LOAD OH –100 2.660 –200 2.655 –300 2.650 0 0 0.9 1.8 2.7 –40 –25 –10 5 20 35 50 65 80 95 110 125 COMMON-MODE VOLTAGE (V) TEMPERATURE (°C) Figure 32. Input Offset Voltage vs. Common-Mode Voltage Figure 35. Output Voltage Swing High vs. Temperature (200 Units, 5 Wafer Lots, Including Process Skews) 250 0.045 V = 2.7V SY V = 2.7V S V = V /2 CM SY 200 0.040 0.035 150 0.030 100 V @ 1mA LOAD OL 0.025 50 0.020 0 0.015 –50 0.010 AD8605 –100 AD8606 0.005 AD8608 –150 0 –50 –25 0 25 50 75 100 125 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 33. Input Bias Current vs. Temperature Figure 36. Output Voltage Swing Low vs. Temperature Rev. L | Page 13 of 24 INPUT BIAS CURRENT (pA) NUMBER OF AMPLIFIERS INPUT OFFSET VOLTAGE (µV) 02731-032 02731-031 02731-039 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT SATURATION VOLTAGE (mV) 02731-033 02731-035 02731-034 AD8605/AD8606/AD8608 Data Sheet 60 100 225 V = 2.7V V = 2.7V S S 80 180 R = 2kΩ T = 25°C L A C = 20pF 50 L A = 1 V 60 135 Φ = 52.5° M PHASE 40 90 40 20 45 –OS 30 0 0 GAIN +OS –20 –45 20 –40 –90 –60 –135 10 –80 –180 –225 0 –100 10 100 1k 10k 100k 1M 10M 40M CAPACITANCE (pF) FREQUENCY (Hz) Figure 40. Small Signal Overshoot vs. Load Capacitance Figure 37. Open-Loop Gain and Phase vs. Frequency V = 2.7V S 3.0 2.5 V = 2.7V S V = 2.6V p-p IN 2.0 T = 25°C A R = 2kΩ L A = 1 V 1.5 1.0 0.5 TIME (1s/DIV) 0 1k 10k 100k 1M 10M Figure 41. 0.1 Hz to 10 Hz Input Voltage Noise FREQUENCY (Hz) Figure 38. Closed-Loop Output Voltage Swing vs. Frequency (FPBW) V = ±1.35V S 100 R = 10kΩ L C = 200pF V = 2.7V L S 90 A = 1 V 80 70 A = 100 V 60 50 A = 10 V 40 30 A = 1 V 20 10 TIME (200ns/DIV) 0 10k 100k 1M 10M 100M 1k FREQUENCY (Hz) Figure 42. Small Signal Transient Response Figure 39. Output Impedance vs. Frequency Rev. L | Page 14 of 24 GAIN (dB) OUTPUT SWING (V p-p) OUTPUT IMPEDANCE (Ω) 02731-038 02731-037 PHASE (Degrees) 02731-036 SMALL SIGNAL OVERSHOOT (%) VOLTAGE (50mV/DIV) VOLTAGE NOISE (1µV/DIV) 02731-041 02731-040 02731-039 Data Sheet AD8605/AD8606/AD8608 V = ±1.35V S R = 10kΩ L C = 200pF L A = 1 V TIME (400ns/DIV) Figure 43. Large Signal Transient Response Rev. L | Page 15 of 24 VOLTAGE (500mV/DIV) 02731-042 AD8605/AD8606/AD8608 Data Sheet APPLICATIONS INFORMATION OUTPUT PHASE REVERSAL V = ±2.5V S V = 6V p-p IN V OUT Phase reversal is defined as a change in polarity at the output of A = 1 V R = 10kΩ L the amplifier when a voltage that exceeds the maximum input common-mode voltage drives the input. V IN Phase reversal can cause permanent damage to the amplifier; it can also cause system lockups in feedback loops. The AD8605 does not exhibit phase reversal even for inputs exceeding the supply voltage by more than 2 V. MAXIMUM POWER DISSIPATION Power dissipated in an IC causes the die temperature to increase, which can affect the behavior of the IC and the TIME (4µs/DIV) application circuit performance. Figure 44. No Phase Reversal The absolute maximum junction temperature of the AD8605/ 1.8 AD8606/AD8608 is 150°C. Exceeding this temperature could 1.7 SOIC-14 1.6 damage or destroy the device. 1.5 1.4 The maximum power dissipation of the amplifier is calculated TSSOP-14 1.3 according to 1.2 1.1 1.0 T −T SOIC-8 J A P = 0.9 DISS 0.8 θ JA 0.7 0.6 MSOP-8 where: 0.5 WLCSP-5 TJ is the junction temperature. 0.4 0.3 T is the ambient temperature. 5-LEAD SOT-23 A 0.2 0.1 θ is the junction-to-ambient thermal resistance. JA 0 –45 –20 5 30 55 80 105 130 Figure 45 compares the maximum power dissipation with AMBIENT TEMPERATURE (°C) temperature for the various AD860x family packages. Figure 45. Maximum Power Dissipation vs. Ambient Temperature INPUT OVERVOLTAGE PROTECTION 0.1 V = ±2.5V SY The AD8605 has internal protective circuitry. However, if the A = 1 V voltage applied at either input exceeds the supplies by more B = 80kHz W than 0.5 V, external resistors should be placed in series with 0.01 the inputs. The resistor values can be determined by V −V IN S ≤ 5mA R S 0.001 The remarkable low input offset current of the AD8605 (<1 pA) allows the use of larger value resistors. With a 10 kΩ resistor at the input, the output voltage has less than 10 nV of error voltage. A 10 kΩ resistor has less than 13 nV/√Hz of thermal noise at 0.0001 room temperature. 20 100 1k 10k 20k FREQUENCY (Hz) THD + NOISE Figure 46. THD + Noise vs. Frequency Total harmonic distortion is the ratio of the input signal in V rms to the total harmonics in V rms throughout the spectrum. Harmonic distortion adds errors to precision measurements and adds unpleasant sonic artifacts to audio systems. The AD8605 has a low total harmonic distortion. Figure 46 shows that the AD8605 has less than 0.005% or −86 dB of THD + N over the entire audio frequency range. The AD8605 is configured in positive unity gain, which is the worst case, and with a load of 10 kΩ. Rev. L | Page 16 of 24 THD + NOISE (%) POWER DISSIPATION (W) VOLTAGE (2V/DIV) 02731-043 02731-044 02731-045 Data Sheet AD8605/AD8606/AD8608 A snubber network, shown in Figure 49, helps reduce the signal TOTAL NOISE INCLUDING SOURCE RESISTORS overshoot to a minimum and maintain stability. Although this The low input current noise and input bias current of the circuit does not recover the loss of bandwidth induced by large AD8605 make it the ideal amplifier for circuits with substantial capacitive loads, it greatly reduces the overshoot and ringing. input source resistance, such as photodiodes. Input offset voltage This method does not reduce the maximum output swing of the increases by less than 0.5 nV per 1 kΩ of source resistance at amplifier. room temperature and increases to 10 nV at 85°C. The total 0 noise density of the circuit is –20 2 2 e = e +(i R) + 4kTR n n n S S , TOTAL –40 where: –60 en is the input voltage noise density of the AD8605. –80 in is the input current noise density of the AD8605. –100 RS is the source resistance at the noninverting terminal. −23 k is Boltzmann’s constant (1.38 × 10 J/K). –120 T is the ambient temperature in Kelvin (T = 273 + °C). –140 For example, with R = 10 kΩ, the total voltage noise density is S –160 roughly 15 nV/√Hz. –180 100 1k 10k 100k 1M 10M 100M For RS < 3.9 kΩ, en dominates and en, TOTAL ≈ en. FREQUENCY (Hz) The current noise of the AD8605 is so low that its total density does Figure 47. Channel Separation vs. Frequency not become a significant term unless RS is greater than 6 MΩ. The total equivalent rms noise over a specific bandwidth is expressed as V = ±2.5V S A = 1 V R = 10kΩ E =(e ) BW L n n, TOTAL C = 1000pF L where BW is the bandwidth in hertz. Note that the previous analysis is valid for frequencies greater than 100 Hz and assumes relatively flat noise, above 10 kHz. For lower frequencies, flicker noise (1/f) must be considered. CHANNEL SEPARATION Channel separation, or inverse crosstalk, is a measure of the signal feed from one amplifier (channel) to another on the same IC. The AD8606 has a channel separation of greater than −160 dB TIME (10µs/DIV) up to frequencies of 1 MHz, allowing the two amplifiers to Figure 48. AD8606 Capacitive Load Drive Without Snubber amplify ac signals independently in most applications. CAPACITIVE LOAD DRIVE V+ The AD860x can drive large capacitive loads without oscillation. Figure 48 shows the output of the AD8606 in response to a 4 200 mV input signal. In this case, the amplifier is configured 2 200mV in positive unity gain, worst case for stability, while driving a 1 AD8605 V 3 1000 pF load at its output. Driving larger capacitive loads in IN R R C S L L unity gain can require the use of additional circuitry. 8 C S V– Figure 49. Snubber Network Configuration Rev. L | Page 17 of 24 CHANNEL SEPARATION (dB) VOLTAGE (100mV/DIV) 02731-047 02731-046 02731-049 AD8605/AD8606/AD8608 Data Sheet 5000 Figure 50 shows a scope of the output at the snubber circuit. 4500 The overshoot is reduced from over 70% to less than 5%, and the ringing is eliminated by the snubber. Optimum values for R S 4000 and C are determined experimentally. S 3500 2 3mW/cm 3000 V = ±2.5V S A = 1 V 2500 R = 10kΩ L 2 2mW/cm R = 90Ω S 2000 C = 1000pF L C = 700pF S 1500 1000 2 1mW/cm 500 0 350 450 550 650 750 850 WAVELENGTH (nm) Figure 51. AD8605ACB Input Bias Current Response to Direct Illumination of Varying Intensity and Wavelength When the WLCSP package is assembled on the board with the TIME (10µs/DIV) bump side of the die facing the PCB, reflected light from the Figure 50. Capacitive Load Drive with Snubber PCB surface is incident on active silicon circuit areas and results Table 5 summarizes a few optimum values for capacitive loads. in the increased I . No performance degradation occurs due to B illumination of the backside (substrate) of the AD8605ACB. Table 5. The AD8605ACB is particularly sensitive to incident light with C (pF) R (Ω) C (pF) L S S wavelengths in the near infrared range (NIR, 700 nm to 1000 nm). 500 100 1000 Photons in this waveband have a longer wavelength and lower 1000 70 1000 energy than photons in the visible (400 nm to 700 nm) and near 2000 60 800 ultraviolet (NUV, 200 nm to 400 nm) bands; therefore, they can An alternate technique is to insert a series resistor inside the penetrate more deeply into the active silicon. Incident light with feedback loop at the output of the amplifier. Typically, the value wavelengths greater than 1100 nm has no photoelectric effect of this resistor is approximately 100 Ω. This method also reduces on the AD8605ACB because silicon is transparent to wavelengths overshoot and ringing but causes a reduction in the maximum in this range. The spectral content of conventional light sources output swing. varies. Sunlight has a broad spectral range, with peak intensity in the visible band that falls off in the NUV and NIR bands; LIGHT SENSITIVITY fluorescent lamps have significant peaks in the visible but not The AD8605ACB (WLCSP package option) is essentially a the NUV or NIR bands. silicon die with additional postfabrication dielectric and Efforts have been made at a product level to reduce the effect of intermetallic processing designed to contact solder bumps ambient light; the under bump metal (UBM) has been designed on the active side of the chip. With this package type, the die to shield the sensitive circuit areas on the active side (bump is exposed to ambient light and is subject to photoelectric side) of the die. However, if an application encounters any light effects. Light sensitivity analysis of the AD8605ACB mounted sensitivity with the AD8605ACB, shielding the bump side of the on standard PCB material reveals that only the input bias WLCSP package with opaque material should eliminate this current (I ) parameter is impacted when the package is B effect. Shielding can be accomplished using materials such as illuminated directly by high intensity light. No degradation in silica-filled liquid epoxies that are used in flip-chip underfill electrical performance is observed due to illumination by low techniques. 2 intensity (0.1 mW/cm ) ambient light. Figure 51 shows that IB increases with increasing wavelength and intensity of incident WLCSP ASSEMBLY CONSIDERATIONS light; IB can reach levels as high as 4500 pA at a light intensity of For detailed information on the WLCSP PCB assembly and 2 3 mW/cm and a wavelength of 850 nm. The light intensities reliability, see Application Note AN-617, MicroCSP™ Wafer shown in Figure 51 are not normal for most applications, that is, Level Chip Scale Package. 2 even though direct sunlight can have intensities of 50 mW/cm , 2 office ambient light can be as low as 0.1 mW/cm . Rev. L | Page 18 of 24 VOLTAGE (100mV/DIV) 02731-048 INPUT BIAS CURRENT (pA) 02731-050 Data Sheet AD8605/AD8606/AD8608 I-V CONVERSION APPLICATIONS At room temperature, the AD8605 has an input bias current of PHOTODIODE PREAMPLIFIER APPLICATIONS 0.2 pA and an offset voltage of 100 µV. Typical values of RD are The low offset voltage and input current of the AD8605 make in the range of 1 GΩ. it an excellent choice for photodiode applications. In addition, the low voltage and current noise make the amplifier ideal for For the circuit shown in Figure 52, the output error voltage is application circuits with high sensitivity. approximately 100 µV at room temperature, increasing to about 1 mV at 85°C. C F 10pF The maximum achievable signal bandwidth is R F 10MΩ f t f = MAX 2πR C F F PHOTODIODE V OS where f is the unity gain frequency of the amplifier. t C D R I AD8605 AUDIO AND PDA APPLICATIONS D D 50pF V OUT The low distortion and wide dynamic range of the AD860x make it a great choice for audio and PDA applications, including microphone amplification and line output buffering. Figure 52. Equivalent Circuit for Photodiode Preamp Figure 53 shows a typical application circuit for headphone/ The input bias current of the amplifier contributes an error line-out amplification. term that is proportional to the value of RF. R1 and R2 are used to bias the input voltage at half the supply, The offset voltage causes a dark current induced by the shunt which maximizes the signal bandwidth range. C1 and C2 are resistance of the Diode R . These error terms are combined at D used to ac couple the input signal. C1, R1, and R2 form a high- the output of the amplifier. The error voltage is written as pass filter whose corner frequency is 1/[2π(R1||R2)C1]. The high output current of the AD8606 allows it to drive heavy  R  F   E = V 1+ + R I O OS F B   resistive loads. R  D The circuit in Figure 53 is tested to drive a 16 Ω headphone. The Typically, RF is smaller than RD, thus RF/RD can be ignored. THD + N is maintained at approximately −60 dB throughout the audio range. 5V R1 C1 20kΩ 8 1µF C3 R4 100µF R2 20Ω 3 1/2 V1 20kΩ AD8606 1 500mV R3 HEADPHONES 2 1kΩ 4 5V C2 R7 8 20kΩ 1µF C4 R6 100µF 5 20Ω 1/2 R8 V2 20kΩ AD8606 7 500mV R5 6 1kΩ 4 Figure 53. Single-Supply Headphone/Speaker Amplifier Rev. L | Page 19 of 24 02731-051 02731-052 AD8605/AD8606/AD8608 Data Sheet INSTRUMENTATION AMPLIFIERS R R R The low offset voltage and low noise of the AD8605 make it an V REF C F ideal amplifier for instrumentation applications. R F Difference amplifiers are widely used in high accuracy circuits R2 R2 R2 to improve the common-mode rejection ratio. Figure 54 shows V+ a simple difference amplifier. Figure 55 shows the common- V OS mode rejection for a unity gain configuration and for a gain of 10. AD8605 Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields a CMRR of 74 dB and minimizes the gain error at the output. R1 R2 1kΩ 10kΩ V– V1 5V Figure 56. Simplified Circuit of the DAC8143 with AD8605 Output Buffer R4 R2 To optimize the performance of the DAC, insert a capacitor in = R3 R1 the feedback loop of the AD8605 to compensate the amplifier R2 AD8605 V OUT V = (V2 – V1) OUT for the pole introduced by the output capacitance of the DAC. R1 Typical values for CF range from 10 pF to 30 pF; it can be adjusted for the best frequency response. The total error at the R3 R4 1kΩ 10kΩ output of the op amp can be computed by V2  R  F   E = V 1+ Figure 54. Difference Amplifier, AV = 10 O OS   Req   120 V = ±2.5V SY where Req is the equivalent resistance seen at the output of the A = 10 V 100 DAC. As previously mentioned, Req is code dependent and varies with the input. A typical value for Req is 15 kΩ. A = 1 V 80 Choosing a feedback resistor of 10 kΩ yields an error of less than 200 µV. 60 Figure 57 shows the implementation of a dual-stage buffer at the output of a DAC. The first stage is used as a buffer. 40 Capacitor C1 with Req creates a low-pass filter, and thus, provides phase lead to compensate for frequency response. 20 The second stage of the AD8606 is used to provide voltage gain at the output of the buffer. 0 100 1k 10k 100k 1M 10M Grounding the positive input terminals in both stages reduces FREQUENCY (Hz) errors due to the common-mode output voltage. Choosing R1, Figure 55. Difference Amplifier CMRR vs. Frequency R2, and R3 to match within 0.01% yields a CMRR of 74 dB and DAC CONVERSION maintains minimum gain error in the circuit. The low input bias current and offset voltage of the AD8605 R CS R3 15V make it an excellent choice for buffering the output of a current 20kΩ output DAC. R2 C1 10kΩ 33pF Figure 56 shows a typical implementation of the AD8605 at the V R DD FB R1 OUT1 10kΩ output of a 12-bit DAC. V AD7545 OUT V REF V R AGND P IN The DAC8143 output current is converted to a voltage by the 1/2 DB11 1/2 AD8606 feedback resistor. The equivalent resistance at the output of the AD8606 DAC varies with the input code, as does the output capacitance. R4 5kΩ Figure 57. Bipolar Operation Rev. L | Page 20 of 24 CMRR (dB) 02731-053 02731-054 02731-055 02731-056 Data Sheet AD8605/AD8606/AD8608 OUTLINE DIMENSIONS 0.50 REF 0.94 0.37 0.90 0.36 SEATING 0.86 PLANE 2 1 0.35 0.87 A 0.23 BALL 1 1.33 0.18 IDENTIFIER 0.50 1.29 0.14 B 1.25 0.21 C 0.17 TOP VIEW 0.20 0.14 (BALL SIDE DOWN) 0.50 0.12 BOTTOM VIEW (BALL SIDE UP) Figure 58. 5-Ball Wafer Level Chip Scale Package [WLCSP] (CB-5-1) Dimensions shown in millimeters 3.00 2.90 2.80 5 4 3.00 1.70 2.80 1.60 2.60 1.50 1 2 3 0.95 BSC 1.90 BSC 1.30 1.15 0.90 0.20 MAX 1.45 MAX 0.08 MIN 0.95 MIN 0.55 0.15 MAX 10° 0.45 SEATING 0.60 0.05 MIN 5° 0.50 MAX 0.35 PLANE BSC 0° 0.35 MIN COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 59. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters Rev. L | Page 21 of 24 11-01-2010-A 101607-A AD8605/AD8606/AD8608 Data Sheet 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 60. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 5 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 61. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 0.675 0.595 1.480 0.515 1.430 1.380 SEATING 3 2 1 PLANE A BALL 1 0.340 IDENTIFIER 0.320 1.825 0.300 1.775 B 1.725 C 0.50 BALL PITCH TOP VIEW BOTTOM VIEW 0.380 (BALL SIDE DOWN) (BALL SIDE UP) 0.355 0.27 0.330 0.24 0.21 Figure 62. 8-Ball Wafer Level Chip Scale Package [WLCSP] (CB-8-1) Dimensions shown in millimeters Rev. L | Page 22 of 24 10-07-2009-B 012407-A 090706-B Data Sheet AD8605/AD8606/AD8608 8.75 (0.3445) 8.55 (0.3366) 8 14 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 63. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 8° 0.15 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 64. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. L | Page 23 of 24 061908-A 060606-A AD8605/AD8606/AD8608 Data Sheet ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8605ACBZ-REEL −40°C to +125°C 5-Ball WLCSP CB-5-1 A1J AD8605ACBZ-REEL7 −40°C to +125°C 5-Ball WLCSP CB-5-1 A1J AD8605ART-REEL −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A AD8605ARTZ-R2 −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A# AD8605ARTZ-REEL −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A# AD8605ARTZ-REEL7 −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A# AD8606ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 B6A AD8606ARMZ-R7 −40°C to +125°C 8-Lead MSOP RM-8 B6A# AD8606ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 B6A# AD8606AR −40°C to +125°C 8-Lead SOIC_N R-8 AD8606AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8606AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8606ARZ −40°C to +125°C 8-Lead SOIC_N R-8 AD8606ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8606ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8606ACBZ-REEL −40°C to +125°C 8-Ball WLCSP CB-8-1 B6A# AD8606ACBZ-REEL7 −40°C to +125°C 8-Ball WLCSP CB-8-1 B6A# AD8608ARZ −40°C to +125°C 14-Lead SOIC_N R-14 AD8608ARZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14 AD8608ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 AD8608ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 AD8608ARUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part, # denotes RoHS compliant product (except for CB-5-1) may be top or bottom marked. ©2002–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02731-0-2/12(L) Rev. L | Page 24 of 24