ANALOG DEVICES AD8600

16-Channel, 8-Bit a Multiplying DAC AD8600 FUNCTIONAL BLOCK DIAGRAM FEATURES 16 Independently Addressable Voltage Outputs V V V V R/W RS LD Full-Scale Set by External Reference DD1 DD2 REF CC 2 μs Settling Time O0 CS CONTROL O1 Double Buffered 8-Bit Parallel Input EN LOGIC O2 O3 High Speed Data Load Rate A3 O4 A2 ADDRESS Data Readback A1 O5 DECODE A0 16 x 8 O6 Operates from Single +5 V 16 DAC O7 8-BIT Optional ±6 V Supply Extends Output Range DB7 REGISTERS O8 DACS DB6 O9 DB5 16 x 8 O10 APPLICATIONS DB4 INPUT O11 Phased Array Ultrasound & Sonar DB3 REGISTERS O12 DB2 O13 Power Level Setting DB1 AD8600 O14 DB0 Receiver Gain Setting O15 Automatic Test Equipment D D DACGND V GND1 GND2 EE LCD Clock Level Setting At system power up or during fault recovery the reset (RS) pin GENERAL DESCRIPTION forces all DAC registers into the zero state which places zero The AD8600 contains 16 independent voltage output digital-to- volts at all DAC outputs. analog converters that share a common external reference input voltage. Each DAC has its own DAC register and input register The AD8600 is offered in the PLCC-44 package. The device is designed and tested for operation over the extended industrial to allow double buffering. An 8-bit parallel data input, four ad- dress pins, a CS select, a LD, EN, R/W, and RS provide the temperature range of –40°C to +85°C. digital interface. R/W•CS•ADDR•EN V LD•EN V V DD2 REF DD1 The AD8600 is constructed in a monolithic CBCMOS process V CC which optimizes use of CMOS for logic and bipolar for speed INPUT R-2R DAC and precision. The digital-to-analog converter design uses volt- DB7...DB0 REGISTER REGISTER DAC O X age mode operation ideally suited to single supply operation. The internal DAC voltage range is fixed at DACGND to V . REF RS The voltage buffers provide an output voltage range that ap- RS D DACGND V GND2 EE proaches ground and extends to 1.0 V below V . Changes in CC reference voltage values and digital inputs will settle within D GND1 ±1 LSB in 2 μs. R/W•CS•ADDRESS Data is preloaded into the input registers one at a time after the internal address decoder selects the input register. In the write Figure 1. Equivalent DAC Channel mode (R/W low) data is latched into the input register during the positive edge of the EN pulse. Pulses as short as 40 ns can be used to load the data. After changes have been submitted to the input registers, the DAC registers are simultaneously up- dated by a common load EN × LD strobe. The new analog out- put voltages simultaneously appear on all 16 outputs. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 AD8600–SPECIFICATIONS (@ V = V = V = +5 V ± 5%, V = 0 V, V = +2.500 V, –40°C ≤ T ≤ +85°C, unless otherwise noted) SINGLE SUPPLY DD1 DD2 CC EE REF A Parameter Symbol Condition Min Typ Max Units 1 STATIC PERFORMANCE Resolution N 8 Bits 2 Relative Accuracy INL –1 ±1/2 +1 LSB 2 Differential Nonlinearity DNL Guaranteed Monotonic –1 ±1/4 +1 LSB Full-Scale Voltage V Data = FF 2.480 2.490 2.500 V FS H Full-Scale Tempco TCV Data = FF ±20 ppm/°C FS H Zero Scale Error V Data = 00 , RS = “0,” T = +25°C +3.5 LSB ZSE H A V Data = 00 , RS = “0” +5 LSB ZSE H Reference Input Resistance R Data = AB 1.2 2 kΩ REF H ANALOG OUTPUT 2 Output Voltage Range OVR V = +2.5 V 0.000 2.500 V SS REF Output Current I Data = 80 ±2mA OUT H Capacitive Load C No Oscillation 50 pF L LOGIC INPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Logic Input Current I 10 μA IL 3 Logic Input Capacitance C 10 pF IL LOGIC OUTPUTS Logic Out High Voltage V I = –0.4 mA 3.5 V OH OH Logic Out Low Voltage V I = 1.6 mA 0.4 V OL OL 3 AC CHARACTERISTICS Slew Rate SR For ΔV or FS Code Change 4 7 V/μs REF 2 Voltage Output Settling Time t ±1 LSB of Final Value, Full-Scale Data Change 2 μs S1 2 Voltage Output Settling Time t ±1 LSB of Final Value, ΔV = 1 V, Data = FF 2 μs S2 REF H POWER SUPPLIES Positive Supply Current I V = 5 V, V = 0 V, No Load 24 35 mA CC IH IL Logic Supply Currents I V = 5 V, V = 0 V, No Load 0.1 mA DD1&2 IH IL Power Dissipation P V = 5 V, V = 0 V, No Load 120 175 mW DISS IH IL Power Supply Sensitivity PSS ΔV = ±5% 0.007 %/% CC Logic Power Supply Range V 4.75 5.25 V DDR 3 Positive Power Supply Range V V 7.0 V CCR DD NOTES 1 When V = 2.500 V, 1 LSB = 9.76 mV. REF 2 Single supply operation does not include the final 2 LSBs near analog ground. If this performance is critical, use a negative supply (V ) pin of at least –0.7 V to EE –5.25 V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 7 to 80 . 10 10 3 Guaranteed by design not subject to production test. Specifications subject to change without notice. –2– REV. 0 AD8600 (@ V = V = V = +5 V ± 5%, V = –5 V ± 5%, V = +3.500 V, –40°C ≤ T ≤ +85°C, unless otherwise noted) DUAL SUPPLY DD1 DD2 CC EE REF A Parameter Symbol Condition Min Typ Max Units 1 STATIC PERFORMANCE Resolution N 8 Bits Total Unadjusted Error TUE All Other DACs Loaded with Data = 55 –1 ±3/4 +1 LSB H Relative Accuracy INL –1 ±1/2 +1 LSB Differential Nonlinearity DNL Guaranteed Monotonic –1 ±1/4 +1 LSB Full-Scale Voltage V Data = FF , V = +3.5 V 3.473 3.486 3.500 V FS H REF Full-Scale Voltage Error V Data = FF , V = +3.5 V –1 +1 LSB FSE H REF Full-Scale Tempco TCV Data = FF , V = +3.5 V ±20 ppm/°C FS H REF Zero Scale Error V Data = 00 , RS = “0,” T = +25°C–2±1+2 mV ZSE H A Zero Scale Error V Data = 00 , All Other DACs Data = 00 –1 +1 LSB ZSE H H Zero Scale Error V Data = 00 , All Other DACs Data = 55 ±1/2 LSB ZSE H H Zero Scale Tempco TCV Data = 00 , V = +5 V, V = –5 V ±10 μV/°C ZS H CC EE Reference Input Resistance R Data = AB 1.2 2 kΩ REF H 2 Reference Input Capacitance C Data = AB 240 pF REF H ANALOG OUTPUT Output Voltage Range OVR V = +3.5 V 0.000 3.500 V 1 REF 2 Output Voltage Range OVR V = V = +7 V, V = –0.7 V, V = 5 V 0.000 5.000 V 2 CC DD2 EE REF Output Current I Data = 80 ±2mA OUT H 2 Capacitive Load C No Oscillation 50 pF L LOGIC INPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Logic Input Current I 10 μA IL 2 Logic Input Capacitance C 10 pF IL LOGIC OUTPUTS Logic Out High Voltage V I = –0.4 mA 3.5 V OH OH Logic Out Low Voltage V I = 1.6 mA 0.4 V OL OL 2 AC CHARACTERISTICS Reference In Bandwidth BW –3 dB Frequency, V = 2.5 V + 0.1 V 500 kHz REF DC AC Slew Rate SR For ΔV or FS Code Change 4 7 V/μs REF Voltage Noise Density e f = 1 kHz, V = 0 V 46 nV/√Hz N REF Digital Feedthrough FT Digital Inputs to DAC Outputs 10 nVs 3 Voltage Output Settling Time t ±1 LSB of Final Value, FS Data Change 1 2 μs S1 3 Voltage Output Settling Time t ±1 LSB of Final Value, ΔV = 1 V, Data = FF 12 μs S2 REF H POWER SUPPLIES Positive Supply Current I V = 5 V, V = 0 V, V = –5 V, No Load 22 35 mA CC IH IL EE Negative Supply Current I V = 5 V, V = 0 V, V = –5 V, No Load 22 35 mA EE IH IL EE Logic Supply Currents I V = 5 V, V = 0 V, V = –5 V, No Load 0.1 mA DD1&2 IH IL EE 4 Power Dissipation P V = 5 V, V = 0 V, V = –5 V, No Load 225 350 mW DISS IH IL EE Power Supply Sensitivity PSS ΔV & ΔV = ±5% 0.007 %/% CC EE Logic Power Supply Range V 4.75 5.25 V DDR 2 Pos Power Supply Range V V 7.0 V CCR DD 2 Neg Power Supply Range V –5.25 0.0 V EER NOTES 1 When V = +3.500 V, 1 LSB = 13.67 mV. REF 2 Guaranteed by design not subject to production test. 3 Settling time test is performed using R = 50 kΩ and C = 35 pF. L L 4 Power Dissipation is calculated using 5 V × (I + |I | + I + I ). DD SS DD1 DD2 Specifications subject to change without notice. REV. 0 –3– AD8600 (@ V = V = V = +5 V ± 5%, V = –5 V, V = +3.500 V, –40°C ≤ T ≤ +85°C, DD1 DD2 CC EE REF A ELECTRICAL CHARACTERISTICS unless otherwise noted) Parameter Symbol Condition Min Typ Max Units 1, 2 INTERFACE TIMING Clock (EN) Frequency f Data Loading 12.5 MHz CLK Clock (EN) High Pulse Width t 40 ns CH Clock (EN) LowPulse Width t 40 ns CL Data Setup Time t 40 ns DS Data Hold Time t 10 ns DH Address Setup Time t 0ns AS Address Hold Time t 0ns AH Valid Address to Data Valid t 160 ns AD Load Enable Setup Time t 0ns LS Load Enable Hold Time t 0ns LH Read/Write to Clock (EN)t 30 ns RWC Read/Write to DataBus Hi-Z t 120 ns RWZ Read/Write to DataBus Active t 120 ns RWD Clock (EN) to Read/Write t 0ns TWH Clock (EN) to Chip Select t 0ns TCH Chip Select to Clock (EN)t 30 ns CSC Chip Select to Data Valid t 120 ns CSD Chip Select to DataBus Hi-Z t 150 ns CSZ Reset Pulse Width t 25 ns RS NOTES 1 Guaranteed by design not subject to production test. 2 All logic input signals have maximum rise and fall times of 2 ns. Specifications subject to change without notice. R/W R/W t TWH tRWD t t RWZ DS t DH HIGH -Z HIGH-Z DATA DATA t AS t AD t AH ADDR ADDR t CH EN t t EN CSD CSZ t TCH t t CL RWC t CSC CS CS Figure 2. Write Timing Figure 3. Readback Timing LD t LS t LH EN t RS RS OUT t t S1 S1 Figure 4. Write to DAC Register & Voltage Output Settling Timing (CS= High, Prevents Input Register Changes) REV. 0 –4– AD8600 ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION (T = +25°C unless otherwise noted) A Pin No. Name Description V (Digital Supply) to GND . . . . . . . . . . . . . . –0.3 V, +7 V DD1 V (DAC Buffer/Driver Supply) . . . . . . . . . . . . –0.3 V, +7 V DD2 1 NC No Connection V (Analog Supply) to GND . . . . . . . . . . . . . . . –0.3 V, +7 V CC 2V Reference input voltage common REF V (Analog Supply) to GND . . . . . . . . . . . . . . . +0.3 V, –7 V EE to all DACs. V to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V REF CC 3 DACGND DAC Analog Ground Return. Sets V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V DD2 REF analog zero-scale voltage. V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V OUT CC 4V Output Amplifier Positive Supply CC Short Circuit Duration 1 5V Output Amplifier Negative Supply V to GND or Power Supplies . . . . . . . . . . . . . . . Continuous EE OUT 6 O7 DAC Channel Output No. 7 Digital Input/Output Voltage to GND . . . –0.3 V, V + 0.3 V DD Thermal Resistance–Theta Junction-to-Ambient (θ ) 7 O6 DAC Channel Output No. 6 JA PLCC-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W 8 O5 DAC Channel Output No. 5 Package Power Dissipation . . . . . . . . . . . . . . . . (T – T )/θ J A JA 9 O4 DAC Channel Output No. 4 Maximum Junction Temperature T max . . . . . . . . . . . 150°C J 10 O3 DAC Channel Output No. 3 Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C 11 O2 DAC Channel Output No. 2 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 12 O1 DAC Channel Output No. 1 Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C 13 O0 DAC Channel Output No. 0 NOTE 14 V Digital Logic Power Supply 1 DD1 No more than four outputs may be shorted to power or GND simultaneously. 15 RS Active Low Reset Input Pin 16 DB0 Data Bit Zero I/O (LSB) PIN CONFIGURATION 17 DB1 Data Bit I/O 18 DB2 Data Bit I/O 19 DB3 Data Bit I/O 20 DB4 Data Bit I/O 645 3 2 1 44 43 42 41 40 21 DB5 Data Bit I/O O6 7 39 O9 22 DB6 Data Bit I/O O5 8 38 O10 23 DB7 Most Significant Data Bit I/O (MSB) O4 9 37 O11 24 A0 Address Bit Zero (LSB) O3 10 36 O12 25 A1 Address Bit O2 11 35 O13 AD8600 26 A2 Address Bit TOP VIEW O1 12 34 O14 27 A3 Most Significant Addr Bit (MSB) (Not to Scale) 13 33 O0 O15 28 R/W Read/Write Select Control Input V 14 32 DD1 DGND1 29 EN Active Low Enable Clock Strobe RS 15 31 LD 30 CS Chip Select Input DB0 16 30 CS 31 LD DAC Register Load Strobe DB1 17 29 EN 32 DGND1 Digital Ground Input No. 1 18 19 20 21 22 23 24 25 26 27 28 33 O15 DAC Channel Output No. 15 34 O14 DAC Channel Output No. 14 35 O13 DAC Channel Output No. 13 NC = NO CONNECT 36 O12 DAC Channel Output No. 12 37 O11 DAC Channel Output No. 11 ORDERING GUIDE 38 O10 DAC Channel Output No. 10 Package Package 39 O9 DAC Channel Output No. 9 Model Temperature Description Option 40 O8 DAC Channel Output No. 8 41 V Output Amplifier Negative Supply EE AD8600AP –40°C to +85°C 44-Lead PLCC P-44A 42 V Output Amplifier Positive Supply CC AD8600Chips +25°C Die* 43 DGND2 Digital Ground Input No. 2 *For die specifications contact your local Analog Devices sales office. 44 V DAC Analog Supply Voltage DD2 The AD8600 contains 5782 transistors. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8600 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– DB2 O7 DB3 V EE DB4 V CC DB5 DACGND DB6 V REF DB7 NC A0 V DD2 A1 DGND2 A2 V CC A3 V EE R/W O8 AD8600 TRANSFER EQUATIONS Decoded DAC Register Output Voltage O = A i V REF O = D × i 256 where A is the decimal value of the decoded address bits A3, A2, A1, A0 (LSB). where i is the DAC channel number and D is the decimal value of the DAC register data. Address, CS, R/W and data inputs should be stable prior to acti- vation of the active low EN input. Input registers are transpar- Table I. Truth Table ent when EN is low. When EN returns high, data is latched into the decoded input register. When the load strobe LD and EN EN R/W CS LD RS Operation pins are active low, all input register data is transferred to the DAC registers. The DAC registers are transparent while they Write to DAC Register are enabled. – X H L H Update DAC Register L X H – H Update DAC Register + X H L H Latches DAC Register Table II. Address Decode Table L X H + H Latches DAC Register L L L L H DAC Register Transparent A3 A2 A1 A0 Addr DAC (MSB) (LSB) Code Updated Write to Input Register (Binary) (Hex) L L L H H Load Data to Input Register at Decoded Address 000 0 0 O0 + L L H H Latches Data in Input Register at 000 1 1 O1 Decoded Address 001 0 2 O2 L L + H H Latches Data in Input Register at 001 1 3 O3 Decoded Address 010 0 4 O4 Readback Input Registers 010 1 5 O5 X H L H H Input Register Readback (Data 011 0 6 O6 Access) 011 1 7 O7 X H + H H Hi-Z Readback Disconnects from 100 0 8 O8 Bus 100 1 9 O9 X X H X X Hi-Z on Data Bus 101 0 A O10 101 1 B O11 Reset 110 0 C O12 X X X X L Clear All Registers to Zero, 110 1 D O13 V = 0 V OUT 111 0 E O14 X X H H + Latches All Registers to Zero 111 1 F O15 LX LH + CS = Low; Input Register Ready for R/W, DAC Register Latched to Zero NOTES 1 + symbol means positive edge of control input line. 2 – symbol means negative edge of control input line. REV. 0 –6– Typical Performances Characteristics–AD8600 8 V = +5V CC DACs 00–07 SUPERIMPOSED +1/2 3.50 V = –5V V = +5V EE CC V = 3.5V V = –5V REF EE 0 4 V = 3.5V REF V = +5V –1/2 CC 3.49 V = –5V EE V = +3.5V REF 0 T = +25°C A +1/2 3.48 0 –2 DACs 08–015 SUPERIMPOSED –1/2 3.47 –4 0 64 128 192 256 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 DIGITAL INPUT CODE – Decimal TEMPERATURE – °C TEMPERATURE – °C Figure 5. Linearity Error vs. Figure 7. Zero-Scale Voltage vs. Figure 6. Full-Scale Voltage vs. Digital Code Temperature Temperature 100 4 V = +5V 15 V = +5V CC CC V = –5V V = –5V EE EE 80 V = 0V 10 RS = 0 3 REF T = +25°C A 5 60 0 2 V = +5V CC –5 V = –5V 40 EE V = 3.5V REF –10 1 –15 20 0 0 10 100 1k 10k –4 –3 –2 –1 0 1 2 3 4 TIME – 250ns/DIV FREQUENCY – Hz V – Volts OUT Figure 8. Output Current vs. Figure 9. Full-Scale Settling Time Figure 10. Voltage Noise Density vs. Voltage Frequency 0 60 DV = 100mV p-p CC V = 100mV p-p + 2.5V V = 2V p-p + 1V T = +25°C IN DC IN DC A CODE = FF –20 RS = 0 CODE = 00 H H 50 T = +25°C T = +25°C A A V = –5V EE –40 GAIN 40 0 0 –60 –45 –5 –10 –90 30 PHASE –80 –15 –100 20 100 1k 10k 100k 1k 10 100 1k 10k 100k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz Figure 11. Gain & Phase vs. Figure 12. AC Feedthrough vs. Figure 13. PSRR vs. Frequency Frequency Frequency REV. 0 –7– GAIN – dB I – mA LINEARITY ERROR – LSB OUT PHASE – Degrees FULL-SCALE OUTPUT – Volts FEEDTHROUGH – dB OUTPUT AMPLITUDE – Volts PSRR – dB NOISE VOLTAGE DENSITY – nV/√Hz ZERO-SCALE – mV AD8600 20 5 V = +5V 4 CC V = –5V EE V = +5V CC 3 V = 3.5V 19 REF V = –5V EE CODE = 00 H 2 c + 3s V = 3.5V REF 1 18 c 0 c - 3s –1 17 –2 c + 3s c –3 16 –4 c - 3s –5 15 0 200 400 600 800 1000 1200 –75 –50 –25 0 25 50 75 100 125 T = HOURS OF OPERATION AT +125°C TEMPERATURE – °C Figure 14. Supply Current vs. Temperature Figure 15. Output Voltage Drift Accelerated by Burn-In Operation Amplifier Section The AD8600 is a 16-channel voltage output, 8-bit digital to The output of the DAC ladder is buffered by a rail-to-rail out- analog converter. The AD8600 operates from a single +5 V put amplifier. This amplifier is configured as a unity gain fol- supply, or for a wider output swing range, the part can operate lower as shown in Figure 16. The input stage of the amplifier from dual supplies of ±5 V or ±6 V or a single supply of +7 V. contains a PNP differential pair to provide low offset drift and The DACs are based upon a unique R-2R ladder structure* noise. The output stage is shown in Figure 17. It employs that removes the possibility of current injection from the refer- complementary bipolar transistors with their collectors con- ence to ground during code switching. Each of the 8-bit DACs nected to the output to provide rail-to-rail operation. The NPN has an output amplifier to provide 16 low impedance outputs. transistor enters into saturation as the output approaches the With a single external reference, 16 independent dc output lev- negative rail. Thus, in single supply, the output low voltage is els can be programmed through a parallel digital interface. The limited by the saturation voltage of the transistor. For the tran- interface includes 4 bits of address (A0–A3), 8 bits of data sistors used in the AD8600, this is approximately 40 mV. The (DB0–DB7), a read/write select pin (R/W), an enable clock AD8600 was not designed to swing to the positive rail in con- strobe (EN), a DAC register load strobe (LD), and a chip select trast to some of ADI’s other DACs (for example, the AD8582). pin (CS). Additionally a reset pin (RS) is provided to asynchro- The output stage of the amplifier is actually capable of swinging nously reset all 16 DACs to 0 V output. to the positive rail, but the input stage limits this swing to ap- proximately 1.0 V below V . CC D/A Converter Section The internal DAC is an 8-bit voltage mode device with an out- V CC put that swings from DACGND to the external reference volt- age, V . The equivalent schematic of one of the DACs is REF shown in Figure 16. The DAC uses an R-2R ladder to ensure accuracy and linearity over the full temperature range of the part. The switches shown are actually N and P-channel MOSFETs to V OUT allow maximum flexibility and range in the choice of reference V REF R R V OUT R V R R EE R TO 15 DACs R Figure 17. Equivalent Analog Output Circuit R R During normal operation, the output stage can typically source and sink ±1 mA of current. However, the actual short circuit *R = 30kW current is much higher. In fact, each DAC is capable of sourc- R R TYPICALLY ing 20 mA and sinking 8 mA during a short condition. The absolute maximum ratings state that, at most, four DACs can 2R be shorted simultaneously. This restriction is due to current DACGND densities in the metal traces. If the current density is too high, voltage drops in the traces will cause a loss in linearity perfor- Figure 16. Equivalent Schematic of Analog Channel mance for the other DACs in the package. Thus to ensure long- voltage. The switches’ low ON resistance and matching is im- term reliability, no more than four DACs should be shorted portant in maintaining the accuracy of the R-2R ladder. simultaneously. *Patent Pending. REV. 0 –8– SUPPLY CURRENT – mA CHANGE IN ZERO SCALE – mV AD8600 V V Power Supply and Grounding Considerations CC DD2 The low power consumption of the AD8600 is a direct result of circuit design optimizing using a CBCMOS process. The over- all power dissipation of 120 mW translates to a total supply cur- ALL DIGITAL INPUTS (A0–A3, DB0–DB7) rent of only 24 mA for 16 DACs. Thus, each DAC consumes (R/W, CS, EN, LD, RS) only 1.5 mA. Because the digital interface is comprised entirely of CMOS logic, the power dissipation is dependent upon the DGND1 logic input levels. As expected for CMOS, the lowest power V dissipation is achieved when the input level is either close to REF ground or +5 V. Thus, to minimize the power consumption, CMOS logic should be used to interface to the AD8600. DACGND The AD8600 has multiple supply pins. V (Pins 4 and 42) is CC the output amplifiers’ positive supply, and V (Pins 5 and 41) EE Figure 18. ESD Protection Diode Locations the amplifiers’ negative supply. The digital input circuitry is Attention should be paid to the ground pins of the AD8600 to powered by V (Pin 14), and finally the DAC register and R- DD1 ensure that noise is not introduced to the output. The pin la- 2R ladder switches are powered by V (Pin 44). To minimize DD2 beled DACGND (Pin 3) is actually the ground for the R-2R noise feedthrough from the supplies, each supply pin should be ladder, and because of this, it is important to connect this pin to decoupled with a 0.1 μF ceramic capacitor close to the pin. a high quality analog ground. Ideally, the analog ground should When applying power to the device, it is important for the digi- be an actual ground plane. This helps create a low impedance, tal supply, V , to power on before the reference voltage and DD2 low noise ground to maintain accuracy in the analog circuitry. for V to remain less than 0.3 V above V during normal REF DD2 operation. Otherwise, an inherent diode will energize, and it The digital ground pins (DGND1 at Pin 32 and DGND2 at could damage the AD8600. Pin 43) provide the ground reference for the internal digital cir- cuitry and latches. The first thought may be to connect both of In order to improve ESD resistance, the AD8600 has several these pins to the system digital ground. However, this is not the ESD protection diodes on its various pins. These diodes shunt best choice because of the high noise typically found on a ESD energy to the power supplies and protect the sensitive ac- system’s digital ground. This noise can feed through to the out- tive circuitry. During normal operation, all the ESD diodes are put through the DAC’s ground pins. Instead, DGND1 and reversed biased and do not affect the part. However, if overvolt- DGND2 should be connected to the analog ground plane. The ages occur on the various inputs, these diodes will energize. If actual switching current in these pins is small and should not the overvoltage is due to ESD, the electrical spike is typically degrade the analog ground. short enough so that the part is not damaged. However, if the overvoltage is continuous and has sufficient current, the part 5 V Output Swing could be damaged. To protect the part, it is important not to The output swing is limited to 1.0 V below the positive supply. forward bias any of the ESD protection diodes during normal This gives a maximum output of +4.0 V on a +5 V supply. To operation or during power up. Figure 18 shows the location of increase the output range, the analog supply, V , and the DAC CC these diodes. For example, the digital inputs have diodes con- ladder supply, V , can be increased to +7 V. This allows an DD2 nected to V and from DGND1. Thus, the voltage on any output of +5 V with a 5 V reference. V should remain at CC DD1 digital input should never exceed the analog supply or drop be- +5 V to ensure that the input logic levels do not change. low ground, which is also indicated in the absolute maximum Reference Input Considerations ratings. The AD8600 is designed for one reference to drive all 16 DACs. The reference pin (V ) is connected directly to the R-2R lad- REF ders of each DAC. With 16 DACs in parallel, the input imped- ance is typically 2 kΩ and a minimum of 1.2 kΩ. The input resistance is code dependent. Thus, the chosen reference device must be able to drive this load. Some examples of +2.5 V refer- ences that easily interface to the AD8600 are the REF43, AD680, and AD780. The unique architecture ensures that the reference does not have to supply “shoot through” current, which is a condition in some voltage mode DACs where the ref- erence is momentarily connected to ground through the CMOS switches. By eliminating this possibility, all 16 DACs in the AD8600 can easily be driven from a single reference. REV. 0 –9– AD8600 Interface Timing and Control To load multiple input registers in the fastest time possible, The AD8600 employs a double buffered DAC structure with both R/W and CS should remain low, and the EN line be used each DAC channel having a unique input register and DAC reg- to “clock” in the data. As the write timing diagram shows, the ister as shown in the diagram entitled “Equivalent DAC Chan- address should be updated at the same time as EN goes low. nel” on the first page of the data sheet. This structure allows Before EN returns high, valid data must be present for a time maximum flexibility in loading the DACs. For example, each equal to the data setup time (t ), and after EN returns high, DS DAC can be updated independently, or, if desired, all 16 input the data Hold Time (t ) must be maintained. If these mini- DH registers can be loaded, followed by a single LD strobe to up- mum times are violated, invalid data may be latched into the in- date all 16 DACs simultaneously. An additional feature is the put register. This cycle can be repeated 16 times to load all of ability to read back from the input register to verify the DAC’s the DACs. The fastest interface time is equal to the sum of the data. low and high times (t and t ) for the EN input, which gives a CL CH minimum of 80 ns. Because the EN input is used to clock in A0 A1 N1 the data, it is often referred to as the clock input, and the timing A2 A3 specifications give a maximum clock frequency of 12.5 MHz, N5 R/W which is just the reciprocal of 80 ns. EN N2 CS After all the input registers have been loaded, a single load strobe will transfer the contents of the input registers to the N6 R/W N3 CS DAC registers. EN must also be low during this time. If the address or data on the inputs could change, then CS should be LD high during this time to ensure that new data is not loaded into N4 EN an input register. Alternatively, a single DAC can be updated 8 8 INPUT DAC R-2R by first loading its input register and then transferring that to the D7–D0 REGISTER REGISTER LADDER DAC register without loading the other 15 input registers. 8 READ BACK The final interface option is to read data from the DAC’s input registers, which is accomplished by setting R/W high and bring- ing CS low. Read back allows the microprocessor to verify that correct data has been loaded into the DACs. During this time Figure 19. Logic Interface Circuit for DAC Channel 0 EN and LD should be high. After a delay equal to t , the RWD data bus becomes active and the contents of the input register The interface logic for a single DAC channel is shown in Figure are read back to the data pins, DB0–DB7. The address can be 19. This figure specifically shows the logic for Channel 0; how- changed to look at the contents of all the input registers. Note ever, by changing the address input configuration to gate N1, that after an address change, the valid data is not available for a the other 15 channels are achieved. All of the logic for the time equal to t . The delay time is due to the internal AD AD8600 is level sensitive and not edge triggered. For example, readback buffers needing to charge up the data bus (measured if all the control inputs (CS, R/W, EN, LD) are low, the input with a 35 pF load). These buffers are low power and do not and DAC registers are transparent and any change in the digital have high current to charge the bus quickly. When CS returns inputs will immediately change the DAC’s R-2R ladder. high, the data pins assume a high impedance state and control Table I details the different logic combinations and their effects. of the data lines or bus passes back to the microprocessor. Chip Select (CS), Enable (EN) and R/W must be low to write the input register. During this time that all three are low, any data on DB7–DB0 changes the contents of the input register. This data is not latched until either EN or CS returns high. The data setup and hold times shown in the timing diagrams must be observed to ensure that the proper data is latched into the input register. REV. 0 –10– AD8600 Unipolar Output Operation Table IV. Bipolar Code Table The AD8600 is configured to give unipolar operation. The full- DAC scale output voltage is equivalent to the reference input voltage Binary Input minus 1 LSB. The output is dependent upon the digital code MSB LSB Analog Output and follows Table III. The actual numbers given for the analog output are calculated assuming a +2.5 V reference. 1 1 1 1 1 1 1 1 +2 V (255/256) – V = +2.49 V REF REF 1 0 0 0 0 0 0 1 +2 V (129/256) – V = +0.02 V REF REF Table III. Unipolar Code Table 1 0 0 0 0 0 0 0 +2 V (128/256) – V = +0.00 V REF REF 0 1 1 1 1 1 1 1 +2 V (127/256) – V = –0.02 V REF REF DAC 0 0 0 0 0 0 0 1 +2 V (001/256) – V = –2.48 V REF REF Binary Input 0 0 0 0 0 0 0 0 +2 V (000/256) – V = –2.50 V REF REF MSB LSB Analog Output 1 1 1 1 1 1 1 1 +V (255/256) = +2.49 V REF Interfacing to the 68HC11 Microcontroller 1 0 0 0 0 0 0 1 +V (129/256) = +1.26 V REF The 68HC11 is a popular microcontroller from Motorola, 1 0 0 0 0 0 0 0 +V (128/256) = +1.25 V REF which is easily interfaced to the AD8600. The connections be- 0 1 1 1 1 1 1 1 +V (127/256) = +1.24 V REF tween the two components are shown in Figure 21. Port C of 0 0 0 0 0 0 0 1 +V (001/256) = +0.01 V REF the 68HC11 is used as a bidirectional input/output data port to 0 0 0 0 0 0 0 0 +V (000/256) = +0.00 V REF write to and read from the AD8600. Port B is used for address- ing and control information. The bottom 4 LSBs of Port B are Bipolar Output Operation the address, and the top 4 MSBs are the control lines (LD, CS, The AD8600 can be configured for bipolar operation with the EN, and R/W). The microcode for the 68 HC11 is shown in addition of an op amp for each output as shown in Figure 20. Figure 22. The comments in the program explain the function The output will now have a swing of ±V , as detailed in Table REF of each step. Three routines are included in this listing: read IV. This modification is only needed on those channels that re- from the AD8600, write to the AD8600, and a continuous loop quire bipolar outputs. For channels which only require unipolar that generates a saw-tooth waveform. This loop is used in the output, no external amplifier is needed. The OP495 quad am- application below. plifier is chosen for the external amplifier because of its low 8 power, rail-to-rail output swing, and DC accuracy. Again, the DB0–DB7 PC0–PC7 values calculated for the analog output are based upon an as- 4 A0–A3 PB0–PB3 sumed +2.5 V reference. LD PB4 AD8600 MOTOROLA EN PB5 V REF 68HC11 R1 R1 R/W PB6 DGND1, DGND2 10k 10k CS PB7 GND DACGND +5V DIGITAL GROUND ANALOG GROUND 1/4 V V REF OP495 OUT OUTş Figure 21. Interfacing the 68HC11 to the AD8600 AD8600 –5V Figure 20. Circuit for Bipolar Output Operation REV. 0 –11– AD8600 * This program contains subroutines to read and write * to the AD8600 from the 68HC11. Additionally, a ramp * program has been included, to continuously ramp the * output giving a triangle wave output. * * The following connections need to be made: * 68HC11 AD8600 * GND DGND1,2 * PC0-PC7 DB0–DB7 respectively, data port * PB0-PB3 A0–A3 respectively, address port * PB4 LD * PB5 EN * PB6 R/W * PB7 CS * portc equ $1003 define port addresses portb equ $1004 ddrc equ $1007 * org $C000 read lds #$CFFF subroutine to read from AD8600 * ldaa #$00 initialize port c to 00000000 staa ddrc configures PC0-PC7 as inputs. * ldx #$00 points to DAC address in 68HC11 memory ldaa 0,x put the address in the accumulator adda #$70 add the control bits to the address * R/W, LD, EN are high, CS is low. staa portb output control and address on port b. * inx points to memory location to store the data ldaa portc read data from DAC staa 0,x Store this data in memory at address “x” * ldy #$1000 bset portb,y $f0 Set CS, LD, EN high jmp $e000 Return to BUFFALO * * write lds #$cfff routine to write to AD8600 ldaa #$ff initialize port c to 11111111 staa ddrc configures PC0-PC7 as outputs. * ldx #$00 points to DAC address in 68HC11 mem ldaa 0,x puts the address in the accumulator adda #$30 set CS, R/W low and LD, EN high staa portb output to portb for control and address * inx points to memory location to store the data ldaa 0,x load the data into the accumulator staa portc write the data to the DAC * ldy #$1000 bclr portb,y $30 Set LD, EN low to latch data bset portb,y $b0 Bring LD, EN, CS high, write is complete * jmp $e000 Return to BUFFALO * * ramp lds #$cfff routine to generate a triangle wave ldaa #$ff configure port c as outputs REV. 0 –12– AD8600 staa ddrc * ldx #$00 set x to point to the DAC address ldaa 0,x load the address from 68HC11 mem staa portb set the address on portb * LD, CS, EN, R/W are all low for * transparent DAC loading ldab #$ff set accumulator b to 255 * loop ldaa #$00 start the triangle wave at zero staa portc write the data to the AD8600 * load inca increase the data by one staa portc send the new data to the AD8600 cba compare a to b bne load we haven’t reached 255 yet jmp loop we have reached 255, so start over Figure 22. 68HC11 Microcode to Interface to the AD8600. needs to be 1.25 V. In this application, the C1LO input is set at Time Dependent Variable Gain Amplifier Using the AD600 the midscale voltage of 0.625 V, which is generated by a simple The AD8600 is ideal for generating a control signal to set the voltage divider from the REF43. The AD8600’s output is di- gain of the AD600, a wideband, low noise variable gain ampli- vided in half, generating a 0 V to 1.25 V ramp, and then applied fier. The AD600 (and similar parts such as the AD602 and to C1HI. This ramp sweeps the gain from 0 dB to 40 dB. AD603) is often used in ultrasound applications, which require the gain to vary with time. When a burst of ultrasound is ap- +5V plied, the reflections from near objects are much stronger than from far objects. To accurately resolve the far objects, the gain R1 V , V , V CC DD1 DD2 10k must be greater than for the near objects. Additionally, the sig- Oş 0V – 1.25V DIGITAL AD8600 CONTROL 13 nals take longer to reach the ultrasound sensor when reflected R2 C1 V REF from a distant object. Thus, the gain must increase as the time 10k 100pF +5V 2 C1HI increases. 16 V POS 13 2 The AD600 requires a dc voltage to adjust its gain over a V IN A1HI V 40 dB range. Since it is a dual, the two variable gain amplifiers OUT (FROM 14 AD600 ULTRASOUND can be cascaded to achieve 80 dB of gain. The AD8600 is used A1OP SENSOR) 3 15 to generate a ramped output to control the gain of the AD600. +5V A1LO A1CM 12 The slope of the ramp should correspond to the time delay 4 1 2 GAT1 C1LO of the ultrasound signal. Since ultrasound applications often –5V require multiple channels, the AD8600 is ideal for this 0.625V 46 REF43 application. +2.5V R4 R3 10k 30k The circuit to achieve a time dependent variable gain amp is shown in Figure 23. The AD600’s gain is controlled by differ- ential inputs, C1LO and C1HI, with a gain constant of Figure 23. Ultrasound Amplifier with Digitally Controlled 32 dB/V. Thus for 40 dB of gain, the differential control input Variable Gain REV. 0 –13– AD8600 The functionality of this circuit is shown in the scope photo in Glitch Impulse Figure 24 The top trace is the control ramp, which goes from A specification of interest in many DAC applications is the 0 V to 1.25 V. The bottom trace is the output of the AD600. glitch impulse. This is the amount of energy contained in any The input is actually a 12 mV p-p, 10 kHz sine wave. Thus, the overshoot when a DAC changes at its major carry transition, in bottom trace shows the envelop of this waveform to illustrate other words, when the DAC switches from code 01111111 to the increase in gain as time progresses. This ramp was gener- code 10000000. This point is the most demanding because all ated under control of the 68HC11 using the “ramp” subroutine of the R-2R ladder switches are changing state. The AD8600’s as mentioned above. The slope of the ramp can easily be glitch impulse is shown in Figure 25. Calculating the value of lengthened by adding some delay in the loop, or the slope can the glitch is accomplished by calculating the area of the pulse, be increased by stepping by 2 or more LSBs instead of the cur- which for the AD8600 is: Glitch Impulse = (1/2) × (100 mV) × rent 1 LSB changes. (200 ns) = 10 nV sec. GAIN CONTROL 1V/DIV V OUT 50mV/DIV AD600 OUTPUT 0.2V/DIV 200ns/DIV 200ns/DIV 200µs/DIV Figure 24. Time Dependent Gain of the AD600 Figure 25. Glitch Impulse REV. 0 –14– AD8600 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Lead Chip Carrier (PLCC) Package (P-44A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.056 (1.42) 0.025 (0.63) 0.042 (1.07) 0.042 (1.07) 0.015 (0.38) 6 40 7 PIN 1 39 0.021 (0.53) 0.048 (1.21) IDENTIFIER 0.013 (0.33) 0.042 (1.07) 0.63 (16.00) 0.59 (14.99) 0.032 (0.81) TOP VIEW 0.026 (0.66) 0.050 (1.27) BSC 29 17 18 28 0.020 0.040 (1.01) 0.656 (16.66) (0.50) 0.025 (0.64) SQ R 0.650 (16.51) 0.110 (2.79) 0.695 (17.65) SQ 0.085 (2.16) 0.685 (17.40) REV. 0 –15– AD8600 REV. 0 –16– PRINTED IN U.S.A. C1921–18–7/94