ANALOG DEVICES AD8597

Single and Dual, Ultralow Distortion, Ultralow Noise Op Amps AD8597/AD8599 FEATURES PIN CONFIGURATIONS Low noise: 1.1 nV/√Hz at 1 kHz NC 1 8 NC –IN 2 AD8597 7 V+ Low distortion: −120 dB THD @ 1 kHz +IN 3 6 OUT TOP VIEW Input noise, 0.1 Hz to 10 Hz: <76 nV p-p (Not to Scale) V– 4 5 NC Slew rate: 14 V/μs Wide bandwidth: 10 MHz NC = NO CONNECT Supply current: 4.8 mA/amp typical Figure 1. AD8597 8-Lead SOIC (R-8) Low offset voltage: 10 μV typical CMRR: 120 dB Unity-gain stable PIN 1 NC 1 8NC INDICATOR ±15 V operation –IN 2 7V+ AD8597 +IN 3 6OUT TOP VIEW APPLICATIONS 5NC V– 4 Professional audio preamplifiers ATE/precision testers NOTES 1. NC = NO CONNECT. Imaging systems 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED Medical/physiological measurements TO V–. Precision detectors/instruments Figure 2. AD8597 8-Lead LFCSP (CP-8-2) Precision data conversion OUT A 1 8 +V –IN A 2 AD8599 7 OUT B +IN A 3 6 –IN B TOP VIEW (Not to Scale) –V 4 5 +IN B Figure 3. AD8599 8-Lead SOIC (R-8) GENERAL DESCRIPTION The AD8597/AD8599 are very low noise, low distortion opera- The AD8597 is available in 8-lead SOIC and LFCSP packages, tional amplifiers ideal for use as preamplifiers. The low noise of while the AD8599 is available in an 8-lead SOIC package. They 1.1 nV/√Hz and low harmonic distortion of −120 dB (or better) are both specified over a −40°C to +125°C temperature range. at audio bandwidths give the AD8597/AD8599 the wide dynamic The AD8597 and AD8599 are members of a growing series of range necessary for preamplifiers in audio, medical, and instru- low noise op amps offered by Analog Devices, Inc., (see Table 1). mentation applications. The excellent slew rate of 14 V/μs and Table 1. Low Noise Op Amps 10 MHz gain bandwidth make them highly suitable for medical Package 0.9 nV 1.1 nV 1.8 nV 2.8 nV 3.8 nV applications. The low distortion and fast settling time make Single AD797 AD8597 ADA4004-1 AD8675 AD8671 them ideal for buffering of high resolution data converters. Dual AD8599 ADA4004-2 AD8676 AD8672 Quad ADA4004-4 AD8674 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06274-060 06274-061 06274-054 AD8597/AD8599 TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution...................................................................................5  Applications ....................................................................................... 1  Typical Performance Characteristics ..............................................6  Pin Configurations ........................................................................... 1  Functional Operation..................................................................... 15  General Description ......................................................................... 1  Input Voltage Range ................................................................... 15  Revision History ............................................................................... 2  Output Phase Reversal ............................................................... 15  Specif ica t ions ..................................................................................... 3  Noise and Source Impedance Considerations ........................... 15  Absolute Maximum Ratings ............................................................ 5  Outline Dimensions ....................................................................... 17  Thermal Resistance ...................................................................... 5  Ordering Guide .......................................................................... 17  Power Sequencing ........................................................................ 5  REVISION HISTORY 12/09—Rev. B to Rev. C 4/07—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 1 Updated Layout ................................................................................. 5 Changes to Figure 45 Caption ...................................................... 12 10/08—Rev. A to Rev. B Added Figure 48 ............................................................................. 12 Added AD8597 ................................................................... Universal Changes to Figure 51 Caption ...................................................... 13 Added LFCSP_VD ............................................................. Universal 2/07—Revision 0: Initial Version Added Table 1 .................................................................................... 1 Changes to Specifications Section .................................................. 3 Changes to Absolute Maximum Ratings Section ......................... 5 Changes to Typical Performance Characteristics Section ........... 6 Added Figure 12 and Figure 15....................................................... 7 Added Figure 18 and Figure 19....................................................... 8 Added Figure 30 and Figure 33..................................................... 10 Added Figure 34 to Figure 38 ........................................................ 11 Added Figure 42 and Figure 45..................................................... 12 Added Figure 52, Figure 55, Figure 57 ......................................... 14 Added Functional Operation Section .......................................... 15 Added Figure 58 .............................................................................. 15 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 Rev. C | Page 2 of 20 AD8597/AD8599 SPECIFICATIONS VSY = ±5 V, VCM = 0 V, VO = 0 V, TA = 25°C, unless otherwise specified. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 15 120 μV OS −40°C ≤ TA ≤ +125°C 180 μV Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.8 2.2 μV/°C Input Bias Current I 40 210 nA B −40°C ≤ T ≤ +125°C 340 nA A Input Offset Current I 65 250 nA OS −40°C ≤ TA ≤ +125°C 340 nA Input Voltage Range IVR −2.0 +2.0 V Common-Mode Rejection Ratio CMRR −2.0 V ≤ VCM ≤ +2.0 V 120 135 dB −40°C ≤ T ≤ +125°C 105 dB A Large Signal Voltage Gain A R ≥ 600 Ω, V = −11 V to +11 V 105 110 dB VO L O −40°C ≤ TA ≤ +125°C 100 dB Input Capacitance Differential Capacitance CDIFF 15.4 pF Common-Mode Capacitance C 5.5 pF CM OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 600 Ω 3.5 3.7 V −40°C ≤ T ≤ +125°C 3.3 V A R = 2 kΩ 3.7 3.8 V L −40°C ≤ TA ≤ +125°C 3.5 V Output Voltage Low VOL RL = 600 Ω −3.6 −3.4 V −40°C ≤ TA ≤ +125°C −3.3 V RL = 2 kΩ −3.7 −3.5 V −40°C ≤ T ≤ +125°C −3.4 V A Output Short-Circuit Current I ±52 mA SC Closed-Loop Output Impedance ZOUT At 1 MHz, AV = 1 5 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±18 V to ±4.5 V 120 140 dB SY −40°C ≤ TA ≤ +125°C 118 dB Supply Current per Amplifier ISY 4.8 5.5 mA −40°C ≤ TA ≤ +125°C 6.5 mA DYNAMIC PERFORMANCE Slew Rate SR AV = −1, RL = 2 kΩ 14 V/μs AV = 1, RL = 2 kΩ 14 V/μs Settling Time t To 0.01%, step = 10 V 2 μs S Gain Bandwidth Product GBP 10 MHz Phase Margin ΦM 60 Degrees NOISE PERFORMANCE Peak-to-Peak Noise e p-p 0.1 Hz to 10 Hz 76 nV p-p n Voltage Noise Density en f = 1 kHz 1.07 1.15 nV/√Hz f = 10 Hz 1.5 nV/√Hz Correlated Current Noise f = 1 kHz 2.0 pA/√Hz f = 10 Hz 4.2 pA/√Hz Uncorrelated Current Noise f = 1 kHz 2.4 pA/√Hz f = 10 Hz 5.2 pA/√Hz Total Harmonic Distortion + Noise THD + N G = 1, RL ≥ 1 kΩ, f = 1 kHz, VRMS = 1 V −120 dB Channel Separation CS f = 10 kHz −120 dB Rev. C | Page 3 of 20 AD8597/AD8599 V = ±15 V, V = 0 V, V = 0 V, T = +25°C, unless otherwise specified. S CM O A Table 3. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 10 120 μV OS −40°C ≤ T ≤ +125°C 180 μV A Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.8 2.2 μV/°C Input Bias Current IB 25 200 nA −40°C ≤ T ≤ +125°C 300 nA A Input Offset Current I 50 200 nA OS −40°C ≤ T ≤ +125°C 300 nA A Input Voltage Range IVR −12.5 +12.5 V Common-Mode Rejection Ratio CMRR −12.5 V ≤ VCM ≤ +12.5 V 120 135 dB −40°C ≤ TA ≤ +125°C 115 dB Large Signal Voltage Gain A R ≥ 600 Ω, V = −11 V to +11 V 110 116 dB VO L O −40°C ≤ T ≤ +125°C 106 dB A Input Capacitance Differential Capacitance CDIFF 12.1 pF Common-Mode Capacitance CCM 5.1 pF OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 600 Ω 13.1 13.4 V −40°C ≤ TA ≤ +125°C 12.8 V R = 2 kΩ 13.5 13.7 V L −40°C ≤ T ≤ +125°C 13.2 V A Output Voltage Low V R = 600 Ω −13.2 −12.9 V OL L −40°C ≤ TA ≤ +125°C −12.8 V RL = 2 kΩ −13.5 −13.4 V −40°C ≤ TA ≤ +125°C −13.3 V Output Short-Circuit Current I ±52 mA SC Closed-Loop Output Impedance Z At 1 MHz, A = 1 5 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±18 V to ±4.5 V 120 140 dB SY −40°C ≤ T ≤ +125°C 118 dB A Supply Current per Amplifier ISY 5.0 5.7 mA −40°C ≤ TA ≤ +125°C 6.75 mA DYNAMIC PERFORMANCE Slew Rate SR AV = −1, RL = 2 kΩ 16 V/μs AV = 1, RL = 2 kΩ 15 V/μs Settling Time ts To 0.01%, step = 10 V 2 μs Gain Bandwidth Product GBP 10 MHz Phase Margin Φ 65 Degrees M NOISE PERFORMANCE Peak-to-Peak Noise e p-p 0.1 Hz to 10 Hz 76 nV p-p n Voltage Noise Density e f = 1 kHz 1.07 1.15 nV/√Hz n f = 10 Hz 1.5 nV/√Hz Correlated Current Noise f = 1 kHz 1.9 pA/√Hz f = 10 Hz 4.3 pA/√Hz Uncorrelated Current Noise f = 1 kHz 2.3 pA/√Hz f = 10 Hz 5.3 pA/√Hz Total Harmonic Distortion + Noise THD + N G = 1, R ≥ 1 kΩ, f = 1 kHz, V = 3 V −120 dB L RMS Channel Separation CS f = 10 kHz −120 dB Rev. C | Page 4 of 20 AD8597/AD8599 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. θ is specified with the device soldered on a circuit board with JA Parameter Rating its exposed paddle soldered to a pad (if applicable) on a 4-layer Supply Voltage ±18 V JEDEC standard PCB with zero air flow. Input Voltage −V ≤ V ≤ +V IN 1 Differential Input Voltage ±1 V Table 5. Output Short-Circuit to GND Indefinite Package Type θ θ Unit JA JC Storage Temperature Range −65°C to +150°C 8-Lead LFCSP_VD (CP-8-2) 78 20 °C/W Operating Temperature Range −40°C to +125°C 8-Lead SOIC (R-8) (AD8597) 140 39 °C/W Lead Temperature Range (Soldering 60 sec) 300°C 8-Lead SOIC (R-8) (AD8599) 120 36 °C/W Junction Temperature 150°C 1 POWER SEQUENCING If the differential input voltage exceeds 1 V, the current should be limited to 5 mA. The op amp supplies should be applied simultaneously. The Stresses above those listed under Absolute Maximum Ratings op amp supplies should be stable before any input signals are may cause permanent damage to the device. This is a stress applied. In any case, the input current must be limited to 5 mA. rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute ESD CAUTION maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 5 of 20 AD8597/AD8599 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 70 70 AD8599 AD8599 MEAN = 8.23 MEAN = 7.91 STDEV = 24.47 STDEV = 21.89 60 60 MIN = –72.62 MIN = –63.02 MAX = 62.09 MAX = 57.5 50 V = ±5V 50 V = ±15V SY SY 40 40 30 30 20 20 10 10 0 0 –75 –65 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 –75 –65 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 V (µV) V (µV) OS OS Figure 4. Input Offset Voltage Distribution Figure 7. Input Offset Voltage Distribution 45 60 AD8599 AD8599 MEAN = 0.346 MEAN = 0.765 40 STDEV = 0.218 STDEV = 0.234 50 MIN = 0.010 MIN = 0.338 35 MAX = 1.155 MAX = 1.709 V = ±5V V = ±15V SY SY 30 40 25 30 20 15 20 10 10 5 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 TCV (µV) TCV (µV) OS OS Figure 8. TCV Distribution, −40°C ≤ T ≤ +125°C Figure 5. TCVOS Distribution, −40°C ≤ TA ≤ +125°C OS A 60 60 AD8599 AD8599 MEAN = 0.342 MEAN = 0.461 STDEV = 0.221 STDEV = 0.245 50 50 MIN = 0.013 MIN = 0.026 MAX = 1.239 MAX = 1.26 V = ±15V V = ±5V SY SY 40 40 30 30 20 20 10 10 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 TCV (µV) TCV (µV) OS OS Figure 6. TCV Distribution, −40°C ≤ T ≤ +85°C Figure 9. TCV Distribution, −40°C ≤ T ≤ +85°C OS A OS A Rev. C | Page 6 of 20 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 06274-006 06274-004 06274-001 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 06274-005 06274-007 06274-002 AD8597/AD8599 100 100 AD8599 AD8599 V = ±5V V = ±15V SY SY 75 75 50 50 25 25 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –5.0 –2.5 0 2.5 5.0 –15 –10 –5 0 5 10 15 V (V) V (V) CM CM Figure 10. Offset Voltage vs. V Figure 13. Offset Voltage vs. V CM CM 350 350 AD8599 AD8599 300 V = ±5V 300 V = ±15V SY SY V = 0V V = 0V CM CM 250 250 200 200 150 150 100 100 50 50 0 0 –50 –50 –100 –100 –150 –150 –200 –200 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Input Bias Current vs. Temperature Figure 14. Input Bias Current vs. Temperature 50 350 AD8597 AD8597 300 V = ±15V SY 40 250 30 200 150 20 T = –40°C A 100 10 50 T = +25°C A 0 0 T = +85°C A –50 ±15V –10 –100 T = +125°C A –20 –150 ±5V –200 –30 –250 –40 –300 –50 –350 –50 –25 0 25 50 75 100 125 150 –12–10 –8 –6 –4 –2 02468 10 12 TEMPERATURE (°C) V (V) CM Figure 12. Input Offset Voltage vs. Temperature Figure 15. Input Bias Current vs. Temperature Rev. C | Page 7 of 20 V (µV) I (nA) V (µV) OS OS B 06274-062 06274-011 06274-009 I (nA) I (nA) V (µV) B B OS 06274-010 06274-063 06274-012 AD8597/AD8599 150 80 AD8597 AD8599 70 100 60 50 50 ±15V 0 40 ±5V I @ V = ±5V OS SY 30 –50 20 I @ V = ±15V OS SY –100 10 –150 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Input Offset Current vs. Temperature Figure 19. Input Offset Current vs. Temperature 114 120 AD8599 AD8599 V = ±5V SY V = ±15V SY 112 118 R = 2kΩ, V = ±11V L O 110 R = 2kΩ, V = ±2V L O 116 108 R = 600Ω, V = ±2V R = 600Ω, V = ±11V L O L O 106 114 104 112 102 100 110 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Large Signal Voltage Gain vs. Temperature Figure 20. Large Signal Voltage Gain vs. Temperature 8 350 AD8597 AD8599 300 V = ±15V 7 SY T = –40°C A 250 T = +125°C A T = +85°C A 200 6 150 T = +25°C A 5 100 T = +25°C A 50 T = –40°C A 4 0 T = +85°C A –50 3 –100 –150 2 T = +125°C A –200 1 –250 –300 0 –350 0 2 4 6 8 101214 161820 222426 283032 3436 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 V (V) V (V) SY CM Figure 18. Supply Current vs. Supply Voltage Figure 21. Input Bias Current vs. VCM Rev. C | Page 8 of 20 A (dB) I (mA) SY VO I (nA) OS 06274-013 06274-064 06274-015 I (nA) A (dB) I (nA) B B VO 06274-014 06274-016 06274-065 AD8597/AD8599 80 80 AD8599 AD8599 V = ±5V V = ±15V SY SY 60 60 I I SINK SINK 40 40 20 20 0 0 –20 –20 –40 –40 I SOURCE I SOURCE –60 –60 –80 –80 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 22. I vs. Temperature Figure 25. I vs. Temperature SC SC 10k 10k AD8599 AD8599 V = ±5V SY V = ±15V SY I I SINK SINK 1k 1k I SOURCE I SOURCE 100 100 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 I (mA) I (mA) L L Figure 23. Output Saturation Voltage vs. Current Load Figure 26. Output Saturation Voltage vs. Current Load 2.5 2.5 AD8599 AD8599 V = ±5V V = ±15V SY SY 2.0 2.0 V – V @ R = 600Ω CC OH L 1.5 1.5 V – V @ R = 600Ω CC OH L V – V @ R = 2kΩ CC OH L 1.0 1.0 V – V @ R = 2kΩ CC OH L 0.5 0.5 0 0 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 24. Output Saturation Voltage vs. Temperature Figure 27. Output Saturation Voltage vs. Temperature Rev. C | Page 9 of 20 OUTPUT SATURATION VOLTAGE (mV) V – V (V) OUTPUT CURRENT (mA) CC OH 06274-017 06274-027 06274-021 OUTPUT SATURATION VOLTAGE (mV) V – V (V) OUTPUT CURRENT (mA) CC OH 06274-018 06274-029 06274-022 AD8597/AD8599 0 0 AD8599 AD8599 V = ±5V V = ±15V SY SY –0.5 –0.5 –1.0 –1.0 V – V @ R = 2kΩ EE OL L V – V @ R = 2kΩ EE OL L –1.5 –1.5 V – V @ R = 600Ω EE OL L V – V @ R = 600Ω EE OL L –2.0 –2.0 –2.5 –2.5 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 28. Output Saturation Voltage vs. Temperature Figure 31. Output Saturation Voltage vs. Temperature –13.0 15.0 V @ R = 600Ω AD8599 OL L 14.8 V = ±15V SY 14.6 –13.5 14.4 V @ R = 2kΩ OL L 14.2 –14.0 14.0 V @ R = 2kΩ OH L 13.8 13.6 –14.5 13.4 V @ R = 600Ω OH L AD8599 13.2 V = ±15V SY –15.0 13.0 –50 0 50 100 150 –50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 29. Output Voltage Low vs. Temperature Figure 32. Output Voltage High vs. Temperature 100 120 80 100 60 80 40 60 C = 20pF L 20 40 C = 20pF L 0 20 –20 0 C = 200pF L –40 –20 C = 200pF L –60 –40 AD8597 AD8597 V = ±5V V = ±15V –80 SY –60 SY R = 2kΩ R = 2kΩ L L –100 –80 10 100 1k 10k 50k 1 10 100 1k 10k 50k FREQUENCY (kHz) FREQUENCY (kHz) Figure 30. Gain and Phase vs. Frequency Figure 33. Gain and Phase vs. Frequency Rev. C | Page 10 of 20 V (V) OL V – V (V) GAIN (dB) AND PHASE (Degrees) EE OL 06274-066 06274-028 06274-032 V (V) V – V (V) GAIN (dB) AND PHASE (Degrees) OH EE OL 06274-067 06274-031 06274-030 AD8597/AD8599 50 50 40 40 A = 100 A = 100 V V 30 30 20 20 A = 10 A = 10 V V 10 10 0 0 A = 1 A = 1 V V –10 –10 –20 –20 AD8597 AD8597 –30 V = ±5V –30 V = ±15V SY SY R = 2kΩ R = 2kΩ L L –40 –40 1 10 100 1k 10k 50k 1 10 100 1k 10k 50k FREQUENCY (kHz) FREQUENCY (kHz) Figure 34. Closed-Loop Gain vs. Frequency Figure 37. Closed-Loop Gain vs. Frequency 100 100 A = –100 A = –100 V V 10 10 A = –10 A = –10 V V A = +1 A = +1 V V 1 1 0.1 0.1 AD8597 AD8597 V = ±5V V = ±15V SY SY 0.01 0.01 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (kHz) FREQUENCY (kHz) Figure 35. Closed-Loop Output Impedance vs. Frequency Figure 38. Closed-Loop Output Impedance vs. Frequency 110 120 AD8599 100 ±5V ≤ V ≤ ±15V SY 100 PSRR+ (dB) 90 PSRR– (dB) 80 80 70 60 60 AD8597 40 V = ±5V, ±15V SY 50 20 40 0 30 20 –20 1 10 100 1k 10k 100 1k 10k 100k 1M 10M FREQUENCY (kHz) FREQUENCY (Hz) Figure 36. Common-Mode Rejection Ratio vs. Frequency Figure 39. Power Supply Rejection Ratio vs. Frequency Rev. C | Page 11 of 20 CMRR (dB) Z (Ω) GAIN (dB) OUT 06274-070 06274-069 06274-068 PSRR (dB) Z (Ω) GAIN (dB) OUT 06274-038 06274-072 06274-071 AD8597/AD8599 600 90 AD8599 AD8599 MEAN = 1.30 MEAN = 1.07 80 STDEV = 0.09 STDEV = 0.02 500 MIN = 1.1 MIN = 1.05 70 MAX = 1.5 MAX = 1.15 ≤ ±15V ±5V ≤ V ≤ ±15V ±5V ≤ V SY SY 400 60 50 300 40 200 30 20 100 10 0 0 0.95 0.98 1.01 1.04 1.07 1.10 1.13 1.16 1.19 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VOLTAGE NOISE DENSITY (nV/ Hz) VOLTAGE NOISE DENSITY (nV/ Hz) Figure 43. Voltage Noise Density @ 1 kHz Figure 40. Voltage Noise Density @ 10 Hz 100 100 AD8599 AD8599 ±5V ≤ V ≤ ±15V ±5V ≤ V ≤ ±15V SY SY 10 10 1 1 0.1 0.1 1 10 100 1k 110 100 1k FREQUENCY (Hz) FREQUENCY (Hz) Figure 41. Voltage Noise Density vs. Frequency Figure 44. Current Noise Density vs. Frequency 1 1 0.1 0.1 R = 600Ω L 0.01 0.01 AD8597 AD8597 V = ±5V V = ±15V SY SY A = +1 A = +1 V V R = 600Ω L 0.001 0.001 R = 100kΩ R = 100kΩ L L 0.0001 0.0001 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 V rms (V) V rms (V) Figure 42. THD + N vs. Amplitude Figure 45. THD + N vs. Amplitude Rev. C | Page 12 of 20 THD + N (%) VOLTAGE NOISE DENSITY (nV/ Hz) NUMBER OF AMPLIFIERS 06274-039 06274-041 06274-073 THD + N (%) CURRTENT NOISE DENSITY (pA/ Hz) NUMBER OF AMPLIFIERS 06274-040 06274-042 06274-074 AD8597/AD8599 0.1 0.1 AD8599 AD8599 V = 3V rms IN V = ±15V V = ±15V SY SY V = 5V rms V = 3V rms IN IN V = 7V rms IN 0.01 0.01 0.001 0.001 R = 600Ω L R = 2kΩ L 0.0001 0.0001 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 46. THD + N vs. Frequency Figure 49. THD + N vs. Frequency 20 20 AD8599 AD8599 15 15 10 10 5 5 V = ±15V SY 0 0 V = 20V p-p V = ±15V IN SY A = –1 V = 20V p-p V IN –5 –5 R = 2kΩ A = 1 F V R = 2kΩ R = 1kΩ S F –10 –10 C = 0pF R = 2kΩ L L VERTICAL AXIS = 5V/DIV VERTICAL AXIS = 5V/DIV HORIZONTAL AXIS = 4µs/DIV HORIZONTAL AXIS = 4µs/DIV –15 –15 –20 –20 –8.6 –4.6 –0.6 3.4 7.4 11.4 15.4 19.4 23.4 27.4 31.4 –8.6 –4.6 –0.6 3.4 7.4 11.4 15.4 19.4 23.4 27.4 31.4 TIME (µs) TIME (µs) Figure 47. Large Signal Response Figure 50. Large Signal Response 80 45 AD8599 AD8599 ≤ ±15V ±5V ≤ V 40 SY 60 A = 1 V R = 10kΩ L 35 40 30 20 25 0 20 V = ±15V, ±5V SY –20 V = 100mV p-p IN 15 A = 1 V –40 EXTERNAL C = 100pF L 10 EXTERNAL R = 10kΩ L –60 VERTICAL AXIS = 20mV/DIV 5 HORIZONTAL AXIS = 400ns/DIV –80 0 –800 –400 0 400 800 1200 1600 2000 2400 2800 3200 10 100 1k TIME (ns) CAPACITANCE (pF) Figure 48. Small Signal Response Figure 51. Overshoot vs. Capacitance Rev. C | Page 13 of 20 THD + N (%) AMPLITUDE (mV) AMPLITUDE (V) 06274-047 06274-046 06274-044 THD + N (%) AMPLITUDE (V) OVERSHOOT (%) 06274-049 06274-048 06274-043 AD8597/AD8599 45 45 AD8597 AD8597 V = ±5V V = ±15V SY SY 40 40 35 35 OS– 30 30 25 25 20 20 OS– 15 15 OS+ 10 10 OS+ 5 5 0 0 10 100 1k 10 100 1k CAPACITANCE (pF) CAPACITANCE (pF) Figure 52. Overshoot vs. Capacitive Load Figure 55. Overshoot vs. Capacitive Load 0 15.0 AD8599 AD8599 V = ±15V SY –20 A = 100 V R = 1kΩ L –40 V = 10V p-p 12.5 IN V = 20V p-p IN –60 –80 10.0 V = ±15V SY –100 V = ±5V SY –120 7.5 –140 –160 5.0 100 1k 10k 100k 1M –50 –25 0 25 50 75 100 125 FREQUENCY (Hz) TEMPERATURE (°C) Figure 53. Channel Separation vs. Frequency Figure 56. Supply Current vs. Temperature 6.0 800 AD8597 AD8599 ±5V ≤ V ≤ ±15V SY 600 5.5 400 V = ±15V 200 SY 5.0 0 V = ±5V SY –200 4.5 –400 –600 4.0 –800 01 2 3 4 5 6 7 8 910 –40 –25 –10 5 20 35 50 65 80 95 110 125 TIME (Seconds) TEMPERATURE (°C) Figure 54. Peak-to-Peak Noise Figure 57. Supply Current vs. Temperature Rev. C | Page 14 of 20 CHANNEL SEPARATION (dB) AMPLITUDE (nV) OVERSHOOT (%) 06274-053 06247-077 06274-050 I (mA) I (mA) OVERSHOOT (%) SY SY 06274-075 06274-020 06247-078 AD8597/AD8599 FUNCTIONAL OPERATION The AD8597/AD8599 amplifiers have been carefully designed INPUT VOLTAGE RANGE to prevent any output phase reversal if both inputs are main- The AD8597/AD8599 are not rail-to-rail input amplifiers; tained within the specified input voltage range. If one or both therefore, care is required to ensure that both inputs do not inputs exceed the input voltage range but remain within the exceed the input voltage range. Under normal negative feedback supply rails, the op amp specifications, such as CMRR, are not operating conditions, the amplifier corrects its output to ensure guaranteed, but the output remains close to the correct value. that the two inputs are at the same voltage. However, if either input exceeds the input voltage range, the loop opens and large NOISE AND SOURCE IMPEDANCE CONSIDERATIONS currents begin to flow through the ESD protection diodes in the The AD8597/AD8599 ultralow voltage noise of 1.1 nV/√Hz is amplifier. achieved with special input transistors running at high collector These diodes are connected between the inputs and each supply current. Therefore, it is important to consider the total input- rail to protect the input transistors against an electrostatic discharge referred noise (e total), which includes contributions from N event and they are normally reverse-biased. However, if the voltage noise (e ), current noise (i ), and resistor noise N N input voltage exceeds the supply voltage, these ESD diodes (√4 kTRS). can become forward-biased. Without current limiting, excessive 2 2 1/2 eN total = [eN + 4 kTRS + (iN × RS) ] (1) amounts of current may flow through these diodes, causing where RS is the total input source resistance. permanent damage to the device. If inputs are subject to over- voltage, insert appropriate series resistors to limit the diode This equation is plotted for the AD8597/AD8599 in Figure 58. current to less than 5 mA maximum. Because optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear The input stage has two diodes between the input pins to from Equation 1 that eliminating the balancing source resistance protect the differential pair. Under high slew rate conditions, lowers the total noise by reducing the total R by a factor of 2. S when the op amp is connected as a voltage follower, the diodes may become forward-biased and the source may try to drive At a very low source resistance (RS < 50 Ω), the voltage noise of the the output. A small resistor should be placed in the feedback amplifier dominates. As source resistance increases, the Johnson loop and in the noninverting input. The noise of a 100 Ω noise of RS dominates until a higher resistance of RS > 2 kΩ is resistor at room temperature is ~1.25 nV/√Hz, which is higher achieved; the current noise component is larger than the than the AD8597/AD8599. Thus, there is a tradeoff between resistor noise. noise performance and protection. If possible, limiting should 100 be placed earlier in the signal path. For further details, see the Amplifier Input Protection…Friend or Foe article at http://www.analog.com/amplifier_input. 10 Because of the large transistors used to achieve low noise, the input capacitance may seem rather high. To take advantage of TOTAL NOISE the low noise performance, impedance around the op amp should RESISTOR NOISE ONLY be low, less than 500 Ω. Under these conditions, the pole from 1 the input capacitance should be greater than 50 MHz, which does not affect the signal bandwidth. OUTPUT PHASE REVERSAL 0.1 Output phase reversal occurs in some amplifiers when the 10 100 1k 10k input common-mode voltage range is exceeded. As the common- SOURCE RESISTANCE (Ω) mode voltage is moved outside the input voltage range, the Figure 58. Noise vs. Source Resistance outputs of these amplifiers can suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down that causes a radical shifting of internal voltages that results in the erratic output behavior. Rev. C | Page 15 of 20 TOTAL NOISE (nV/ Hz) 06274-076 AD8597/AD8599 The AD8597/AD8599 are the optimum choice for low noise general noise theory with extensive calculations, see the performance if the source resistance is kept < 1 kΩ. At higher AN-358 Application Note, Noise and Operational Amplifier values of source resistance, optimum performance with respect Circuits. A good selection table for low noise op amps can to only noise is obtained with other amplifiers from Analog be found in AN-940 Application Note, Low Noise Amplifier Devices. Both voltage noise and current noise need to be consi- Selection Guide for Optimal Noise Performance. An interesting dered. For more information on avoiding noise from grounding note on using one section of a monolithic dual to phase compen- problems and inadequate bypassing, see the AN-345 Application sate the other section is in the AN-107 Application Note, Active Note, Grounding for Low- and High-Frequency Circuits. For Feedback Improves Amplifier Phase Accuracy. V+ 7 Q36 R18 R19 D1 D31 R31 D2 D34 6 2 OUTPUT INVERTING C1 – Q18 Q19 V R1 B INPUT Q19 Q20 D39 D41 D3 R32 D40 D42 3 NONINVERTING + INPUT Q32 D2 Q27 Q28 4 V– Figure 59. Simplified Schematic Rev. C | Page 16 of 20 06247-079 AD8597/AD8599 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 60. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.25 0.60 MAX 3.00 SQ 0.50 2.75 BSC 0.60 MAX 5 8 2.95 1.60 EXPOSED TOP 2.75 SQ PIN 1 1.45 PAD VIEW 2.55 INDICATOR (BOTTOM VIEW) 1.30 4 1 PIN 1 0.50 INDICATOR 1.89 0.40 1.74 12° MAX 0.70 MAX 0.30 1.59 0.90 MAX 0.65 TYP 0.85 NOM 0.05 MAX FOR PROPER CONNECTION OF 0.01 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATIONS 0.30 SEATING SECTION OF THIS DATA SHEET. PLANE 0.23 0.20 REF 0.18 Figure 61. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD8597ACPZ-R2 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22 1 AD8597ACPZ-REEL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22 1 AD8597ACPZ-REEL7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22 1 AD8597ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8597ARZ-REEL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8597ARZ-REEL7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8599ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8599ARZ-REEL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8599ARZ-REEL7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 Z = RoHS Complaint Part. Rev. C | Page 17 of 20 012407-A 101708-B AD8597/AD8599 NOTES Rev. C | Page 18 of 20 AD8597/AD8599 NOTES Rev. C | Page 19 of 20 AD8597/AD8599 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06274-0-12/09(C) Rev. C | Page 20 of 20