ANALOG DEVICES AD8592

CMOS Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers with Shutdown AD8591/AD8592/AD8594 FEATURES PIN CONFIGURATIONS Single-supply operation: 2.5 V to 6 V OUT A 1 6 V+ High output current: ±250 mA AD8591 V– 2 5 SD TOP VIEW Extremely low shutdown supply current: 100 nA (Not to Scale) Low supply current: 750 μA/Amp +IN A 3 4 –IN A Wide bandwidth: 3 MHz Slew rate: 5 V/μs Figure 1. 6-Lead SOT-23 (RJ Suffix) No phase reversal OUT A 1 10 V+ Very low input bias current –IN A 2 9 OUT B AD8592 High impedance outputs when in shutdown mode +IN A 3 8 –IN B TOP VIEW Unity-gain stable (Not to Scale) 4 7 +IN B V– SDA 5 6 SDB APPLICATIONS Figure 2. 10-Lead MSOP (RM Suffix) Mobile communication handset audio OUT A 1 16 OUT D PC audio –IN A 2 15 –IN D PCMCIA/modem line driving +IN A 3 14 +IN D AD8594 V+ 4 13 V– Battery-powered instrumentation TOP VIEW +IN B 5 (Not to Scale) 12 +IN C Data acquisition –IN B 6 11 –IN C ASIC input or output amplifiers OUT B 7 10 OUT C LCD display reference level drivers NC 8 9 SD NC = NO CONNECT GENERAL DESCRIPTION Figure 3. 16-Lead Narrow SOIC (R Suffix) The AD8591, AD8592, and AD8594 are single, dual, and quad 1 16 OUT A OUT D rail-to-rail, input and output single-supply amplifiers featuring 2 –IN A 15 –IN D 250 mA output drive current and a power saving shutdown mode. 3 14 +IN A +IN D AD8594 The AD8592 includes an independent shutdown function for TOP VIEW 4 13 V+ V– (Not to Scale) each amplifier. When both amplifiers are in shutdown mode, 5 12 +IN B +IN C the total supply current is reduced to less than 1 μA. The AD8591 6 11 –IN B –IN C and AD8594 include a single master shutdown function that 7 10 OUT B OUT C reduces the total supply current to less than 1 μA. All amplifier 8 9 SD NC outputs are in a high impedance state when in shutdown mode. NC = NO CONNECT These amplifiers have very low input bias currents, making them Figure 4. 16-Lead TSSOP (RU Suffix) suitable for integrators and diode amplification. Outputs are stable with virtually any capacitive load. Supply current is less than 750 μA per amplifier in active mode. The AD8591, AD8592, and AD8594 are specified over the industrial temperature range (−40°C to +85°C). The AD8591, Applications for these amplifiers include audio amplification for single, is available in the tiny 6-lead SOT-23 package. The AD8592, portable computers, portable phone headsets, sound ports, sound dual, is available in the 10-lead surface-mount MSOP package. The cards, and set-top boxes. The AD859x family is capable of driving AD8594, quad, is available in 16-lead narrow SOIC and 16-lead heavy capacitive loads, such as LCD panel reference levels. TSSOP packages. The ability to swing rail to rail at both the input and output enables designers to buffer CMOS DACs, ASICs, and other wide output swing devices in single-supply systems. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 01106-001 01106-003 01106-002 01106-004 AD8591/AD8592/AD8594 TABLE OF CONTENTS Features .............................................................................................. 1  Output Short-Circuit Protection .............................................. 11  Applications ....................................................................................... 1  Power Dissipation....................................................................... 11  General Description ......................................................................... 1  Capacitive Loading ..................................................................... 12  Pin Configurations ........................................................................... 1  PC98-Compliant Headphone/Speaker Amplifier .................. 12  Revision History ............................................................................... 2  A Combined Microphone and Speaker Amplifier for Cellphone and Portable Headsets ............................................ 13  Specif ica t ions ..................................................................................... 3  An Inexpensive Sample-and-Hold Circuit ............................. 13  Electrical Characteristics ............................................................. 3  Direct Access Arrangement for PCMCIA Modems Absolute Maximum Ratings ............................................................ 5  (Telephone Line Interface) ........................................................ 14  Thermal Resistance ...................................................................... 5  Single-Supply Differential Line Driver .................................... 14  ESD Caution .................................................................................. 5  Outline Dimensions ....................................................................... 15  Typical Performance Characteristics ............................................. 6  Ordering Guide .......................................................................... 16  Theory of Operation ...................................................................... 11  Input Voltage Protection............................................................ 11  Output Phase Reversal ............................................................... 11  REVISION HISTORY 1/09—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Deleted Spice Model for AD8591/AD8592/AD8594 Amplifiers Sections ............................................................................................ 12 Changes to PC98-Compliant Headphone/Speaker Amplifier Section and Figure 38 ..................................................................... 12 Changes to Figure 39 ...................................................................... 13 Changes to Figure 42 and Figure 43 ............................................. 14 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 Rev. B | Page 2 of 16 AD8591/AD8592/AD8594 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 2.7 V, V = 1.35 V, T = 25°C, unless otherwise noted. S CM A Table 1. Parameter Symbol Test Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 25 mV −40°C < T < +85°C 30 mV A Input Bias Current I 5 50 pA B −40°C < TA < +85°C 60 pA Input Offset Current IOS 1 25 pA −40°C < TA < +85°C 30 pA Input Voltage Range 0 2.7 V Common-Mode Rejection Ratio CMRR V = 0 V to 2.7 V 38 45 dB CM Large Signal Voltage Gain A R = 2 kΩ, V = 0.3 V to 2.4 V 25 V/mV VO L O Offset Voltage Drift ΔVOS/ΔT −40°C < TA < +85°C 20 μV/°C Bias Current Drift ΔIB/ΔT −40°C < TA < +85°C 50 fA/°C Offset Current Drift ΔIOS/ΔT −40°C < TA < +85°C 20 fA/°C OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 10 mA 2.55 2.61 V −40°C to +85°C 2.5 V Output Voltage Low V I = 10 mA 60 100 mV OL L −40°C to +85°C 125 mV Output Current IOUT ±250 mA Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 60 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 2.5 V to 6 V 45 55 dB Supply Current per Amplifier ISY VO = 0 V 1 mA −40°C < TA < +85°C 1.25 mA Supply Current Shutdown Mode I All amplifiers shut down 0.1 1 μA SD −40°C < T < +85°C 1 μA A ISD1 Amplifier 1 shut down (AD8592) 1.4 mA ISD2 Amplifier 2 shut down (AD8592) 1.4 mA SHUTDOWN INPUTS Logic High Voltage VINH −40°C < TA < +85°C 1.6 V Logic Low Voltage VINL −40°C < TA < +85°C 0.5 V Logic Input Current IIN −40°C < TA < +85°C 1 μA DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ 3.5 V/μs Settling Time tS To 0.01% 1.4 μs Gain Bandwidth Product GBP 2.2 MHz Phase Margin Φo 67 Degrees Channel Separation CS f = 1 kHz, R = 2 kΩ 65 dB L NOISE PERFORMANCE Voltage Noise Density e f = 1 kHz 45 nV/√Hz n f = 10 kHz 30 nV/√Hz Current Noise Density in f = 1 kHz 0.05 pA/√Hz Rev. B | Page 3 of 16 AD8591/AD8592/AD8594 V = 5.0 V, V = 2.5 V, T = 25°C, unless otherwise noted. S CM A Table 2. Parameter Symbol Test Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 2 25 mV OS −40°C < T < +85°C 30 mV A Input Bias Current I 5 50 pA B −40°C < TA < +85°C 60 pA Input Offset Current IOS 1 25 pA −40°C < TA < +85°C 30 pA Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V = 0 V to 5 V 38 47 dB CM Large Signal Voltage Gain A R = 2 kΩ, V = 0.5 V to 4.5 V 15 30 V/mV VO L O Offset Voltage Drift ΔVOS/ΔT −40°C < TA < +85°C 20 μV/°C Bias Current Drift ΔIB/ΔT −40°C < TA < +85°C 50 fA/°C Offset Current Drift ΔIOS/ΔT −40°C < TA < +85°C 20 fA/°C OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 10 mA 4.9 4.94 V −40°C to +85°C 4.85 V Output Voltage Low V I = 10 mA 50 100 mV OL L −40°C to +85°C 125 mV Output Current IOUT ±250 mA Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 40 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 2.5 V to 6 V 45 55 dB Supply Current per Amplifier ISY VO = 0 V 1.25 mA −40°C < TA < +85°C 1.75 mA Supply Current Shutdown Mode I All amplifiers shut down 0.1 1 μA SD −40°C < T < +85°C 1 μA A ISD1 Amplifier 1 shut down (AD8592) 1.6 mA ISD2 Amplifier 2 shut down (AD8592) 1.6 mA SHUTDOWN INPUTS Logic High Voltage VINH −40°C < TA < +85°C 2.4 V Logic Low Voltage VINL −40°C < TA < +85°C 0.8 V Logic Input Current IIN −40°C < TA < +85°C 1 μA DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ 5 V/μs Full Power Bandwidth BWP 1% distortion 325 kHz Settling Time t To 0.01% 1.6 μs S Gain Bandwidth Product GBP 3 MHz Phase Margin Φo 70 Degrees Channel Separation CS f = 1 kHz, RL = 10 kΩ 65 dB NOISE PERFORMANCE Voltage Noise Density en f = 1 kHz 45 nV/√Hz f = 10 kHz 30 nV/√Hz Current Noise Density in f = 1 kHz 0.05 pA/√Hz Rev. B | Page 4 of 16 AD8591/AD8592/AD8594 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Supply Voltage 6 V Input Voltage GND to V S Table 4. Differential Input Voltage ±6 V Package Type θ θ Unit JA JC 1 Output Short-Circuit Duration to GND Observe Derating Curves 6-Lead SOT-23 (RJ) 230 92 °C/W Storage Temperature Range −65°C to +150°C 10-Lead MSOP (RM) 200 44 °C/W Operating Temperature Range −40°C to +85°C 16-Lead SOIC (R) 120 36 °C/W Junction Temperature Range −65°C to +150°C 16-Lead TSSOP (RU) 180 35 °C/W Lead Temperature (Soldering, 60 sec) 300°C 1 For supplies less than ±5 V, the differential input voltage is limited to the supplies. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 5 of 16 AD8591/AD8592/AD8594 TYPICAL PERFORMANCE CHARACTERISTICS 1k 0.8 V = 2.7V S T = 25°C A T = 25°C A 0.7 100 0.6 0.5 SOURCE SINK 10 0.4 0.3 1 0.2 0.1 0.1 0 0.01 0.1 1 10 100 1k 0.75 1.25 1.75 2.25 2.75 3.00 LOAD CURRENT (mA) SUPPLY VOLTAGE (±V) Figure 5. Output Voltage to Supply Rail vs. Load Current Figure 8. Supply Current per Amplifier vs. Supply Voltage –2 10k V = 5V S V = 5V S T = 25°C A V = 2.5V CM –3 1k –4 100 –5 SINK SOURCE 10 –6 1 –7 –8 0.1 –50 –35 –15 5 25 45 65 85 0.01 0.1 1 10 100 1k LOAD CURRENT (mA) TEMPERATURE (°C) Figure 6. Output Voltage to Supply Rail vs. Load Current Figure 9. Input Offset Voltage vs. Temperature 0.90 8 V = 2.7V, 5V S V = V /2 CM S 0.85 7 0.80 6 0.75 V = 5V S 0.70 5 0.65 4 0.60 V = 2.7V S 3 0.55 2 0.50 –40 –20 0 20406080 100 –50 –35 –15 5 25 45 65 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Supply Current per Amplifier vs. Temperature Figure 10. Input Bias Current vs. Temperature Rev. B | Page 6 of 16 SUPPLY CURRENT/AMPLIFIER (mA) ΔOUTPUT VOLTAGE (mV) ΔOUTPUT VOLTAGE (mV) 01106-007 01106-006 01106-005 SUPPLY CURRENT/AMPLIFIER (mA) INPUT BIAS CURRENT (pA) INPUT OFFSET VOLTAGE (mV) 01106-010 01106-009 01106-008 AD8591/AD8592/AD8594 4 80 V = 5V S V = 2.7V, 5V S R = NO LOAD L V = V /2 CM S T = 25°C A 45 60 3 90 40 2 135 20 1 180 0 0 –1 –2 –50 –35 –15 5 25 45 65 85 1k 10k 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 11. Input Offset Current vs. Temperature Figure 14. Open-Loop Gain and Phase vs. Frequency 8 5 V = 2.7V V = 5V S S R = 2kΩ T = 25°C A L T = 25°C A 7 V = 2.5V p-p IN 4 6 3 5 4 2 3 1 2 1 0 0 1 234 5 1k 10k 100k 1M 10M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 12. Input Bias Current vs. Common-Mode Voltage Figure 15. Closed-Loop Output Voltage Swing vs. Frequency 80 5 V = 2.7V V = 5V S S R = NO LOAD R = 2kΩ L L T = 25°C T = 25°C A A 45 60 V = 2.5V p-p IN 4 90 40 3 135 20 180 0 2 1 0 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Open-Loop Gain and Phase vs. Frequency Figure 16. Closed-Loop Output Voltage Swing vs. Frequency Rev. B | Page 7 of 16 GAIN (dB) INPUT OFFSET CURRENT (pA) INPUT BIAS CURRENT (pA) PHASE SHIFT (Degrees) 01106-012 01106-011 01106-013 GAIN (dB) OUTPUT SWING (V p-p) OUTPUT SWING (V p-p) PHASE SHIFT (Degrees) 01106-017 01106-016 01106-014 AD8591/AD8592/AD8594 200 140 V = 5V V = 5V S S T = 25°C T = 25°C A A 180 120 A = 10 V 160 100 –PSRR 140 80 120 60 +PSRR 100 40 80 20 A = 1 V 60 0 40 –20 20 –40 0 –60 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Closed-Loop Output Impedance vs. Frequency Figure 20. Power Supply Rejection Ratio vs. Frequency 110 60 V = 5V S V = 2.5V S T = 25°C A R = 2kΩ L T = 25°C A 100 50 +OS –OS 90 40 80 30 70 20 60 10 50 0 1k 10k 100k 1M 10M 10 100 1k 10k FREQUENCY (Hz) CAPACITANCE (pF) Figure 18. Common-Mode Rejection Ratio vs. Frequency Figure 21. Small Signal Overshoot vs. Load Capacitance 140 60 V = 2.5V S V = 5V S T = 25°C A R = 2kΩ L 120 T = 25°C A 50 100 80 40 –OS 60 +PSRR +OS 40 30 –PSRR 20 20 0 –20 10 –40 –60 0 100 1k 10k 100k 1M 10M 10 100 1k 10k FREQUENCY (Hz) CAPACITANCE (pF) Figure 19. Power Supply Rejection Ratio vs. Frequency Figure 22. Small Signal Overshoot vs. Load Capacitance Rev. B | Page 8 of 16 PSRR (dB) CMRR (dB) IMPEDANCE (Ω) 01106-020 01106-019 01106-018 PSRR (dB) SMALL SIGNAL OVERSHOOT (%) SMALL SIGNAL OVERSHOOT (%) 01106-023 01106-022 01106-021 AD8591/AD8592/AD8594 V = ±2.5V S A = +1 V R = 2kΩ L 100 T = 25°C A 90 V = ±1.35V S 0V V = ±50mV IN A = +1 V R = 2kΩ L C = 300pF L T = 25°C A 10 0 500mV 500ns 500 ns/DIV Figure 23. Small Signal Transient Response Figure 26. Large Signal Transient Response 1V 10µs 100 90 V = ±2.5V S 0V V = ±50mV IN A = +1 V R = 2kΩ L C = 300pF L T = 25°C A 10 0 V = ±2.5V S A = +1 V T = +25°C 1V A 500 ns/DIV Figure 24. Small Signal Transient Response Figure 27. No Phase Reversal 1 V = 5V V = ±1.35V S S T = 25°C A = +1 A V R = 2kΩ L 100 T = 25°C A 90 0.1 10 0 500mV 500ns 0.01 10 100 1k 10k 100k FREQUENCY (Hz) Figure 25. Large Signal Transient Response Figure 28. Current Noise Density vs. Frequency Rev. B | Page 9 of 16 20mV/DIV 20mV/DIV 01106-026 01106-025 01106-024 CURRENT NOISE DENSITY (pA/√Hz) 01106-028 01106-027 01106-029 AD8591/AD8592/AD8594 600 V = 5V V = 2.7V S S V = 1.35V A = +1000 V CM T = 25°C T = 25°C A A 100 500 FREQUENCY = 1kHz 90 400 300 200 10 0 100 0 MARKER 41µV/√Hz –14 –12 –10 –8 –6 –4 –2 0 2 4 6 INPUT OFFSET VOLTAGE (mV) Figure 29. Voltage Noise Density vs. Frequency Figure 31. Input Offset Voltage Distribution 600 V = 5V S V = 5V S = +1000 A V = 2.5V V CM T = 25°C T = 25°C A A 100 500 FREQUENCY = 10kHz 90 400 300 200 10 0 100 0 MARKER 25.9µV/√Hz –14 –12 –10 –8 –6 –4 –2 0 2 4 6 INPUT OFFSET VOLTAGE (mV) Figure 30. Voltage Noise Density vs. Frequency Figure 32. Input Offset Voltage Distribution Rev. B | Page 10 of 16 200µV/DIV 100µV/DIV 01106-031 01106-030 QUANTITY (Amplifiers) QUANTITY (Amplifiers) 01106-033 01106-032 AD8591/AD8592/AD8594 THEORY OF OPERATION The AD859x amplifiers are CMOS, high output drive, rail-to- OUTPUT PHASE REVERSAL rail input and output single-supply amplifiers designed for low The AD8591/AD8592/AD8594 are immune to output voltage cost and high output current drive. The parts include a power phase reversal with an input voltage within the supply voltages saving shutdown function that makes the AD8591/AD8592/ of the device. However, if either of the inputs of the device exceeds AD8594 op amps ideal for portable multimedia and 0.6 V outside of the supply rails, the output could exhibit phase telecommunications applications. reversal. This is due to the ESD protection diodes becoming Figure 33 shows the simplified schematic for the AD8591/AD8592/ forward-biased, thus causing the polarity of the input terminals AD8594 amplifiers. Two input differential pairs, consisting of of the device to switch. an n-channel pair (M1, M2) and a p-channel pair (M3, M4), The technique recommended in the Input Voltage Protection provide a rail-to-rail input common-mode range. The outputs of section should be applied in applications where the possibility the input differential pairs are combined in a compound folded- of input voltages exceeding the supply voltages exists. cascode stage that drives the input to a second differential pair OUTPUT SHORT-CIRCUIT PROTECTION gain stage. The outputs of the second gain stage provide the gate voltage drive to the rail-to-rail output stage. To achieve high output current drive and rail-to-rail performance, the outputs of the AD859x family do not have internal short- The rail-to-rail output stage consists of M15 and M16, which circuit protection circuitry. Although these amplifiers are are configured in a complementary common source configuration. designed to sink or source as much as 250 mA of output current, As with any rail-to-rail output amplifier, the gain of the output shorting the output directly to the positive supply could damage or stage, and thus the open-loop gain of the amplifier, is dependent destroy the device. To protect the output stage, limit the maximum on the load resistance. In addition, the maximum output voltage output current to ±250 mA. swing is directly proportional to the load current. The difference between the maximum output voltage to the supply rails, known as By placing a resistor in series with the output of the amplifier, the dropout voltage, is determined by the on-channel resistance as shown in Figure 34, the output current can be limited. The of the AD8591/AD8592/AD8594 output transistors. The output minimum value for R is X dropout voltage is given in Figure 5 and Figure 6. V SY R ≥ (2) 100µA V+ X 250 mA * * * * 50µA 100µA For a 5 V single-supply application, R should be at least 20 Ω. X 20µA M11 Because RX is inside the feedback loop, VOUT is not affected. The INV M337 M5 M12 SD M30 trade-off in using RX is a slight reduction in output voltage M8 V B2 swing under heavy output current loads. RX also increases the M3 M1 M4 M15 effective output impedance of the amplifier to RO + RX, where RO IN– OUT is the output impedance of the device. M2 M6 M16 IN+ +5V V M9 B3 M14 R V X IN * 20µA 20Ω INV V AD8592 OUT M340 M13 * M7 M10 M31 50µA Figure 34. Output Short-Circuit Protection V– *ALL CURRENT SOURCES GO TO 0µA IN SHUTDOWN MODE. POWER DISSIPATION Figure 33. Simplified Schematic Although the AD859x amplifiers are able to provide load INPUT VOLTAGE PROTECTION currents of up to 250 mA, proper attention should be given to not exceeding the maximum junction temperature for the device. Although not shown in the simplified schematic, ESD protection The junction temperature equation is diodes are connected from each input to each power supply rail. These diodes are normally reverse-biased, but turn on if either TJ = PDISS × θJA + TA (3) input voltage exceeds either supply rail by more than 0.6 V. If this where: condition occurs, limit the input current to less than ±5 mA. TJ is the AD859x junction temperature. This is done by placing a resistor in series with the input(s). PDISS is the AD859x power dissipation. The minimum resistor value should be θ is the AD859x junction-to-ambient thermal resistance of the JA V package. IN ,MAX R ≥ (1) IN T is the ambient temperature of the circuit. 5 mA A Rev. B | Page 11 of 16 01106-034 01106-035 AD8591/AD8592/AD8594 In any application, the absolute maximum junction temperature 50mV must be limited to 150°C. If the junction temperature is exceeded, the device could suffer premature failure. If the output voltage 47nF LOAD ONLY and output current are in phase, for example, with a purely resistive load, the power dissipated by the AD859x can be found as PDISS = ILOAD × (VSY − VOUT) (4) where: I is the AD859x output load current. LOAD SNUBBER IN CIRCUIT V is the AD859x supply voltage. SY V is the output voltage. OUT 50mV 10µs By calculating the power dissipation of the device and using the thermal resistance value for a given package type, the maximum Figure 37. Snubber Network Reduces Overshoot and Ringing Caused by Driving Heavy Capacitive Loads allowable ambient temperature for an application can be found using Equation 3. The optimum values for the snubber network should be determined empirically based on the size of the capacitive load. CAPACITIVE LOADING Table 5 shows a few sample snubber network values for a given The AD859x exhibits excellent capacitive load driving capabilities load capacitance. and can drive to 10 nF directly. Although the device is stable with large capacitive loads, there is a decrease in amplifier Table 5. Snubber Networks for Large Capacitive Loads bandwidth as the capacitive load increases. Figure 35 shows Snubber Network a graph of the AD8592 unity-gain bandwidth under various Load Capacitance, C (nF) R (Ω) C (μF) L S S capacitive loads. 0.47 300 0.1 4.0 4.7 30 1 V = ±2.5V S R = 1kΩ L 47 5 1 3.5 T = 25°C A 3.0 PC98-COMPLIANT HEADPHONE/SPEAKER AMPLIFIER 2.5 Because of its high output current performance and shutdown 2.0 feature, the AD8592 makes an excellent amplifier for driving an 1.5 audio output jack in a computer application. Figure 38 shows how the AD8592 can be interfaced with an AC’97 codec to 1.0 drive headphones or speakers. 0.5 +5V 0 +5V 0.01 0.1 110 100 25 AV DD1 C1 CAPACITIVE LOAD (nF) R4 10 100µF AV 38 DD2 2 20Ω Figure 35. Unity-Gain Bandwidth vs. Capacitive Load U1-A 1 R2 NC 4 LINE_OUT_L 35 2kΩ When driving heavy capacitive loads directly from the AD859x 3 +5V 5 output, a snubber network can be used to improve the transient R1 AD1881A* 100kΩ response. This network consists of a series RC connected from (AC’97) the output of the amplifier to ground, placing it in parallel with the capacitive load. The configuration is shown in Figure 36. 6 C2 Although this network does not increase the bandwidth of the 36 LINE_OUT_R R5 100µF 7 20Ω amplifier, it significantly reduces the amount of overshoot, as U1-B AV 26 SS1 9 R3 shown in Figure 37. 2kΩ 8 +5V U1 = AD8592 *ADDITIONAL PINS OMITTED FOR CLARITY. V AD8592 OUT V R Figure 38. PC98-Compliant Headphone/Line Out Amplifier IN S 100mV p-p 5Ω C C S L 1µF 47nF Figure 36. Configuration for Snubber Network to Compensate for Capacitive Loads Rev. B | Page 12 of 16 BANDWIDTH (MHz) 01106-037 01106-036 01106-038 01106-039 AD8591/AD8592/AD8594 When headphones are plugged into the jack, the normalizing A COMBINED MICROPHONE AND SPEAKER contacts disconnect from the audio contacts. This allows the AMPLIFIER FOR CELLPHONE AND PORTABLE voltage to the AD8592 shutdown pins to be pulled to 5 V, HEADSETS activating the amplifiers. With no plug in the output jack, the The dual amplifiers in the AD8592 make an efficient design for shutdown voltage is pulled to 100 mV through the R1 and R3 + R5 interfacing with a headset containing a microphone and speaker. voltage divider. This powers the AD8592 down when it is not Figure 40 demonstrates a simple method for constructing an needed, saving current from the power supply or battery. interface to a codec. If gain is required from the output amplifier, add four additional R3 100kΩ +5V resistors, as shown in Figure 39. The gain of the AD8592 can C1 R1 be set as +5V R2 2.2kΩ 0.1µF 10kΩ 10 R7 2 NC TO A = (5) U1-A V CODEC 1 R6 4 3 +5V 5 R7 +5V 1kΩ R7 R8 MICROPHONE V AV 25 10kΩ REF DD1 100kΩ AND SPEAKER FROM CODEC JACK AV 38 DD2 +5V 6 C2 10µF C1 7 R4 LINE_OUT_L 35 10 R4 100µF U1-B 2 FROM CODEC 20Ω 9 10kΩ R6 MONO OUT U1-A 10kΩ 1 8 (OR LEFT OUT) R2 4 NC +5V U1 = AD8592 2kΩ (RIGHT OUT) 3 R5 R6 5 R1 10kΩ 10kΩ 100kΩ (OPTIONAL) VREF 27 Figure 40. Speaker/Microphone Headset Amplifier Circuit 6 C2 AD1881A* R5 100µF (AC’97) U1-A is used as a microphone preamplifier, where the gain of 7 20Ω R6 U1-B 10kΩ 9 the preamplifier is set as R3/R2. R1 is used to bias an electret R3 LINE_OUT_R 36 2kΩ 8 microphone, and C1 blocks any dc voltages from the amplifier. 26 AV SS1 U1-B is the speaker amplifier, and its gain is set at R5/R4. To R7 U1 = AD8592 10kΩ sum a stereo output, add R6, equal in value to R4. R7 Using the same principle described in the PC98-Compliant A = = 6dB WITH VALUES SHOWN V R6 Headphone/Speaker Amplifier section, the normalizing contact *ADDITIONAL PINS OMITTED FOR CLARITY. on the microphone/speaker jack can be used to put the AD8592 into shutdown when the headset is not plugged in. The AD8592 Figure 39. PC98-Compliant Headphone/Line Out Amplifier with Gain shutdown inputs can also be controlled with TTL- or CMOS- Input coupling capacitors are not required for either circuit compatible logic, allowing microphone or speaker muting, if because the reference voltage is supplied from the AD1881A. desired. R4 and R5 help protect the AD8592 output in case the output AN INEXPENSIVE SAMPLE-AND-HOLD CIRCUIT jack or headphone wires accidentally are shorted to ground. The The independent shutdown control of each amplifier in the output coupling capacitors, C1 and C2, block dc current from the AD8592 allows a degree of flexibility in circuit design. One headphones and create a high-pass filter with a corner frequency of particular application for which this feature is useful is in 1 designing a sample-and-hold circuit for data acquisition. Figure 41 f − 3dB= (6) 2πC1(R4+R) L shows a schematic of a simple, yet extremely effective, sample- and-hold circuit using a single AD8592 and one capacitor. where RL is the resistance of the headphones. 8 +5V SAMPLE 2 9 10 U1-B AND HOLD OUTPUT U1-A 6 +5V 1 7 4 C1 V IN 5 1nF 3 U1 = AD8592 SAMPLE CLOCK Figure 41. An Efficient Sample-and-Hold Circuit Rev. B | Page 13 of 16 01106-040 01106-042 01106-041 AD8591/AD8592/AD8594 The U1-A amplifier is configured as a unity-gain buffer driving SINGLE-SUPPLY DIFFERENTIAL LINE DRIVER a 1 nF capacitor. The input signal is connected to the noninverting Figure 43 shows a single-supply differential line driver circuit input, and the sample clock controls the shutdown for that that can drive a 600 Ω load with less than 0.7% distortion from amplifier. When the sample clock is high, the U1-A amplifier is 20 Hz to 15 kHz with an input signal of 4 V p-p and a single 5 V active and the output follows VIN. When the sample clock goes supply. The design uses an AD8594 to mimic the performance low, U1-A shuts down with the output of the amplifier going to of a fully balanced transformer-based solution. However, this a high impedance state, holding the voltage on the C1 capacitor. design occupies much less board space, while maintaining low The U1-B amplifier is used as a unity-gain buffer to prevent distortion, and can operate down to dc. Like the transformer-based loading on C1. Because of the low input bias current of the U1-B design, either output can be shorted to ground for unbalanced CMOS input stage and the high impedance state of the U1-A line driver applications without changing the circuit gain of 1. output in shutdown, there is little voltage droop from C1 during R3 10kΩ the hold period. This circuit can be used with sample frequencies as C3 2 R5 47µF 50Ω high as 500 kHz and as low as 1 Hz. By increasing the C1 value, 1 A2 V O1 3 lower voltage droop is achieved for very low sample rates. R6 10kΩ R2 DIRECT ACCESS ARRANGEMENT FOR PCMCIA 10kΩ R7 10kΩ +5V MODEMS (TELEPHONE LINE INTERFACE) +5V +5V 2 8 Figure 42 illustrates a 5 V transmit/receive telephone line C1 10 10 R8 1 22µF R 100kΩ A1 L A1 3 interface for 600 Ω systems. It allows full duplex transmission 7 600Ω 9 V 4 4 IN C2 of signals on a transformer-coupled 600 Ω line in a differential R9 1µF 100kΩ R1 R11 manner. Amplifier A1 provides gain that can be adjusted to 10kΩ R12 10kΩ 10kΩ meet the modem output drive requirements. Both A1 and A2 C4 R10 8 R14 47µF 10kΩ 50Ω are configured to apply the largest possible signal on a single 9 A2 V O2 7 A1, A2 = 1/2 AD8592 supply to the transformer. Because of the high output current R13 R3 10kΩ GAIN = R2 drive and low dropout voltages of the AD8594, the largest signal SET: R7, R10, R11 = R2 available on a single 5 V supply is approximately 4.5 V p-p into SET: R6, R12, R13 = R3 a 600 Ω transmission system. Amplifier A3 is configured as a Figure 43. Low Noise, Single-Supply Differential Line Driver difference amplifier for two reasons. It prevents the transmit R8 and R9 set up the common-mode output voltage equal to signal from interfering with the receive signal, and it extracts half of the supply voltage. C1 is used to couple the input signal the receive signal from the transmission line for amplification and can be omitted if the dc voltage of the input is equal to half by A4. The gain of A4 can be adjusted in the same manner as of the supply voltage. the gain of A1 to meet the input signal requirements of the The circuit can also be configured to provide additional gain, if modem. Standard resistor values permit the use of single desired. The gain of the circuit is inline package (SIP) format resistor arrays. Couple this with the 16-lead TSSOP or SOIC footprint of the AD8594, and this V R3 OUT A = = (7) circuit offers a compact, cost-effective solution. V V R2 IN P1 Tx GAIN where: ADJUST R2 9.09kΩ VOUT = VO1 − VO2 C1 TRANSMIT R1 TO TELEPHONE 2kΩ 0.1µF TxA 10kΩ R2 = R7 = R10 = R11 R3 LINE 2 360Ω 1 1:1 A1 R3 = R6 = R12 = R1 3 R5 9 6.2V Z SHUTDOWN O 10kΩ 600Ω 6.2V +5V T1 R6 9 6 MIDCOM 10kΩ R7 7 671-8005 10kΩ A2 5 R8 10µF 10kΩ R9 R10 10kΩ 10kΩ P2 Rx GAIN ADJUST 9 RECEIVE 11 R13 R14 10kΩ 14.3kΩ RxA R11 10 A3 10kΩ 12 2kΩ 15 9 C2 R12 16 0.1µF A4 10kΩ 14 A1, A2 = 1/4 AD8594 A3, A4 = 1/4 AD8594 Figure 42. Single-Supply Direct Access Arrangement for PCMCIA Modems Rev. B | Page 14 of 16 01106-043 01106-044 AD8591/AD8592/AD8594 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 2.80 BSC 1.60 BSC 1 2 3 PIN 1 INDICATOR 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 10° 0.60 0.50 0.15 MAX 4° 0.45 SEATING 0.30 0° 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 44. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.33 0.60 SEATING 0.23 0° 0.05 0.17 PLANE 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 10.00 (0.3937) 9.80 (0.3858) 9 16 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 8 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 8° 1.35 (0.0531) 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 0.25 (0.0098) PLANE 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 46. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. B | Page 15 of 16 060606-A AD8591/AD8592/AD8594 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8591ART-REEL −40°C to +85°C 6-Lead SOT-23 RJ-6 A9A AD8591ART-REEL7 −40°C to +85°C 6-Lead SOT-23 RJ-6 A9A 1 AD8591ARTZ-REEL −40°C to +85°C 6-Lead SOT-23 RJ-6 A9A# 1 AD8591ARTZ-REEL7 −40°C to +85°C 6-Lead SOT-23 RJ-6 A9A# AD8592ARM-REEL −40°C to +85°C 10-Lead MSOP RM-10 AQA 1 AD8592ARMZ-REEL −40°C to +85°C 10-Lead MSOP RM-10 AQA# AD8594AR −40°C to +85°C 16-Lead SOIC_N R-16 AD8594AR-REEL −40°C to +85°C 16-Lead SOIC_N R-16 AD8594AR-REEL7 −40°C to +85°C 16-Lead SOIC_N R-16 1 AD8594ARZ −40°C to +85°C 16-Lead SOIC_N R-16 1 AD8594ARZ-REEL −40°C to +85°C 16-Lead SOIC_N R-16 1 AD8594ARZ-REEL7 −40°C to +85°C 16-Lead SOIC_N R-16 AD8594ARU-REEL −40°C to +85°C 16-Lead TSSOP RU-16 1 AD8594ARUZ-REEL −40°C to +85°C 16-Lead TSSOP RU-16 1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01106-0-1/09(B) Rev. B | Page 16 of 16