ANALOG DEVICES AD8582

+5 Volt, Parallel Input a Complete Dual 12-Bit DAC AD8582 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete Dual 12-Bit DAC No External Components AD8582 V DD 12 Single +5 Volt Operation 12-BIT DAC A LDA V OUTA DAC A 1 mV/Bit with 4.095 V Full Scale REGISTER True Voltage Output, ±5 mA Drive INPUT A CS Very Low Power: 5 mW REGISTER A/B APPLICATIONS 12 2 DATA REFERENCE V REF Digitally Controlled Calibration Portable Equipment INPUT B REGISTER Servo Controls Process Control Equipment 12 DAC B 12-BIT LDB PC Peripherals REGISTER V OUTB DAC B AGND MSB DGND RST GENERAL DESCRIPTION The high speed parallel data interface connects to the fastest The AD8582 is a complete, parallel input, dual 12-bit, voltage processors without wait states. The double-buffered input struc- output DAC designed to operate from a single +5 volt supply. ture allows the user to load the input registers one at a time, Built using a CBCMOS process, this monolithic DAC offers the then a single load strobe tied to both LDA + LDB inputs will user low cost, and ease-of-use in +5 volt only systems. update both DAC outputs simultaneously. LDA and LDB can also be activated independently to immediately update their re- Included on the chip, in addition to the DACs, are a rail-to-rail spective DAC registers. An address input decodes DAC A or amplifier, latch and reference. The reference (V ) is trimmed REF DAC B when the chip select CS input is strobed. An asynchro- to 2.5 volts output, and the on-chip amplifier gains up the DAC nous reset input sets the output to zero scale. The MSB bit can output to 4.095 volts full scale. The user needs only supply a +5 be used to establish a preset to midscale when the reset input is volt supply. strobed. The AD8582 is coded natural binary. The op amp output The AD8582 is available in the 24-pin plastic DIP and the sur- swings from 0 volt to +4.095 volts for a one-millivolt-per-bit face mount SOIC-24. Each part is fully specified for operation resolution, and is capable of driving ±5 mA. Operation down to over –40°C to +85°C, and the full +5 V ± 5% power supply 4.3 V is possible with output load currents less than 1 mA. range. 5.0 2.0 ΔΔVFS ≤ 1 LSB DATA = FFF H 1.5 V = +5V T = +25°C DD 4.8 A T = –55°C, +25°C, +85°C A 1.0 4.6 0.5 PROPER OPERATION WHEN V SUPPLY 0.0 DD 4.4 VOLTAGE ABOVE –0.5 CURVE 4.2 –1.0 = +25°C & +85°C = –55°C –1.5 4.0 –2.0 0.01 0.1 1.0 10 100 0 1024 2048 3072 4096 OUTPUT LOAD CURRENT – mA DIGITAL INPUT CODE – Decimal Figure 1. Minimum Supply Voltage vs. Load Figure 2. Linearity Error vs. Digital Code and Temperature REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 V MIN – Volts DD LINEARITY ERROR – LSB AD8582–SPECIFICATIONS (@ V = +5.0 V ± 5%, R = No Load, –40°C ≤ T ≤ +85°C, unless otherwise noted) DD L A ELECTRICAL CHARACTERISTICS Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N Note 1 12 Bits Relative Accuracy INL –2 ±3/4 +2 LSB Differential Nonlinearity DNL Monotonic –1 ±3/4 +1 LSB Zero-Scale Error V Data = 000 +0.2 +3 mV ZSE H 2 Full-Scale Voltage V Data = FFF , 4.079 4.095 4.111 V FS H Full-Scale Tempco TCV Notes 2 and 3 ±16 ppm/°C FS MATCHING PERFORMANCE Linearity Matching Error ΔV A/B ±1 LSB FS REFERENCE OUTPUT Output Voltage V 2.484 2.500 2.516 V REF Output Source Current I Note 4 –5 mA REF Line Rejection LN 0.08 %/V REJ Load Regulation LD I = 0 mA to 5 mA 0.1 %/mA REG REF ANALOG OUTPUT Output Current I Data = 800 ±5mA OUT H Load Regulation at Half Scale LD R = 402 Ω to ∞, Data = 800 1 3 LSB REG L H 3 Capacitive Load C No Oscillation 500 pF L 3 DYNAMIC CHARACTERISTICS Crosstalk C >64 dB T 5 Voltage Output Settling Time t To ±1 LSB of Final Value 16 μs S Digital Feedthrough F Signal Measured at DAC Output, While 35 nV s T Changing Data (LDA = LDB = “1”) LOGIC INPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 10 μA IL Input Capacitance C Note 3 10 pF IL 3, 6 TIMING SPECIFICATIONS Chip Select Pulse Width t 30 ns CSW DAC Select Setup t 30 ns AS DAC Select Hold t 0ns AH Data Setup t 30 ns DS Data Hold t 10 ns DH Load Setup t 20 ns LS Load Hold t 10 ns LH Load Pulse Width t 20 ns LDW Reset Pulse Width t 30 ns RSW SUPPLY CHARACTERISTICS Positive Supply Current I V = 2.4 V, V = 0.8 V 4 7 mA DD IH IL V = 0 V, V = +5 V 1 2 mA IL DD 7 Power Dissipation P V = 2.4 V, V = 0.8 V 20 35 mW DISS IH IL V = 0 V, V = +5 V 5 10 mW IL DD Power Supply Sensitivity PSS ΔV = ±5% 0.002 0.004 %/% DD NOTES 1 1 LSB = 1 mV for 0 V to +4.095 V output range. 2 Includes internal voltage reference error. 3 These parameters are guaranteed by design and not subject to production testing. 4 Very little sink current is available at the V pin. Use external buffer if setting up a virtual ground. REF 5 Settling time is not guaranteed for the first six codes 0 through 5. 6 All input control signals are specified with t = t = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. R F 7 Power dissipation is a calculated value I × 5 V. DD Specifications subject to change without notice. REV. 0 –2– AD8582 PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS* V to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V DD Pin No. Name Description Logic Inputs to DGND . . . . . . . . . . . . . . .–0.3 V, V + 0.3 V DD V to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V + 0.3 V OUT DD 1, 24 V Voltage outputs from the DACs. Fixed OUTA V to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V + 0.3 V REF DD V output voltage range of 0 V to 4.095 V OUTB AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V DD with 1 mV/LSB. An internal I Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA OUT temperature stabilized reference Package Power Dissipation . . . . . . . . . . . . . . .(T max–T )/θ J A JA maintains a fixed full-scale voltage Thermal Resistance, θ JA independent of time, temperature and 24-Pin Plastic DIP Package (N-24) . . . . . . . . . . . . . 62°C/W power supply variations. 24-Lead SOIC Package (SOL-24) . . . . . . . . . . . . . . 73°C/W 2 AGND Analog Ground. Ground reference for Maximum Junction Temperature (T max) . . . . . . . . . . 150°C J the internal bandgap reference voltage, Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C the DAC, and the output buffer. Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C 3 DGND Digital ground for input logic. Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C 4, 21 LDA, Load DAC register strobes. Transfers *Stresses above those listed under “Absolute Maximum Ratings” may cause LDB input register data to the DAC registers. permanent damage to the device. This is a stress rating only and functional Active low inputs, Level sensitive latch. operation of the device at these or any other conditions above those indicated in the May be connected together to double- operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. buffer load DAC registers. 5 MSB Digital Input: High presets DAC t CSW registers to half scale (800 ), Low H CS clears DAC registers to zero (000 ) H t AH t upon RST assertion. AS 6 RST Active low digital input that clears the A/B t DAC register to zero, setting the DAC DH t DS to minimum scale when MSB pin = 0, D0–D11 or half-scale when MSB pin = 1. t LDW t LH t 7–18 DB Twelve Binary Data Bit Inputs. DB11 is LS 0–11 LDA, LDB the MSB and DB0 is the LSB. t RSW 19 CS Chip Select. Active low input. RST 20 A/B Select DAC A = 0 or DAC B = 1. t t S S ± 1LSB 22 V Positive Supply. Nominal value +5 V, ±5%. ERROR BAND V DD OUT 23 V Nominal 2.5 V reference output REF voltage. This node must be buffered if required to drive external loads. Timing Diagram PIN CONFIGURATIONS N-24 ORDERING INFORMATION* SOL-24 24-Pin Plastic DIP 24-Pin SOIC Temperature Package Package 1 24 Model Range Description Option V 1 24 V OUTA OUTB AGND 2 23 V AD8582AN –40°C to +85°C 24-Pin Plastic DIP N-24 REF AD8582AR –40°C to +85°C 24-Lead SOIC SOL-24 DGND 3 22 V DD AD8582 AD8582Chips +25°C Die 4 21 LDB LDA TOP VIEW (Not to Scale) MSB 5 20 A/B *For die specifications contact your local Analog Devices sales office. The AD8582 AD8582 contains 1270 transistors. RST 6 19 CS TOP VIEW DB0 7 18 DB11 (Not to Scale) 12 13 DB1 DB10 8 17 DB2 9 16 DB9 DB3 10 15 DB8 DB4 14 DB7 11 13 DB5 12 DB6 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. WARNING! Although the AD8582 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– AD8582 Table I. Control Logic Truth Table CS A/B LDA LDB RST MSB Input Register DAC Register L L HHHX Write to A Latched L HHHHX Write to B Latched LLL H H X Write to A A Transparent L H H L H X Write to B B Transparent H X L L H X Latched A & B Transparent H X ^ ^ H X Latched Latched XXXXL L Reset to Zero Scale Reset to Zero Scale XXXXL H Reset to Midscale Reset to Midscale H XXX^ X Latch Reset Value Latch Reset Value ^Denotes positive edge triggered. OPERATION V VOLTAGE SWITCHED 12-BIT REF RAIL-TO-RAIL BANDGAP 2.5V R-2R D/A CONVERTER OUTPUT The AD8582 is a complete, ready-to-use dual 12-bit digital-to- REFERENCE AMPLIFIER 2R analog converter. Only one +5 V power supply is necessary for operation. It contains two voltage-switched, 12-bit, laser- V OUT R trimmed digital-to-analog converters, a curvature-corrected BUFFER R2 2R bandgap reference, rail-to-rail output op amps, input registers, and DAC registers. The parallel data interface consists of twelve R1 R data bits, DB0–DB11, an address select pin A/B, two load 2R AV = 4.095/2.5 strobe pins (LDA, LDB) and an active low CS strobe. In addi- = 1.638V/V tion an asynchronous RST pin will set all DAC register bits to zero causing the V to become zero volts, or to midscale for OUT 2R trimming applications when the MSB pin is programmed to SPDT N CH FET Logic 1. This function is useful for power on reset or system 2R SWITCHES failure recovery to a known state. D/A CONVERTER SECTION Figure 3. Equivalent Schematic of Analog Portion The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 volt in- OUTPUT SECTION ternal bandgap voltage. It uses a laser trimmed R-2R The rail-to-rail output stage of this amplifier has been designed ladder which is switched by N channel MOSFETs. The out- to provide precision performance while operating near either put voltage of the DAC has a constant resistance independent power supply. Figure 4 shows an equivalent output schematic of of digital input code. The DAC output (not available to the the rail-to-rail amplifier with its N channel pull-down FETs that user) is internally connected to the rail-to-rail output op amp. will pull an output load directly to GND. The output sourcing current is provided by a P channel pull-up device that can sup- AMPLIFIER SECTION ply GND terminated loads, especially important at the –5% The internal DAC’s output is buffered by a low power con- supply tolerance value of 4.75 volts. sumption precision amplifier. This low power amplifier contains V DD a differential PNP pair input stage which provides low offset P-CH voltage and low noise, as well as the ability to amplify the zero- scale DAC output voltages. The rail-to-rail amplifier is config- ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the V 4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an OUT N-CH equivalent circuit schematic of the analog section. The op amp has a 16 μs typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals AGND versus positive. See the oscilloscope photos in the Typical Per- formances section of this data sheet. Figure 4. Equivalent Analog Output Circuit REV. 0 –4– AD8582 Figures 5 and 6 in the typical performance characteristics sec- One advantage of the rail-to-rail output amplifiers used in the tion provide information on output swing performance near AD8582 is the wide range of usable supply voltage. The part is ground and full-scale as a function of load. In addition to resis- fully specified and tested over temperature for operation from tive load driving capability, the amplifier has also been carefully +4.75 V to +5.25 V. If reduced linearity and source current designed and characterized for up to 500 pF capacitive load capability near full scale can be tolerated, operation of the driving capability. AD8582 is possible down to +4.3 volts. The minimum operat- ing supply voltage versus load current plot, in Figure 1, pro- REFERENCE SECTION vides information for operation below V = +4.75 V. DD The internal 2.5 V curvature-corrected bandgap voltage refer- ence is laser trimmed for both initial accuracy and low tempera- TIMING AND CONTROL ture coefficient. The voltage generated by the reference is The input registers are level triggered and acquire data from the available at the V pin. Since V is not intended to drive ex- REF REF data bus during the time period when CS is low. The input reg- ternal loads, it must be buffered. The equivalent emitter fol- ister selected is determined by the A/B select pin, see Table I. lower output circuit of the V pin is shown in Figure 3. REF for a complete description. When CS goes high, the data is latched into the register and held until CS returns low. The Bypassing the V pin will improve noise performance; how- REF minimum time required for the data to be present on the bus ever, bypassing is not required for proper operation. Figure 8 before CS returns high is called the data setup time (t ) as seen DS shows broadband noise performance. in Timing Diagram. The data hold time (t ) is the amount DH of time that the data has to remain on the bus after CS goes POWER SUPPLY high. The high speed timing offered by the AD8582 provides The very low power consumption of the AD8582 is a direct re- for direct interface with no wait states in all but the fastest sult of a circuit design optimizing use of the CBCMOS process. microprocessors. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary The data from the input registers is transferred to the DAC reg- bipolar transistors good analog accuracy is achieved. isters by the active low LDA and LDB pins. If these inputs are tied together, a single logic input can perform a double buffer For power-consumption sensitive applications it is important to update of the DAC registers, which in turn simultaneously note that the internal power consumption of the AD8582 is changes the analog output voltages to a new value. If the LDA strongly dependent on the actual logic-input voltage levels and LDB pins are wired low, they become transparent. In this present on the DB0–DB11, CS, A/B, MSB, LDA, LDB and mode the input register data will directly control the output RST pins. Since these inputs are standard CMOS logic struc- voltages. Refer to the Control Logic Truth Table for a com- tures they contribute static power dissipation dependent on the plete description. actual driving logic V and V voltage levels. The graph in OH OL Figure 9 shows the effect on total AD8582 supply current as a Unipolar Output Operation function of the actual value of input logic voltage. Conse- This is the basic mode of operation for the AD8582. The quently, for optimum dissipation use of CMOS logic versus AD8582 has been designed to drive loads as low as 820Ω in par- TTL provides minimal dissipation in the static state. A V = INL allel with 500 pF. The code table for this operation is shown in 0 V on the DB0–11 pins provides the lowest standby dissipation Table II. of 1 mA typical with a +5 V power supply. As with any analog system, it is recommended that the AD8582 Table II. Unipolar Code Table power supply be bypassed on the same PC card that contains the chip. Figure 10 shows the power supply rejection versus fre- Hexadecimal quency performance. This should be taken into account when Number in DAC Decimal Number Analog Output using higher frequency switched-mode power supplies with Register in DAC Register Voltage (V) ripple frequencies of 100 kHz and higher. FFF 4095 + 4.095 801 2049 + 2.049 800 2048 + 2.048 7FF 2047 + 2.047 000 0 0 REV. 0 –5– AD8582–Typical Performance Characteristics 80 100 5 V = +5V DD V = +5V POSITIVE0 DD T = +25°C 60 A CURRENT0 DATA = 000 H LIMIT0 4 10 40 R TIED TO AGND L DATA = FFF H 20 3 DATA = 800 H 0 1 R TIED TO +2V L 2 T = +85°C –20 A T = –40°C A –40 0.1 R TIED TO +5V L 1 NEGATIVE DATA = 000 H –60 CURRENT T = +25°C LIMIT A 0 0.01 –80 1 10 100 1000 1 2 3 10 100 1k 10k 100k OUTPUT VOLTAGE – Volts LOAD RESISTANCE – Ω OUTPUT SINK CURRENT – µA Figure 5. Output Swing vs. Load Figure 6. Pull-Down Voltage vs. Figure 7. I vs. V OUT OUT Output Sink Current Capability 5 100 V = +5V ±200mV AC DD T = +25°C T = +25°C A A T = +25°C 80 A 4 NBW = 630kHz V = +4.75V DATA = FFF DD H V = +5V DD 3 60 40 2 20 1 0 0 0124 3 5 TIME = 100µs/DIV 10 100 1k 10k 100k FREQUENCY – Hz LOGIC VOLTAGE VALUE – Volts Figure 8. Broadband Noise Figure 9. Supply Current vs. Logic Figure 10. Power Supply Rejection Input Voltage vs. Frequency 5 5V 5 5 0 100 LDB 90 0 0 2048 TO 2047 15µs 10 10 4 V = +5V DD 2.048 3 T = +25°C A 2.038 2 V = +5V DD 10 T = +25°C 1 A 2.028 0% 0 2.018 1V 20µs 2.008 TIME = 20µs/DIV TIME – 500ns/DIV TIME – 5µs/DIV Figure 13. Output Voltage Rise Figure 11. Midscale Transition Figure 12. Large Signal Settling Time Time Detail Performance REV. 0 –6– V – Volts OUT OUTPUT VOLTAGE – Volts LD OUTPUT NOISE VOLTAGE – 200µV/DIV OUTPUT INPUT OUTPUT PULL-DOWN VOLTAGE – mV SUPPLY CURRENT – mA OUTPUT CURRENT – mA POWER SUPPLY REJECTION – dB OUTPUT VOLTAGE DATA 1mV/DIV AD8582 45 4.115 TUE = ΣINL+ZS+FS V = +5V DD 40 V = +4.75V 4.110 SS = 297 UNITS DD T = +25°C A NO LOAD 5 V = +4.75V DD 35 4.105 SS = 298 UNITS T = +25°C A 0 30 4.100 σAVG +1σ 25 4.095 20 15µs 4.090 15 4.085 10 AVG σAVG –1σ 4.080 5 4.075 0 –8 –7 –6 –5 –4 –3 –2 –1 0 1 TIME – 5µs/DIV –50 –25 0 25 50 75 100 125 TOTAL UNADJUSTED ERROR – mV TEMPERATURE – °C Figure 14. Output Voltage Fall Figure 15. Total Unadjusted Error Figure 16. Full-Scale Voltage vs. Time Detail Histogram Temperature 3 100 3 V = +5V DD V = +5V V = +4.75V DD DD SS = 135 UNITS 2 T = +25°C NO LOAD DATA = FFF A H DATA = FFF 2 SS = 298 UNITS H 10 1 σAVG +2σ 1 0 AVG –1 1.0 0 –2 σAVG –2σ 0.1 –3 –1 0 100 200 300 400 500 600 –50 –25 0 25 50 75 100 125 10 100 1k 10k 100k TEMPERATURE – °C HOURS OF OPERATION AT +150°C FREQUENCY – Hz Figure 17. Zero-Scale Voltage vs. Figure 18. Output Voltage Noise Figure 19. Long-Term Drift Temperature Density vs. Frequency Accelerated by Burn-In 8 V = +2.4V DATA 5V 5µs 2V 1µs 7 NO LOAD 1 CS = HIGH 100 100 6 90 90 0 V = +5.25V ∞T = +25°C DD V A DD 5 R = ∞ L V = +5.00V DD V = +5V DD 0V 4 V REF 3 10 10 0V V = +4.75V DD 0% 2 0% 10mV 2V 1 TIME – 5µs/DIV 0 TIME – 1µs/DIV –50 –25 0 25 50 75 100 125 TEMPERATURE – °C Figure 20. Supply Current vs. Figure 21. Reference Startup vs. Figure 22. Digital Feedthrough vs. Temperature Time Time REV. 0 –7– ZERO-SCALE OUTPUT – Volts SUPPLY CURRENT – mA OUTPUT VOLTAGE DATA 1mV/DIV FREQUENCY OUTPUT NOISE DENSITY – µV/ Hz V OUT FULL-SCALE OUTPUT – Volts DATA NOMINAL FULL-SCALE 10mV/DIV VOLTAGE CHANGE – mV AD8582 0.10 10 0.000 V = +4.75V 8 Δ V = +4.75 TO +5.25V DD DD ΔV = +4.75V DD –0.001 6 0.08 ΔI = 5mA L 4 σAVG +1σ AVG 2 –0.002 0.06 σAVG +1σ σAVG +1σ 0 AVG AVG –2 –0.003 0.04 –4 –0.004 –6 0.02 σAVG –1σ σAVG –1σσAVG – 1σ –8 –10 –0.005 0.00 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE – °C TEMPERATURE – °C TEMPERATURE – °C Figure 23. Reference Error vs. Figure 24. Reference Load Regulation Figure 25. Reference Line Regulation Temperature vs. Temperature vs. Temperature OUTLINE DIMENSIONS Dimensions shown in inches and (mm). N-24 24-Pin Narrow Body Plastic DIP 13 24 0.280 (7.11) PIN 1 0.240 (6.10) 1 12 1.275 (32.30) 0.325 (8.25) 1.125 (28.60) 0.300 (7.62) 0.060 (1.52) 0.210 0.195 (4.95) 0.015 (0.38) (5.33) 0.115 (2.93) MAX 0.150 0.200 (5.05) (3.81) MIN 0.125 (3.18) 0.015 (0.381) 0.022 (0.558) 0.008 (0.204) 0.100 (2.54) 0.070 (1.77) SEATING 0.014 (0.356) BSC PLANE 0.045 (1.15) SOL-24 24-Lead Wide Body SOIC 13 24 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) PIN 1 0.3937 (10.00) 1 12 0.1043 (2.65) 0.6141 (15.60) 0.0926 (2.35) 0.5985 (15.20) 0.0291 (0.74) x 45° 0.0098 (0.25) 0.0500 (1.27) 8° 0° 0.0157 (0.40) 0.0118 (0.30) 0.0500 (1.27) 0.0192 (0.49) 0.0125 (0.32) BSC 0.0040 (0.10) 0.0138 (0.35) 0.0091 (0.23) REV. 0 –8– REFERENCE ERROR – mV REF LOAD REGULATION – %/mA REF LINE REGULATION – %/Volt PRINTED IN U.S.A. C1869–18–12/93