ANALOG DEVICES AD8571

Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers AD8571/AD8572/AD8574 FEATURES PIN CONFIGURATIONS Low offset voltage: 1 μV 1 8 NC NC AD8571 Input offset drift: 0.005 μV/°C –IN A 2 7 V+ TOP VIEW +IN A 3 6 OUT A Rail-to-rail input and output swing (Not to Scale) V– 4 5 NC 5 V/2.7 V single-supply operation High gain: 145 dB typical NC = NO CONNECT CMRR: 140 dB typical Figure 1. 8-Lead MSOP (RM Suffix) PSRR: 130 dB typical NC 1 8 NC Ultralow input bias current: 10 pA typical –IN A 2 7 V+ AD8571 Low supply current: 750 μA per op amp +IN A 3 6 OUT A TOP VIEW (Not to Scale) Overload recovery time: 50 μs V– 4 5 NC No external capacitors required NC = NO CONNECT Figure 2. 8-Lead SOIC (R Suffix) APPLICATIONS OUT A 1 8 V+ Temperature sensors AD8572 –IN A 2 7 OUT B TOP VIEW Pressure sensors +IN A 3 6 –IN B (Not to Scale) Precision current sensing V– 4 5 +IN B Strain gage amplifiers Figure 3. 8-Lead TSSOP (RU Suffix) Medical instrumentation OUT A 1 8 V+ Thermocouple amplifiers AD8572 2 7 –IN A OUT B TOP VIEW +IN A 3 6 –IN B (Not to Scale) V– 4 5 +IN B GENERAL DESCRIPTION Figure 4. 8-Lead SOIC (R Suffix) This family of amplifiers has ultralow offset, drift, and bias OUT A 1 14 OUT D current. The AD8571, AD8572, and AD8574 are single, dual, –IN A 2 13 –IN D and quad amplifiers, respectively, featuring rail-to-rail input +IN A 3 12 +IN D AD8574 and output swings. All are guaranteed to operate from 2.7 V to V+ 4 11 V– TOP VIEW 5 V single supply. (Not to Scale) +IN B 5 10 +IN C –IN B 6 9 –IN C The AD857x family provides benefits previously found only in OUT B 7 8 OUT C expensive auto-zeroing or chopper-stabilized amplifiers. Using Figure 5. 14-Lead TSSOP (RU Suffix) Analog Devices, Inc., topology, these zero-drift amplifiers combine low cost with high accuracy. (No external capacitors OUT A 1 14 OUT D are required.) Using a patented spread-spectrum, auto-zero –IN A 2 13 –IN D technique, the AD857x family eliminates the intermodulation +IN A 3 12 +IN D AD8574 V+ 4 11 V– effects from interaction of the chopping function with the TOP VIEW (Not to Scale) +IN B 5 10 +IN C signal frequency in ac applications. –IN B 6 9 –IN C OUT B 7 8 OUT C With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the AD857x family is perfectly suited for applications where error Figure 6. 14-Lead SOIC (R Suffix) sources cannot be tolerated. Position and pressure sensors, The AD857x family is specified for the extended industrial/ medical equipment, and strain gage amplifiers benefit greatly automotive temperature range (−40°C to +125°C). The AD8571 from nearly zero drift over their operating temperature range. single amplifier is available in 8-lead MSOP and narrow SOIC Many more systems require the rail-to-rail input and output packages. The AD8572 dual amplifier is available in 8-lead narrow swings provided by the AD857x family. SOIC and surface-mount TSSOP packages. The AD8574 quad amplifier is available in 14-lead narrow SOIC and TSSOP packages. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1999–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01104-004 01104-001 01104-006 01104-003 01104-002 01104-005 AD8571/AD8572/AD8574 TABLE OF CONTENTS Features .............................................................................................. 1 Maximizing Performance Through Proper Layout............... 16 Applications....................................................................................... 1 1/f Noise Characteristics ........................................................... 17 General Description ......................................................................... 1 Random Auto-Zero Correction Eliminates Intermodulation Distortion .................................................................................... 17 Pin Configurations ........................................................................... 1 Broadband and External Resistor Noise Considerations.......... 18 Revision History ............................................................................... 2 Output Overdrive Recovery...................................................... 18 Specifications..................................................................................... 3 Input Overvoltage Protection ................................................... 18 5 V Electrical Characteristics...................................................... 3 Output Phase Reversal............................................................... 18 2.7 V Electrical Characteristics................................................... 4 Capacitive Load Drive ............................................................... 19 Absolute Maximum Ratings............................................................ 5 Power-Up Behavior.................................................................... 19 Thermal Characteristics .............................................................. 5 Applications Information .............................................................. 20 ESD Caution.................................................................................. 5 5 V Precision Strain Gage Circuit ............................................ 20 Typical Performance Characteristics ............................................. 6 3 V Instrumentation Amplifier ................................................ 20 Functional Description .................................................................. 14 High Accuracy Thermocouple Amplifier............................... 21 Amplifier Architecture .............................................................. 14 Precision Current Meter............................................................ 21 Basic Auto-Zero Amplifier Theory.......................................... 14 Precision Voltage Comparator.................................................. 21 Auto-Zero Phase......................................................................... 15 Outline Dimensions....................................................................... 22 Amplification Phase................................................................... 15 Ordering Guide .......................................................................... 23 High Gain, CMRR, and PSRR .................................................. 16 REVISION HISTORY 9/06—Rev. A to Rev. B 2/11—Rev. D to Rev. E Updated Format..................................................................Universal Changes to Figure 66...................................................................... 21 Changes to Table 1.............................................................................3 Updated Outline Dimensions ....................................................... 22 Changes to Table 2.............................................................................4 Changes to Ordering Guide .......................................................... 23 Changes to Figure 50...................................................................... 14 6/08—Rev. C to Rev. D Changes to Figure 51...................................................................... 15 Changes to Figure 19 and Figure 20............................................... 8 Changes to Figure 66...................................................................... 21 Changes to Figure 44...................................................................... 12 Deleted Figure 69 and SPICE Macro-Model Section ................ 17 Changes to Figure 38...................................................................... 13 Deleted SPICE Macro-Model for the AD857x Section............. 18 Moved Figure 50 and Figure 51 .................................................... 14 Updated Outline Dimensions....................................................... 22 Changes to Figure 66, Precision Current Meter Section, Layout, Changes to Ordering Guide .......................................................... 23 Figure 67, Equation 24, and Figure 68......................................... 21 7/03—Rev. 0 to Rev. A 5/07—Rev. B to Rev. C Renumbered Figures ..........................................................Universal Changes to Features.......................................................................... 1 Changes to Ordering Guide .............................................................4 Changes to Table 1............................................................................ 3 Change to Figure 15. ...................................................................... 16 Changes to Table 2............................................................................ 4 Updated Outline Dimensions....................................................... 19 Changes to Basic Auto-Zero Amplifier Theory Section ........... 14 10/99—Revision 0: Initial Version Changes to Figure 50...................................................................... 15 Changes to Figure 55...................................................................... 16 Changes to Figure 66...................................................................... 21 Updated Outline Dimensions ....................................................... 22 Rev. E | Page 2 of 24 AD8571/AD8572/AD8574 SPECIFICATIONS 5 V ELECTRICAL CHARACTERISTICS V = 5 V, V = 2.5 V, V = 2.5 V, T = 25°C, unless otherwise noted. S CM O A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 1 5 μV −40°C ≤ T ≤ +125°C 10 μV A Input Bias Current I 10 50 pA B AD8571/AD8574 −40°C ≤ TA ≤ +125°C 1.0 1.5 nA AD8572 −40°C ≤ TA ≤ +85°C 160 300 pA −40°C ≤ TA ≤ +125°C 2.5 4 nA Input Offset Current I 20 70 pA OS AD8571/AD8574 −40°C ≤ T ≤ +125°C 150 200 pA A AD8572 −40°C ≤ T ≤ +85°C 30 150 pA A −40°C ≤ TA ≤ +125°C 150 400 pA Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 120 140 dB −40°C ≤ T ≤ +125°C 115 130 dB A 1 Large Signal Voltage Gain A R = 10 kΩ, V = 0.3 V to 4.7 V 125 145 dB VO L O −40°C ≤ TA ≤ +125°C 120 135 dB Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 0.005 0.04 μV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 100 kΩ to GND 4.99 4.998 V RL = 100 kΩ to GND @ −40°C to +125°C 4.99 4.997 V RL = 10 kΩ to GND 4.95 4.98 V R = 10 kΩ to GND @ −40°C to +125°C 4.95 4.975 V L Output Voltage Low V R = 100 kΩ to V+ 1 10 mV OL L R = 100 kΩ to V+ @ −40°C to +125°C 2 10 mV L RL = 10 kΩ to V+ 10 30 mV RL = 10 kΩ to V+ @ −40°C to +125°C 15 30 mV Short-Circuit Limit ISC ±25 ±50 mA −40°C to +125°C ±40 mA Output Current I ±30 mA O −40°C to +125°C ±15 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 5.5 V 120 130 dB S −40°C ≤ TA ≤ +125°C 115 130 dB Supply Current per Amplifier ISY VO = 0 V 850 975 μA −40°C ≤ TA ≤ +125°C 1000 1075 μA DYNAMIC PERFORMANCE Slew Rate SR RL = 10 kΩ 0.4 V/μs Overload Recovery Time 0.05 0.3 ms Gain Bandwidth Product GBP 1.5 MHz NOISE PERFORMANCE Voltage Noise en p-p 0 Hz to 10 Hz 1.3 μV p-p 0 Hz to 1 Hz 0.41 μV p-p Voltage Noise Density e f = 1 kHz 51 nV/√Hz n Current Noise Density in f = 10 Hz 2 fA/√Hz 1 Gain testing is dependent upon test bandwidth. Rev. E | Page 3 of 24 AD8571/AD8572/AD8574 2.7 V ELECTRICAL CHARACTERISTICS VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 1 5 μV −40°C ≤ TA ≤ +125°C 10 μV Input Bias Current IB 10 50 pA AD8571/AD8574 −40°C ≤ T ≤ +125°C 1.0 1.5 nA A AD8572 −40°C ≤ T ≤ +85°C 160 300 pA A −40°C ≤ TA ≤ +125°C 2.5 4 nA Input Offset Current IOS 10 50 pA AD8571/AD8574 −40°C ≤ TA ≤ +125°C 150 200 pA AD8572 −40°C ≤ T ≤ +85°C 30 150 pA A −40°C ≤ TA ≤ +125°C 150 400 pA Input Voltage Range 0 2.7 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 115 130 dB −40°C ≤ T ≤ +125°C 110 130 dB A 1 Large Signal Voltage Gain A R = 10 kΩ, V = 0.3 V to 2.4 V 110 140 dB VO L O −40°C ≤ T ≤ +125°C 105 130 dB A Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 0.005 0.04 μV/°C OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND 2.685 2.697 V OH L RL = 100 kΩ to GND @ −40°C to +125°C 2.685 2.696 V RL = 10 kΩ to GND 2.67 2.68 V RL = 10 kΩ to GND @ −40°C to +125°C 2.67 2.675 V Output Voltage Low V R = 100 kΩ to V+ 1 10 mV OL L R = 100 kΩ to V+ @ −40°C to +125°C 2 10 mV L RL = 10 kΩ to V+ 10 20 mV RL = 10 kΩ to V+ @ −40°C to +125°C 15 20 mV Short-Circuit Limit ISC ±10 ±15 mA −40°C to +125°C ±10 mA Output Current I ±10 mA O −40°C to +125°C ±5 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 5.5 V 120 130 dB S −40°C ≤ T ≤ +125°C 115 130 dB A Supply Current per Amplifier ISY VO = 0 V 750 900 μA −40°C ≤ TA ≤ +125°C 950 1000 μA DYNAMIC PERFORMANCE Slew Rate SR RL = 10 kΩ 0.5 V/μs Overload Recovery Time 0.05 ms Gain Bandwidth Product GBP 1 MHz NOISE PERFORMANCE Voltage Noise en p-p 0 Hz to 10 Hz 2.0 μV p-p Voltage Noise Density e f = 1 kHz 94 nV/√Hz n Current Noise Density i f = 10 Hz 2 fA/√Hz n 1 Gain testing is dependent upon test bandwidth. Rev. E | Page 4 of 24 AD8571/AD8572/AD8574 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage 6 V other conditions above those indicated in the operational section of Input Voltage GND to VS + 0.3 V this specification is not implied. Exposure to absolute maximum 1 Differential Input Voltage ±5.0 V rating conditions for extended periods may affect device reliability. ESD (Human Body Model) 2000 V Output Short-Circuit Duration to GND Indefinite THERMAL CHARACTERISTICS Storage Temperature Range −65°C to +150°C θ is specified for the worst-case conditions, that is, θ is JA JA Operating Temperature Range −40°C to +125°C specified for a device soldered in a circuit board for SOIC and Junction Temperature Range −65°C to +150°C TSSOP packages. Lead Temperature (Soldering, 60 sec) 300°C 1 Table 4. Thermal Resistance Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less. Package Type θ θ Unit JA JC 8-Lead SOIC (R) 158 43 °C/W 8-Lead MSOP (RM) 190 44 °C/W 8-Lead TSSOP (RU) 240 43 °C/W 14-Lead SOIC (R) 120 36 °C/W 14-Lead TSSOP (RU) 180 36 °C/W ESD CAUTION Rev. E | Page 5 of 24 AD8571/AD8572/AD8574 TYPICAL PERFORMANCE CHARACTERISTICS 180 180 V = 5V V = 2.7V S S 160 160 V = 2.5V V = 1.35V CM CM T = 25°C T = 25°C A A 140 140 120 120 100 100 80 80 60 60 40 40 20 20 0 0 –2.5 –1.5 –0.5 0.5 1.5 2.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 OFFSET VOLTAGE (µV) OFFSET VOLTAGE (µV) Figure 7. Input Offset Voltage Distribution Figure 10. Input Offset Voltage Distribution 50 12 V = 5V S T = –40°C, +25°C, +85°C 40 A V = 5V S V = 2.5V 10 CM T = –40°C TO +125°C A 30 +85°C 8 20 10 6 +25°C 0 4 –10 –40°C 2 –20 –30 0 01235 4 01 234 5 6 INPUT COMMON-MODE VOLTAGE (V) INPUT OFFSET DRIFT (nV/°C) Figure 8. Input Bias Current vs. Input Common-Mode Voltage Figure 11. Input Offset Voltage Drift Distribution 10k 1500 V = 5V S V = 5V S T = 125°C A T = 25°C A 1000 1k 500 100 0 SOURCE –500 10 SINK –1000 1 –1500 0.1 –2000 0.0001 0.001 0.01 0.1 1 10 100 012 345 LOAD CURRENT (mA) COMMON-MODE VOLTAGE (V) Figure 9. Input Bias Current vs. Common-Mode Voltage Figure 12. Output Voltage to Supply Rail vs. Load Current Rev. E | Page 6 of 24 INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (pA) NUMBER OF AMPLIFIERS 01104-007 01104-009 01104-008 OUTPUT VOLTAGE (mV) NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 01104-011 01104-010 01104-012 AD8571/AD8572/AD8574 10k 800 V = 2.7V S T = 25°C A T = 25°C A 700 1k 600 500 100 400 SINK SOURCE 10 300 200 1 100 0.1 0 0.0001 0.001 0.01 0.1 1 10 100 01 2 3 4 5 6 LOAD CURRENT (mA) SUPPLY VOLTAGE (V) Figure 13. Output Voltage to Supply Rail vs. Load Current Figure 16. Supply Current per Amplifier vs. Supply Voltage 1000 60 V = 2.7V S V = 2.5V CM 50 C = 0pF L V = 5V S R = L ∞ 40 0 750 30 45 20 90 500 10 135 0 180 –10 225 250 –20 270 –30 0 –40 –75 –50 –25 0 25 50 75 100 125 150 10k 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 14. Input Bias Current vs. Temperature Figure 17. Open-Loop Gain and Phase Shift vs. Frequency 1.0 60 V = 5V S C = 0pF 50 L 5V R = L ∞ 0.8 40 0 2.7V 30 45 0.6 20 90 10 135 0.4 0 180 –10 225 0.2 –20 270 –30 0 –40 –75 –50 –25 0 25 50 75 100 125 150 10k 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 15. Supply Current vs. Temperature Figure 18. Open-Loop Gain and Phase Shift vs. Frequency Rev. E | Page 7 of 24 INPUT BIAS CURRENT (pA) OUTPUT VOLTAGE (mV) SUPPLY CURRENT (mA) 01104-015 01104-013 01104-014 OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) SUPPLY CURRENT PER AMPLIFIER (µA) PHASE SHIFT (Degrees) PHASE SHIFT (Degrees) 01104-016 01104-018 01104-017 AD8571/AD8572/AD8574 60 300 V = 2.7V S V = 5V 50 270 S C = 20pF L R = 2kΩ L 40 240 A = 100 V 30 210 20 180 A = 10 V 10 150 A = 100 V 0 120 A = 1 V –10 90 A = 10 V –20 60 –30 30 A = 1 V –40 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. Closed-Loop Gain vs. Frequency Figure 22. Output Impedance vs. Frequency 60 V = 2.7V S V = 5V S 50 C = 300pF L C = 20pF L R = 2kΩ L R = 2kΩ L A = 1 V 40 A = 100 V 30 20 A = 10 V 10 0 A = 1 V –10 –20 –30 2µs 500mV –40 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 20. Closed-Loop Gain vs. Frequency Figure 23. Large Signal Transient Response 300 V = 5V S V = 2.7V 270 C = 300pF S L R = 2kΩ L A = 1 V 240 210 180 A = 100 V 150 120 A = 10 V 90 60 30 A = 1 5µs 1V V 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 21. Output Impedance vs. Frequency Figure 24. Large Signal Transient Response Rev. E | Page 8 of 24 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) OUTPUT IMPEDANCE (Ω) 01104-021 01104-020 01104-019 OUTPUT IMPEDANCE (Ω) 01104-024 01104-023 01104-022 AD8571/AD8572/AD8574 45 V = ±1.35V S V = ±2.5V S C = 50pF L R = 2kΩ L 40 R = L ∞ T = 25°C A A = 1 V 35 +OS 30 25 20 –OS 15 10 5 5µs 50mV 0 10 100 1k 10k CAPACITANCE (pF) Figure 25. Small Signal Transient Response Figure 28. Small Signal Overshoot vs. Load Capacitance V = ±2.5V S C = 50pF 0V L R = ∞ L V = ±2.5V A = 1 S V V = –200mV p-p V IN IN (RET TO GND) C = 0pF L R = 10kΩ L A = –100 V V OUT 0V 20µs 1V 5µs 50mV BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV Figure 26. Small Signal Transient Response Figure 29. Positive Overvoltage Recovery 50 V = ±1.35V S V 45 R = 2kΩ IN L T = 25°C A 40 0V 35 V = ±2.5V S V = 200mV p-p IN (RET TO GND) 30 C = 0pF L +OS R = 10kΩ L 25 A = –100 V 0V –OS 20 15 V OUT 10 5 20µs 1V 0 0 BOTTOM SCALE: 1V/DIV 10 100 1k 10k TOP SCALE: 200mV/DIV CAPACITANCE (pF) Figure 27. Small Signal Overshoot vs. Load Capacitance Figure 30. Negative Overvoltage Recovery Rev. E | Page 9 of 24 SMALL SIGNAL OVERSHOOT (%) 01104-026 01104-025 01104-027 SMALL SIGNAL OVERSHOOT (%) 01104-030 01104-029 01104-028 AD8571/AD8572/AD8574 140 V = ±2.5V S V = ±1.35V S R = 2kΩ L A = –100 120 V V = 60mV p-p IN 100 80 60 –PSRR +PSRR 40 20 200µs 1V 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 31. No Phase Reversal Figure 34. PSRR vs. Frequency 140 140 V = ±2.5V V = 2.7V S S 120 120 +PSRR 100 100 80 80 60 60 –PSRR 40 40 20 20 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 32. CMRR vs. Frequency Figure 35. PSRR vs. Frequency 140 3.0 V = 5V S 120 2.5 V = ±1.35V S R = 2kΩ L 100 A = 1 V THD + N < 1% 2.0 T = 25°C A 80 1.5 60 1.0 40 0.5 20 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 33. CMRR vs. Frequency Figure 36. Maximum Output Swing vs. Frequency Rev. E | Page 10 of 24 CMRR (dB) CMRR (dB) 01104-031 01104-033 01104-032 PSRR (dB) PSRR (dB) OUTPUT SWING (V p-p) 01104-036 01104-035 01104-034 AD8571/AD8572/AD8574 5.5 V = ±2.5V S V = 2.7V 5.0 R = 2kΩ S L 364 R = 0Ω A = 1 V S THD + N < 1% 4.5 T = 25°C A 312 4.0 260 3.5 3.0 208 2.5 156 2.0 1.5 104 1.0 52 0.5 0 0 0.5 1.0 1.5 2.0 2.5 100 1k 10k 100k 1M FREQUENCY (kHz) FREQUENCY (Hz) Figure 37. Maximum Output Swing vs. Frequency Figure 40. Voltage Noise Density from 0 Hz to 2.5 kHz V = ±1.35V S V = 2.7V S 112 A = 120,000 V R = 0Ω S 96 80 0V 64 48 32 16 50mV 1sec 0 5 10 15 20 25 FREQUENCY (kHz) Figure 38. 0.1 Hz to 10 Hz Noise Figure 41. Voltage Noise Density from 0 Hz to 25 kHz V = ±2.5V V = 5V S S 182 A = 120,000 V R = 0Ω S 156 130 104 78 52 26 50mV 1sec 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (kHz) Figure 39. 0.1 Hz to 10 Hz Noise Figure 42. Voltage Noise Density from 0 Hz to 2.5 kHz Rev. E | Page 11 of 24 OUTPUT SWING (V p-p) 01104-039 01104-038 01104-037 e e e n (nV/ Hz) n (nV/ Hz) n (nV/ Hz) 01104-042 01104-041 01104-040 AD8571/AD8572/AD8574 150 V = 5V S V = 2.7V TO 5.5V 112 S R = 0Ω S 145 96 80 140 64 135 48 32 130 16 125 0 5 10 15 20 25 –75 –50 –25 0 25 50 75 100 125 150 FREQUENCY (kHz) TEMPERATURE (°C) Figure 43. Voltage Noise Density from 0 Hz to 25 kHz Figure 45. Power Supply Rejection vs. Temperature 50 V = 5V S V = 2.7V 40 S 210 R = 0Ω S 30 180 I SC– 20 150 10 120 0 –10 90 I –20 SC+ 60 –30 30 –40 –50 05 10 –75 –50 –25 0 25 50 75 100 125 150 FREQUENCY (Hz) TEMPERATURE (°C) Figure 46. Output Short-Circuit Current vs. Temperature Figure 44. Voltage Noise Density from 0 Hz to 10 Hz Rev. E | Page 12 of 24 e e n (nV/ Hz) n (nV/ Hz) 01104-044 01104-043 OUTPUT SHORT-CIRCUIT CURRENT (mA) POWER SUPPLY REJECTION (dB) 01104-046 01104-045 AD8571/AD8572/AD8574 100 250 80 V = 5V V = 5V S 225 S 60 200 I SC– 40 175 R = 1kΩ L 20 150 0 125 –20 100 –40 75 I SC+ –60 50 R = 10kΩ L R = 100kΩ L –80 25 –100 0 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 49. Output Voltage to Supply Rail vs. Temperature Figure 47. Output Short-Circuit Current vs. Temperature 250 V = 2.7V 225 S 200 175 150 R = 1kΩ L 125 100 75 50 R = 10kΩ R = 100kΩ L L 25 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 48. Output Voltage to Supply Rail vs. Temperature Rev. E | Page 13 of 24 OUTPUT VOLTAGE (mV) OUTPUT SHORT-CIRCUIT CURRENT (mA) 01104-048 01104-047 OUTPUT VOLTAGE (mV) 01104-049 AD8571/AD8572/AD8574 FUNCTIONAL DESCRIPTION The AD8571/AD8572/AD8574 are CMOS amplifiers that BASIC AUTO-ZERO AMPLIFIER THEORY achieve their high degree of precision through random frequency Autocorrection amplifiers are not a new technology. Various IC auto-zero stabilization. The autocorrection topology allows the implementations have been available for more than 15 years, AD857x to maintain its low offset voltage over a wide temperature and some improvements have been made over time. The range, and the randomized auto-zero clock eliminates any inter- AD857x design offers a number of significant performance modulation distortion (IMD) errors at the amplifier output. improvements over older versions while attaining a very substantial reduction in device cost. This section offers a The AD857x can run from a single-supply voltage as low as 2.7 V. simplified explanation of how the AD857x is able to offer The extremely low offset voltage of 1 μV and no IMD products extremely low offset voltages and high open-loop gains. allow the amplifier to be easily configured for high gains without risk of excessive output voltage errors, which makes the AD857x As noted in the Amplifier Architecture section, each AD857x an ideal amplifier for applications requiring both dc precision op amp contains two internal amplifiers. One is used as the and low distortion for ac signals. The extremely small temperature primary amplifier, and the other as an autocorrection, or nulling, drift of 5 nV/°C ensures a minimum of offset voltage error over amplifier. Each amplifier has an associated input offset voltage its −40°C to +125°C temperature range. These combined features that can be modeled as a dc voltage source in series with the make the AD857x an excellent choice for a variety of sensitive noninverting input. In Figure 50 and Figure 51, these are labeled measurement and automotive applications. as VOSA and VOSB, where A denotes the nulling amplifier and B denotes the primary amplifier. The open-loop gain for the +IN AMPLIFIER ARCHITECTURE and −IN inputs of each amplifier is given as A . Both amplifiers X Each AD857x op amp consists of two amplifiers: a main amplifier also have a third voltage input with an associated open-loop and a secondary amplifier that is used to correct the offset voltage gain of B . X of the main amplifier. Both consist of a rail-to-rail input stage, V OSB allowing the input common-mode voltage range to reach both + V IN+ supply rails. The input stage consists of an NMOS differential A V B OUT V IN– pair operating concurrently with a parallel PMOS differential B B ΦB pair. The outputs from the differential input stages are combined in V OA C M2 V ΦB OSA another gain stage whose output is used to drive a rail-to-rail ΦA 1 + output stage. A A V NB The wide voltage swing of the amplifier is achieved by using two –B A ΦA 2 C M1 output transistors in a common-source configuration. The output voltage range is limited by the drain-to-source resistance of V NA these transistors. As the amplifier is required to source or sink Figure 50. Auto-Zero Phase of the Amplifier more output current, the voltage drop across these transistors V OSB increases due to their on resistance (R ). Simply put, the output DS + V IN+ voltage does not swing as close to the rail under heavy output A V B OUT V current conditions as it does with light output current. This is a IN– B B ΦB characteristic of all rail-to-rail output amplifiers. Figure 12 and V OA C M2 V ΦB ΦA OSA Figure 13 show how close the output voltage can get to the rails + with a given output current. The output of the AD857x is short- A A V NB circuit protected to approximately 50 mA of current. –B A ΦA C M1 The AD857x amplifiers have exceptional gain, yielding greater than 120 dB of open-loop gain with a load of 2 kΩ. Because V NA the output transistors are configured in a common-source Figure 51. Output Phase of the Amplifier configuration, the gain of the output stage, and thus the open- loop gain of the amplifier, is dependent on the load resistance. There are two modes of operation determined by the action of Open-loop gain decreases with smaller load resistances, which two sets of switches in the amplifier: an auto-zero phase and an is another characteristic of rail-to-rail output amplifiers. amplification phase. Rev. E | Page 14 of 24 01104-051 01104-050 AD8571/AD8572/AD8574 For the sake of simplification, it can be assumed that the auto- AUTO-ZERO PHASE correction frequency is much faster than any potential change In this phase, all ΦAX switches are closed, and all ΦB switches in V or V . This is a good assumption because changes in OSA OSB are open. Here, the nulling amplifier is taken out of the gain offset voltage are a function of temperature variation or long- loop by shorting its two inputs together. Of course, there is a term wear time, both of which are much slower than the degree of offset voltage, shown as V , inherent in the nulling OSA auto-zero clock frequency of the AD857x, which effectively amplifier, that maintains a potential difference between the +IN makes the VOS time invariant, and Equation 5 can be rewritten as and −IN inputs. The nulling amplifier feedback loop is closed A (1+ B )V − A B V through ΦA2, and VOSA appears at the output of the nulling A A OSA A A OSA V [] t = A V [t]+ (6) OA A IN amplifier and on CM1, an internal capacitor in the AD857x. 1+ B A Mathematically, this can be expressed in the time domain as or VOA[t] = AAVOSA[t] − BAVOA[t] (1) ⎛ ⎞ V This can also be expressed as OSA ⎜ ⎟ V [] t = A V [t]+ (7) OA A IN ⎜ ⎟ 1+ B A A V [] t ⎝ ⎠ A OSA V [] t = (2) OA 1+ B A Here, the auto-zeroing becomes apparent. Note that the V OS term is reduced by a factor of 1 + B , which shows how the A The previous equations show that the offset voltage of the nulling nulling amplifier has greatly reduced its own offset voltage error amplifier times a gain factor appears at the output of the nulling even before correcting the primary amplifier. Therefore, the amplifier and thus on the C capacitor. M1 primary amplifier output voltage is the voltage at the output of the AD857x amplifier. It is equal to AMPLIFICATION PHASE VOUT[t] = AB(VIN[t] + VOSB) + BBVNB (8) When the ΦB switches close and the ΦA switches open for X the amplification phase, the offset voltage remains on CM1 and In the amplification phase, V = V , so this can be rewritten as OA NB essentially corrects any error from the nulling amplifier. The V [t]= voltage across CM1 is designated as VNA. The potential difference OUT between the two inputs to the primary amplifier is designated as ⎡ ⎤ (9) ⎛ ⎞ V OSA ⎜ ⎟ VIN, or VIN = (VIN+ − VIN−). The output of the nulling amplifier A V [] t + A V + B A V [] t + ⎢ ⎥ B IN B OSB B A IN ⎜ ⎟ 1+ B ⎢ ⎝ A⎠⎥ ⎣ ⎦ can then be expressed as V [t] = A (V [t] − V [t]) − B V [t] (3) OA A IN OSA A NA Combining terms yield Because ΦA is now open and there is no place for C to V [t]= X M1 OUT discharge, the voltage (V ) at the present time (t) is equal to NA A B V (10) A B OSA V [] t() A + A B + + A V IN B A B B OSB the voltage at the output of the nulling amp (VOA) at the time when 1+ B A ΦAX is closed. If the period of the autocorrection switching frequency is designated as TS, the amplifier switches between The AD857x architecture is optimized in such a way that phases every 0.5 × TS. Therefore, in the amplification phase A = A , B = B , and B >> 1. In addition, the gain product to A B A B A AABB is much greater than AB. Therefore, Equation 10 can be ⎡ 1 ⎤ V [] t = V t− T (4) simplified to NA NA S ⎢ ⎥ ⎣ 2 ⎦ VOUT[t] = VIN[t]AABA + AA(VOSA+ VOSB) (11) and substituting Equation 4 and Equation 2 into Equation 3 yields Most obvious is the gain product of both the primary and nulling 1 ⎡ ⎤ amplifiers. This A B term is what gives the AD857x its extremely A A A B V t− T A A OSA S ⎢ ⎥ ⎣ 2 ⎦ high open-loop gain. To understand how V and V relate to OSA OSB []= []+ []− (5) V t A V t A V t OA A IN A OSA the overall effective input offset voltage of the complete amplifier, 1+ B A set up the generic amplifier equation of VOUT = k × (VIN + VOS, EFF) (12) where: k is the open-loop gain of an amplifier. V is its effective offset voltage. OS, EFF Putting Equation 12 into the form of Equation 11 gives V [t] = V [t]A B + V A B (13) OUT IN A A OS, EFF A A Rev. E | Page 15 of 24 AD8571/AD8572/AD8574 V+ Therefore, R1 R2 AD8572 R2 R1 V + V OSA OSB V IN1 V ≈ (14) OS,EFF V IN2 B A GUARD GUARD Thus, the offset voltages of both the primary and nulling V RING REF RING amplifiers are reduced by the gain factor B , which takes a typical V A REF V– input offset voltage from several millivolts down to an effective Figure 53. Top View of AD8572 SOIC Layout with Guard Rings input offset voltage of submicrovolts. This autocorrection scheme makes the AD857x family of amplifiers extremely precise. Other potential sources of offset error are thermoelectric HIGH GAIN, CMRR, AND PSRR voltages on the circuit board. This voltage, also called Seebeck voltage, occurs at the junction of two dissimilar metals and is Common-mode and power supply rejection are indications of the proportional to the junction temperature. The most common amount of offset voltage an amplifier has as a result of a change in metallic junctions on a circuit board are solder-to-board trace its input common-mode or power supply voltages. As shown in and solder-to-component lead. Figure 54 shows a cross-section the Amplification Phase section, the autocorrection architecture view of the thermal voltage error sources. When the temperature of the AD857x allows it to effectively minimize offset voltages. of the PCB at one end of the component (TA1) differs from the The technique also corrects for offset errors caused by common- temperature at the other end (TA2), the Seebeck voltages are not mode voltage swings and power supply variations, which results equal, resulting in a thermal voltage error. in superb CMRR and PSRR figures in excess of 130 dB. Because the autocorrection occurs continuously, these figures can be This thermocouple error can be reduced by using dummy maintained across the temperature range of the device (−40°C components to match the thermoelectric error source. Placing to +125°C). the dummy component as close as possible to its partner ensures that both Seebeck voltages are equal, thus canceling the thermo- MAXIMIZING PERFORMANCE THROUGH PROPER couple error. Maintaining a constant ambient temperature on the LAYOUT circuit board further reduces this error. The use of a ground To achieve the maximum performance of the extremely high plane helps distribute heat throughout the board and also input impedance and low offset voltage of the AD857x, care reduces EMI noise pickup. should be taken in the circuit board layout. The PCB surface COMPONENT must remain clean and free of moisture to avoid leakage currents LEAD between adjacent traces. Surface coating of the circuit board SOLDER V V SC2 SC1 reduces surface moisture and provides a humidity barrier, reducing + SURFACE MOUNT + – – COMPONENT V V TS1 TS2 parasitic resistance on the board. The use of guard rings around + + – – the amplifier inputs further reduces leakage currents. Figure 52 PC BOARD shows how the guard ring should be configured, and Figure 53 shows the top view of how a surface-mount layout can be T T A1 A2 arranged. The guard ring does not need to be a specific width, COPPER IF T ≠ T , THEN A1 A2 TRACE V V ≠ V V TS1 + SC1 TS2 + SC2 but it should form a continuous loop around both inputs. By Figure 54. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error setting the guard ring voltage equal to the voltage at the non- inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted R to the PCB using Teflon® standoff insulators. F R1 V OUT V IN V V OUT OUT AD8571/AD8572/ V IN V R = R1 S IN AD8574 AD8572 AD8572 A = 1 + (R /R1) V F R SHOULD BE PLACED IN CLOSE PROXIMITY AND S ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES V IN Figure 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors V OUT AD8572 Figure 52. Guard Ring Layout and Connections to Reduce PCB Leakage Currents Rev. E | Page 16 of 24 01104-052 01104-055 01104-054 01104-053 AD8571/AD8572/AD8574 0 1/f NOISE CHARACTERISTICS V = 5V S Another advantage of auto-zero amplifiers is their ability to A = 60dB –20 V cancel flicker noise. Flicker noise, also known as 1/f noise, is noise inherent in the physics of semiconductor devices and –40 increases 3 dB for every octave decrease in frequency. The 1/f corner frequency of an amplifier is the frequency at which the –60 flicker noise is equal to the broadband noise of the amplifier. At lower frequencies, flicker noise dominates, causing higher –80 degrees of error for sub-Hertz frequencies or dc precision applications. –100 Because the AD857x amplifiers are self-correcting op amps, –120 0123 45678 9 10 they do not have increasing flicker noise at lower frequencies. In FREQUENCY (kHz) essence, low frequency noise is treated as a slowly varying offset Figure 57. Spectral Analysis of AD857x Output with 60 dB Gain error and is greatly reduced with autocorrection. The correction becomes more effective as the noise frequency approaches dc, Figure 58 shows the spectral output of an AD8572 configured in offsetting the tendency of the noise to increase exponentially as a high gain (60 dB) with a 1 mV input signal applied. Note the frequency decreases, which allows the AD857x to have lower absence of any IMD products in the spectrum. The signal-to- noise near dc than standard low noise amplifiers that are noise ratio (SNR) of the output signal is better than 60 dB, or 0.1%. susceptible to 1/f noise. 0 RANDOM AUTO-ZERO CORRECTION ELIMINATES V = 5V S A = 60dB INTERMODULATION DISTORTION V –20 The AD857x can be used as a conventional op amp for gains up –40 to 1 MHz. The auto-zero correction frequency of the device continuously varies, based on a pseudorandom generator with a –60 uniform distribution from 2 kHz to 4 kHz. The randomization of the autocorrection clock creates a continuous randomization –80 of IMD products that show up as simple broadband noise at the output of the amplifier. This broadband noise naturally combines –100 with the amplifier voltage noise in a root-squared-sum fashion, resulting in an output free IMD. Figure 56 shows the spectral –120 output of an AD8572 with the amplifier configured for unity 0123 45678 9 10 FREQUENCY (kHz) gain and the input grounded. Figure 57 shows the spectral Figure 58. Spectral Analysis of AD8572 in High Gain with an Input Signal output with the amplifier configured for a gain of 60 dB. 0 V = 5V –20 S A = 0dB V –40 –60 –80 –100 –120 –140 –160 1 23456789 10 FREQUENCY (kHz) Figure 56. Spectral Analysis of AD8572 Output in Unity Gain Configuration Rev. E | Page 17 of 24 OUTPUT SIGNAL 01104-056 OUTPUT SIGNAL OUTPUT SIGNAL 01104-058 01104-057 AD8571/AD8572/AD8574 BROADBAND AND EXTERNAL RESISTOR NOISE CONSIDERATIONS The total broadband noise output from any amplifier is primarily a The output overdrive recovery for an autocorrection amplifier is function of three types of noise: input voltage noise from the defined as the time it takes for the output to correct to its final amplifier, input current noise from the amplifier, and Johnson voltage from an overload state. It is measured by placing the noise from the external resistors used around the amplifier. amplifier in a high gain configuration with an input signal that Input voltage noise, or e , is strictly a function of the amplifier forces the output voltage to the supply rail. The input voltage is n used. The Johnson noise from a resistor is a function of the then stepped down to the linear region of the amplifier, usually resistance and the temperature. Input current noise, or i , to halfway between the supplies. The time from the input signal n creates an equivalent voltage noise proportional to the resistors step-down to the output settling to within 100 μV of its final used around the amplifier. These noise sources are not correlated value is the overdrive recovery time. Many autocorrection with each other and their combined noise sums in a root- amplifiers require a number of auto-zero clock cycles to recover squared-sum fashion. The full equation is given as from output overdrive, and some can take several milliseconds 2 1/2 for the output to settle properly. 2 en, TOTAL = [en + 4kTrs + (inrs) ] (15) INPUT OVERVOLTAGE PROTECTION where: e is the input voltage noise of the amplifier. Although the AD857x are rail-to-rail input amplifiers, care n i is the input current noise of the amplifier. should be taken to ensure that the potential difference between n the inputs does not exceed 5 V. Under normal operating conditions, rs is the source resistance connected to the noninverting the amplifier corrects its output to ensure that the two inputs terminal. −23 are at the same voltage. However, if the device is configured as k is Boltzmann’s constant (1.38 × 10 J/K). a comparator, or is under some unusual operating condition, the T is the ambient temperature in Kelvin (K = 273.15 + °C). input voltages may be forced to different potentials, which could The input voltage noise density, e , of the AD857x is 51 nV/√Hz, n cause excessive current to flow through the internal diodes in the and the input noise, i , is 2 fA/√Hz. The e is dominated by n n, TOTAL AD857x used to protect the input stage against overvoltage. the input voltage noise provided that the source resistance is less If either input exceeds either supply rail by more than 0.3 V, than 172 kΩ. With source resistance greater than 172 kΩ, the large amounts of current begin to flow through the ESD overall noise of the system is dominated by the Johnson noise of protection diodes in the amplifier. These diodes are connected the resistor itself. between the inputs and each supply rail to protect the input Because the input current noise of the AD857x is very small, in transistors against an electrostatic discharge event and are does not become a dominant term unless r > 4 GΩ, which is an s normally reverse-biased. However, if the input voltage exceeds impractical value of source resistance. the supply voltage, these ESD diodes become forward-biased. Without current-limiting, excessive amounts of current can The total noise, e , , is expressed in volts-per-square-root n TOTAL flow through these diodes, causing permanent damage to the Hertz, and the equivalent rms noise over a certain bandwidth device. If inputs are subject to overvoltage, appropriate series can be found as resistors should be inserted to limit the diode current to less en = en, TOTAL × BW (16) than 2 mA. where BW is the bandwidth of interest in Hertz. OUTPUT PHASE REVERSAL Output phase reversal occurs in some amplifiers when the input OUTPUT OVERDRIVE RECOVERY common-mode voltage range is exceeded. As common-mode The AD857x amplifiers have an excellent overdrive recovery voltage moves outside the common-mode range, the outputs of of only 200 μs from either supply rail. This characteristic is these amplifiers suddenly jump in the opposite direction to particularly difficult for autocorrection amplifiers because the the supply rail. This is the result of the differential input pair nulling amplifier requires a substantial amount of time to error shutting down, causing a radical shifting of internal voltages correct the main amplifier back to a valid output. Figure 29 and that results in the erratic output behavior. Figure 30 show the positive and negative overdrive recovery times for the AD857x. The AD857x amplifier has been carefully designed to prevent any output phase reversal, provided that both inputs are maintained within the supply voltages. If one or both inputs exceed either supply voltage, a resistor should be placed in series with the input to limit the current to less than 2 mA to ensure that the output does not reverse its phase. Rev. E | Page 18 of 24 AD8571/AD8572/AD8574 CAPACITIVE LOAD DRIVE The optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically The AD857x have excellent capacitive load driving capabilities because actual C includes stray capacitances and can differ and can safely drive up to 10 nF from a single 5 V supply. L Although the device is stable, capacitive loading limits the substantially from the nominal capacitive load. Table 5 shows bandwidth of the amplifier. Capacitive loads also increase the some snubber network values that can be used as starting points. amount of overshoot and ringing at the output. The RC snubber network shown in Figure 59 can be used to reduce the capacitive Table 5. Snubber Network Values for Driving Capacitive Loads load ringing and overshoot. CL (nF) Rx (Ω) Cx 1 200 1 nF 5V AD8571/ 4.7 60 0.47 μF AD8572/ – AD8574 10 20 10 μF V OUT Rx V IN + 60Ω C L POWER-UP BEHAVIOR 200mV p-p Cx 4.7nF 0.47µF At power-up, the AD857x settles to a valid output within 5 μs. Figure 61 shows an oscilloscope photo of the output of the Figure 59. Snubber Network Configuration for Driving Capacitive Loads amplifier along with the power supply voltage. Figure 62 shows the test circuit. With the amplifier configured for unity gain, the Although the snubber network does not recover the loss of device takes approximately 5 μs to settle to its final output amplifier bandwidth from the load capacitance, it does allow the amplifier to drive larger values of capacitance while voltage, hundreds of microseconds faster than many other maintaining a minimum of overshoot and ringing. Figure 60 autocorrection amplifiers. shows the output of an AD857x driving a 1 nF capacitor with and without a snubber network. 10μs V OUT WITH SNUBBER 0V V+ 0V WITHOUT SNUBBER 5µs 1V BOTTOM TRACE = 2V/DIV V = 5V TOP TRACE = 1V/DIV S 100mV C = 4.7nF L Figure 61. AD857x Output Behavior at Power-Up Figure 60. Overshoot and Ringing Are Substantially Reduced Using a Snubber Network V = 0V TO 5V SY 100kΩ V OUT 100kΩ AD8571/ AD8572/ AD8574 Figure 62. AD857x Test Circuit for Power-Up Time Rev. E | Page 19 of 24 01104-059 01104-060 01104-062 01104-061 AD8571/AD8572/AD8574 APPLICATIONS INFORMATION R2 5 V PRECISION STRAIN GAGE CIRCUIT R1 The extremely low offset voltage of the AD8572 makes it an ideal V2 V R3 OUT amplifier for any application requiring accuracy with high gains, V1 AD8571/ such as a weigh scale or strain gage. Figure 63 shows a configura- R4 AD8572/ AD8574 tion for a single-supply, precision strain gage measurement system. R4 R2 R2 IF = , THEN V = (V1 – V2) OUT R3 R1 R1 The REF192 provides a 2.5 V precision reference voltage for A2. Figure 64. Using the AD857x as a Difference Amplifier The A2 amplifier boosts this voltage to provide a 4.0 V reference for the top of the strain gage resistor bridge. Q1 provides the In an ideal difference amplifier, the ratio of the resistors is set current drive for the 350 Ω bridge network. A1 is used to amplify equal to the output of the bridge with the full-scale output voltage equal to R2 R4 A = = (19) 2×(R1+ R2) V (17) R1 R3 R B Set the output voltage of the system to where R is the resistance of the load cell. B VOUT = AV (V1 − V2) (20) Using the values given in Figure 63, the output voltage linearly Due to finite component tolerance, the ratio between the four varies from 0 V with no strain to 4 V under full strain. resistors is not exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. Referring 2 5V 2.5V 6 3 to Figure 64, the exact common-mode rejection ratio can be REF192 1kΩ Q1 A2 expressed as 2N2222 4 OR AD8572-B EQUIVALENT R1R4+ 2R2R4+ R2R3 12kΩ 20kΩ CMRR= (21) 4.0V 2R1R4− 2R2R3 R2 R1 100Ω 17.4kΩ In the 3-op amp instrumentation amplifier configuration shown in Figure 65, the output difference amplifier is set to unity gain 40mV A1 V OUT with all four resistors equal in value. If the tolerance of the FULL-SCALE 350Ω 0V TO 4V LOAD AD8572-A resistors used in the circuit is given as δ, the worst-case CMRR CELL of the instrumentation amplifier is R4 R3 100Ω 17.4kΩ NOTE: 1 USE 0.1% TOLERANCE RESISTORS. CMRR = (22) MIN 2δ Figure 63. 5 V Precision Strain Gage Amplifier AD8574-A V2 R 3 V INSTRUMENTATION AMPLIFIER The high common-mode rejection, high open-loop gain, R R and operation down to 3 V of the supply voltage make the V R R R OUT G AD857x family an excellent op amp choice for discrete single- AD8574-C R supply instrumentation amplifiers. The common-mode rejection ratio of the AD857x is greater than 120 dB, but the R V1 TRIM AD8574-B CMRR of the system is also a function of the external resistor 2R tolerances. The gain of the difference amplifier shown in Figure 64 (V1 – V2) V = 1 + OUT R G is given as Figure 65. Discrete Instrumentation Amplifier Configuration ⎛ R4 ⎞⎛ R1⎞ ⎛ R2⎞ V = V1 1+ − V 2 (18) ⎜ ⎟⎜ ⎟ ⎜ ⎟ OUT Therefore, using 1% tolerance resistors results in a worst-case ⎝ R3+ R4⎠⎝ R2⎠ ⎝ R1⎠ system CMRR of 0.02, or 34 dB. To achieve high common- mode rejection, either high precision resistors or an additional trimming resistor, as shown in Figure 65, should be used. The value of this trimming resistor should be equal to the value of R multiplied by its tolerance. For example, using 10 kΩ resistors with 1% tolerance would require a series trimming resistor equal to 100 Ω. Rev. E | Page 20 of 24 01104-063 01104-064 01104-065 AD8571/AD8572/AD8574 Monitor Output = R2 × (R /R1) × I (23) HIGH ACCURACY THERMOCOUPLE AMPLIFIER SENSE L Figure 66 shows a K-type thermocouple amplifier configuration Using the components shown in Figure 67, the monitor output with cold-junction compensation. Even from a 5 V supply, the transfer function is 2.49 V/A. AD8571 can provide enough accuracy to achieve a resolution of R SENSE I L better than 0.02°C from 0°C to 500°C. D1 is used as a tempera- 0.1Ω V+ ture measuring device to correct the cold-junction error from V+ 0.1µF the thermocouple and should be placed as close as possible to R1 the two terminating junctions. With the thermocouple measuring 3 8 100Ω LOAD + tip immersed in a 0°C ice bath, R6 should be adjusted until the 1/2 1 AD8572 2 output is at 0 V. – 4 S G Using the values shown in Figure 66, the output voltage tracks M1 Si9433 temperature at 10 mV/°C. For a wider range of temperature D MONITOR measurement, R9 can be decreased to 62 kΩ. This creates a OUTPUT R2 5 mV/°C change at the output, allowing measurements of up 2.49kΩ to 1000°C. Figure 67. High-Side Load Current Monitor REF02EZ 5V 2 6 12V Figure 68 shows the low-side monitor equivalent. In this circuit, 0.1µF 4 the input common-mode voltage to the AD8572 is at or near R5 R9 40.2kΩ ground. Again, a 0.1 Ω resistor provides a voltage drop propor- 124kΩ R1 10.7kΩ tional to the return current. The output voltage is given as 5V 1N4148 10µF R2 ⎛ ⎞ D1 Monitor Output= V − × R × I (24) ⎜ ⎟ + SENSE L R1 ⎝ ⎠ 0.1µF R2 R8 2.74kΩ 453Ω 2 – – 7 K-TYPE For the component values shown in Figure 68, the monitor 6 THERMOCOUPLE + + R6 3 output transfer function is V+ − 2.49 V/A. 40.7µV/°C 200Ω 4 AD8571 V+ 0V TO 5V R4 R3 (0°C TO 500°C) 5.62kΩ 53.6Ω R2 2.49kΩ MONITOR Figure 66. Precision K-Type Thermocouple Amplifier OUTPUT V+ with Cold-Junction Compensation Q1 V+ PRECISION CURRENT METER 2 LOAD Because of its low input bias current and superb offset voltage at 3 R1 1/2 AD8572 single-supply voltages, the AD857x family is an excellent amplifier 100Ω R SENSE for precision current monitoring. Its rail-to-rail input allows the 0.1Ω amplifier to be used as either a high-side or a low-side current I L monitor. Using both amplifiers in the AD8572 provides a simple Figure 68. Low-Side Load Current Monitor method to monitor both current supply and return paths for load or fault detection. PRECISION VOLTAGE COMPARATOR The AD857x can be operated open loop and used as a precision Figure 67 shows a high-side current monitor configuration. comparator. The AD857x have less than 50 μV of offset voltage Here, the input common-mode voltage of the amplifier is at or when they run in this configuration. The slight increase of near the positive supply voltage. The rail-to-rail input of the offset voltage stems from the fact that the autocorrection amplifier provides a precise measurement, even with the input architecture operates with the lowest offset in a closed-loop common-mode voltage at the supply voltage. The CMOS input configuration, that is, one with negative feedback. With 50 mV structure does not draw any input bias current, ensuring a of overdrive, the device has a propagation delay of 15 μs on the minimum of measurement error. rising edge and 8 μs on the falling edge. The 0.1 Ω resistor creates a voltage drop to the noninverting Care should be taken to ensure that the maximum differential input of the AD857x. The output of the amplifier is corrected voltage of the device is not exceeded. For more information, see until this voltage appears at the inverting input, which creates a the Input Overvoltage Protection section. current through R1 that in turn flows through R2. The monitor output is given by Rev. E | Page 21 of 24 + 01104-066 01104-067 01104-068 AD8571/AD8572/AD8574 OUTLINE DIMENSIONS 3.20 3.10 3.00 3.00 2.80 2.90 8 5 8 5 5.15 3.20 4.90 4.50 3.00 4.65 4.40 6.40 BSC 1 2.80 4 4.30 PIN 1 1 4 IDENTIFIER PIN 1 0.65 BSC 0.65 BSC 0.95 15° MAX 0.15 1.20 0.85 1.10 MAX 0.05 MAX 0.75 8° 0.80 0.75 0.30 0° 0.15 SEATING 0.23 COPLANARITY 0.20 6° 0.55 0.40 0.60 0.19 PLANE 0.10 0.05 0.09 0° 0.40 0.09 0.25 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AA COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 71. 8-Lead Thin Shrink Small Outline Package [TSSOP] Figure 69. 8-Lead Mini Small Outline Package [MSOP] (RU-8) (RM-8) Dimensions shown in millimeters Dimensions shown in millimeters 5.10 5.00 (0.1968) 5.00 4.80 (0.1890) 4.90 85 14 8 4.00 (0.1574) 6.20 (0.2441) 4.50 1 5.80 (0.2284) 3.80 (0.1497) 4 6.40 4.40 BSC 4.30 1 7 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) PIN 1 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.65 BSC 0.51 (0.0201) COPLANARITY 1.05 1.27 (0.0500) 1.20 0.10 0.31 (0.0122) 1.00 0.25 (0.0098) 0.20 MAX SEATING 0.40 (0.0157) 0.80 PLANE 0.17 (0.0067) 0.09 0.75 8° 0.15 0.60 SEATING 0° COMPLIANT TO JEDEC STANDARDS MS-012-AA 0.05 0.45 0.30 PLANE COPLANARITY CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.19 0.10 (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP] Figure 70. 8-Lead Standard Small Outline Package [SOIC_N] (RU-14) Narrow Body (R-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) Rev. E | Page 22 of 24 10-07-2009-B 012407-A 061908-A AD8571/AD8572/AD8574 8.75 (0.3445) 8.55 (0.3366) 8 14 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 73. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8571ARZ −40°C to +125°C 8-Lead SOIC_N R-8 AD8571ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8571ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8571ARMZ −40°C to +125°C 8-Lead MSOP RM-8 AJA# AD8571ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 AJA# AD8572AR −40°C to +125°C 8-Lead SOIC_N R-8 AD8572AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8572AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8572ARZ −40°C to +125°C 8-Lead SOIC_N R-8 AD8572ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8572ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8572ARUZ −40°C to +125°C 8-Lead TSSOP RU-8 AD8572ARUZ-REEL −40°C to +125°C 8-Lead TSSOP RU-8 AD8574AR −40°C to +125°C 14-Lead SOIC_N R-14 AD8574AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14 AD8574AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 AD8574ARZ −40°C to +125°C 14-Lead SOIC_N R-14 AD8574ARZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14 AD8574ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 AD8574ARU −40°C to +125°C 14-Lead TSSOP RU-14 AD8574ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14 AD8574ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 AD8574ARUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. Rev. E | Page 23 of 24 060606-A AD8571/AD8572/AD8574 NOTES ©1999–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01104-0-2/11(E) Rev. E | Page 24 of 24