ANALOG DEVICES AD8567

16 V Rail-to-Rail Operational Amplifiers AD8565/AD8566/AD8567 FEATURES PIN CONFIGURATIONS Single-supply operation: 4.5 V to 16 V AD8565 OUT 1 5 V– Input capability beyond the rails V+ 2 Rail-to-rail output swing Continuous output current: 35 mA 3 4 +IN –IN TOP VIEW Peak output current: 250 mA (Not to Scale) Offset voltage: 10 mV Figure 1. 5-Lead SC70 Pin Configuration Slew rate: 6 V/μs Unity gain stable with large capacitive loads AD8566 1 OUT A 8 V+ Supply current: 700 μA per amplifier Qualified for automotive applications –IN A 2 7 OUT B APPLICATIONS +IN A36 –IN B LCD reference drivers V– 45 +IN B TOP VIEW Portable electronics (Not to Scale) Communications equipment Figure 2. 8-Lead MSOP Pin Configuration Automotive infotainment systems GENERAL DESCRIPTION 1 OUT A 14 OUT D The AD8565/AD8566/AD8567 are low cost, single-supply, rail- –IN A 2 13 –IN D to-rail input and output operational amplifiers optimized for LCD monitor applications. They are built on an advanced high +IN A 3 12 +IN D voltage CBCMOS process. The AD8565 contains a single AD8567 amplifier, the AD8566 has two amplifiers, and the AD8567 has TOP VIEW V+ 4 11 V– (Not to Scale) four amplifiers. 510 +IN B +IN C These LCD op amps have high slew rates, 35 mA continuous output drive, 250 mA peak output drive, and a high capacitive –IN B 6 9 –IN C load drive capability. They have a wide supply range and offset voltages below 10 mV. The AD8565/AD8566/AD8567 are ideal 7 8 OUT C OUT B for LCD grayscale reference buffer and VCOM applications. Figure 3. 14-Lead TSSOP Pin Configuration The AD8565/AD8566/AD8567 are specified over the −40°C to +85°C temperature range. The AD8565 single is available in a 5- lead SC70 package. The AD8566 dual is available in an 8-lead MSOP package. The AD8567 quad is available in a 14-lead 16 15 14 13 TSSOP package and a 16-lead LFCSP package. 1 12 –IN A –IN D AD8567 2 11 +IN A +IN D The AD8566WARMZ is the automotive grade version. TOP VIEW V+ 3 10 V– (Not to Scale) 4 9 +IN B +IN C 5 6 7 8 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO PIN 3, THAT IS, V+. 2. NC = NO CONNECT. Figure 4. 16-Lead LFCSP Pin Configuration Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2001–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. –IN B NC OUT B OUT A OUT C OUT D NC –IN C 01909-001 01909-002 01909-004 01909-003 AD8565/AD8566/AD8567 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation .........................................................................9 Applications ....................................................................................... 1 Input Overvoltage Protection ......................................................9 General Description ......................................................................... 1 Output Phase Reversal ............................................................... 10 Pin Configurations ........................................................................... 1 Power Dissipation....................................................................... 10 Revision History ............................................................................... 2 Thermal Pad—AD8567 ............................................................. 10 Specifications ..................................................................................... 3 Total Harmonic Distortion + Noise (THD + N)........................ 11 Electrical Characteristics ............................................................. 3 Short-Circuit Output Conditions............................................. 11 Absolute Maximum Ratings ............................................................ 4 LCD Panel Applications ............................................................ 11 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 12 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 13 Typical Performance Characteristics ............................................. 5 REVISION HISTORY 3/10—Rev. F to Rev. G Changes to Figure 6 and Figure 8 .................................................... 5 Changes to Figure 4 .......................................................................... 1 Added the Thermal Pad—AD8567 Section ................................ 10 Changes to the Thermal Pad—AD8567 Section ........................ 10 Changes to Ordering Guide .......................................................... 13 3/04—Rev. B to Rev. C 1/10—Rev. E to Rev. F Changes to Specifications ................................................................. 2 Changes to Applications and General Description Sections ...... 1 Changes to TPC 4 .............................................................................. 4 Changes to Figure 4 .......................................................................... 1 Changes to TPC 10 ............................................................................ 5 Added Exposed Pad Notation to Outline Dimensions ............. 12 Changes to TPC 14 ............................................................................ 6 Changes to Ordering Guide .......................................................... 13 Changes to TPC 20 ............................................................................ 7 12/03—Rev. A to Rev. B 8/07—Rev. D to Rev. E Updated Ordering Guide ................................................................. 3 Changes to Features Section............................................................ 1 Updated Outline Dimensions ....................................................... 11 Changes to Phase Margin ................................................................ 3 Changes to Table 2 ............................................................................ 4 10/01—Rev. 0 to Rev. A Changes to Figure 30 ...................................................................... 10 Edit to 16-Lead CSP and 5-Lead SC70 Pin Configuration .......... 1 Edit to Ordering Guide ..................................................................... 3 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 13 7/01—Revision 0: Initial Version 2/06—Rev. C to Rev. D Updated Format .................................................................. Universal Rev. G | Page 2 of 16 AD8565/AD8566/AD8567 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 4.5 V ≤ V ≤ 16 V, V = V /2, T = 25°C, unless otherwise noted. S CM S A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 2 10 mV Offset Voltage Drift ΔV /ΔT −40°C ≤ T ≤ +85°C 5 µV/°C OS A Input Bias Current I 80 600 nA B −40°C ≤ TA ≤ +85°C 800 nA Input Offset Current IOS 1 80 nA −40°C ≤ TA ≤ +85°C 130 nA Input Voltage Range Common-mode input −0.5 V + 0.5 V S Common-Mode Rejection Ratio CMRR V = 0 V to V , −40°C ≤ T ≤ +85°C 54 95 dB CM S A Large Signal Voltage Gain A R = 10 kΩ, V = 0.5 V to (V − 0.5 V) 3 10 V/mV VO L O S Input Impedance ZIN 400 kΩ Input Capacitance CIN 1 pF OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 100 µA VS − 0.005 V VS = 16 V, IL = 5 mA 15.85 15.95 V −40°C ≤ T ≤ +85°C 15.75 V A V = 4.5 V, I = 5 mA 4.2 4.38 V S L −40°C ≤ T ≤ +85°C 4.1 V A Output Voltage Low VOL IL = 100 µA 5 mV VS = 16 V, IL = 5 mA 42 150 mV −40°C ≤ TA ≤ +85°C 250 mV V = 4.5 V, I = 5 mA 95 300 mV S L −40°C ≤ T ≤ +85°C 400 mV A Continuous Output Current I 35 mA OUT Peak Output Current IPK VS = 16 V 250 mA POWER SUPPLY Supply Voltage VS 4.5 16 V Power Supply Rejection Ratio PSRR VS = 4 V to 17 V, −40°C ≤ T A ≤ +85°C 70 90 dB Supply Current/Amplifier ISY VO = VS/2, no load 700 850 µA −40°C ≤ T ≤ +85°C 1 mA A DYNAMIC PERFORMANCE Slew Rate SR RL = 10 kΩ, CL = 200 pF 4 6 V/µs Gain Bandwidth Product GBP R = 10 kΩ, C = 10 pF 5 MHz L L Phase Margin Ø R = 10 kΩ, C = 10 pF 65 Degrees m L L Channel Separation 75 dB NOISE PERFORMANCE Voltage Noise Density e f = 1 kHz 26 nV/√Hz n e f = 10 kHz 25 nV/√Hz n Current Noise Density in f = 10 kHz 0.8 pA/√Hz Rev. G | Page 3 of 16 AD8565/AD8566/AD8567 ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL RESISTANCE Parameter Rating θ is specified for worst-case conditions, that is, for a device JA soldered onto a circuit board for surface-mount packages. Supply Voltage (V ) 18 V S Input Voltage −0.5 V to V + 0.5 V S Table 3. Thermal Resistance Differential Input Voltage V S Package Type θ θ Unit JA JC Storage Temperature Range −65°C to +150°C 5-Lead SC70 (KS-5) 376 126 °C/W Operating Temperature Range −40°C to +85°C 8-Lead MSOP (RM-8) 210 45 °C/W Junction Temperature Range −65°C to +150°C 14-Lead TSSOP (RU-14) 180 35 °C/W Lead Temperature (Soldering, 60 sec) 300°C 1 1 16-Lead LFCSP (CP-16-4) 38 30 °C/W 1 DAP is soldered down to PCB. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ESD CAUTION rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. G | Page 4 of 16 AD8565/AD8566/AD8567 TYPICAL PERFORMANCE CHARACTERISTICS 0 1000 4.5V ≤ V ≤ 16V S V = V /2 CM S T = 25°C A –0.25 100 –0.50 V = 16V S –0.75 V = 4.5V S 10 –1.00 –1.25 1 –1.50 10 100 1k 10k –40 25 85 TEMPERATURE (°C) FREQUENCY (Hz) Figure 8. Voltage Noise Density vs. Frequency Figure 5. Input Offset Voltage vs. Temperature 1.0 10 V = V /2 O S 4.5V ≤ V ≤ 16V S A = +1 V T = 25°C A T = 25°C A 0.8 0.6 1 0.4 0.2 0 0.1 0 2 4 6 8 10 12 14 16 18 10 100 1k 10k SUPPLY VOLTAGE (V) FREQUENCY (Hz) Figure 6. Current Noise Figure 9. Supply Current/Amplifier vs. Supply Voltage 0.80 V = 16V S V = V /2 R = 10kΩ CM S L C = 100pF L 0.75 A = +1 V T = 25°C V = 16V A S 0.70 0.65 0.60 V = 4.5V S 0.55 0.50 25 85 –40 FREQUENCY (1µs/DIV) TEMPERATURE (°C) Figure 7. Small Signal Transient Response Figure 10. Supply Current/Amplifier vs. Temperature Rev. G | Page 5 of 16 CURRENT NOISE DENSITY (pA/√Hz) INPUT OFFSET VOLTAGE (mV) TIME (50mV/DIV) 01909-007 01909-005 01909-006 VOLTAGE NOISE DENSITY (nV/√Hz) SUPPLY CURRENT/AMPLIFIER (mA) SUPPLY CURRENT/AMPLIFIER (mA) 01909-010 01909-009 01909-008 AD8565/AD8566/AD8567 100 V = 16V S V = 16V S 100 R = 10kΩ L 90 V = 100mV p-p IN C = 40pF L R = 10kΩ L 80 0 T = 25°C 80 A A = +1 V 45 T = 25°C 60 A 70 90 40 60 –OS 20 135 50 180 0 40 +OS 225 30 270 20 10 0 1k 10k 100k 1M 10M 100M 10 100 1k FREQUENCY (Hz) LOAD CAPACITANCE (pF) Figure 11. Small Signal Overshoot vs. Load Capacitance Figure 14. Open-Loop Gain and Phase Shift vs. Frequency 18 1k T = 25°C A 16 14 100 12 V = 4.5V S 10 V = 16V S 10 8 6 V = 16V S A = +1 V 1 4 R = 10kΩ L DISTORTION < 1% 2 T = 25°C A 0 0.1 10 100 1k 10k 100k 1M 10M 0.001 0.01 0.1 1 10 100 FREQUENCY (Hz) LOAD CURRENT (mA) Figure 12. Closed-Loop Output Swing vs. Frequency Figure 15. Output Voltage to Supply Rail vs. Load Current 150 4.5V ≤ V ≤ 16V S I = 5mA SINK 60 R = 10kΩ L 135 C = 40pF L 50 T = 25°C A 120 A = –100 VCL V = 4.5V S 40 105 30 90 A = –10 VCL 20 75 10 60 A = +1 VCL V = 16V S 0 45 30 15 10 100 1k 10k 100k 1M 10M 0 –40 25 85 FREQUENCY (Hz) TEMPERATURE (°C) Figure 16. Output Voltage Swing to Rail vs. Temperature Figure 13. Closed-Loop Gain vs. Frequency Rev. G | Page 6 of 16 OUTPUT SWING (V p-p) CLOSED-LOOP GAIN (dB) OVERSHOOT (%) 01909-011 01909-013 01909-012 GAIN (dB) OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (mV) PHASE SHIFT (Degrees) 01909-016 01909-015 01909-014 AD8565/AD8566/AD8567 150 160 I = 5mA SOURCE V = 16V S 135 140 T = 25°C A V = 4.5V S 120 120 100 105 90 80 75 60 +PSRR V = 16V 40 60 –PSRR S 45 20 0 30 15 –20 –40 0 –40 25 85 100 1k 10k 100k 1M 10M TEMPERATURE (°C) FREQUENCY (Hz) Figure 17. Output Voltage Swing to Rail vs. Temperature Figure 20. Power Supply Rejection Ratio vs. Frequency 500 V = 16V S A = +1 V R = 10kΩ 450 L T = 25°C A A = +1 V 400 T = 25°C A 350 V = 4.5V 300 S 250 200 150 100 50 V = 16V S 0 100 1k 10k 100k 1M 10M TIME (40µs/DIV) FREQUENCY (Hz) Figure 18. Closed-Loop Output Impedance vs. Frequency Figure 21. No Phase Reversal 1.8k V = 16V S V = 16V S 140 T = 25°C 1.6k A T = 25°C A 120 1.4k 100 1.2k 80 1.0k 60 800 40 600 20 0 400 200 0 10 100 1k 10k 100k 1M 10M –10 –8 –6 –4 –2 0 2 4 6 8 10 FREQUENCY (Hz) INPUT OFFSETVOLTAGE (mV) Figure 19. Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 22. Input Offset Voltage Distribution Rev. G | Page 7 of 16 CMRR (dB) IMPEDANCE (Ω) OUTPUT VOLTAGE (mV) 01909-017 01909-019 01909-018 POWER SUPPLY REJECTION RATIO (dB) QUANTITY (Amplifiers) VOLTAGE (3V/DIV) 01909-021 01909-022 01909-020 AD8565/AD8566/AD8567 7 5 4 6 3 5 2 1 4 V = 4.5V S 0 V = 16V S 3 –1 –2 2 V = 16V S –3 A = +1 V 1 R = x L –4 T = 25°C A 0 –5 0 2 4 6 8 10 12 14 16 –40 25 85 COMMON-MODE VOLTAGE (V) TEMPERATURE (°C) Figure 23. Input Offset Current vs. Temperature Figure 26. Frequency vs. Common-Mode Voltage (V = 16 V) S 0 6 V = 5V V = V /2 CM S S A = +1 V –50 5 R = 10kΩ L T = 25°C V = 16V A S –100 4 –150 V = 4.5V S 3 –200 2 –250 1 –300 –350 0 –40 25 85 0 1 2 3 4 5 TEMPERATURE (°C) COMMON-MODE VOLTAGE (V) Figure 24. Input Bias Current vs. Temperature Figure 27. Frequency vs. Common-Mode Voltage (V = 5 V) S –20 –40 –60 –80 4.5V –100 –120 16V –140 –160 –180 50 100 1k 10k 60k FREQUENCY (Hz) Figure 25. Channel A vs. Channel B Crosstalk Rev. G | Page 8 of 16 CROSSTALK (dB) INPUT BIAS CURRENT (nA) INPUT OFFSET CURRENT (nA) 01909-024 01909-023 01909-025 BANDWIDTH (MHz) BANDWIDTH (MHz) 01909-027 01909-026 AD8565/AD8566/AD8567 THEORY OF OPERATION The AD8565/AD8566/AD8567 are designed to drive large The benefit of this type of input stage is low bias current. The capacitive loads in LCD applications. They have high output input bias current is the sum of base currents of Q4 to Q5 and current drive and rail-to-rail input/output operation and are Q6 to Q8 over the range from (VNEG + 1 V) to (VPOS − 1 V). powered from a single 16 V supply. They are also intended for Outside this range, the input bias current is dominated by the other applications where low distortion and high output current sum of base currents of Q10 to Q11 for input signals close to drive are needed. V and of Q6 to Q8 (Q10 to Q11) for signals close to V . NEG POS From this type of design, the input bias current of the AD8565/ Figure 28 shows a simplified equivalent circuit for the AD8565/ AD8566/AD8567 not only exhibits different amplitude but also AD8566/AD8567. The rail-to-rail bipolar input stage is com- exhibits different polarities. Figure 29 provides the characteris- posed of two PNP differential pairs, Q4 to Q5 and Q10 to Q11, tics of the input bias current vs. the common-mode voltage. It is operating in series with diode protection networks, D1 to D2. important to keep in mind that the source impedances driving Diode network D1 to D2 serves as protection against large the inputs are balanced for optimum dc and ac performance. transients for Q4 to Q5 to accommodate rail-to-rail input swing. 1000 D5 to D6 protect Q10 to Q11 against Zenering. In normal oper- V = 16V S 800 ation, Q10 to Q11 are off, and their input stage is buffered from T = 25°C A the operational amplifier inputs by Q6 to D3 and Q8 to D4. 600 Operation of the input stage is best understood as a function of 400 applied common-mode voltage: when the inputs of the AD8565/ 200 AD8566/AD8567 are biased midway between the supplies, the 0 differential signal path gain is controlled by resistive loads Q4 to –200 Q5 (via R9, R10). As the input common-mode level is reduced –400 toward the negative supply (V or GND), the input transistor NEG –600 current sources, I1 and I2, are forced into saturation, thereby forcing the Q6 to D3 and Q8 to D4 networks into cutoff. –800 However, Q4 to Q5 remain active, providing input stage gain. –1000 0 2 4 6 8 10 12 14 16 Inversely, when common-mode input voltage is increased INPUT COMMON-MODE VOLTAGE (V) toward the positive supply, Q4 to Q5 are driven into cutoff, Q3 Figure 29. AD8565/AD8566/AD8567 Input Bias Current vs. Common-Mode Voltage is driven into saturation, and Q4 becomes active, providing bias to the Q10 to Q11 differential pair. The point at which the Q10 to To achieve rail-to-rail output performance, the AD8565/ Q11 differential pair becomes active is approximately equal to AD8566/AD8567 design uses a complementary common- (V − 1 V). POS source (or gmRL) output. This con-figuration allows output V POS voltages to approach the power supply rails, particularly if the output transistors are allowed to enter the triode region on R1 extremes of signal swing, which are limited by VGS, the transistor sizes, and output load current. In addition, this type BIAS LINE Q3 Q4 of output stage exhibits voltage gain in an open-loop gain configuration. The amount of gain depends on the total load D1 D2 resistance at the output of the AD8565/AD8566/AD8567. R3 R4 INPUT OVERVOLTAGE PROTECTION Q6 Q8 C1 V+ V– Q4 Q5 As with any semiconductor device, whenever the input exceeds either supply voltages, attention needs to be paid to the input R5 R6 D3 D4 overvoltage characteristics. As an overvoltage occurs, the amplifier C2 could be damaged, depending on the voltage level and the Q10 Q11 D5 magnitude of the fault current. When the input voltage exceeds either supply by more than 0.6 V, internal positive-negative (pn) junctions allow current to flow from the input to the supplies. I1 I2 D6 FOLDED CASCADE R9 R10 V NEG Figure 28. AD8565/AD8566/AD8567 Equivalent Input Circuit Rev. G | Page 9 of 16 01909-028 INPUT BIAS CURRENT (nA) 01909-029 AD8565/AD8566/AD8567 This input current is not inherently damaging to the device as The power dissipated by the device can be calculated as long as it is limited to 5 mA or less. If a condition exists using P = (V − V ) × I DISS S OUT LOAD the AD8565/AD8566/AD8567 where the input exceeds the where: supply more than 0.6 V, an external series resistor should be VS is the supply voltage. added. The size of the resistor can be calculated by using the VOUT is the output voltage. maximum over-voltage divided by 5 mA. This resistance should ILOAD is the output load current. be placed in series with either input exposed to an overvoltage. Figure 30 shows the maximum power dissipation vs. temper- OUTPUT PHASE REVERSAL ature. To achieve proper operation, use the previous equation to The AD8565/AD8566/AD8567 are immune to phase reversal. calculate P for a specific package at any given temperature or DISS Although device output does not change phase, large currents use Figure 30. due to input overvoltage could damage the device. In applica- 1.25 tions where the possibility of an input voltage exceeding the 16-LEAD LFCSP supply voltage exists, overvoltage protection should be used as 1.00 described in the Input Overvoltage Protection section. POWER DISSIPATION 0.75 14-LEAD TSSOP The maximum allowable internal junction temperature of 8-LEAD MSOP 150°C limits the maximum power dissipation of AD8565/ 0.50 AD8566/AD8567 devices. As the ambient temperature 5-LEAD SC70 increases, the maximum power dissipated by AD8565/AD8566/ AD8567 devices must decrease linearly to maintain maximum 0.25 junction temperature. If this maximum junction temperature is exceeded momentarily, the device still operates properly once 0 –35 –15 5 25 45 65 85 the junction temperature is reduced below 150°C. If the AMBIENT TEMPERATURE (°C) maximum junction temperature is exceeded for an extended Figure 30. Maximum Power Dissipation vs. Temperature for 5-Lead SC70, period, overheating could lead to permanent damage of the 8-Lead MSOP, 14-Lead TSSOP, and 16-Lead LFCSP Packages device. THERMAL PAD—AD8567 The maximum safe junction temperature, T JMAX, is 150°C. Using The AD8567 LFCSP comes with a thermal pad that is attached the following formula, the maximum power that an AD8565/ to the substrate. This substrate is connected to the most positive AD8566/AD8567 device can safely dissipate as a function of supply, that is, Pin 3 in the LFCSP package and Pin 4 in the temperature can be obtained: TSSOP package. To be electrically safe, the thermal pad should P = T − T /θ DISS JMAX A JA be soldered to an area on the board that is electrically isolated where: or connected to V . Attaching the thermal pad to ground DD P is the AD8565/AD8566/AD8567 power dissipation. DISS adversely affects the performance of the part. TJMAX is the AD8565/AD8566/AD8567 maximum allowable Soldering down this thermal pad dramatically improves the junction temperature (150°C). heat dissipation of the package. It is necessary to attach vias that TA is the ambient temperature of the circuit. connect the soldered thermal pad to another layer on the board. θJA is the AD8565/AD8566/AD8567 package thermal resistance, This provides an avenue to dissipate the heat away from the junction-to-ambient. part. Without vias, the heat is isolated directly under the part. Rev. G | Page 10 of 16 MAXIMUM POWER DISSIPATION (W) 01909-030 AD8565/AD8566/AD8567 TOTAL HARMONIC DISTORTION + NOISE (THD + N) LCD PANEL APPLICATIONS The AD8565/AD8566/AD8567 feature low total harmonic dis- The AD8565/AD8566/AD8567 amplifier is designed for LCD tortion. Figure 31 shows THD + N vs. frequency. The THD + N panel applications or applications where large capacitive load over the entire supply range is below 0.008%. When the device drive is required. It can instantaneously source/sink greater than is powered from a 16 V supply, the THD + N stays below 250 mA of current. At unity gain, it can drive 1 µF without 0.003%. Figure 31 shows the AD8566 in a unity noninverting compensation. This makes the AD8565/AD8566/AD8567 ideal configuration. for LCD V driver applications. COM 10 To evaluate the performance of the AD8565/AD8566/AD8567, a test circuit was developed to simulate the VCOM driver application for an LCD panel. Figure 32 shows the test circuit. Series capacitors and resistors connected to the output of the op 1 amp represent the load of the LCD panel. The 300 Ωand 3 kΩ feedback resistors are used to improve settling time. This test circuit simulates the worst-case scenario for a V . It drives a COM represented load that is connected to a signal switched symmet- 0.1 V = ±2.5V rically around VCOM. S V = ±8V S Figure 33 shows a scope photo of the instantaneous output peak current capability of the AD8565/AD8566/AD8567. 0.01 20 100 1k 10k 30k FREQUENCY (Hz) 300Ω INPUT 0VTO 8V SQUARE WAVE WITH Figure 31. THD + N vs. Frequency 15.6µs PULSE WIDTH 8V 3kΩ SHORT-CIRCUIT OUTPUT CONDITIONS 10Ω 10Ω 10Ω 10Ω The AD8565/AD8566/AD8567 do not have internal short- 4V circuit protection circuitry. As a precautionary measure, it is 10nF 10nF 10nF 10nF MEASURE recommended not to short the output directly to the positive CURRENT 10Ω TO 20Ω power supply or to ground. Figure 32. V Test Circuit with Supply Voltage at 16 V COM It is not recommended to operate the AD8565/AD8566/AD8567 with more than 35 mA of continuous output current. The output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using 100 90 V S R ≥ X 35 mA CH 2 = 100mA/DIV For a 5 V single-supply operation, R should have a minimum X value of 143 Ω. CH 1 = 5V/DIV 10 0% TIME (2µs/DIV) Figure 33. Scope Photo of the VCOM Instantaneous Peak Current Rev. G | Page 11 of 16 THD+N (%) 01909-031 01909-033 01909-032 AD8565/AD8566/AD8567 OUTLINE DIMENSIONS 3.20 3.00 2.80 2.20 8 5 5.15 2.00 3.20 1.80 4.90 3.00 4.65 1 2.80 4 2.40 1.35 5 4 2.10 1.25 PIN 1 1 2 3 1.80 1.15 IDENTIFIER 0.65 BSC 0.65 BSC 0.95 15° MAX 1.00 0.40 1.10 0.85 0.90 1.10 MAX 0.10 0.80 0.70 0.75 0.80 0.15 0.23 0.46 6° 0.55 0.40 0.22 SEATING 0.10 MAX 0.05 0.09 0.36 0° 0.30 0.40 0.08 PLANE 0.25 COPLANARITY COPLANARITY 0.15 0.26 0.10 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 35. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] Figure 34. 8-Lead Mini Small Outline Package [MSOP] (KS-5) (RM-8) Dimensions shown in millimeters Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 8° 0.15 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. G | Page 12 of 16 100709-B 061908-A 072809-A 2.25 2.10 SQ 1.95 AD8565/AD8566/AD8567 4.00 0.60 MAX BSC SQ (BOTTOM VIEW) 0.60 MAX PIN 1 INDICATOR 13 16 1 12 PIN 1 0.65 BSC INDICATOR TOP 3.75 VIEW BSC SQ 0.75 9 0.60 4 8 5 0.50 0.25 MIN 0.80 MAX 12° MAX 1.95 BSC 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF 1.00 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.85 0.35 FUNCTION DESCRIPTIONS 0.20 REF 0.80 0.30 COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 0.25 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Temperature Package 1 Model Abs Max (V) Range Package Description Option Branding AD8565AKSZ-REEL7 18 −40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-5 A0N AD8566ARM-R2 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 ATA AD8566ARM-REEL 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 ATA AD8566ARMZ-R2 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 ATA# AD8566ARMZ-REEL 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 ATA# 2 AD8566WARMZ-REEL 18 −40°C to +85°C 8-Lead Mini Small Outline Package (MSOP) RM-8 LG3 AD8567ARU 18 −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14 AD8567ARU-REEL 18 −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14 AD8567ARUZ 18 −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14 AD8567ARUZ-REEL 18 −40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14 AD8567ACP-R2 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 AD8567ACP-REEL7 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 AD8567ACPZ-R2 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 AD8567ACPZ-REEL 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 AD8567ACPZ-REEL7 18 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4 1 Z = RoHS Compliant Part. 2 Qualified for automotive applications. Rev. G | Page 13 of 16 072808-A AD8565/AD8566/AD8567 NOTES Rev. G | Page 14 of 16 AD8565/AD8566/AD8567 NOTES Rev. G | Page 15 of 16 AD8565/AD8566/AD8567 NOTES ©2001–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01909-0-3/10(G) Rev. G | Page 16 of 16