ANALOG DEVICES AD8557

Digitally Programmable Sensor Signal Amplifier AD8557 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD Very low offset voltage: 12 μV maximum over temperature Very low input offset voltage drift: 65 nV/°C maximum VCLAMP VDD A4 High CMRR: 96 dB minimum P3 VNEG R4 R6 Digitally programmable gain and output offset voltage A1 VSS Gain range from 28 to 1300 R1 VDD Qualified for automotive applications VSS P1 Single-wire serial interface R3 A3 Stable with any capacitive load VOUT P2 SOIC_N and LFCSP_VQ packages VDD VSS R2 2.7 V to 5.5 V operation R5 R7 A2 APPLICATIONS P4 VPOS VDD Automotive sensors VSS Pressure and position sensors DIGIN Precision current sensing Thermocouple amplifiers VSS Industrial weigh scales Figure 1. Strain gages GENERAL DESCRIPTION The AD8557 is a zero drift, sensor signal amplifier with digitally also includes a pull-up current source at the input pins and a programmable gain and output offset. Designed to easily and pull-down current source at the VCLAMP pin. Output accurately convert variable pressure sensor and strain bridge clamping set via an external reference voltage allows the outputs to a well-defined output voltage range, the AD8557 AD8557 to drive lower voltage ADCs safely and accurately. accurately amplifies many other differential or single-ended When used in conjunction with an ADC referenced to the same sensor outputs. The AD8557 uses the Analog Devices, Inc. supply, the system accuracy becomes immune to normal supply patented low noise auto-zero and DigiTrim® technologies to voltage variations. Output offset voltage can be adjusted with a create an accurate and flexible signal processing solution in a resolution of better than 0.4% of the difference between VDD compact footprint. and VSS. A lockout trim after gain and offset adjustment Gain is digitally programmable in a wide range from 28 to 1300 further ensures field reliability. through a serial data interface. Gain adjustment can be fully The AD8557 is fully specified from −40°C to +125°C. simulated in circuit and then permanently programmed with Operating from single-supply voltages of 2.7 V to 5.5 V, the reliable polyfuse technology. Output offset voltage is also AD8557 is offered in an 8-lead SOIC_N, and a 4 mm × 4 mm, digitally programmable and is ratiometric to the supply voltage. 16-lead LFCSP_VQ. In addition to extremely low input offset voltage and input offset voltage drift and very high dc and ac CMRR, the AD8557 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 06013-001 AD8557 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Gain Values ................................................................................. 15 Functional Block Diagram .............................................................. 1 Open Wire Fault Detection ....................................................... 16 General Description ......................................................................... 1 Shorted Wire Fault Detection ................................................... 16 Revision History ............................................................................... 2 Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 16 Specifications ..................................................................................... 3 Device Programming ................................................................. 16 Absolute Maximum Ratings ............................................................ 5 Outline Dimensions ....................................................................... 21 Thermal Resistance ...................................................................... 5 Ordering Guide .......................................................................... 22 ESD Caution .................................................................................. 5 Automotive Products ................................................................. 22 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 6/11—Rev. B to Rev. C Added EPAD Note to Figure 3 and Table 5 ................................... 6 Changes to Open Wire Fault Detection Section and Table 8 ... 16 7/10—Rev. A to Rev. B Changes to Features Section and Figure 1..................................... 1 Changes to Figure 45 ...................................................................... 14 Changes to Simulation Mode Section and Programming Mode Section................................................................................... 18 Changes to Ordering Guide .......................................................... 22 Added Automotive Products Section........................................... 22 1/08—Rev. 0 to Rev. A Changes to Theory of Operation Section .................................... 14 Changes to Determining Optimal Gain and Offset Codes Section .................................................................................. 20 5/07—Revision 0: Initial Version Rev. C | Page 2 of 24 AD8557 SPECIFICATIONS VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VOUT = 2.5 V, gain = 28, TA = −40°C to +125°C, unless otherwise specified. Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT STAGE Input Offset Voltage VOS 2 12 μV Input Offset Voltage Drift TCVOS 27 65 nV/°C Input Bias Current IB 10 18 25 nA Input Offset Current IOS 1 4 nA Input Voltage Range 0.6 3.8 V Common-Mode Rejection Ratio CMRR V = 0.9 V to 3.6 V, A = 28 75 85 dB CM V VCM = 0.9 V to 3.6 V, AV = 1300 96 112 dB Linearity VOUT = 0.2 V to 3.4 V 20 ppm VOUT = 0.2 V to 4.8 V 1000 ppm Differential Gain Accuracy Second stage gain = 10 to 70 1.6 % Differential Gain Accuracy Second stage gain = 100 to 250 2.5 % Differential Gain Temperature Coefficient Second stage gain = 10 to 250 15 40 ppm/°C DAC Accuracy Offset codes = 8 to 248 0.7 0.8 % Ratiometricity Offset codes = 8 to 248 50 ppm Output Offset Offset codes = 8 to 248 5 35 mV Temperature Coefficient 20 80 ppm FS/°C VCLAMP Clamp Input Bias Current ICLAMP 1.25 V to 5.0 V 200 nA Clamp Input Voltage Range 1.25 5.0 V OUTPUT STAGE Short-Circuit Current ISC Source −45 −25 mA ISC Sink 40 55 mA Output Voltage, Low V R = 10 kΩ to 5 V 30 mV OL L Output Voltage, High V R = 10 kΩ to 0 V 4.94 V OH L POWER SUPPLY Supply Current I VPOS = VNEG = 2.5 V, 1.8 mA SY VDAC code = 128, VOUT = 2.5 V Power Supply Rejection Ratio PSRR VDD = 2.7 V to 5.5 V 105 125 dB DYNAMIC PERFORMANCE Gain Bandwidth Product GBP First gain stage, T = 25°C 2 MHz A Second gain stage, TA = 25°C 8 MHz Settling Time ts To 0.1%, 4 V output step 8 µs NOISE PERFORMANCE Input Referred Noise f = 1 kHz, TA = 25°C 32 nV/√Hz Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz, TA = 25°C 0.5 µV p-p Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz, −100 dB T = 25°C A DIGITAL INTERFACE Input Current 2 µA DIGIN Pulse Width to Load 0 tw T = 25°C 0.05 10 µs 0 A DIGIN Pulse Width to Load 1 tw T = 25°C 50 µs 1 A Time Between Pulses at DIGIN tw T = 25°C 10 µs s A DIGIN Low TA = 25°C 0.2 × VDD V DIGIN High TA = 25°C 0.8 × VDD V DIGOUT Logic 0 T = 25°C 0.2 × VDD V A DIGOUT Logic 1 T = 25°C 0.8 × VDD V A Rev. C | Page 3 of 24 AD8557 VDD = 2.7 V, VSS = 0.0 V, V = 1.35 V, VOUT = 1.35 V, gain = 28, T = −40°C to +125°C, unless otherwise specified. CM A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT STAGE Input Offset Voltage V 2 12 µV OS Input Offset Voltage Drift T V 65 nV/°C C OS Input Bias Current I 10 18 25 nA B Input Offset Current IOS 1 4 nA Input Voltage Range 0.6 1.5 V Common-Mode Rejection Ratio CMRR VCM = 0.9 V to 1.5 V, AV = 28 71 82 dB V = 0.9 V to 1.5 V, A = 1300 96 112 dB CM V Linearity VOUT = 0.2 V to 1.8 V 20 ppm VOUT = 0.2 V to 2.5 V 1000 ppm Differential Gain Accuracy Second stage gain = 10 to 250 1.6 % Differential Gain Temperature Coefficient Second stage gain = 10 to 250 15 40 ppm/°C DAC Accuracy Offset codes = 8 to 248 0.7 0.8 % Ratiometricity Offset codes = 8 to 248 50 ppm Output Offset Offset codes = 8 to 248 5 35 mV Temperature Coefficient 20 80 ppm FS/°C VCLAMP Input Bias Current ICLAMP 1.25 V to 2.7 V 200 nA Input Voltage Range 1.25 2.7 V OUTPUT STAGE Short-Circuit Current I Source −12 −7 mA SC Sink 15 25 mA Output Voltage, Low VOL RL = 10 kΩ to 2.7 V 30 mV Output Voltage, High VOH RL = 10 kΩ to 0 V 2.64 V POWER SUPPLY Supply Current ISY VPOS = VNEG = 1.35 V, 1.8 mA VDAC code = 128, VOUT = 1.35 V Power Supply Rejection Ratio PSRR VDD = 2.7 V to 5.5 V 105 125 dB DYNAMIC PERFORMANCE Gain Bandwidth Product GBP First gain stage, TA = 25°C 2 MHz Second gain stage, TA = 25°C 8 MHz Settling Time t To 0.1%, 2 V output step, 8 µs s T = 25°C A NOISE PERFORMANCE Input Referred Noise f = 1 kHz 32 nV/√Hz Low Frequency Noise e p-p f = 0.1 Hz to 10 Hz 0.5 µV p-p n Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz −100 dB DIGITAL INTERFACE Input Current 2 µA DIGIN Pulse Width to Load 0 tw0 TA = 25°C 0.05 10 µs DIGIN Pulse Width to Load 1 tw1 TA = 25°C 50 µs Time Between Pulses at DIGIN tws TA = 25°C 10 µs DIGIN Low T = 25°C 0.2 × VDD V A DIGIN High T = 25°C 0.8 × VDD V A DIGOUT Logic 0 T = 25°C 0.2 × VDD V A DIGOUT Logic 1 TA = 25°C 0.8 × VDD V Rev. C | Page 4 of 24 AD8557 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for LFCSP_VQ packages. Supply Voltage 6 V Input Voltage VSS − 0.3 V to VDD + 0.3 V Table 4. Thermal Resistance 1 Differential Input Voltage ±6.0 V Package Type θ θ Unit JA JC Output Short-Circuit Duration to Indefinite 8-Lead SOIC_N (R) 158 43 °C/W VSS or VDD 16-Lead LFCSP_VQ (CP) 44 31.5 °C/W ESD (Human Body Model) 2000 V Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C ESD CAUTION Junction Temperature Range −65°C to +150°C Lead Temperature 300°C 1 Differential input voltage is limited to ±5.0 V or ± the supply voltage, whichever is less. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 5 of 24 AD8557 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 12 VOUT PIN 1 INDICATOR 11 NC DIGOUT 2 AD8557 NC 3 10 VCLAMP TOP VIEW DIGIN 4 9 NC (Not to Scale) VDD 1 8 VSS DIGOUT 2 AD8557 7 VOUT NOTES TOP VIEW 1. THE EXPOSED PAD SHOULD BE CONNECTED DIGIN 3 6 VCLAMP (Not to Scale) TO AVSS (PIN 14) OR LEFT UNCONNECTED. VNEG 4 5 VPOS 2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 2. 8-Lead SOIC_N Pin Configuration Figure 3. 16-Lead LFCSP_VQ Pin Configuration Table 5. Pin Function Descriptions Pin No. SOIC_N LFCSP_VQ Mnemonic Description 1 VDD Positive Supply Voltage. 2 2 DIGOUT In read mode, this pin functions as a digital output. 3 4 DIGIN Digital Input. 4 6 VNEG Negative Amplifier Input (Inverting Input). 5 8 VPOS Positive Amplifier Input (Noninverting Input). 6 10 VCLAMP Set Clamp Voltage at Output. 7 12 VOUT Amplifier Output. 8 VSS Negative Supply Voltage. 13, 14 DVSS, AVSS Negative Supply Voltage. 15, 16 DVDD, AVDD Positive Supply Voltage. 1, 3, 5, 7, 9, 11 NC Do Not Connect. EPAD EPAD Exposed Pad. The exposed pad should be connected to AVSS (Pin 14) or left unconnected. Rev. C | Page 6 of 24 06013-002 NC 5 16 AVDD VNEG 6 15 DVDD NC 7 14 AVSS VPOS 8 13 DVSS 06013-003 AD8557 TYPICAL PERFORMANCE CHARACTERISTICS 20 180 V = 5V SY 160 15 140 10 120 +125°C 5 100 +25°C 0 80 –5 60 –40°C –10 40 –15 20 –20 0 0 1 2 3 4 5 –10 –8 –6 –4 –2 0 2 4 6 8 10 COMMON-MODE VOLTAGE (V) INPUT OFFSET VOLTAGE (µV) Figure 4. Input Offset Voltage vs. Common-Mode Voltage, VSY = 5 V Figure 7. Input Offset Voltage Distribution, VSY = 2.7 V 10 15 V = 2.7V SY 8 10 6 4 +125°C 5 2 5V 0 0 +25°C –2 –5 –4 2.7V –40°C –6 –10 –8 –10 –15 0 0.5 1.0 1.5 2.0 2.5 –50 –25 0 25 50 75 100 125 150 175 COMMON-MODE VOLTAGE (V) TEMPERATURE (°C) Figure 5. Input Offset Voltage vs. Common-Mode Voltage, V = 2.7 V Figure 8. Input Offset Voltage vs. Temperature SY 180 30 160 25 140 120 20 100 15 80 60 10 40 5 20 0 0 –10 –8 –6 –4 –2 0 2 4 6 8 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 INPUT OFFSET VOLTAGE (µV ) T V (nV/°C) C OS Figure 9. T V at V = 5 V, −40°C ≤T ≤ +125°C Figure 6. Input Offset Voltage Distribution, VSY = 5 V C OS SY A Rev. C | Page 7 of 24 INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) NUMBER OF AMPLIFIERS 06013-006 06013-004 06013-005 INPUT OFFSET VOLTAGE (µV) NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 06013-009 06013-007 06013-008 AD8557 35 0.5 30 0.3 25 0.1 20 15 –0.1 10 –0.3 5 –0.5 0 05 10 15 20 25 30 35 40 45 50 55 60 65 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) T V (nV/°C) C OS Figure 10. T V at V = 2.7 V, −40°C ≤ T ≤ +125°C C OS SY A Figure 13. Input Offset Current vs. Temperature 20 3.0 –40°C 2.5 18 +125°C 2.0 –I 5V B +25°C 16 1.5 +I 5V B 1.0 14 0.5 V = 5V SY 12 0 123 4 –50 –25 0 25 50 75 100 125 150 175 05 TEMPERATURE (°C) DIGITAL INPUT VOLTAGE (V) Figure 11. Input Bias Current at VPOS, VNEG vs. Temperature, Figure 14. Digital Input Current vs. Digital Input Voltage (Pin 4) V = 5 V, 2.7 V SY 100 1000 +25°C +125°C 10 100 –40°C 1 V = 5V SY 0.1 10 123 4 05 123 4 05 COMMON-MODE VOLTAGE (V) VCLAMP VOLTAGE (V) Figure 12. Input Bias Current at VPOS, VNEG Figure 15. VCLAMP Current over Temperature at V = 5 V SY vs. Common-Mode Voltage, T = 25°C vs. VCLAMP Voltage A Rev. C | Page 8 of 24 INPUT BIAS CURRENT (nA) NUMBER OF AMPLIFIERS INPUT BIAS CURRENT (nA) 06013-013 06013-010 06013-011 I (nA) OS VCLAMP CURRENT (nA) DIGITAL INPUT CURRENT (µA) 06013-015 06013-014 06013-012 AD8557 1000 120 100 +125°C +25°C 80 HIGH GAIN +1300 100 60 –40°C LOW GAIN +28 40 20 V = 2.7V SY 10 0 0.5 1.0 1.5 2.0 2.5 03.0 0.1 1 10 100 1000 VCLAMP VOLTAGE (V) FREQUENCY (kHz) Figure 16. VCLAMP Current over Temperature at VSY = 2.7 V Figure 19. CMRR vs. Frequency, VSY = 5 V vs. VCLAMP Voltage 2.0 120 100 1.5 HIGH GAIN +1300 80 1.0 60 LOW GAIN +28 40 0.5 20 0 0 06 1 234 5 0.1 1 10 100 1000 V (V) FREQUENCY (kHz) SY Figure 20. CMRR vs. Frequency, VSY = 2.7 V Figure 17. Supply Current (I ) vs. Supply Voltage SY 150 3.0 130 CMRR GAIN +28 2.5 110 CMRR GAIN +448 2.0 I 5V SY 90 CMRR GAIN +1300 1.5 I 2.7V SY 70 1.0 50 0.5 30 10 0 –50 –25 0 25 50 75 100 125 150 175 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) TEMPERATURE (°C) Figure 21. CMRR vs. Temperature at Different Gains, V = 5 V Figure 18. Supply Current (I ) vs. Temperature SY SY Rev. C | Page 9 of 24 I (mA) I (mA) VCLAMP CURRENT (nA) SY SY 06013-018 06013-017 06013-016 CMRR (dB) CMRR (dB) CMRR (dB) 06013-021 06013-020 06013-019 AD8557 140 CMRR GAIN +28 120 CMRR GAIN +448 100 CHANNEL 1 16.6mV p-p CMRR GAIN +1300 80 1 60 40 20 0 –50 –25 0 25 50 75 100 125 150 175 CH1 10.0mV M 1.00s A CH1 –2.80mV TEMPERATURE (°C) Figure 25. Low Frequency Input Voltage Noise 0.1 Hz to 10 Hz, VSY = 2.7 V Figure 22. CMRR vs. Temperature at Different Gains, VSY = 2.7 V REF 502µV MARKER 20 000.0Hz 5dB/DIV RANGE 12.5mV 1.89µV/√Hz 70 V = 5V SY 60 HIGH GAIN +1300 62.28dB 50 40 30 LOW GAIN +28 28.9dB 20 10 0 –10 –20 0.1 1 10 100 1k 10k FREQUENCY (kHz) START .0 Hz STOP 1 000 000.0Hz RBW 100Hz VBW 300Hz ST 900s Figure 23. Input Voltage Noise Density vs. Frequency (0 Hz to 1000 kHz) Figure 26. Closed-Loop Gain vs. Frequency Measured at Output Pin, V = 5 V SY 70 V = 2.7V SY 60 HIGH GAIN +1300 62.28dB 50 CHANNEL 1 15.2mV p-p 40 30 1 LOW GAIN +28 28.9dB 20 10 0 –10 –20 CH1 10.0mV M 1.00s A CH1 –2.80mV 0.1 1 10 100 1k 10k FREQUENCY (kHz) Figure 24. Low Frequency Input Voltage Noise, 0.1 Hz to 10 Hz, V = 5 V SY Figure 27. Closed-Loop Gain vs. Frequency Measured at Output Pin, VSY = 2.7 V Rev. C | Page 10 of 24 CMRR (dB) VOLTAGE NOISE, GAIN = 28 × 1000 06013-023 06013-024 06013-022 GAIN (dB) GAIN (dB) VOLTAGE NOISE, GAIN = 28 × 1000 06013-025 06013-027 06013-026 AD8557 10 V = 5V SY 1 SOURCE 0.1 SINK 1 0.01 2 0.001 0.01 0.1 1 10 100 CH1 2.0V CH2 1.0V M 100µs A CH1 800mV T 23.80% LOAD CURRENT (mA) Figure 31. Power-On Response at 125°C Figure 28. Output Voltage to Supply Rail vs. Load Current 100 ILIMSINK 5V 50 ILIMSINK 2.7V 1 0 ILIMSRC 2.7V ILIMSRC 5V –50 2 –100 CH1 2.0V CH2 1.0V M 100µs A CH1 800mV –50 –25 0 25 50 75 100 125 150 175 T 23.80% TEMPERATURE (°C) Figure 32. Power-On Response at −40°C Figure 29. Output Short-Circuit vs. Temperature 175 PSRR 2.7V TO 5.5V 160 145 1 130 115 2 100 –50 –25 0 25 50 75 100 125 150 175 CH1 2.0V CH2 1.0V M 100µs A CH1 800mV TEMPERATURE (°C) T 23.80% Figure 33. PSRR vs. Temperature Figure 30. Power-On Response at 25°C Rev. C | Page 11 of 24 I (mA) OUTPUT VOLTAGE (V) SC 06013-041 06013-029 06013-028 PSRR (dB) 06013-043 06013-042 06013-030 AD8557 140 120 100 GAIN = +1300 80 2 60 GAIN = +28 40 20 0 0.01 0.1 0.1 1 10 100 CH2 1.0V M 10.0µs A CH2 0V T 23.20% FREQUENCY (kHz) Figure 37. Large Signal Response, C = 0 pF L Figure 34. PSRR vs. Frequency CHANNEL 3 +OVER 5.967% CHANNEL 3 –OVER 6.878% 2 3 CH2 1.0V M 10.0µs A CH2 0V CH3 50.0mV M 10.0µs A CH3 12.0mV T 23.20% T 24.20% Figure 38. Large Signal Response, C = 5 nF Figure 35. Small Signal Response, V = 5 V, C = 100 pF L SY L 60 V = 5V SY CHANNEL 3 GAIN = +28 +OVER 50 98.13% CHANNEL 3 40 –OVER 54.94% 30 20 3 10 0 –10 –20 0.1 1 10 100 1000 CH3 50.0mV M 10.0µs A CH2 480µV T 24.20% FREQUENCY (kHz) Figure 36. Small Signal Response, V = 5 V, C = 15 nF Figure 39. Output Impedance vs. Frequency SY L Rev. C | Page 12 of 24 PSRR (dB) 06013-033 06013-032 06013-031 Z (dB) OUT 06013-045 06013-044 06013-034 AD8557 V = ±2.5V V = ±2.5V SY SY GAIN = +28 GAIN = +1300 T = 25°C T = 25°C A A 1 1 2 2 CH1 50.0mV CH2 2.00V M 1.00µs A CH1 –21.0mV CH1 50.0mV CH2 2.00V M 1.00µs A CH1 57.0mV T 4.00µs Figure 43. Positive Overload Recovery (Gain = 1300) Figure 40. Positive Overload Recovery 10 5 1 2 V = ±2.5V 1 SY GAIN = +28 T = 25°C A 0.5 0.2 0.1 2 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k CH1 10.0mV CH2 2.00V M 10.0µs A CH1 –5.80mV FREQUENCY (Hz) Figure 41. Negative Overload Recovery Figure 44. THD + N vs. Frequency V = ±2.5V SY GAIN = +1300 T = 25°C A 1 2 CH1 10.0mV CH2 2.00V M 10.0µs A CH1 10.8mV T 10.00% Figure 42. Negative Overload Recovery (Gain = 1300) Rev. C | Page 13 of 24 06013-037 06013-036 06013-035 THD + N (%) 06013-038 06013-046 AD8557 THEORY OF OPERATION A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the to be monotonic. To preserve the ratiometric nature of the input differential amplifier. A1 and A2 are auto-zeroed op amps that signal, the DAC references are driven from VSS and VDD, and minimize input offset errors. P1 and P2 are digital potentiome- the DAC output can swing from VSS (Code 0) to VDD (Code ters, guaranteed to be monotonic. Programming P1 and P2 255). The 8-bit resolution is equivalent to 0.39% of the difference allows the first stage gain to be varied from 2.8 to 5.2 with 7-bit between VDD and VSS, for example, 19.5 mV with a 5 V supply. resolution (see Table 6 and Equation 1), giving a fine gain The DAC output voltage (VDAC) is given approximately by adjustment resolution of 0.49%. Because R1, R2, R3, P1, and P2 Code+ 0.5   each have a similar temperature coefficient, the first stage gain VDAC≈ (VDD−VSS)+VSS (2) 256   temperature coefficient is lower than 100 ppm/°C. where the temperature coefficient of VDAC is lower than Code     5.2  127    200 ppm/°C. GAIN1≈ 2.8× (1)   2.8   The amplifier output voltage (VOUT) is given by A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the VOUT=GAIN(VPOS−VNEG)+VDAC (3) differential amplifier. A3 is an auto-zeroed op amp that mini- where GAIN is the product of the first and second stage gains. mizes input offset errors and also includes an output buffer. P3 VDD and P4 are digital potentiometers, which allow the second stage VCLAMP gain to be varied from 10 to 250 in eight steps (see Table 7). R4, VDD A4 R5, R6, R7, P3, and P4 each have a similar temperature coefficient, P3 VNEG R4 R6 A1 so the second stage gain temperature coefficient is lower than VSS 100 ppm/°C. The output stage of A3 is supplied from a buffered R1 VDD VSS version of VCLAMP instead of VDD, allowing the positive P1 swing to be limited. A3 R3 VOUT A4 implements a voltage buffer, which provides the positive P2 VDD supply to the output stage of A3. Its function is to limit VOUT VSS R2 to a maximum value, useful for driving analog-to-digital R5 R7 A2 converters (ADC) operating on supply voltages lower than VPOS P4 VDD VDD. The input to A4, VCLAMP, has a very high input VSS resistance. It should be connected to a known voltage and not DIGIN be left floating. However, the high input impedance allows the clamp voltage to be set using a high impedance source, such as a VSS potential divider. If the maximum value of VOUT does not Figure 45. Functional Schematic need to be limited, VCLAMP should be connected to VDD. An 8-bit digital-to-analog converter (DAC) is used to generate a variable offset for the amplifier output. This DAC is guaranteed Rev. C | Page 14 of 24 06013-047 AD8557 GAIN VALUES Table 6. First Stage Gain vs. First Stage Gain Code First Stage First Stage First Stage First Stage Gain Code First Stage Gain Gain Code First Stage Gain Gain Code First Stage Gain Gain Code First Stage Gain 0 2.800 32 3.273 64 3.825 96 4.471 1 2.814 33 3.289 65 3.844 97 4.493 2 2.827 34 3.305 66 3.863 98 4.515 3 2.841 35 3.321 67 3.881 99 4.537 4 2.855 36 3.337 68 3.900 100 4.559 5 2.869 37 3.353 69 3.919 101 4.581 6 2.883 38 3.370 70 3.939 102 4.603 7 2.897 39 3.386 71 3.958 103 4.626 8 2.911 40 3.403 72 3.977 104 4.649 9 2.926 41 3.419 73 3.997 105 4.671 10 2.940 42 3.436 74 4.016 106 4.694 11 2.954 43 3.453 75 4.036 107 4.717 12 2.969 44 3.470 76 4.055 108 4.740 13 2.983 45 3.487 77 4.075 109 4.763 14 2.998 46 3.504 78 4.095 110 4.786 15 3.012 47 3.521 79 4.115 111 4.810 16 3.027 48 3.538 80 4.135 112 4.833 17 3.042 49 3.555 81 4.156 113 4.857 18 3.057 50 3.573 82 4.176 114 4.881 19 3.072 51 3.590 83 4.196 115 4.905 20 3.087 52 3.608 84 4.217 116 4.929 21 3.102 53 3.625 85 4.237 117 4.953 22 3.117 54 3.643 86 4.258 118 4.977 23 3.132 55 3.661 87 4.279 119 5.001 24 3.147 56 3.679 88 4.300 120 5.026 25 3.163 57 3.697 89 4.321 121 5.050 26 3.178 58 3.715 90 4.342 122 5.075 27 3.194 59 3.733 91 4.363 123 5.100 28 3.209 60 3.751 92 4.384 124 5.125 29 3.225 61 3.770 93 4.406 125 5.150 30 3.241 62 3.788 94 4.427 126 5.175 31 3.257 63 3.806 95 4.449 127 5.200 Table 7. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code Second Stage Gain Code Second Stage Gain Minimum Combined Gain Maximum Combined Gain 0 10 28.0 52.0 1 16 44.8 83.2 2 25 70.0 130.0 3 40 112.0 208.0 4 63 176.4 327.6 5 100 280.0 520.0 6 160 448.0 832.0 7 250 700.0 1300.0 Rev. C | Page 15 of 24 AD8557 OPEN WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT The inputs to A1 and A2, VNEG and VPOS, each have a com- DETECTION parator to detect whether VNEG or VPOS exceeds a threshold A floating fault condition at the VPOS, VNEG, or VCLAMP voltage, nominally VDD − 1.1 V. If VNEG > (VDD − 1.1 V) or pins is detected by using a low current to pull a floating input VPOS > (VDD − 1.1 V), VOUT is clamped to VSS. The output into an error voltage range, defined in the previous section. In current limit circuit is disabled in this mode, but the maximum this way, the VOUT pin is shorted to VSS when a floating input sink current is approximately 10 mA when VDD = 5 V. The is detected. Table 9 lists the currents used. inputs to A1 and A2, VNEG and VPOS, are also pulled up to Table 9. Floating Fault Detection at VPOS, VNEG, VDD by currents IP1 and IP2. These are both nominally 16 nA and VCLAMP and matched to within 3 nA. If the inputs to A1 or A2 are accidentally left floating, as with an open wire fault, IP1 and IP2 Pin Typical Current Goal of Current pull them to VDD, which would cause VOUT to swing to VSS, VPOS 16 nA pull-up Pull VPOS above VINH allowing this fault to be detected. It is not possible to disable IP1 VNEG 16 nA pull-up Pull VNEG above VINH and IP2, nor the clamping of VOUT to VSS, when VNEG or VCLAMP 0.2 µA pull-down Pull VCLAMP below VCLL VPOS approaches VDD. DEVICE PROGRAMMING Digital Interface SHORTED WIRE FAULT DETECTION The digital interface allows the first stage gain, second stage The AD8557 provides fault detection in the case where VPOS, gain, and output offset to be adjusted and allows desired values VNEG, or VCLAMP shorts to VDD and VSS. Figure 46 shows for these parameters to be permanently stored by selectively the voltage regions at VPOS, VNEG, and VCLAMP that trigger blowing polysilicon fuses. To minimize pin count and board an error condition. When an error condition occurs, the VOUT space, a single-wire digital interface is used. The digital input pin is shorted to VSS. Table 8 lists the voltage levels shown in pin, DIGIN, has hysteresis to minimize the possibility of Figure 46. inadvertent triggering with slow signals. It also has a pull-down VPOS VNEG VCLAMP current sink to allow it to be left floating when programming is VDD VDD VDD not being performed. The pull-down ensures inactive status of ERROR ERROR VINH VINH the digital input by forcing a dc low voltage on DIGIN. NORMAL A short pulse at DIGIN from low to high and back to low again, NORMAL NORMAL such as between 50 ns and 10 µs long, loads a 0 into a shift VCLL register. A long pulse at DIGIN, such as 50 µs or longer, loads a ERROR VINL VINL ERROR ERROR 1 into the shift register. The time between pulses should be at VSS VSS VSS least 10 µs. Assuming VSS = 0 V, voltages at DIGIN between Figure 46. Voltage Regions at VPOS, VNEG, and VCLAMP VSS and 0.2 × VDD are recognized as a low, and voltages at that Trigger a Fault Condition DIGIN between 0.8 × VDD and VDD are recognized as a high. Table 8. Typical VINL, VINH, and VCLL Values A timing diagram example, Figure 47, shows the waveform for (VDD = 5 V) entering Code 010011 into the shift register. Voltage Min (V) Max (V) VOUT Condition VINH 3.9 4.2 Short to VDD fault detection VINL 0.195 0.55 Short to VSS fault detection VCLL 1.0 1.2 Short to VSS fault detection t t t W1 WS W1 t t t t WS WS W0 WS t t t t W0 W0 WS W1 WAVEFORM CODE 0 1 0 0 1 1 Figure 47. Timing Diagram for Code 010011 Rev. C | Page 16 of 24 06013-039 06013-040 AD8557 Table 10. Timing Specifications Timing Parameter Description Specification tw0 Pulse width for loading 0 into shift register Between 50 ns and 10 µs tw1 Pulse width for loading 1 into shift register ≥50 µs t Width between pulses ≥10 µs ws Table 11. 38-Bit Serial Word Format Field No. Bits Description 0 0 to 11 12-bit start of packet 1000 0000 0001 1 12 to 13 2-bit function 00: change sense current 01: simulate parameter value 10: program parameter value 11: read parameter value 2 14 to 15 2-bit parameter 00: second stage gain code 01: first stage gain code 10: output offset code 11: other functions 3 16 to 17 2-bit dummy 10 4 18 to 25 8-bit value Parameter 00 (second stage gain code): 3 LSBs used Parameter 01 (first stage gain code): 7 LSBs used Parameter 10 (output offset code): all 8 bits used Parameter 11 (other functions) Bit 0 (LSB): master fuse Bit 1: fuse for production test at Analog Devices 5 26 to 37 12-bit end of packet 0111 1111 1110 A 38-bit serial word is used, divided into 6 fields. Assuming Initial State each bit can be loaded in 60 µs, the 38-bit serial word transfers Initially, all the polysilicon fuses are intact. Each parameter has in 2.3 ms. Table 11 summarizes the word format. the value 0 assigned (see Table 12). Field 0 and Field 5 are the start-of-packet field and end-of- Table 12. Initial State Before Programming packet field, respectively. Matching the start-of-packet field with Second Stage Gain Code = 0 Second Stage Gain = 10 1000 0000 0001 and the end-of-packet field with 0111 1111 First stage gain code = 0 First stage gain = 2.8 1110 ensures that the serial word is valid and enables decoding Output offset code = 0 Output offset = VSS of the other fields. Master fuse = 0 Master fuse not blown Field 3 breaks up the data and ensures that no data combination can inadvertently trigger the start-of-packet and end-of-packet When power is applied to a device, parameter values are taken fields. Field 0 should be written first and Field 5 written last. either from internal registers, if the master fuse is not blown, or from the polysilicon fuses, if the master fuse is blown. Within each field, the MSB must be written first and the LSB Programmed values have no effect until the master fuse is written last. The shift register features power-on reset to mini- blown. The internal registers feature power-on reset, so the mize the risk of inadvertent programming; power-on reset unprogrammed devices enter a known state after power-up. occurs when VDD is between 0.7 V and 2.2 V. Power-on reset occurs when VDD is between 0.7 V and 2.2 V. Rev. C | Page 17 of 24 AD8557 Simulation Mode Parameters are programmed by setting Field 1 to 10, selecting the desired parameter in Field 2, and selecting a single bit with The simulation mode allows any parameter to be temporarily the value 1 in Field 4. changed. These changes are retained until the simulated value is reprogrammed, the power is removed, or the master fuse is As an example, suppose the user wants to permanently set the blown. Parameters are simulated by setting Field 1 to 01, second stage gain to 40. Parameter 00 needs to have the value selecting the desired parameter in Field 2, and selecting the 0000 0011 assigned. Two bits have the value 1, so two fuses need desired value for the parameter in Field 4. Note that a value of to be blown. Because only one fuse can be blown at a time, this 11 for Field 2 is ignored during the simulation mode. Examples code can be used to blow one fuse: of temporary settings follow: 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110  Setting the second stage gain code (Parameter 00) to 011 The MOS switch that blows the fuse closes when the complete packet is recognized, and opens when the start-of-packet, and the second stage gain to 40 produces: dummy, or end-of-packet fields are no longer valid. After 1 ms, 1000 0000 0001 01 00 10 0000 0011 0111 1111 1110 this second code is entered to blow the second fuse:  Setting the first stage gain code (Parameter 01) to 000 1011 1000 0000 0001 10 00 10 0000 0001 0111 1111 1110 and the first stage gain to 4.166 produces: To permanently set the first stage gain to a nominal value of 1000 0000 0001 01 01 10 0000 1011 0111 1111 1110 2.954, Parameter 01 needs to have the value 000 1011 assigned. A first stage gain of 2.954 with a second stage gain of 40 Three fuses need to be blown, and the following codes are used, gives a total gain of 118.16. This gain has a maximum with a 1 ms delay after each code: tolerance of 2.5%. 1000 0000 0001 10 01 10 0000 1000 0111 1111 1110  Set the output offset code (Parameter 10) to 0100 0000 1000 0000 0001 10 01 10 0000 0010 0111 1111 1110 and the output offset to 1.260 V when VDD = 5 V and 1000 0000 0001 10 01 10 0000 0001 0111 1111 1110 VSS = 0 V. This output offset has a maximum tolerance To permanently set the output offset to a nominal value of of 0.8%: 1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs 1000 0000 0001 01 10 10 0100 0000 0111 1111 1110 to have the value 0100 0000 assigned. If one fuse needs to be Programming Mode blown, use the following code: 1000 0000 0001 10 10 10 0100 0000 0111 1111 1110 Intact fuses give a bit value of 0. Bits with a desired value of 1 need to have the associated fuse blown. Because a relatively Finally, to blow the master fuse to deactivate the simulation large current is needed to blow a fuse, only one fuse can be mode and prevent further programming, use code: reliably blown at a time. Thus, a given parameter value may 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110 need several 38-bit words to allow reliable programming. There are a total of 20 programmable fuses. Because each fuse A 5.75 V (±0.25 V) supply is required when blowing fuses to requires 1 ms to blow, and each serial word can be loaded in minimize the on resistance of the internal MOS switches that 2.3 ms, the maximum time needed to program the fuses can be blow the fuse. The power supply voltage must not exceed the as low as 66 ms. absolute maximum rating and must be able to deliver 250 mA Read Mode of current. The values stored by the polysilicon fuses can be sent to the At least 10 μF (tantalum type) of decoupling capacitance is DIGOUT pin to verify correct programming. Normally, the needed across the power pins of the device during program- DIGOUT pin is only connected to the second gain stage output. ming. The capacitance can be on the programming apparatus as During read mode, however, the DIGOUT pin is also connected long as it is within 2 inches of the device being programmed. to the output of a shift register to allow the polysilicon fuse An additional 0.1 μF (ceramic type) in parallel with the 10 μF is contents to be read. Because VOUT is a buffered version of recommended within ½ inch of the device being programmed. DIGOUT, VOUT also outputs a digital signal during read mode. A minimum period of 1 ms should be allowed for each fuse to Read mode is entered by setting Field 1 to 11 and selecting the blow. There is no need to measure the supply current during desired parameter in Field 2. Field 4 is ignored. The parameter programming. value, stored in the polysilicon fuses, is loaded into an internal The best way to verify correct programming is to use the read shift register, and the MSB of the shift register is connected to mode to read back the programmed values. Then, remeasure the DIGOUT pin. Pulses at DIGIN shift out the shift register the gain and offset to verify these values. Programmed fuses contents to the DIGOUT pin, allowing the 8-bit parameter have no effect on the gain and output offset until the master value to be read after seven additional pulses; shifting occurs on fuse is blown. After blowing the master fuse, the gain and the falling edge of DIGIN. An eighth pulse at DIGIN disconnects output offset are determined solely by the blown fuses, and the DIGOUT from the shift register and terminates the read mode. simulation mode is permanently deactivated. Rev. C | Page 18 of 24 AD8557 If a parameter value is less than eight bits long, the MSBs of the Programming Procedure shift register are padded with 0s. For reliable fuse programming, it is imperative to follow the For example, to read the second stage gain, this code is used: programming procedure requirements, especially the proper supply voltage during programming: 1000 0000 0001 11 00 10 0000 0000 0111 1111 1110 Because the second stage gain parameter value is only three bits 1. When programming the AD8557, the temperature of the long, the DIGOUT pin has a value of 0 when this code is device must be between 10°C to 40°C. entered, and remains 0 during four additional pulses at DIGIN. 2. Set VDD and VSS to the desired values in the application. The fifth, sixth, and seventh pulses at DIGIN return the 3-bit Use simulation mode to test and determine the desired value at DIGOUT, the seventh pulse returns the LSB. An eighth codes for the second stage gain, first stage gain, and output pulse at DIGIN terminates the read mode. offset. The nominal values for these parameters are shown Sense Current in Table 6, Table 7, Equation 2, and Equation 3; use the A sense current is sent across each polysilicon fuse to determine codes corresponding to these values as a starting point. whether it has been blown. When the voltage across the fuse is However, because actual parameter values for given codes less than approximately 1.5 V, the fuse is considered not blown, vary from device to device, some fine tuning is necessary and Logic 0 is output from the OTP cell. When the voltage for the best possible accuracy. across the fuse is greater than approximately 1.5 V, the fuse is One way to choose these values is to set the output offset to considered blown, and Logic 1 is output. an approximate value, such as Code 128 for midsupply, to When the AD8557 is manufactured, all fuses have a low allow the required gain to be determined. Then, set the resistance. When a sense current is sent through the fuse, a second stage gain so the minimum first stage gain (Code 0) voltage less than 0.1 V is developed across the fuse. This is gives a lower gain than required, and the maximum first much lower than 1.5 V, so Logic 0 is output from the OTP cell. stage gain (Code 127) gives a higher gain than required. When a fuse is electrically blown, it should have a very high After choosing the second stage gain, the first stage gain resistance. When the sense current is applied to the blown fuse, can be chosen to fine tune the total gain. Finally, the output the voltage across the fuse should be larger than 1.5 V, so offset can be adjusted to give the desired value. After determining the desired codes for second stage gain, first Logic 1 is output from the OTP cell. stage gain, and output offset, the device is ready for It is theoretically possible, though very unlikely, for a fuse to permanent programming. be incompletely blown during programming, assuming the required conditions are met. In this situation, the fuse could Note that once a programming attempt has been made for have a medium resistance, neither low nor high, and a voltage of any fuse, there should be no further attempt to blow that approximately 1.5 V could be developed across the fuse. Thus, fuse. If a fuse does not program to the expected state, the OTP cell could output Logic 0 or Logic 1, depending on discard the unit. The expected incidence rate of attempted temperature, supply voltage, and other variables. but unblown fuses is very small when following the proper programming procedure and conditions. To detect this undesirable situation, the sense current can be lowered by a factor of 4 using a specific code. The voltage devel- 3. Set VSS to 0 V and VDD to 5.75 V (±0.25 V). Power oped across the fuse would then change from 1.5 V to 0.38 V, supplies should be capable of supplying 250 mA at the and the output of the OTP would be a Logic 0 instead of the required voltage and properly bypassed as described in the expected Logic 1 from a blown fuse. Correctly blown fuses would Programming Mode section. Use program mode to still output a Logic 1. In this way, incorrectly blown fuses can be permanently enter the desired codes for the first stage gain, detected. Another specific code would return the sense current second stage gain, and output offset. Blow the master fuse to the normal (larger) value. The sense current cannot be to allow the AD8557 to read data from the fuses and to permanently programmed to the low value. When the AD8557 prevent further programming. is powered up, the sense current defaults to the high value. 4. Set VDD and VSS to the desired values in the application. The low sense current code is Use read mode with low sense current followed by high 1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110 sense current to verify programmed codes. The normal (high) sense current code is 5. Measure gain and offset to verify correct functionality. 1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110 Rev. C | Page 19 of 24 AD8557 Determining Optimal Gain and Offset Codes 9. Calculate the error (in relative terms) E = G /G − 1. G2 C A First, determine the desired gain: 10. Calculate the error (in the number of the first stage gain codes) C = E /0.00489. EG2 G2 1. Determine the desired gain, GA (using the measurements obtained from the simulation). 11. Set the first stage gain code to CG1 − CEG1 − CEG2. The resulting gain should be within one code of GA. 2. Use Table 7 to determine G2, the second stage gain, such that (2.8 × 1.05) < (G /G ) < (5.2/1.05). This ensures the A 2 Finally, determine the desired output offset: first and last codes for the first stage gain are not used, 1. Determine the desired output offset OA (using the thereby allowing enough first stage gain codes within each measurements obtained from the simulation). second stage gain range to adjust for the 3% accuracy. 2. Use Equation 2 to set the output offset code C such that O1 Next, set the second stage gain: the output offset is nominally O . A 1. Use the simulation mode to set the second stage gain to G2. 3. Measure the output offset (OB). OB should be within 2. Set the output offset to allow the AD8557 gain to be 3% of OA. measured, for example, use Code 128 to set it to midsupply. 4. Calculate the error (in relative terms) EO1 = OB/OA − 1. 3. Use Table 6 or Equation 1 to set the first stage gain code 5. Calculate the error (in the number of the output offset C , so the first stage gain is nominally G /G . G1 A 2 codes) C = E /0.00392. EO1 O1 4. Measure the resulting gain (G ). G should be within B B 6. Set the output offset code to C − C . O1 EO1 3% of GA. 7. Measure the output offset (O ). O should be closer to O C C A 5. Calculate the first stage gain error (in relative terms) than to O . B EG1 = GB/GA − 1. 8. Calculate the error (in relative terms) EO2 = OC/OA − 1. 6. Calculate the error (in the number of the first stage gain 9. Calculate the error (in the number of the output offset codes) C = E /0.00489. EG1 G1 codes) CEO2 = EO2/0.00392. 7. Set the first stage gain code to C − C . G1 EG1 10. Set the output offset code to CO1 − CEO1 − CEO2. The 8. Measure the gain (G ). G should be closer to G than to G . C C A B resulting offset should be within one code of O . A Rev. C | Page 20 of 24 AD8557 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 48. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 4.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 13 16 1 12 PIN 1 0.65 BSC 2.50 INDICATOR TOP 3.75 EXPOSED 2.35 SQ VIEW PAD BSC SQ (BOTTOM VIEW) 2.20 0.50 9 0.40 4 8 5 0.30 0.25 MIN 0.80 MAX 12° MAX 1.95 BSC 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF 1.00 0.02 NOM THE EXPOSED PAD, REFER TO 0.85 THE PIN CONFIGURATION AND 0.35 FUNCTION DESCRIPTIONS 0.80 0.20 REF 0.30 COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 0.25 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-10) Dimensions shown in millimeters Rev. C | Page 21 of 24 012407-A 082008-A AD8557 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8557ACPZ-R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-10 AD8557ACPZ-REEL −40°C to +125°C 16-Lead LFCSP_VQ CP-16-10 AD8557ACPZ-REEL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-10 AD8557ARZ −40°C to +125°C 8-Lead SOIC_N R-8 AD8557ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8557ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1 Z = RoHS Compliant Part. AUTOMOTIVE PRODUCTS The AD8557 models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. C | Page 22 of 24 AD8557 NOTES Rev. C | Page 23 of 24 AD8557 NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06013-0-6/11(C) Rev. C | Page 24 of 24