ANALOG DEVICES AD8556

Digitally Programmable Sensor Signal Amplifier with EMI Filters AD8556 FEATURES APPLICATIONS EMI filters at input pins Automotive sensors Specified from −40°C to +140°C Pressure and position sensors Low offset voltage: 10 μV maximum Precision current sensing Low input offset voltage drift: Strain gages 65 nV/°C maximum High CMRR: 94 dB minimum Digitally programmable gain and output offset voltage Programmable output clamp voltage Open and short wire fault detection Low-pass filtering Single-wire serial interface Stable with any capacitive load SOIC_N and LFCSP_VQ packages 4.5 V to 5.5 V operation FUNCTIONAL BLOCK DIAGRAM DIGIN VCLAMP VDD 1 EMI +IN 3 FILTER A5 OUT 2 LOGIC DAC –IN VSS VDD 1 EMI +IN R5 P4 R7 VPOS 3 FILTER A1 OUT 2 –IN R2 VSS P2 VDD VDD EMI FILTER R3 1 RF +IN 3 EMI 1 A3 +IN OUT 2 FILTER 3 A4 V P1 OUT –IN OUT 2 VDD –IN VSS R1 1 +IN R4 R5 VSS 3 A2 OUT EMI 2 VNEG –IN P3 FILTER VSS AD8556 VSS FILT/DIGOUT Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05448-053 AD8556 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications....................................................................................... 1 Theory of Operation ...................................................................... 16 Functional Block Diagram .............................................................. 1 Gain Values ................................................................................. 17 Revision History ............................................................................... 2 Open Wire Fault Detection....................................................... 18 General Description ......................................................................... 3 Shorted Wire Fault Detection................................................... 18 Specifications..................................................................................... 4 Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 18 Electrical Specifications............................................................... 4 Device Programming................................................................. 18 Absolute Maximum Ratings............................................................ 6 EMI/RFI Performance ................................................................... 24 Thermal Resistance ...................................................................... 6 Outline Dimensions ....................................................................... 26 ESD Caution.................................................................................. 6 Ordering Guide .......................................................................... 26 Pin Configurations and Function Descriptions ........................... 7 REVISION HISTORY 12/07—Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to General Description .................................................... 3 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 5/05—Revision 0: Initial Version Rev. A | Page 2 of 28 AD8556 GENERAL DESCRIPTION The AD8556 is a zero-drift, sensor signal amplifier with In addition to extremely low input offset voltage, low input offset digitally programmable gain and output offset. Designed to voltage drift, and very high dc and ac CMRR, the AD8556 also easily and accurately convert variable pressure sensor and includes a pull-up current source at the input pins and a pull- strain bridge outputs to a well-defined output voltage range, down current source at the VCLAMP pin, which allows open the AD8556 accurately amplifies many other differential or wire and shorted wire fault detection. A low-pass filter function single-ended sensor outputs. The AD8556 uses the Analog is implemented via a single low cost external capacitor. Output Devices, Inc. patented low noise, auto-zero and DigiTrim® clamping set via an external reference voltage allows the AD8556 technologies to create an incredibly accurate and flexible to drive lower voltage ADCs safely and accurately. signal processing solution in a very compact footprint. When used in conjunction with an ADC referenced to the same Gain is digitally programmable in a wide range from 70 to supply, the system accuracy becomes immune to normal supply 1280 through a serial data interface. Gain adjustment can voltage variations. Output offset voltage can be adjusted with a be fully simulated in-circuit and then permanently pro- resolution of better than 0.4% of the difference between VDD grammed with reliable polyfuse technology. Output offset and VSS. A lockout trim after gain and offset adjustment further voltage is also digitally programmable and is ratiometric to ensures field reliability. the supply voltage. The AD8556 also features internal EMI The AD8556 is fully specified from −40°C to +140°C. filters on the VNEG, VPOS, FILT and VCLAMP pins. Operating from single-supply voltages of 4.5 V to 5.5 V, the AD8556 is offered in the 8-lead SOIC_N and 4 mm × 4 mm 16-lead LFCSP_VQ. Rev. A | Page 3 of 28 AD8556 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 5.0 V, VSS = 0.0 V, V = 2.5 V, V = 2.5 V, −40°C ≤ T ≤ +140°C, unless otherwise specified. CM O A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT STAGE Input Offset Voltage VOS −40°C ≤ TA ≤ +125°C 2 10 μV −40°C ≤ T ≤ +140°C 3 12 μV A Input Offset Voltage Drift T V 25 65 nV/°C C OS Input Bias Current IB TA = 25°C 38 49 54 nA −40°C ≤ TA ≤ +125°C 58 nA −40°C ≤ TA ≤ +140°C 60 nA Input Offset Current I T = 25°C 0.2 2.5 nA OS A −40°C ≤ T ≤ +125°C 3.0 nA A −40°C ≤ T ≤ +140°C 4.0 nA A Input Voltage Range 2.1 2.9 V Common-Mode Rejection Ratio CMRR VCM = 2.1 V to 2.9 V, AV = 70 80 92 dB VCM = 2.1 V to 2.9 V, AV = 1280 94 112 dB Linearity V = 0.2 V to 3.4 V 20 ppm O V = 0.2 V to 4.8 V 1000 ppm O Differential Gain Accuracy Second stage gain = 17.5 to 100 0.35 1.6 % Second stage gain = 140 to 200 0.5 2.5 % Differential Gain Temperature Coefficient Second stage gain = 17.5 to 100 7 20 ppm/°C Second stage gain = 140 to 200 10 40 ppm/°C RF 14 18 22 kΩ RF Temperature Coefficient 600 ppm/°C DAC Accuracy A = 70, offset codes = 8 to 248 0.2 0.6 % V Ratiometricity AV = 70, offset codes = 8 to 248 50 ppm Output Offset AV = 70, offset codes = 8 to 248 5 35 mV Temperature Coefficient −40°C ≤ T ≤ +125°C 3.3 15 ppm FS/°C A −40°C ≤ T ≤ +140°C 25 ppm FS/°C A VCLAMP Input Bias Current T = 25°C, VCLAMP = 5 V 200 nA A −40°C ≤ T ≤ +125°C, VCLAMP = 5 V 500 nA A −40°C ≤ T ≤ +140°C, VCLAMP = 5 V 550 nA A Input Voltage Range 1.2 4.94 V OUTPUT BUFFER STAGE Buffer Offset 3 7 mV Short-Circuit Current ISC 5 10 mA Output Voltage, Low VOL RL = 10 kΩ to 5 V 20 mV Output Voltage, High V R = 10 kΩ to 0 V 4.94 V OH L POWER SUPPLY Supply Current ISY −40°C ≤ TA ≤ +125°C, VO = 2.5 V, 2.0 2.7 mA VPOS = VNEG = 2.5 V, VDAC code = 128 −40°C ≤ T ≤ +140°C, V = 2.5 V, 2.78 mA A O VPOS = VNEG = 2.5 V, VDAC Code = 128 Power Supply Rejection Ratio PSRR AV = 70 109 125 dB Supply Voltage Required During Programming 5.0 5.25 5.5 V 10°C < TPROG < 40°C, supply capable of driving 250 mA Rev. A | Page 4 of 28 AD8556 Parameter Symbol Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Gain Bandwidth Product GBP First gain stage, TA = 25°C 2 MHz Second gain stage, TA = 25°C 8 MHz Output buffer stage, T = 25°C 1.5 MHz A Output Buffer Slew Rate SR A = 70, R = 10 kΩ, C = 100 pF, T = 25°C 1.2 V/μs V L L A Settling Time t To 0.1%, A = 70, 4 V output step, T = 25°C 8 μs s V A NOISE PERFORMANCE Input Referred Noise T = 25°C, f = 1 kHz 32 nV/√Hz A Low Frequency Noise en p-p f = 0.1 Hz to 10 Hz, TA = 25°C 0.5 μV p-p Total Harmonic Distortion THD VIN = 16.75 mV rms, f = 1 kHz, −100 dB AV = 100, TA = 25°C DIGITAL INTERFACE Input Current 2 μA DIGIN Pulse Width to Load 0 tw0 TA = 25°C 0.05 10 μs DIGIN Pulse Width to Load 1 tw T = 25°C 50 μs 1 A Time Between Pulses at DIGIN tw T = 25°C 10 μs s A DIGIN Low T = 25°C 1 V A DIGIN High TA = 25°C 4 V DIGOUT Logic 0 TA = 25°C 1 V DIGOUT Logic 1 TA = 25°C 4 V Rev. A | Page 5 of 28 AD8556 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage 6 V other conditions above those indicated in the operational Input Voltage VSS − 0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute 1 Differential Input Voltage ±5.0 V maximum rating conditions for extended periods may affect Output Short-Circuit Duration to Indefinite device reliability. VSS or VDD Storage Temperature Range −65°C to +150°C THERMAL RESISTANCE Operating Temperature Range −40°C to +150°C θ is specified for the worst-case conditions, that is, a device JA Junction Temperature Range −65°C to +150°C soldered in a circuit board for surface-mount packages. Lead Temperature 300°C Table 3. Thermal Resistance 1 Differential input voltage is limited to ±5.0 V or ± the supply voltage, 1 Package Type θ θ Unit JA JC whichever is less. 8-Lead SOIC_N (R) 158 43 °C/W 16-Lead LFCSP_VQ (CP) 44 31.5 °C/W 1 θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for LFCSP_VQ package. ESD CAUTION Rev. A | Page 6 of 28 AD8556 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 PIN 1 12 VOUT INDICATOR FILT/DIGOUT 2 11 NC AD8556 NC 3 10 VCLAMP TOP VIEW DIGIN 4 9 NC VDD 1 8 VSS AD8556 FILT/DIGOUT 2 7 VOUT TOP VIEW DIGIN 3 6 VCLAMP (Not to Scale) NC = NO CONNECT VNEG 4 5 VPOS Figure 3.16-Lead LFCSP_VQ Pin Configuration Figure 2. 8-Lead SOIC_N Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description SOIC_N LFCSP_VQ 1 VDD Positive Supply Voltage. 2 2 FILT/DIGOUT Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output. 3 4 DIGIN Digital Input. 4 6 VNEG Negative Amplifier Input (Inverting Input). 5 8 VPOS Positive Amplifier Input (Noninverting Input). 6 10 VCLAMP Set Clamp Voltage at Output. 7 12 VOUT Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output. 8 VSS Negative Supply Voltage. 13, 14 DVSS, AVSS Negative Supply Voltage. 15, 16 DVDD, AVDD Positive Supply Voltage. 1, 3, 5, 7, 9, 11 NC Do Not Connect. Rev. A | Page 7 of 28 05448-002 NC 5 16 AVDD VNEG 6 15 DVDD NC 7 14 AVSS VPOS 8 13 DVSS 05448-003 AD8556 TYPICAL PERFORMANCE CHARACTERISTICS 25 N: 363 V = 5V SY 100 MEAN: –0.389938 SD: 1.65684 20 80 15 60 10 40 5 20 0 0 –10 –5 0 5 10 0 102030 40 MORE V 5V (µV) T V (nV/°C) OS C OS Figure 4. Input Offset Voltage Distribution Figure 7. TCVOS at VSY = 5 V 2.0 V = 5V SY V = 5V SY 1.9 T = 25°C 1.5 A 1.7 1.0 V = 0.3V OUT 0.5 1.5 0 1.3 –0.5 V = 4.7V OUT 1.1 –1.0 –1.5 0.9 –2.0 0.7 –2.5 0.5 –3.0 –50 –25 0 25 50 75 100 125 150 1.52.02.53.0 3.5 TEMPERATURE (°C) V (V) CM Figure 5. Input Offset Voltage vs. Common-Mode Voltage Figure 8. Output Buffer Offset Voltage? vs. Temperature 10 100 V = 5V SY V = 5V SY 8 6 4 2 0 10 –2 –4 –6 –8 –10 1 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. Input Offset Voltage vs. Temperature Figure 9. Input Bias Current at VPOS, VNEG vs. Temperature Rev. A | Page 8 of 28 V (µV) HITS OSi INPUT OFFSET VOLTAGE (µV) 05448-005 05448-004 05448-006 INPUT BIAS CURRENT (nA) BUFFER OFFSET VOLTAGE (mV) NUMBER OF AMPLIFIERS 05448-010 05448-009 05448-007 AD8556 100 1000 V = 5V V = 5V SY SY I – B T = 25°C A +125°C I + B +25°C –40°C 10 100 1 10 012 345 6 02143 5 6 V (V) VCLAMP VOLTAGE (V) CM Figure 13. VCLAMP Current over Temperature at Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage V = 5 V vs. VCLAMP Voltage S 3.0 0.8 V = 5V SY T = 25°C A 0.6 2.5 0.5 0.3 2.0 0.2 0 1.5 –0.2 1.0 –0.3 –0.5 0.5 –0.6 –0.8 0 –50 –25 0 25 50 75 100 125 150 01 23 4 5 6 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 14. Supply Current (I ) vs. Supply Voltage Figure 11. Input Offset Current vs. Temperature SY 2.5 2.5 V = 5V V = 5.5V SY SY 2.3 2.1 2.0 1.9 1.5 1.7 1.5 1.3 1.0 1.1 0.5 0.9 0.7 0 0.5 012 345 6 –50 –25 0 25 50 75 100 125 150 DIGITAL INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 12. Digital Input Current vs. Digital Input Voltage (Pin 4) Figure 15. Supply Current (ISY) vs. Temperature Rev. A | Page 9 of 28 DIGITAL INPUT CURRENT (µA) I (nA) B INPUT OFFSET CURRENT (nA) 05448-013 05448-011 05448-012 VCLAMP CURRENT (nA) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 05448-014 05448-016 05448-015 AD8556 V = ±2.5V SY V = ±2.5V SY GAIN = 70 GAIN = 70 120 60 80 50 40 30 40 20 10 0 100 1k 10k 100k 1M 0 5 10 FREQUENCY (Hz) FREQUENCY (kHz) Figure 16. CMRR vs. Frequency Figure 19. Voltage Noise Density vs. Frequency (0 Hz to 10 kHz) V = ±2.5V SY GAIN = 1280 V = ±2.5V SY GAIN = 70 120 35 30 80 25 20 15 10 5 0 100 1k 10k 100k 1M FREQUENCY (Hz) 0 250 500 FREQUENCY (kHz) Figure 17. CMRR vs. Frequency Figure 20. Voltage Noise Density vs. Frequency (0 Hz to 500 kHz) V = 5V SY 145 V = ±2.5V SY GAIN = 1000 0.6 135 GAIN = 800 0.4 GAIN = 1280 GAIN = 400 125 0.2 115 0 105 –0.2 95 GAIN = 70 –0.4 GAIN = 100 85 –0.6 75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TIME (1s/DIV) Figure 21. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz) Figure 18. CMRR vs. Temperature at Different Gains Rev. A | Page 10 of 28 40 CMRR (dB) CMRR (dB) CMRR (dB) 05448-018 05448-017 05448-019 NOISE (µV) VOLTAGE NOISE DENSITY (nV/√Hz) VOLTAGE NOISE DENSITY (nV/√Hz) 05448-022 05448-021 05448-020 AD8556 V = ±2.5V SY V = ±2.5V SY 8 GAIN = 70 0.6 0.4 4 0.2 0 0 –0.2 –4 –0.4 –0.6 –8 1k 10k 100k 1M 10M FREQUENCY (Hz) TIME (1s/DIV) Figure 22. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz) Figure 25. Output Buffer Gain vs. Frequency 60 V = ±2.5V V = ±2.5V SY SY C = 40pF GAIN = 1280 L R S R = 0Ω S 50 60 C L OUTPUT BUFFER 40 40 30 GAIN = 70 R = 10Ω S 20 20 R = 50Ω R = 20Ω S S 0 10 R = 100Ω S 0 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) LOAD CAPACITANCE (nF) Figure 23. Closed-Loop Gain vs. Frequency Measured at FILT/DIGOUT Pin Figure 26. Output Buffer Positive Overshoot 60 V = ±2.5V V = ±2.5V SY SY GAIN = 1280 R S 50 60 C R = 0Ω S L 40 40 30 GAIN = 70 R = 10Ω S 20 20 R = 50Ω S 0 10 R = 100Ω R = 20Ω S S 0 1k 10k 100k 1M 0.1 1.0 10.0 100.0 LOAD CAPACITANCE (nF) FREQUENCY (Hz) Figure 27. Output Buffer Negative Overshoot Figure 24. Closed-Loop Gain vs. Frequency Measured at VOUT Pin Rev. A | Page 11 of 28 NOISE (µV) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 05448-023 05448-025 05448-024 OVERSHOOT (%) OVERSHOOT (%) GAIN (dB) 05448-028 05448-027 05448-026 AD8556 1.000 V = ±2.5V SY 6 SUPPLY VOLTAGE SOURCE 0.100 5 4 SINK 3 0.010 2 1 V OUT 0 0.001 0.01 0.10 1.00 10.0 TIME (100µs/DIV) LOAD CURRENT (mA) Figure 28. Output Voltage to Supply Rail vs. Load Current Figure 31. Power-On Response at 125°C 15 12 SINK 5V 9 6 SUPPLY VOLTAGE 6 5 3 4 0 –3 3 –6 2 SOURCE 5V –9 1 –12 V OUT 0 –15 –75 –50 –25 0 25 50 75 100 125 150 175 TIME (100µs/DIV) TEMPERATURE (°C) Figure 29. Output Short Circuit vs. Temperature Figure 32. Power-On Response at −40°C 150 V = 2.7V TO 5.5V SY SUPPLY VOLTAGE 145 140 4 135 2 130 0 125 3 120 115 2 110 1 V 105 OUT 0 100 –75 –50 –25 0 25 50 75 100 125 150 TIME (100µs/DIV) TEMPERATURE (°C) Figure 30. Power-On Response at 25°C Figure 33. PSRR vs. Temperature Rev. A | Page 12 of 28 VDD – OUTPUT VOLTAGE (V) OUTPUT SHORT CIRCUIT (mA) VOLTAGE 05448-029 05448-031 05448-030 PSRR (dB) VOLTAGE (1V/DIV) VOLTAGE (1V/DIV) 05448-034 05448-033 05448-032 AD8556 140 V = 2.7V TO 2.5V SY T V = ±2.5V SY GAIN = 70 120 C = 100pF L 100 80 2 60 40 20 0 0.01 0.1 1 10 100 FREQUENCY (kHz) TIME (10µs/DIV) Figure 34. PSRR vs. Frequency Figure 37. Large Signal Response at CL = 100 pF T T V = ±2.5V V = ±2.5V SY SY GAIN = 70 GAIN = 70 C = 0.05µF C = 0.1µF L L F = 10kHz IN 2 2 TIME (100µs/DIV) TIME (10µs/DIV) Figure 35. Small Signal Response at CL = 0.1 μF and FIN = 10 kHz Figure 38. Large Signal Response at C = 0.05 μF L 1k V = ±2.5V SY T V = ±2.5V SY A = 70 V GAIN = 70 C = 100pF L F = 1kHz IN 100 2 10 1 0.111 10001M FREQUENCY (kHz) TIME (100µs/DIV) Figure 36. Small Signal Response at C = 100 pF and F = 1 kHz Figure 39. Output Impedance vs. Frequency L IN Rev. A | Page 13 of 28 VOUT (50mV/DIV) VOUT (50mV/DIV) PSRR (dB) 05448-037 05448-036 05448-035 VOUT (1V/DIV) VOUT (1V/DIV) 05448-039 05448-038 05448-040 20.5Ω 294Ω 20.5Ω 294Ω AD8556 0V 1 V IN 1 V 0V IN 2 0V V OUT V OUT 0V 2 CH1 10.0mV CH2 2.00V M 4.00µs A CH1 8.40mV CH1 50.0mV CH2 2.00V M 1.00µs A CH1 –21.0mV Figure 40. Negative Overload Recovery (Gain = 70) Figure 43. Positive Overload Recovery (Gain = 1280) V IN GAIN = 70 OFFSET = 128 1 V = ±2.5V SY +V 1 0V 4V pp 0.1µF 1 4 6 7 V OUT 5 DUT 8 0V 2 0.1µF –V 10kΩ 1kΩ 10kΩ 2 OUT CH1 50.0mV CH2 2.00V M 1.00µs A CH1 57.0mV CH1 2.00mV CH2 2.00mV M 1.00µs A CH1 40.0mV Figure 41. Positive Overload Recovery (Gain = 70) Figure 44. Settling Time 0.1% 0V 1 GAIN = 70 OFFSET = 128 0V 1 V = ±2.5V SY V IN +V 4V pp 0.1µF 1 4 6 7 0V 2 5 DUT 8 –2.5V 0.1µF –V 10kΩ 1kΩ 10kΩ 2 0V OUT CH1 10.0mV CH2 2.00V M 4.00µs A CH1 –9.40mV CH1 2.00mV CH2 2.00mV M 1.00µs A CH1 40.0mV Figure 45. Settling Time 0.01% Figure 42. Negative Overload Recovery (Gain = 1280) Rev. A | Page 14 of 28 05448-042 05448-041 05448-043 05448-045 05448-046 05448-044 AD8556 1.00 V = ±2.5V SY 0.50 0.20 0.10 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 46. THD vs. Frequency Rev. A | Page 15 of 28 THD (%) 05448-047 AD8556 THEORY OF OPERATION A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the A4 implements a rail-to-rail input and output unity-gain differential amplifier. A1 and A2 are auto-zeroed op amps that voltage buffer. The output stage of A4 is supplied from a minimize input offset errors. P1 and P2 are digital potentiometers, buffered version of VCLAMP instead of VDD, allowing the guaranteed to be monotonic. Programming P1 and P2 allows positive swing to be limited. The maximum output current is the first stage gain to be varied from 4.0 to 6.4 with 7-bit limited between 5 mA to 10 mA. resolution (see Table 5 and Equation 1), giving a fine gain An 8-bit DAC is used to generate a variable offset for the adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each amplifier output. This DAC is guaranteed to be monotonic. have a similar temperature coefficient; therefore, the first stage To preserve the ratiometric nature of the input signal, the DAC gain temperature coefficient is lower than 100 ppm/°C. references are driven from VSS and VDD, and the DAC output Code ⎛ ⎞ can swing from VSS (Code 0) to VDD (Code 255). The 8-bit ⎜ ⎟ 6.4 ⎝ 127 ⎠ ⎛ ⎞ resolution is equivalent to 0.39% of the difference between GAIN1≈ 4× (1) ⎜ ⎟ 4 ⎝ ⎠ VDD and VSS, for example, 19.5 mV with a 5 V supply. The DAC output voltage (VDAC) is given approximately by A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the differential amplifier. A3 is also an auto-zeroed op amp that Code+ 0.5 ⎛ ⎞ () VDAC≈ VDD−VSS+VSS (2) minimizes input offset errors. P3 and P4 are digital potentiometers ⎜ ⎟ 256 ⎝ ⎠ that allow the second stage gain to be varied from 17.5 to 200 in where the temperature coefficient of VDAC is lower than eight steps (see Table 6). R4, R5, R6, R7, P3, and P4 each have a 200 ppm/°C. similar temperature coefficient; therefore, the second stage gain temperature coefficient is lower than 100 ppm/°C. The amplifier output voltage (VOUT) is given by RF together with an external capacitor, connected between VOUT = GAIN (VPOS − VNEG) + VDAC (3) FILT/DIGOUT and VSS or VDD, form a low-pass filter. The where GAIN is the product of the first and second stage gains. filtered signal is buffered by A4 to give a low impedance output VDD at VOUT. RF is nominally 18 kΩ, allowing an 880 Hz low-pass VCLAMP VDD filter to be implemented by connecting a 10 nF external capacitor A5 between FILT/DIGOUT and VSS or between FILT/DIGOUT P3 VNEG R4 R6 A1 and VDD. If low-pass filtering is not needed, the FILT/DIGOUT VSS R1 pin must be left floating. VDD VSS VDD P1 A5 implements a voltage buffer that provides the positive supply RF R3 A3 to A4, the amplifier output buffer. Its function is to limit VOUT VOUT A4 to a maximum value, useful for driving ADCs operating on P2 VDD VSS FILT/ supply voltages lower than VDD. The input to A5, VCLAMP, R2 DIGOUT VSS R5 R7 has a very high input resistance. It should be connected to a A2 known voltage and not left floating. However, the high input VPOS P4 VDD impedance allows the clamp voltage to be set using a high VSS impedance source, such as a potential divider. If the maximum DAC value of VOUT does not need to be limited, VCLAMP should be connected to VDD. VSS Figure 47. Functional Schematic Rev. A | Page 16 of 28 05448-001 AD8556 GAIN VALUES Table 5. First Stage Gain vs. First Stage Gain Code First Stage First Stage First Stage First Stage Gain Code First Stage Gain Gain Code First Stage Gain Gain Code First Stage Gain Gain Code First Stage Gain 0 4.000 32 4.503 64 5.069 96 5.706 1 4.015 33 4.520 65 5.088 97 5.727 2 4.030 34 4.536 66 5.107 98 5.749 3 4.045 35 4.553 67 5.126 99 5.770 4 4.060 36 4.570 68 5.145 100 5.791 5 4.075 37 4.587 69 5.164 101 5.813 6 4.090 38 4.604 70 5.183 102 5.834 7 4.105 39 4.621 71 5.202 103 5.856 8 4.120 40 4.638 72 5.221 104 5.878 9 4.135 41 4.655 73 5.241 105 5.900 10 4.151 42 4.673 74 5.260 106 5.921 11 4.166 43 4.690 75 5.280 107 5.943 12 4.182 44 4.707 76 5.299 108 5.965 13 4.197 45 4.725 77 5.319 109 5.988 14 4.213 46 4.742 78 5.339 110 6.010 15 4.228 47 4.760 79 5.358 111 6.032 16 4.244 48 4.778 80 5.378 112 6.054 17 4.260 49 4.795 81 5.398 113 6.077 18 4.276 50 4.813 82 5.418 114 6.099 19 4.291 51 4.831 83 5.438 115 6.122 20 4.307 52 4.849 84 5.458 116 6.145 21 4.323 53 4.867 85 5.479 117 6.167 22 4.339 54 4.885 86 5.499 118 6.190 23 4.355 55 4.903 87 5.519 119 6.213 24 4.372 56 4.921 88 5.540 120 6.236 25 4.388 57 4.939 89 5.560 121 6.259 26 4.404 58 4.958 90 5.581 122 6.283 27 4.420 59 4.976 91 5.602 123 6.306 28 4.437 60 4.995 92 5.622 124 6.329 29 4.453 61 5.013 93 5.643 125 6.353 30 4.470 62 5.032 94 5.664 126 6.376 31 4.486 63 5.050 95 5.685 127 6.400 Table 6. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code Second Stage Gain Code Second Stage Gain Minimum Combined Gain Maximum Combined Gain 0 17.5 70 112 1 25 100 160 2 35 140 224 3 50 200 320 4 70 280 448 5 100 400 640 6 140 560 896 7 200 800 1280 Rev. A | Page 17 of 28 AD8556 OPEN WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION The inputs to A1 and A2, VNEG and VPOS, each have a com- parator to detect whether VNEG or VPOS exceeds a threshold A floating fault condition at the VPOS, VNEG, or VCLAMP voltage, nominally VDD − 2.0 V. If (VNEG > VDD − 2.0 V) or pins is detected by using a low current to pull a floating input (VPOS > VDD − 2.0 V), VOUT is clamped to VSS. The output into an error voltage range, defined in the Shorted Wire Fault current limit circuit is disabled in this mode, but the maximum Detection section. In this way, the VOUT pin is shorted to VSS sink current is approximately 10 mA when VDD = 5 V. The inputs when a floating input is detected. Table 8 lists the currents used. to A1 and A2, VNEG and VPOS, are also pulled up to VDD by Table 8. Floating Fault Detection at VPOS, VNEG, and currents IP1 and IP2. These are both nominally 49 nA and VCLAMP matched to within 3 nA. If the inputs to A1 or A2 are accidentally Mnemonic Typical Current Goal of Current left floating, as with an open wire fault, IP1 and IP2 pull them VPOS 49 nA pull-up Pull VPOS above VINH to VDD, which would cause VOUT to swing to VSS, allowing VNEG 49 nA pull-up Pull VNEG above VINH this fault to be detected. It is not possible to disable IP1 and IP2, VCLAMP 0.2 μA pull-down Pull VCLAMP below VCLL nor the clamping of VOUT to VSS, when VNEG or VPOS approaches VDD. DEVICE PROGRAMMING SHORTED WIRE FAULT DETECTION Digital Interface The AD8556 provides fault detection when VPOS, VNEG, or The digital interface allows the first stage gain, second stage VCLAMP shorts to VDD and VSS. Figure 48 shows the voltage gain, and output offset to be adjusted and allows desired values regions at VPOS, VNEG, and VCLAMP that trigger an error for these parameters to be permanently stored by selectively condition. When an error condition occurs, the VOUT pin is blowing polysilicon fuses. To minimize pin count and board shorted to VSS. Table 7 lists the voltage levels shown in Figure 48. space, a single-wire digital interface is used. The digital input pin, VPOS VNEG VCLAMP DIGIN, has hysteresis to minimize the possibility of inadvertent VDD VDD VDD ERROR ERROR triggering with slow signals. It also has a pull-down current sink VINH VINH to allow it to be left floating when programming is not being NORMAL performed. The pull-down ensures inactive status of the digital NORMAL NORMAL input by forcing a dc low voltage on DIGIN. VCLL A short pulse at DIGIN from low to high and back to low again, ERROR VINL VINL ERROR ERROR VSS VSS VSS such as between 50 ns and 10 μs long, loads 0 into the shift register. A long pulse at DIGIN, such as 50 μs or longer, loads 1 into the Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP shift register. The time between pulses should be at least 10 μs. that Trigger a Fault Condition Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 × Table 7. Typical VINL, VINH, and VCLL Values (VDD = 5 V) VDD are recognized as a low, and voltages at DIGIN between Voltage Min (V) Typ (V) Max (V) VOUT Condition 0.8 × VDD and VDD are recognized as a high. The timing VINH 2.95 3.0 3.05 Short to VSS fault diagram example in Figure 49 shows the waveform for entering detection code 010011 into the shift register. VINL 1.95 2.0 2.05 Short to VSS fault detection VCLL 1.05 1.1 1.15 Short to VSS fault detection Rev. A | Page 18 of 28 05448-048 AD8556 t t t W1 WS W1 t t t t WS WS W0 WS t t t t W0 W0 WS W1 WAVEFORM CODE 01 00 1 1 Figure 49. Timing Diagram for Code 010011 Table 9. Timing Specifications Timing Parameter Description Specification t Pulse width for loading 0 into shift register Between 50 ns and 10 μs w0 t Pulse width for loading 1 into shift register ≥50 μs w1 tws Width between pulses ≥10 μs Table 10. 38-Bit Serial Word Format Field No. Bits Description 0 0 to 11 12-Bit Start of Packet 1000 0000 0001 1 12 to 13 2-Bit Function 00: Change Sense Current 01: Simulate Parameter Value 10: Program Parameter Value 11: Read Parameter Value 2 14 to 15 2-Bit Parameter 00: Second Stage Gain Code 01: First Stage Gain Code 10: Output Offset Code 11: Other Functions 3 16 to 17 2-Bit Dummy 10 4 18 to 25 8-Bit Value Parameter 00 (Second Stage Gain Code): 3 LSBs Used Parameter 01 (First Stage Gain Code): 7 LSBs Used Parameter 10 (Output Offset Code): All 8 Bits Used Parameter 11 (Other Functions) Bit 0 (LSB): Master Fuse Bit 1: Fuse for Production Test at Analog Devices Bit 2: Parity Fuse 5 26 to 37 12-Bit End of Packet 0111 1111 1110 A 38-bit serial word is used, divided into 6 fields. Assuming Field 3 breaks up the data and ensures that no data combination each bit can be loaded in 60 μs, the 38-bit serial word transfers can inadvertently trigger the start-of-packet and end-of-packet in 2.3 ms. Table 10 summarizes the word format. fields. Field 0 should be written first and Field 5 written last. Field 0 and Field 5 are the start-of-packet field and end-of- Within each field, the MSB must be written first and the LSB packet field, respectively. Matching the start-of-packet field with written last. The shift register features power-on reset to minimize 1000 0000 0001 and the end-of-packet field with 0111 1111 the risk of inadvertent programming; power-on reset occurs 1110 ensures that the serial word is valid and enables decoding when VDD is between 0.7 V and 2.2 V. of the other fields. Rev. A | Page 19 of 28 05448-049 AD8556 Initial State At least 10 μF (tantalum type) of decoupling capacitance is needed across the power pins of the device during programming. Initially, all the polysilicon fuses are intact. Each parameter has The capacitance can be on the programming apparatus as long the value 0 assigned (see Table 11). as it is within 2 inches of the device being programmed. An Table 11. Initial State Before Programming additional 0.1 μF (ceramic type) in parallel with the 10 μF is Second Stage Gain Code = 0 Second Stage Gain = 17.5 recommended within ½ inch of the device being programmed. First stage gain code = 0 First stage gain = 4.0 A minimum period of 1 ms should be allowed for each fuse to Output offset code = 0 Output offset = VSS blow. There is no need to measure the supply current during Master fuse = 0 Master fuse not blown programming. The best way to verify correct programming is to use the read When power is applied to a device, parameter values are taken mode to read back the programmed values. Then, remeasure either from internal registers, if the master fuse is not blown, or the gain and offset to verify these values. Programmed fuses from the polysilicon fuses, if the master fuse is blown. Programmed have no effect on the gain and output offset until the master values have no effect until the master fuse is blown. The internal fuse is blown. After blowing the master fuse, the gain and registers feature power-on reset; therefore, the unprogrammed output offset are determined solely by the blown fuses, and devices enter a known state after power-up. Power-on reset the simulation mode is permanently deactivated. occurs when VDD is between 0.7 V and 2.2 V. Parameters are programmed by setting Field 1 to 10, selecting Simulation Mode the desired parameter in Field 2, and selecting a single bit with The simulation mode allows any parameter to be temporarily the value 1 in Field 4. changed. These changes are retained until the simulated value is As an example, suppose the user wants to permanently set the reprogrammed, the power is removed, or the master fuse is second stage gain to 50. Parameter 00 needs to have the value blown. Parameters are simulated by setting Field 1 to 01, selecting 0000 0011 assigned. Two bits have the value 1; therefore, two the desired parameter in Field 2, and the desired value for the fuses need to be blown. Because only one fuse can be blown at a parameter in Field 4. Note that a value of 11 for Field 2 is ignored time, this code can be used to blow one fuse: during the simulation mode. Examples of temporary settings 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110. are as follows: The MOS switch that blows the fuse closes when the complete • Setting the second stage gain code (Parameter 00) to 011 and packet is recognized and opens when the start-of-packet, the second stage gain to 50 produces: dummy, or end-of-packet fields are no longer valid. After 1 ms, 1000 0000 0001 01 00 10 0000 0011 0111 1111 1110. this second code is entered to blow the second fuse: • Setting the first stage gain code (Parameter 01) to 000 1011 1000 0000 0001 10 00 10 0000 0001 0111 1111 1110. and the first stage gain to 4.166 produces: To permanently set the first stage gain to a nominal value of 1000 0000 0001 01 01 10 0000 1011 0111 1111 1110. 4.151, Parameter 01 needs to have the value 000 1011 assigned. A first stage gain of 4.166 with a second stage gain of 50 gives a Three fuses need to be blown, and the following codes are used, total gain of 208.3. This gain has a maximum tolerance of 2.5%. with a 1 ms delay after each code: • Set the output offset code (Parameter 10) to 0100 0000 and 1000 0000 0001 10 01 10 0000 1000 0111 1111 1110 the output offset to 1.260 V when VDD = 5 V and VSS = 0 V. 1000 0000 0001 10 01 10 0000 0010 0111 1111 1110 This output offset has a maximum tolerance of 0.8%: 1000 0000 0001 10 01 10 0000 0001 0111 1111 1110. 1000 0000 0001 01 10 10 0100 0000 0111 1111 1110. To permanently set the output offset to a nominal value of Programming Mode 1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs to have the value 0100 0000 assigned. If one fuse needs to be Intact fuses give a bit value of 0. Bits with a desired value of 1 blown, use the following code: need to have the associated fuse blown. Because a relatively 1000 0000 0001 10 10 10 0100 0000 0111 1111 1110. large current is needed to blow a fuse, only one fuse can be reliably blown at a time. Therefore, a given parameter value may Finally, to blow the master fuse to deactivate the simulation need several 38-bit words to allow reliable programming. A mode and prevent further programming, use code: 5.25 V (±0.25 V) supply is required when blowing fuses to 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110. minimize the on resistance of the internal MOS switches that There are 20 programmable fuses. Because each fuse requires blow the fuse. The power supply voltage must not exceed the 1 ms to blow, and each serial word can be loaded in 2.3 ms, absolute maximum rating and must be able to deliver 250 mA the maximum time needed to program the fuses can be as of current. low as 66 ms. Rev. A | Page 20 of 28 AD8556 Parity Error Detection The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18). A parity check is used to determine whether the programmed The output of Cell EOR18 is the DAT_SUM signal. If there is data of an AD8556 is valid, or whether data corruption has an even number of 1s in the 18-bit word, DAT_SUM = 0; and if occurred in the nonvolatile memory. Figure 50 shows the there is an odd number of 1s in the 18-bit word, DAT_SUM = 1. schematic implemented in the AD8556. See Table 12 for examples. VA0 to VA2 is the 3-bit control signal for the second stage gain, After the second stage gain, first stage gain, and output offset VB0 to VB6 is the 7-bit control signal for the first stage gain, are programmed, compute DAT_SUM and set the parity bit and VC0 to VC7 is the 8-bit control signal for the output offset. equal to DAT_SUM. If DAT_SUM is 0, the parity fuse should PFUSE is the signal from the parity fuse, and MFUSE is the not be blown in order for the PFUSE signal to be 0. If DAT_SUM is signal from the master fuse. 1, the parity fuse should be blown to set the PFUSE signal to 1. The function of the 2-input AND gate (Cell AND2) is to ignore The code to blow the parity fuse is: the output of the parity circuit (PAR_SUM signal) when the 1000 0000 0001 10 11 10 0000 0100 01111111 1110. master fuse is not blown. PARITY_ERROR is set to 0 when After setting the parity bit, the master fuse can be blown to MFUSE = 0. In the simulation mode, for example, parity check prevent further programming, using the code: is disabled. After the master fuse is blown, that is, after the 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110. AD8556 is programmed, the output from the parity circuit (PAR_SUM signal) is fed to PARITY_ERROR. When Signal PAR_SUM is the output of the 2-input exclusive-OR gate PARITY_ERROR is 0, the AD8556 behaves as a programmed (Cell EOR2). After the master fuse is blown, set PARITY_ERROR amplifier. When PARITY_ERROR is 1, a parity error is detected, to PAR_SUM. As previously mentioned, the AD8556 behaves as and VOUT is connected to VSS. a programmed amplifier when PARITY_ERROR = 0 (no parity error). On the other hand, VOUT is connected to VSS when a parity error is detected, that is, when PARITY_ERROR = 1. I0 VA0 IN01 VA1 IN02 VA2 IN03 VB0 IN04 VB1 IN05 VB2 IN06 VB3 IN07 VB4 IN08 DAT_SUM VB5 IN09 EOR18 OUT IN1 PAR_SUM I1 IN1 VB6 IN10 I2 PFUSE IN2 OUT PARITY_ERROR OUT VC0 IN11 MFUSE IN2 EOR2 AND2 VC1 IN12 VC2 IN13 VC3 IN14 VC4 IN15 VC5 IN16 VC6 IN17 VC7 IN18 Figure 50. Functional Circuit of AD8556 Parity Check Table 12. Examples of DAT_SUM Second Stage Gain Code First Stage Gain Code Output Offset Code Number of Bits with 1 DAT_SUM 000 000 0000 0000 0000 0 0 000 000 0000 1000 0000 1 1 000 000 0000 1000 0001 2 0 000 000 0001 0000 0000 1 1 000 100 0001 0000 0000 2 0 001 000 0000 0000 0000 1 1 001 000 0001 1000 0000 3 1 111 111 1111 1111 1111 18 0 Rev. A | Page 21 of 28 05448-050 AD8556 Read Mode It is theoretically possible, though very unlikely, for a fuse to be incompletely blown during programming, assuming the The values stored by the polysilicon fuses can be sent to the required conditions are met. In this situation, the fuse could FILT/DIGOUT pin to verify correct programming. Normally, have a medium resistance, neither low nor high, and a voltage the FILT/DIGOUT pin is only connected to the second gain stage of approximately 1.5 V could be developed across the fuse. output via RF. During read mode, however, the FILT/DIGOUT pin Therefore, the OTP cell could output Logic 0 or Logic 1, depending is also connected to the output of a shift register to allow the on temperature, supply voltage, and other variables. polysilicon fuse contents to be read. Because VOUT is a buffered version of FILT/DIGOUT, VOUT also outputs a digital signal To detect this undesirable situation, the sense current can be during read mode. lowered by a factor of 4 using a specific code. The voltage developed across the fuse would then change from 1.5 V to Read mode is entered by setting Field 1 to 11 and selecting the 0.38 V, and the output of the OTP would be Logic 0 instead of desired parameter in Field 2. Field 4 is ignored. The parameter the expected Logic 1 from a blown fuse. Fuses blown correctly value, stored in the polysilicon fuses, is loaded into an internal would still output Logic 1. In this way, fuses blown incorrectly shift register, and the MSB of the shift register is connected to can be detected. Another specific code would return the sense the FILT/DIGOUT pin. Pulses at DIGIN shift out the shift current to the normal (larger) value. The sense current cannot register contents to the FILT/DIGOUT pin, allowing the 8‒bit be permanently programmed to the low value. When the AD8556 parameter value to be read after seven additional pulses; shifting is powered up, the sense current defaults to the high value. occurs on the falling edge of DIGIN. An eighth pulse at DIGIN disconnects FILT/DIGOUT from the shift register and terminates The low sense current code is: the read mode. If a parameter value is less than eight bits long, 1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110. the MSBs of the shift register are padded with 0s. The normal (high) sense current code is: For example, to read the second stage gain, this code is used: 1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110. 1000 0000 0001 11 00 10 0000 0000 0111 1111 1110. Because Programming Procedure the second stage gain parameter value is only three bits long, For reliable fuse programming, it is imperative to follow the the FILT/DIGOUT pin has a value of 0 when this code is programming procedure requirements, especially the proper entered, and remains 0 during four additional pulses at DIGIN. supply voltage during programming. The fifth, sixth, and seventh pulses at DIGIN return the 3-bit value at FILT/DIGOUT, the seventh pulse returns the LSB. An 1. When programming the AD8556, the temperature of the eighth pulse at DIGIN terminates the read mode. device must be between 10°C and 40°C. 2. Set VDD and VSS to the desired values in the application. Sense Current Use simulation mode to test and determine the desired A sense current is sent across each polysilicon fuse to determine codes for the second stage gain, first stage gain, and output whether it has been blown. When the voltage across the fuse is offset. The nominal values for these parameters are shown less than approximately 1.5 V, the fuse is considered not blown, in Table 5, Table 6, Equation 2, and Equation 3; use the and Logic 0 is output from the OTP cell. When the voltage across codes corresponding to these values as a starting point. the fuse is greater than approximately 1.5 V, the fuse is considered However, because actual parameter values for given codes blown, and Logic 1 is output. vary from device to device, some fine tuning is necessary When the AD8556 is manufactured, all fuses have a low for the best possible accuracy. resistance. When a sense current is sent through the fuse, a One way to choose these values is to set the output offset voltage less than 0.1 V is developed across the fuse, which is to an approximate value, such as Code 128 for midsupply, much lower than 1.5 V; therefore, Logic 0 is output from the to allow the required gain to be determined. Then set the OTP cell. When a fuse is electrically blown, it should have a second stage gain so the minimum first stage gain (Code 0) very high resistance. When the sense current is applied to the gives a lower gain than required, and the maximum first blown fuse, the voltage across the fuse should be larger than stage gain (Code 127) gives a higher gain than required. 1.5 V; therefore, Logic 1 is output from the OTP cell. After choosing the second stage gain, the first stage gain can be chosen to fine tune the total gain. Finally, the output offset can be adjusted to give the desired value. After determining the desired codes for second stage gain, first stage gain, and output offset, the device is ready for permanent programming. Rev. A | Page 22 of 28 AD8556 Important: Once a programming attempt is made for any 4. Measure the resulting gain, G . G should be within BBBB fuse, there should be no further attempt to blow that fuse. 3% of G . A If a fuse does not program to the expected state, discard 5. Calculate the first stage gain error (in relative terms) the unit. The expected incidence rate of attempted but E = G /G − 1. G1 BBA unblown fuses is very small when following the proper 6. Calculate the error (in the number of the first stage gain programming procedure and conditions. codes) CEG1 = EG1/0.00370. 3. Set VSS to 0 V and VDD to 5.25 V (±0.25 V). Power 7. Set the first stage gain code to CG1 − CEG1. supplies should be capable of supplying 250 mA at the required voltage and properly bypassed as described 8. Measure the gain, GC. GC should be closer to GA than to GBB. in the Programming Mode section. Use program mode to 9. Calculate the error (in relative terms) E = G /G − 1. G2 C A permanently enter the desired codes for the first stage gain, 10. Calculate the error (in the number of the first stage gain second stage gain, and output offset. Blow the parity bit codes) C = E /0.00370. EG2 G2 fuse if necessary (see Parity Error Detection section). Blow the master fuse to allow the AD8556 to read data from the 11. Set the first stage gain code to CG1 − CEG1 − CEG2. The fuses and to prevent further programming. resulting gain should be within one code of GA. 4. Set VDD and VSS to the desired values in the application. Use read mode with low sense current followed by high Finally, determine the desired output offset: sense current to verify programmed codes. 5. Measure gain and offset to verify correct functionality. 1. Determine the desired output offset O (using the A measurements obtained from the simulation). Determining Optimal Gain and Offset Codes 2. Use Equation 2 to set the output offset code C such that O1 First, determine the desired gain: the output offset is nominally O . A 1. Determine the desired gain, GA (using the measurements 3. Measure the output offset, OBB. OBB should be within obtained from the simulation). 3% of OA. 2. Use Table 6 to determine G , the second stage gain, such 2 that (4.00 × 1.04) < (G /G ) < (6.4/1.04). This ensures the A 2 4. Calculate the error (in relative terms) EO1 = OBB/OA − 1. first and last codes for the first stage gain are not used, 5. Calculate the error (in the number of the output offset thereby allowing enough first stage gain codes within each codes) C = E /0.00392. EO1 O1 second stage gain range to adjust for the 3% accuracy. 6. Set the output offset code to C − C . O1 EO1 Next, set the second stage gain: 7. Measure the output offset, O . O should be closer to O C C A 1. Use the simulation mode to set the second stage gain to G2. than to O . BB 2. Set the output offset to allow the AD8556 gain to be 8. Calculate the error (in relative terms) EO2 = OC/OA − 1. measured, for example, use Code 128 to set it to 9. Calculate the error (in the number of the output offset midsupply. codes) CEO2 = EO2/0.00392. 3. Use Table 5 or Equation 1 to set the first stage gain code 10. Set the output offset code to C − C − C . The O1 EO1 EO2 CG1, so the first stage gain is nominally GA/G2. resulting offset should be within one code of O . A Rev. A | Page 23 of 28 AD8556 EMI/RFI PERFORMANCE Real-world applications must work with ever increasing The AD8556 features internal EMI filters on the VNEG, VPOS, radio/magnetic frequency interference (RFI and EMI). In FILT, and VCLAMP pins. These built-in filters on the pins limit situations where signal strength is low and transmission lines the interference bandwidth and provide good RFI suppression are long, instrumentation amplifiers, such as the AD8556, are without reducing performance within the pass-band of the needed to extract weak, small differential signals riding on instrumentation amplifier. A functional diagram of the common-mode noise and interference. Additionally, wires and AD8556 along with its EMI/RFI filters is shown in Figure 51. PCB traces act as antennas and pick up high frequency EMI The AD8556 has built-in filters on its inputs, VCLAMP, and signals. The longer the wire, the larger the voltage it picks up. filter pins. The first-order, low-pass filters inside the AD8556 The amount of voltages picked up is dependent on the impedances are useful to reject high frequency EMI signals picked up by at the wires, as well as the EMI frequency. These high frequency wires and PCB traces outside the AD8556. The most sensitive voltages are then passed into the in-amp through its pins. All pin of any amplifier to RFI/EMI signal is the noninverting pin. instrumentation amplifiers can rectify high frequency out-of- Signals present at this pin appear as common-mode signals and band signals. Unfortunately, the EMI/RFI rectification occurs create problems. because amplifiers do not have any significant common-mode The filters built at the input of the AD8556 have two different rejection above 100 kHz. Once these high frequency signals are bandwidths: common mode and differential mode. The common- rectified, they appear as dc offset errors at the output. mode bandwidth defines what a common-mode RF signal sees between the two inputs tied together and ground. The EMI filters placed on the input pins of the AD8556 reject EMI/RFI suppressions that appear as common-mode signals. DIGIN VCLAMP VDD EMI 1 +IN 3 FILTER A5 OUT 2 LOGIC DAC –IN VSS VDD EMI 1 +IN R5 P4 R7 VPOS 3 FILTER A1 OUT 2 –IN R2 VSS P2 VDD VDD EMI FILTER R3 1 RF +IN 3 EMI 1 A3 +IN OUT 2 3 FILTER A4 P1 OUT V –IN OUT 2 –IN VDD VSS R1 1 +IN R4 R5 VSS 3 A2 OUT EMI 2 VNEG –IN P3 FILTER VSS AD8556 VSS FILT/DIGOUT Figure 51. Block Diagram Showing EMI/RFI Built-In Filters Rev. A | Page 24 of 28 05448-053 AD8556 To show the benefits that the AD8556 brings to new applications The differential bandwidth defines the frequency response of where EMI/RFI signals are present, a part was programmed the filters with a differential signal applied between the two with a gain of 70 and a dc offset of 2.5 V to produce a VOUT of inputs, VPOS (that is, +IN ) and VNEG (that is, –IN). Figure 54 0 V. A test circuit like that shown in Figure 52 was used. shows the circuit used to test for AD8556 EMI/RFI susceptibility. The part is programmed as previously stated during the Figure 52 simulates the presence of a noisy common-mode common-mode testing. signal, and Figure 53 shows the response dc values at VOUT. +2.5V –2.5V +2.5V –2.5V U2 U3 1 8 VCC VEE 1 8 VCC VEE 2 7 7 FILTER VOUT VOUT 2 FILTER VOUT VOUT 3 6 DATA VCLAMP +2.5V 3 6 VCLAMP DATA +2.5V 45 –IN +IN 45 –IN +IN AD8556 V2 AD8556 + – 200mV p-p Figure 54. Test Circuit to Show AD8556 Performance Exposed to V3 + Differential Mode RFI/EMI Signals VARIABLE – The response of AD8556 to EMI/RFI differential signals is shown in Figure 55. Figure 52. Test Circuit to Show AD8556 Performance Exposed to Common-Mode RFI/EMI Signals 600 100 400 200 80 AD8556 0 –200 60 NON-ENHANCED FOR EMI –400 40 –600 –800 20 –1000 NON-ENHANCED PART 0 –1200 AD8556 (ENHANCED PART FOR EMI) –1400 0 200 400 600 800 1000 1200 –20 FREQUENCY (MHz) 0 200 400 600 800 1000 1200 Figure 55. Response of AD8556 to EMI/RFI Differential Signals FREQUENCY (MHz) Figure 53. DC Offset Values at VOUT Caused by Frequency Seep of Input To make a board robust against EMI, the leads at VPOS and VNEG should be as similar as possible. In this way, any EMI received by the VPOS and VNEG pins will be similar (that is, a common-mode input), and rejected by the AD8556. Furthermore, additional filtering at the VPOS and VNEG pins should give a better reduction of unwanted behavior compared with filtering at the other pins. Rev. A | Page 25 of 28 DEVIATION FROM DC OUTPUT (mV) 05448-051 05448-054 DC OFFSET (mV) 05448-052 05448-055 AD8556 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2440) 4.00 (0.1574) 5.80 (0.2284) 3.80 (0.1497) 1 4 1.27 (0.0500) 0.50 (0.0196) × 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 8° 0.51 (0.0201) 0° 1.27 (0.0500) COPLANARITY 0.25 (0.0098) 0.31 (0.0122) SEATING 0.10 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 56. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 4.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 13 16 1 12 PIN 1 0.65 BSC 2.50 INDICATOR TOP 3.75 EXPOSED 2.35 SQ VIEW PAD BSC SQ (BOTTOM VIEW) 2.20 0.50 9 0.40 4 8 5 0.30 0.25 MIN 0.80 MAX 1.95 BSC 12° MAX 0.65 TYP 0.05 MAX 1.00 0.02 NOM 0.85 0.35 0.80 0.20 REF 0.30 COPLANARITY SEATING 0.08 0.25 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-10) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD8556ARZ −40°C to +140°C 8-Lead SOIC_N R-8 1 AD8556ARZ-REEL −40°C to +140°C 8-Lead SOIC_N R-8 1 AD8556ARZ-REEL7 −40°C to +140°C 8-Lead SOIC_N R-8 1 AD8556ACPZ-R2 −40°C to +140°C 16-Lead LFCSP_VQ CP-16-10 1 AD8556ACPZ-REEL −40°C to +140°C 16-Lead LFCSP_VQ CP-16-10 1 AD8556ACPZ-REEL7 −40°C to +140°C 16-Lead LFCSP_VQ CP-16-10 1 Z = RoHS Compliant Part. Rev. A | Page 26 of 28 010606-0 AD8556 NOTES Rev. A | Page 27 of 28 AD8556 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05448-0-12/07(A) Rev. A | Page 28 of 28