ANALOG DEVICES AD8554

Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers AD8551/AD8552/AD8554 FEATURES PIN CONFIGURATIONS Low offset voltage: 1 μV 18 NC NC Input offset drift: 0.005 μV/°C –IN A V+ AD8551 +IN A OUT A Rail-to-rail input and output swing V– 45 NC 5 V/2.7 V single-supply operation NC = NO CONNECT Figure 1. 8-Lead MSOP (RM Suffix) High gain, CMRR, PSRR: 130 dB Ultralow input bias current: 20 pA Low supply current: 700 μA/op amp NC 1 8 NC –IN A 2 7 V+ Overload recovery time: 50 μs AD8551 +IN A 3 6 OUT A No external capacitors required V– 4 5 NC APPLICATIONS NC = NO CONNECT Temperature sensors Figure 2. 8-Lead SOIC (R Suffix) Pressure sensors OUT A 18 V+ Precision current sensing –IN A OUT B AD8552 +IN A –IN B Strain gage amplifiers V– 45 +IN B Medical instrumentation Figure 3. 8-Lead TSSOP (RU Suffix) Thermocouple amplifiers GENERAL DESCRIPTION OUT A 1 8 V+ –IN A 2 7 OUT B This family of amplifiers has ultralow offset, drift, and bias AD8552 +IN A 3 6 –IN B current. The AD8551, AD8552, and AD8554 are single, dual, V– 4 5 +IN B and quad amplifiers featuring rail-to-rail input and output swings. Figure 4. 8-Lead SOIC (R Suffix) All are guaranteed to operate from 2.7 V to 5 V with a single supply. OUT A 114 OUT D The AD855x family provides the benefits previously found only –IN A –IN D +IN A +IN D in expensive auto-zeroing or chopper-stabilized amplifiers. V+ AD8554 V– +IN B +IN C Using Analog Devices, Inc. topology, these new zero-drift –IN B –IN C amplifiers combine low cost with high accuracy. No external OUT B 78 OUT C capacitors are required. Figure 5. 14-Lead TSSOP (RU Suffix) With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the OUT A 1 14 OUT D AD855x are perfectly suited for applications in which error 2 13 –IN A –IN D sources cannot be tolerated. Temperature, position and pressure 3 12 +IN A +IN D sensors, medical equipment, and strain gage amplifiers benefit 4 11 V+ V– AD8554 greatly from nearly zero drift over their operating temperature 5 10 +IN B +IN C range. The rail-to-rail input and output swings provided by the 6 9 –IN B –IN C AD855x family make both high-side and low-side sensing easy. 7 8 OUT B OUT C The AD855x family is specified for the extended industrial/auto Figure 6. 14-Lead SOIC (R Suffix) motive temperature range (−40°C to +125°C). The AD8551 single amplifier is available in 8-lead MSOP and 8-lead narrow SOIC packages. The AD8552 dual amplifier is available in 8-lead narrow SOIC and 8-lead TSSOP surface-mount packages. The AD8554 quad is available in 14-lead narrow SOIC and 14-lead TSSOP packages. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1999–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01101-002 01101-001 01101-004 01101-003 01101-006 01101-005 AD8551/AD8552/AD8554 TABLE OF CONTENTS Features .............................................................................................. 1  1/f Noise Characteristics ........................................................... 17  Applications ....................................................................................... 1  Intermodulation Distortion ...................................................... 17  General Description ......................................................................... 1  Broadband and External Resistor Noise Considerations ...... 18  Pin Configurations ........................................................................... 1  Output Overdrive Recovery ...................................................... 18  Revision History ............................................................................... 2  Input Overvoltage Protection ................................................... 18  Specif ica t ions ..................................................................................... 3  Output Phase Reversal ............................................................... 19  Electrical Characteristics ............................................................. 3  Capacitive Load Drive ............................................................... 19  Absolute Maximum Ratings ............................................................ 5  Power-Up Behavior .................................................................... 19  Thermal Characteristics .............................................................. 5  A pplica t ions ..................................................................................... 20  ESD Caution .................................................................................. 5  A 5 V Precision Strain Gage Circuit ........................................ 20  Typical Performance Characteristics ............................................. 6  3 V Instrumentation Amplifier ................................................ 20  Functional Description .................................................................. 14  A High Accuracy Thermocouple Amplifier ........................... 21  Amplifier Architecture .............................................................. 14  Precision Current Meter ............................................................ 21  Basic Auto-Zero Amplifier Theory .......................................... 14  Precision Voltage Comparator .................................................. 21  High Gain, CMRR, PSRR .......................................................... 16  Outline Dimensions ....................................................................... 22  Maximizing Performance Through Proper Layout ............... 16  Ordering Guide .......................................................................... 23  REVISION HISTORY 9/08—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 23 3/07—Rev. B to Rev. C Changes to Specifications Section .................................................. 3 2/07—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Figure 54 ...................................................................... 16 Deleted Spice Model Section ......................................................... 19 Deleted Figure 63, Renumbered Sequentially ............................ 19 Changes to Ordering Guide .......................................................... 24 11/02—Rev. 0 to Rev. A Edits to Figure 60 ............................................................................ 16 Updated Outline Dimensions ....................................................... 20 Rev. D | Page 2 of 24 AD8551/AD8552/AD8554 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 5 V, V = 2.5 V, V = 2.5 V, T = 25°C, unless otherwise noted. S CM O A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 1 5 μV OS −40°C ≤ T ≤ +125°C 10 μV A Input Bias Current I 10 50 pA B AD8551/AD8554 −40°C ≤ TA ≤ +125°C 1.0 1.5 nA AD8552 −40°C ≤ TA ≤ +85°C 160 300 pA AD8552 −40°C ≤ TA ≤ +125°C 2.5 4 nA Input Offset Current I 20 70 pA OS AD8551/AD8554 −40°C ≤ T ≤ +125°C 150 200 pA A AD8552 −40°C ≤ T ≤ +85°C 30 150 pA A AD8552 −40°C ≤ TA ≤ +125°C 150 400 pA Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V = 0 V to +5 V 120 140 dB CM −40°C ≤ T ≤ +125°C 115 130 dB A 1 Large Signal Voltage Gain A R = 10 kΩ, V = 0.3 V to 4.7 V 125 145 dB VO L O −40°C ≤ TA ≤ +125°C 120 135 dB Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.005 0.04 μV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 100 kΩ to GND 4.99 4.998 V RL = 100 kΩ to GND @ −40°C to +125°C 4.99 4.997 V RL = 10 kΩ to GND 4.95 4.98 V R = 10 kΩ to GND @ −40°C to +125°C 4.95 4.975 V L Output Voltage Low V R = 100 kΩ to V+ 1 10 mV OL L R = 100 kΩ to V+ @ −40°C to +125°C 2 10 mV L RL = 10 kΩ to V+ 10 30 mV RL = 10 kΩ to V+ @ −40°C to +125°C 15 30 mV Output Short-Circuit Limit Current I ±25 ±50 mA SC −40°C to +125°C ±40 mA Output Current I ±30 mA O −40°C to +125°C ±15 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 5.5 V 120 130 dB S −40°C ≤ TA ≤ +125°C 115 130 dB Supply Current/Amplifier ISY VO = 0 V 850 975 μA −40°C ≤ TA ≤ +125°C 1000 1075 μA DYNAMIC PERFORMANCE Slew Rate SR RL = 10 kΩ 0.4 V/μs Overload Recovery Time 0.05 0.3 ms Gain Bandwidth Product GBP 1.5 MHz NOISE PERFORMANCE Voltage Noise en p-p 0 Hz to 10 Hz 1.0 μV p-p e p-p 0 Hz to 1 Hz 0.32 μV p-p n Voltage Noise Density e f = 1 kHz 42 nV/√Hz n Current Noise Density in f = 10 Hz 2 fA/√Hz 1 Gain testing is dependent upon test bandwidth. Rev. D | Page 3 of 24 AD8551/AD8552/AD8554 V = 2.7 V, V = 1.35 V, V = 1.35 V, T = 25°C, unless otherwise noted. S CM O A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 1 5 μV OS −40°C ≤ T ≤ +125°C 10 μV A Input Bias Current I 10 50 pA B AD8551/AD8554 −40°C ≤ TA ≤ +125°C 1.0 1.5 nA AD8552 −40°C ≤ TA ≤ +85°C 160 300 pA AD8552 −40°C ≤ TA ≤ +125°C 2.5 4 nA Input Offset Current I 10 50 pA OS AD8551/AD8554 −40°C ≤ T ≤ +125°C 150 200 pA A AD8552 −40°C ≤ T ≤ +85°C 30 150 pA A AD8552 −40°C ≤ TA ≤ +125°C 150 400 pA Input Voltage Range 0 2.7 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 115 130 dB −40°C ≤ T ≤ +125°C 110 130 dB A 1 Large Signal Voltage Gain A R = 10 kΩ, V = 0.3 V to 2.4 V 110 140 dB VO L O −40°C ≤ TA ≤ +125°C 105 130 dB Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.005 0.04 μV/°C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 100 kΩ to GND 2.685 2.697 V RL = 100 kΩ to GND @ −40°C to +125°C 2.685 2.696 V RL = 10 kΩ to GND 2.67 2.68 V R = 10 kΩ to GND @ −40°C to +125°C 2.67 2.675 V L Output Voltage Low V R = 100 kΩ to V+ 1 10 mV OL L R = 100 kΩ to V+ @ −40°C to +125°C 2 10 mV L RL = 10 kΩ to V+ 10 20 mV RL = 10 kΩ to V+ @ −40°C to +125°C 15 20 mV Short-Circuit Limit ISC ±10 ±15 mA −40°C to +125°C ±10 mA Output Current I ±10 mA O −40°C to +125°C ±5 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 5.5 V 120 130 dB S −40°C ≤ TA ≤ +125°C 115 130 dB Supply Current/Amplifier ISY VO = 0 V 750 900 μA −40°C ≤ TA ≤ +125°C 950 1000 μA DYNAMIC PERFORMANCE Slew Rate SR RL = 10 kΩ 0.5 V/μs Overload Recovery Time 0.05 ms Gain Bandwidth Product GBP 1 MHz NOISE PERFORMANCE Voltage Noise en p-p 0 Hz to 10 Hz 1.6 μV p-p Voltage Noise Density e f = 1 kHz 75 nV/√Hz n Current Noise Density i f = 10 Hz 2 fA/√Hz n 1 Gain testing is dependent upon test bandwidth. Rev. D | Page 4 of 24 AD8551/AD8552/AD8554 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 3. Parameter Rating Table 4. Supply Voltage 6 V Package Type θ θ Unit JA JC Input Voltage GND to V + 0.3 V S 8-Lead MSOP (RM) 190 44 °C/W 1 Differential Input Voltage ±5.0 V 8-Lead TSSOP (RU) 240 43 °C/W ESD (Human Body Model) 2000 V 8-Lead SOIC (R) 158 43 °C/W Output Short-Circuit Duration to GND Indefinite 14-Lead TSSOP (RU) 180 36 °C/W Storage Temperature Range −65°C to +150°C 14-Lead SOIC (R) 120 36 °C/W Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C ESD CAUTION Lead Temperature Range (Soldering, 60 sec) 300°C 1 Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 5 of 24 AD8551/AD8552/AD8554 TYPICAL PERFORMANCE CHARACTERISTICS 180 180 V = 2.7V V = 5V SY SY V = 1.35V V = 2.5V 160 CM 160 CM T = 25°C T = 25°C A A 140 140 120 120 100 100 80 80 60 60 40 40 20 20 0 0 –2.5 –1.5 –0.5 0.5 1.5 2.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 OFFSET VOLTAGE (µV) OFFSET VOLTAGE (µV) Figure 7. Input Offset Voltage Distribution at 2.7 V Figure 10. Input Offset Voltage Distribution at 5 V 50 12 V = 5V SY V = 5V SY T = –40°C, +25°C, +85°C A V = 2.5V 40 CM 10 T = –40°C TO +125°C A +85°C 30 8 20 10 6 +25°C 0 4 –40°C –10 2 –20 0 –30 01 2 3 4 5 0 1 2 345 6 INPUT COMMON-MODE VOLTAGE (V) INPUT OFFSET DRIFT (nV/°C) Figure 8. Input Bias Current vs. Common-Mode Voltage Figure 11. Input Offset Voltage Drift Distribution at 5 V 1500 10k V = 5V SY V = 5V SY T = 125°C A T = 25°C A 1000 1k 500 100 0 SOURCE –500 10 –1000 SINK 1 –1500 0.1 –2000 01 2 3 4 5 0.0001 0.001 0.01 0.1 1 10 100 INPUT COMMON-MODE VOLTAGE (V) LOAD CURRENT (mA) Figure 9. Input Bias Current vs. Common-Mode Voltage Figure 12. Output Voltage to Supply Rail vs. Load Current at 5 V Rev. D | Page 6 of 24 INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (pA) NUMBER OF AMPLIFIERS 01101-008 01101-007 01101-009 OUTPUT VOLTAGE (mV) NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 01101-011 01101-010 01101-012 AD8551/AD8552/AD8554 10k 800 V = 2.7V T = +25°C SY A T = 25°C A 700 1k 600 500 100 400 SOURCE 10 300 SINK 200 1 100 0.1 0 06 1 23 45 0.0001 0.001 0.01 0.1 1 10 100 SUPPLY VOLTAGE (V) LOAD CURRENT (mA) Figure 16. Supply Current per Amplifier vs. Supply Voltage Figure 13. Output Voltage to Supply Rail vs. Load Current at 2.7 V 60 0 V = 2.7V SY V = 2.5V CM 50 C = 0pF L V = 5V SY R = L ∞ 40 0 –250 30 45 20 90 10 135 –500 180 0 –10 225 –750 270 –20 –30 –40 –1000 10k 100k 1M 10M 100M –75 –50 –25 025 50 75 100 125 150 FREQUENCY (Hz) TEMPERATURE (°C) Figure 17. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V Figure 14. Input Bias Current vs. Temperature 1.0 60 V = 5V SY V = 2.5V CM 50 C = 0pF L V = 5V SY R = 5V L ∞ 40 0 0.8 2.7V 30 45 20 90 0.6 10 135 180 0 0.4 –10 225 270 –20 0.2 –30 0 –40 10k 100k 1M 10M 100M –75 –50 –25 025 50 75 100 125 150 FREQUENCY (Hz) TEMPERATURE (°C) Figure 18. Open-Loop Gain and Phase Shift vs. Frequency at 5 V Figure 15. Supply Current vs. Temperature Rev. D | Page 7 of 24 INPUT BIAS CURRENT (pA) OUTPUT VOLTAGE (mV) SUPPLY CURRENT (mA) 01101-013 01101-015 01101-014 OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) SUPPLY CURRENT PER AMPLIFIER (µA) PHASE SHIFT (Degrees) PHASE SHIFT (Degrees) 01101-016 01101-017 01101-018 AD8551/AD8552/AD8554 60 300 V = 5V SY V = 2.7V SY 50 270 C = 0pF L A = –100 V R = 2kΩ L 240 40 30 210 A = –10 V 20 180 10 150 A = +1 V 0 120 A = 100 V –10 90 A = 10 V –20 60 A = 1 V –30 30 –40 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. Closed-Loop Gain vs. Frequency at 2.7 V Figure 22. Output Impedance vs. Frequency at 5 V 60 V = 2.7V SY V = 5V SY C = 300pF L 50 C = 0pF L R = 2kΩ L A = –100 V R = 2kΩ L A = 1 V 40 30 A = –10 V 20 10 A = +1 V 0 –10 –20 –30 2µs 500mV –40 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 20. Closed-Loop Gain vs. Frequency at 5 V Figure 23. Large Signal Transient Response at 2.7 V 300 V = 5V SY V = 2.7V SY 270 C = 300pF L R = 2kΩ L 240 A = 1 V 210 180 150 120 90 A = 100 V 60 A = 10 V 30 A = 1 V 5µs 1V 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 21. Output Impedance vs. Frequency at 2.7 V Figure 24. Large Signal Transient Response at 5 V Rev. D | Page 8 of 24 OUTPUT IMPEDANCE (Ω) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 01101-021 01101-020 01101-019 OUTPUT IMPEDANCE (Ω) 01101-024 01101-023 01101-022 AD8551/AD8552/AD8554 45 V = ±1.35V SY V = ±2.5V SY C = 50pF L R = 2kΩ 40 L R = ∞ L T = 25°C A A = 1 V 35 30 25 20 +OS 15 –OS 10 5 50mV 5µs 0 10 100 1k 10k CAPACITANCE (pF) Figure 25. Small Signal Transient Response at 2.7 V Figure 28. Small Signal Overshoot vs. Load Capacitance at 5 V V = ±2.5V SY C = 50pF L 0V R = L ∞ A = 1 V V V = ±2.5V IN SY V = –200mV p-p IN (RET TO GND) C = 0pF L R = 10kΩ L A = –100 V V OUT 0V 5µs 50mV 20µs 1V BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV Figure 26. Small Signal Transient Response at 5 V Figure 29. Positive Overvoltage Recovery 50 V = ±1.35V SY R = 2kΩ 45 L V IN T = 25°C A 40 0V 35 V = ±2.5V SY V = 200mV p-p 30 IN (RET TO GND) +OS 0V 25 C = 0pF L R = 10kΩ L 20 A = –100 V –OS 15 V 10 OUT 5 20µs 1V 0 BOTTOM SCALE: 1V/DIV 10 100 1k 10k TOP SCALE: 200mV/DIV CAPACITANCE (pF) Figure 27. Small Signal Overshoot vs. Load Capacitance at 2.7 V Figure 30. Negative Overvoltage Recovery Rev. D | Page 9 of 24 SMALL SIGNAL OVERSHOOT (%) 01101-026 01101-025 01101-027 SMALL SIGNAL OVERSHOOT (%) 01101-030 01101-029 01101-028 AD8551/AD8552/AD8554 140 V = ±2.5V S V = ±1.35V SY R = 2kΩ L A = –100 120 V V = 60mV p-p IN 100 80 60 +PSRR 40 –PSRR 20 1V 200µs 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 31. No Phase Reversal Figure 34. PSRR vs. Frequency at ±1.35 V 140 140 V = 2.7V V = ±2.5V SY SY 120 120 100 100 80 80 +PSRR 60 60 40 40 –PSRR 20 20 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 32. CMRR vs. Frequency at 2.7 V Figure 35. PSRR vs. Frequency at ±2.5 V 140 3.0 V = 5V V = ±1.35V SY SY R = 2kΩ L 120 A = 1 2.5 V THD+N < 1% T = 25°C A 100 2.0 80 1.5 60 1.0 40 0.5 20 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 33. CMRR vs. Frequency at 5 V Figure 36. Maximum Output Swing vs. Frequency at 2.7 V Rev. D | Page 10 of 24 CMRR (dB) CMRR (dB) 01101-031 01101-033 01101-032 PSRR (dB) PSRR (dB) OUTPUT SWING (V p-p) 01101-036 01101-035 01101-034 AD8551/AD8552/AD8554 5.5 V = 2.7V SY V = ±2.5V SY R = 0Ω 5.0 S R = 2kΩ L 182 A = 1 V 4.5 THD+N < 1% 156 T = 25°C 4.0 A 130 3.5 3.0 104 2.5 78 2.0 52 1.5 1.0 26 0.5 0 0 0.5 1.0 1.5 2.0 2.5 100 1k 10k 100k 1M FREQUENCY (kHz) FREQUENCY (Hz) Figure 37. Maximum Output Swing vs. Frequency at 5 V Figure 40. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz V = ±1.35V V = 2.7V SY SY A = 10000 R = 0Ω V S 112 96 80 0V 64 48 32 16 1s 2mV 0 5 10 15 20 25 FREQUENCY (kHz) Figure 38. 0.1 Hz to 10 Hz Noise at 2.7 V Figure 41. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz V = ±2.5V V = 5V SY SY A = 10000 R = 0Ω V S 91 78 65 52 39 26 13 1s 2mV 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (kHz) Figure 39. 0.1 Hz to 10 Hz Noise at 5 V Figure 42. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHz Rev. D | Page 11 of 24 OUTPUT SWING (V p-p) 01101-039 01101-038 01101-037 e (nV/√Hz) e (nV/√Hz) e (nV/√Hz) n n n 01101-042 01101-041 01101-040 AD8551/AD8552/AD8554 150 V = 5V SY V = 2.7V TO 5.5V SY R = 0Ω S 112 145 96 80 140 64 135 48 32 130 16 125 0 5 10 15 20 25 –75 –50 –25 0 25 50 75 100 125 150 FREQUENCY (kHz) TEMPERATURE (°C) Figure 43. Voltage Noise Density at 5 V from 0 Hz to 25 kHz Figure 45. Power Supply Rejection vs. Temperature 50 V = 5V SY V = 2.7V SY R = 0Ω 40 S 168 30 144 I SC– 20 120 10 96 0 I SC+ –10 72 –20 48 –30 24 –40 –50 0 510 –75 –50 –25 0 25 50 75 100 125 150 FREQUENCY (Hz) TEMPERATURE (°C) Figure 44. Voltage Noise Density at 5 V from 0 Hz to 10 Hz Figure 46. Output Short-Circuit Current vs. Temperature Rev. D | Page 12 of 24 e (nV/√Hz) e (nV/√Hz) n n 01101-044 01101-043 SHORT-CIRCUIT CURRENT (mA) POWER SUPPLY REJECTION (dB) 01101-046 01101-045 AD8551/AD8552/AD8554 100 250 V = 5.0V V = 5.0V SY SY 80 225 I SC– 60 200 40 175 20 150 R = 1kΩ L 0 125 –20 100 I SC+ –40 75 –60 50 R = 100kΩ L –80 25 R = 10kΩ L –100 0 –75 25 100 125 150 –50 –25 0 50 75 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 49. Output Voltage to Supply Rail vs. Temperature Figure 47. Output Short-Circuit Current vs. Temperature 250 V = 2.7V SY 225 200 175 150 125 R = 1kΩ L 100 75 50 R = 100kΩ L 25 R = 10kΩ L 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 48. Output Voltage to Supply Rail vs. Temperature Rev. D | Page 13 of 24 SHORT-CIRCUIT CURRENT (mA) OUTPUT VOLTAGE TO SUPPLY RAIL (mV) 01101-048 01101-047 OUTPUT VOLTAGE TO SUPPLY RAIL (mV) 01101-049 AD8551/AD8552/AD8554 FUNCTIONAL DESCRIPTION BASIC AUTO-ZERO AMPLIFIER THEORY The AD855x family of amplifiers are high precision, rail-to-rail operational amplifiers that can be run from a single-supply Autocorrection amplifiers are not a new technology. Various IC voltage. Their typical offset voltage of less than 1 μV allows implementations have been available for more than 15 years with these amplifiers to be easily configured for high gains without some improvements made over time. The AD855x design offers risk of excessive output voltage errors. The extremely small a number of significant performance improvements over previous temperature drift of 5 nV/°C ensures a minimum of offset versions while attaining a very substantial reduction in device voltage error over its entire temperature range of −40°C to cost. This section offers a simplified explanation of how the +125°C, making the AD855x amplifiers ideal for a variety of AD855x is able to offer extremely low offset voltages and high sensitive measurement applications in harsh operating open-loop gains. environments, such as underhood and braking/suspension As noted in the Amplifier Architecture section, each AD855x systems in automobiles. op amp contains two internal amplifiers. One is used as the The AD855x family are CMOS amplifiers and achieve their primary amplifier, the other as an autocorrection, or nulling, high degree of precision through auto-zero stabilization. This amplifier. Each amplifier has an associated input offset voltage autocorrection topology allows the AD855x to maintain its low that can be modeled as a dc voltage source in series with the offset voltage over a wide temperature range and over its noninverting input. In Figure 50 and Figure 51 these are labeled operating lifetime. as VOSX, where x denotes the amplifier associated with the offset: A for the nulling amplifier and B for the primary amplifier. The AMPLIFIER ARCHITECTURE open-loop gain for the +IN and −IN inputs of each amplifier is Each AD855x op amp consists of two amplifiers, a main ampli- given as A . Both amplifiers also have a third voltage input with X fier and a secondary amplifier, used to correct the offset voltage an associated open-loop gain of B . X of the main amplifier. Both consist of a rail-to-rail input stage, There are two modes of operation determined by the action of allowing the input common-mode voltage range to reach both two sets of switches in the amplifier: an auto-zero phase and an supply rails. The input stage consists of an NMOS differential amplification phase. pair operating concurrently with a parallel PMOS differential pair. The outputs from the differential input stages are combined Auto-Zero Phase in another gain stage whose output is used to drive a rail-to-rail In this phase, all φA switches are closed and all φB switches are output stage. opened. Here, the nulling amplifier is taken out of the gain loop The wide voltage swing of the amplifier is achieved by using two by shorting its two inputs together. Of course, there is a degree of offset voltage, shown as VOSA, inherent in the nulling amplifier output transistors in a common-source configuration. The which maintains a potential difference between the +IN and output voltage range is limited by the drain-to-source resistance −IN inputs. The nulling amplifier feedback loop is closed through of these transistors. As the amplifier is required to source or φB and V appears at the output of the nulling amp and on sink more output current, the rDS of these transistors increases, 2 OSA C , an internal capacitor in the AD855x. Mathematically, this raising the voltage drop across these transistors. Simply put, the M1 is expressed in the time domain as output voltage does not swing as close to the rail under heavy output current conditions as it does with light output current. VOA[t] = AAVOSA[t] − BAVOA[t] (1) This is a characteristic of all rail-to-rail output amplifiers. which can be expressed as Figure 12 and Figure 13 show how close the output voltage can get to the rails with a given output current. The output of the A V [t] A OSA V [] t = (2) AD855x is short-circuit protected to approximately 50 mA of OA 1+ B A current. This demonstrates that the offset voltage of the nulling amplifier The AD855x amplifiers have exceptional gain, yielding greater times a gain factor appears at the output of the nulling amplifier than 120 dB of open-loop gain with a load of 2 kΩ. Because the and, thus, on the C capacitor. M1 output transistors are configured in a common-source configuration, the gain of the output stage, and thus the open- loop gain of the amplifier, is dependent on the load resistance. Open-loop gain decreases with smaller load resistances. This is another characteristic of rail-to-rail output amplifiers. Rev. D | Page 14 of 24 AD8551/AD8552/AD8554 V IN+ A (1+ B )V − A B V A A OSA A A OSA A V V [] t = A V [t]+ (6) B OUT OA A IN V IN– 1+ B A B B ФB V OA C M2 V or ФB OSA ФA + ⎛ ⎞ A V A V NB OSA ⎜ ⎟ V [] t A V [] t = + (7) OA A IN ⎜ ⎟ 1+ B –B ⎝ A⎠ A ФA C M1 From these equations, the auto-zeroing action becomes evident. V NA Note the V term is reduced by a 1 + B factor. This shows how OS A Figure 50. Auto-Zero Phase of the AD855x the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. This results Amplification Phase in the primary amplifier output voltage becoming the voltage at When the φB switches close and the φA switches open for the the output of the AD855x amplifier. It is equal to amplification phase, this offset voltage remains on C and, M1 V [t]= A(V [t]+ V )+ B V (8) OUT B IN OSB B NB essentially, corrects any error from the nulling amplifier. The voltage across C is designated as V . Furthermore, V is M1 NA IN In the amplification phase, VOA = VNB, so this can be rewritten as designated as the potential difference between the two inputs to the primary amplifier, or VIN = (VIN+ − VIN−). Thus, the nulling ⎡ ⎤ ⎛ ⎞ V OSB ⎜ ⎟ V [] t = A V [] t + A V + B A V [] t + (9) amplifier can be expressed as ⎢ ⎥ OUT B IN B OSB B A IN ⎜ ⎟ 1+ B ⎢ A ⎥ ⎝ ⎠ ⎣ ⎦ V [t]= A (V [] t − V [] t)− B V [] t (3) OA A IN OSA A NA Combining terms, V IN+ A V B OUT A B V V A A OSA IN– V [] t = V [] t() A + A B + + A V (10) B B OUT IN B B B B OSA 1+ B ФB A V OA C M2 V ФB OSA + The AD855x architecture is optimized in such a way that ФA A A V NB A = A and B = B and B >> 1 A B A B A –B A ФA C M1 Also, the gain product of A B is much greater than A . These A B B allow Equation 10 to be simplified to V NA V [t]≈ V [t]A B + A (V + V ) (11) IN Figure 51. Output Phase of the Amplifier OUT A A A OSA OSB Most obvious is the gain product of both the primary and Because φA is now open and there is no place for C to M1 nulling amplifiers. This AABA term is what gives the AD855x its discharge, the voltage (VNA), at the present time (t), is equal to extremely high open-loop gain. To understand how VOSA and the voltage at the output of the nulling amp (VOA) at the time V relate to the overall effective input offset voltage of the OSB when φA was closed. If the period of the autocorrection switching complete amplifier, establish the generic amplifier equation of frequency is labeled tS, then the amplifier switches between phases every 0.5 × tS. Therefore, in the amplification phase V = k×(V + V ) (12) OUT IN OS,EFF 1 ⎡ ⎤ V [] t = V t− t (4) where k is the open-loop gain of an amplifier and V is its NA NA S OS, EFF ⎢ ⎥ ⎣ 2 ⎦ effective offset voltage. Substituting Equation 4 and Equation 2 into Equation 3 yields Putting Equation 12 into the form of Equation 11 gives 1 ⎡ ⎤ A B V t− t V [t]≈ V [t]A B + V A B (13) A A OSA S OUT IN A A OS,EFF A A ⎢ ⎥ ⎣ 2 ⎦ V [] t = A V [] t + A V [] t − (5) OA A IN A OSA 1+ B A Thus, it is evident that V + V For the sake of simplification, assume that the autocorrection OSA OSB V ≈ (14) OS,EFF B frequency is much faster than any potential change in V or OSA A VOSB. This is a valid assumption because changes in offset The offset voltages of both the primary and nulling amplifiers voltage are a function of temperature variation or long-term are reduced by the Gain Factor B . This takes a typical input A wear time, both of which are much slower than the auto-zero offset voltage from several millivolts down to an effective input clock frequency of the AD855x. This effectively renders VOS offset voltage of submicrovolts. This autocorrection scheme is time invariant; therefore, Equation 5 can be rearranged and the outstanding feature of the AD855x series that continues to rewritten as Rev. D | Page 15 of 24 01101-051 01101-050 AD8551/AD8552/AD8554 earn the reputation of being among the most precise amplifiers Other potential sources of offset error are thermoelectric available on the market. voltages on the circuit board. This voltage, also called Seebeck voltage, occurs at the junction of two dissimilar metals and is HIGH GAIN, CMRR, PSRR proportional to the temperature of the junction. The most Common-mode and power supply rejection are indications common metallic junctions on a circuit board are solder-to- of the amount of offset voltage an amplifier has as a result of a board trace and solder-to-component lead. Figure 54 shows a change in its input common-mode or power supply voltages. As cross-section of the thermal voltage error sources. If the shown in the previous section, the autocorrection architecture temperature of the PC board at one end of the component (T ) A1 of the AD855x allows it to quite effectively minimize offset volt- is different from the temperature at the other end (T ), the A2 ages. The technique also corrects for offset errors caused by resulting Seebeck voltages are not equal, resulting in a thermal common-mode voltage swings and power supply variations. voltage error. This results in superb CMRR and PSRR figures in excess of This thermocouple error can be reduced by using dummy 130 dB. Because the autocorrection occurs continuously, these components to match the thermoelectric error source. Placing figures can be maintained across the entire temperature range the dummy component as close as possible to its partner ensures of the device, from −40°C to +125°C. both Seebeck voltages are equal, thus canceling the thermo- MAXIMIZING PERFORMANCE THROUGH couple error. Maintaining a constant ambient temperature on PROPER LAYOUT the circuit board further reduces this error. The use of a ground plane helps distribute heat throughout the board and reduces To achieve the maximum performance of the extremely high EMI noise pickup. input impedance and low offset voltage of the AD855x, care is needed in laying out the circuit board. The PC board surface COMPONENT LEAD must remain clean and free of moisture to avoid leakage cur- rents between adjacent traces. Surface coating of the circuit V V SC2 SC1 SOLDER SURFACE-MOUNT + COMPONENT board reduces surface moisture and provides a humidity barrier, V V TS1 TS2 + reducing parasitic resistance on the board. The use of guard PC BOARD rings around the amplifier inputs further reduces leakage cur- rents. Figure 52 shows proper guard ring configuration, and T T A1 A2 Figure 53 shows the top view of a surface-mount layout. The IF T ≠ T , THEN COPPER A1 A2 TRACE V + V ≠ V + V guard ring does not need to be a specific width, but it should TS1 SC1 TS2 SC2 form a continuous loop around both inputs. By setting the Figure 54. Mismatch in Seebeck Voltages Causes Thermoelectric Voltage Error guard ring voltage equal to the voltage at the noninverting input, parasitic capacitance is minimized as well. For further R F reduction of leakage currents, components can be mounted to R 1 the PC board using Teflon standoff insulators. V OUT V IN AD8551/ R = R S 1 AD8552/ AD8554 A = 1 + (R /R ) V F 1 V V OUT OUT V V IN IN NOTES AD8552 AD8552 1. R SHOULD BE PLACED IN CLOSE PROXIMITY AND S ALIGNMENT TO R TO BALANCE SEEBECK VOLTAGES. 1 Figure 55. Using Dummy Components to Cancel V Thermoelectric Voltage Errors IN V OUT AD8552 Figure 52. Guard Ring Layout and Connections to Reduce PC Board Leakage Currents V+ R R 1 2 AD8552 R R 2 1 V IN1 V IN2 GUARD RING V GUARD REF RING V REF V– Figure 53. Top View of AD8552 SOIC Layout with Guard Rings Rev. D | Page 16 of 24 01101-053 01101-052 01101-055 01101-054 + + AD8551/AD8552/AD8554 0 1/f NOISE CHARACTERISTICS V = 5V SY A = 60dB V Another advantage of auto-zero amplifiers is their ability to –20 cancel flicker noise. Flicker noise, also known as 1/f noise, is –40 noise inherent in the physics of semiconductor devices, and it increases 3 dB for every octave decrease in frequency. The 1/f –60 corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier. –80 At lower frequencies, flicker noise dominates, causing higher –100 degrees of error for sub-Hertz frequencies or dc precision applications. –120 Because the AD855x amplifiers are self-correcting op amps, they –140 01 1 2 3 4 5 678 90 do not have increasing flicker noise at lower frequencies. In FREQUENCY (kHz) essence, low frequency noise is treated as a slowly varying offset Figure 57. Spectral Analysis of AD855x Output with +60 dB Gain error and is greatly reduced as a result of autocorrection. The correction becomes more effective as the noise frequency When an input signal is applied, the output contains some approaches dc, offsetting the tendency of the noise to increase degree of intermodulation distortion (IMD). This is another exponentially as frequency decreases. This allows the AD855x characteristic feature of all autocorrection amplifiers. IMD to have lower noise near dc than standard low noise amplifiers appears as sum and difference frequencies between the input that are susceptible to 1/f noise. signal and the 4 kHz clock frequency (and its harmonics) and is at a level similar to, or less than, the clock feedthrough at the INTERMODULATION DISTORTION output. The IMD is also proportional to the closed-loop gain of The AD855x can be used as a conventional op amp for gain/ the amplifier. Figure 58 shows the spectral output of an AD8552 bandwidth combinations up to 1.5 MHz. The auto-zero correction configured as a high gain stage (+60 dB) with a 1 mV input frequency of the device is fixed at 4 kHz. Although a trace signal applied. The relative levels of all IMD products and amount of this frequency feeds through to the output, the harmonic distortion add up to produce an output error of amplifier can be used at much higher frequencies. Figure 56 −60 dB relative to the input signal. At unity gain, these add shows the spectral output of the AD8552 with the amplifier up to only −120 dB relative to the input signal. configured for unity gain and the input grounded. 0 V = 5V OUTPUT SIGNAL SY The 4 kHz auto-zero clock frequency appears at the output with 1V rms @ 200Hz A = 60dB V less than 2 μV of amplitude. Harmonics are also present, but at –20 reduced levels from the fundamental auto-zero clock frequency. The amplitude of the clock frequency feedthrough is proportional –40 to the closed-loop gain of the amplifier. Like other autocorrection amplifiers, at higher gains there is more clock frequency –60 feedthrough. Figure 57 shows the spectral output with the amplifier configured for a gain of 60 dB. –80 IMD < 100µV rms 0 V = 5V SY –100 A = 0dB V –20 –120 01 1 23 456 7 890 –40 FREQUENCY (kHz) Figure 58. Spectral Analysis of AD8552 in High Gain with a 1 mV Input Signal –60 For most low frequency applications, the small amount of auto- –80 zero clock frequency feedthrough does not affect the precision –100 of the measurement system. If it is desired, the clock frequency feedthrough can be reduced through the use of a feedback –120 capacitor around the amplifier. However, this reduces the bandwidth of the amplifier. Figure 59 and Figure 60 show a –140 0 1 2 3 4 5 678 910 configuration for reducing the clock feedthrough and the FREQUENCY (kHz) corresponding spectral analysis at the output. The −3 dB Figure 56. Spectral Analysis of AD8552 Output in Unity Gain Configuration bandwidth of this configuration is 480 Hz. Rev. D | Page 17 of 24 OUTPUT SIGNAL (dB) 01101-056 OUTPUT SIGNAL (dB) OUTPUT SIGNAL (dB) 01101-058 01101-057 AD8551/AD8552/AD8554 3.3nF Because the input current noise of the AD855x is very small, it does not become a dominant term unless R is greater than S 100kΩ 4 GΩ, which is an impractical value of source resistance. 100Ω The total noise (e ) is expressed in volts per square root n, TOTAL V = 1mV rms IN @ 200Hz Hertz, and the equivalent rms noise over a certain bandwidth can be found as Figure 59. Reducing Autocorrection Clock Noise Using a Feedback Capacitor e = e × BW (16) n n,TOTAL 0 V = 5V SY where BW is the bandwidth of interest in Hertz. A = 60dB V –20 OUTPUT OVERDRIVE RECOVERY The AD855x amplifiers have an excellent overdrive recovery of –40 only 200 μs from either supply rail. This characteristic is par- ticularly difficult for autocorrection amplifiers because the –60 nulling amplifier requires a nontrivial amount of time to error correct the main amplifier back to a valid output. Figure 29 and –80 Figure 30 show the positive and negative overdrive recovery times for the AD855x. –100 The output overdrive recovery for an autocorrection amplifier is –120 0 1 2 3 4 5 678 910 defined as the time it takes for the output to correct to its final FREQUENCY (kHz) voltage from an overload state. It is measured by placing the Figure 60. Spectral Analysis Using a Feedback Capacitor amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail. The input voltage is BROADBAND AND EXTERNAL RESISTOR NOISE then stepped down to the linear region of the amplifier, usually CONSIDERATIONS to halfway between the supplies. The time from the input signal The total broadband noise output from any amplifier is primarily stepdown to the output settling to within 100 μV of its final a function of three types of noise: input voltage noise from the value is the overdrive recovery time. amplifier, input current noise from the amplifier, and Johnson noise from the external resistors used around the amplifier. INPUT OVERVOLTAGE PROTECTION Input voltage noise, or en, is strictly a function of the amplifier Although the AD855x is a rail-to-rail input amplifier, exercise used. The Johnson noise from a resistor is a function of the re- care to ensure that the potential difference between the inputs sistance and the temperature. Input current noise, or in, creates does not exceed 5 V. Under normal operating conditions, the an equivalent voltage noise proportional to the resistors used amplifier corrects its output to ensure the two inputs are at the around the amplifier. These noise sources are not correlated same voltage. However, if the device is configured as a comparator, with each other and their combined noise sums in a root- or is under some unusual operating condition, the input voltages squared-sum fashion. The full equation is given as may be forced to different potentials. This can cause excessive 1 2 2 current to flow through internal diodes in the AD855x used to 2 e =[e + 4kTr +() i R] (15) n S n S n _ TOTAL protect the input stage against overvoltage. Where: If either input exceeds either supply rail by more than 0.3 V, en = the input voltage noise density of the amplifier. large amounts of current begin to flow through the ESD pro- in = the input current noise of the amplifier. tection diodes in the amplifier. These diodes connect between RS = source resistance connected to the noninverting terminal. the inputs and each supply rail to protect the input transistors −23 k = Boltzmann’s constant (1.38 × 10 J/K). against an electrostatic discharge event and are normally T = ambient temperature in Kelvin (K = 273.15 + °C). reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes become forward-biased. Without The input voltage noise density (e ) of the AD855x is 42 nV/√Hz, n current limiting, excessive amounts of current can flow through and the input noise, in, is 2 fA/√Hz. The en, TOTAL is dominated by these diodes, causing permanent damage to the device. If inputs the input voltage noise, provided the source resistance is less are subjected to overvoltage, appropriate series resistors should than 106 kΩ. With source resistance greater than 106 kΩ, the be inserted to limit the diode current to less than 2 mA maximum. overall noise of the system is dominated by the Johnson noise of the resistor itself. Rev. D | Page 18 of 24 OUTPUT SIGNAL 01101-059 01101-060 AD8551/AD8552/AD8554 The optimum value for the resistor and capacitor is a function OUTPUT PHASE REVERSAL of the load capacitance and is best determined empirically because Output phase reversal occurs in some amplifiers when the input actual C (C ) includes stray capacitances and may differ LOAD L common-mode voltage range is exceeded. As common-mode substantially from the nominal capacitive load. Table 5 shows voltage moves outside of the common-mode range, the outputs some snubber network values that can be used as starting points. of these amplifiers suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair Table 5. Snubber Network Values for Driving Capacitive Loads shutting down and causing a radical shifting of internal CLOAD RX CX voltages, resulting in the erratic output behavior. 1 nF 200 Ω 1 nF 4.7 nF 60 Ω 0.47 μF The AD855x amplifiers have been carefully designed to prevent 10 nF 20 Ω 10 μF any output phase reversal, provided both inputs are maintained within the supply voltages. If there is the potential of one or POWER-UP BEHAVIOR both inputs exceeding either supply voltage, place a resistor in series with the input to limit the current to less than 2 mA to At power-up, the AD855x settles to a valid output within 5 μs. ensure the output does not reverse its phase. Figure 63 shows an oscilloscope photo of the output of the amplifier with the power supply voltage, and Figure 64 shows CAPACITIVE LOAD DRIVE the test circuit. With the amplifier configured for unity gain, the The AD855x family has excellent capacitive load driving device takes approximately 5 μs to settle to its final output capabilities and can safely drive up to 10 nF from a single 5 V voltage. This turn-on response time is much faster than most supply. Although the device is stable, capacitive loading limits other autocorrection amplifiers, which can take hundreds of the bandwidth of the amplifier. Capacitive loads also increase microseconds or longer for their output to settle. the amount of overshoot and ringing at the output. An R-C snubber network, shown in Figure 61, can be used to compensate the amplifier against capacitive load ringing and overshoot. V OUT 5V 0V V OUT V IN R X 200mV p-p AD8551/ V+ C 60Ω L AD8552/ 4.7nF C AD8554 X 0V 0.47µF 1V 5µs Figure 61. Snubber Network Configuration for Driving Capacitive Loads BOTTOM TRACE = 2V/DIV TOP TRACE = 1V/DIV Although the snubber does not recover the loss of amplifier Figure 63. AD855x Output Behavior on Power-Up bandwidth from the load capacitance, it does allow the amplifier to drive larger values of capacitance while maintaining a minimum of overshoot and ringing. Figure 62 shows the V = 0V TO 5V 100kΩ SY output of an AD855x driving a 1 nF capacitor with and without V a snubber network. OUT 100kΩ AD8551/ AD8552/ 10µs AD8554 Figure 64. AD855x Test Circuit for Turn-On Time WITH SNUBBER WITHOUT SNUBBER 100mV V = 5V SY C = 4.7nF LOAD Figure 62. Overshoot and Ringing are Substantially Reduced Using a Snubber Network Rev. D | Page 19 of 24 01101-061 01101-062 01101-064 01101-063 AD8551/AD8552/AD8554 R 2 APPLICATIONS R 1 V2 A 5 V PRECISION STRAIN GAGE CIRCUIT V OUT V1 The extremely low offset voltage of the AD8552 makes it an AD8551/ R 3 R 4 AD8552/ ideal amplifier for any application requiring accuracy with high AD8554 gains, such as a weigh scale or strain gage. Figure 65 shows a R R R 4 2 2 configuration for a single-supply, precision, strain gage IF =, THEN V =× (V1 – V2) OUT R R R 3 1 1 measurement system. Figure 66. Using the AD855x as a Difference Amplifier A REF192 provides a 2.5 V precision reference voltage for A2. In an ideal difference amplifier, the ratio of the resistors are set The A2 amplifier boosts this voltage to provide a 4.0 V refer- exactly equal to ence for the top of the strain gage resistor bridge. Q1 provides R R the current drive for the 350 Ω bridge network. A1 is used to 2 4 A = = (19) V amplify the output of the bridge with the full-scale output R R 1 3 voltage equal to Which sets the output voltage of the system to 2×() R+ R 1 2 (17) = A (V1 − V2) (20) VOUT V R B Due to finite component tolerance, the ratio between the four where RB is the resistance of the load cell. resistors is not exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. Using the values given in Figure 65, the output voltage linearly Referring to Figure 66, the exact common-mode rejection ratio varies from 0 V with no strain to 4.0 V under full strain. can be expressed as 2 5V R R + 2R R + R R 3 1 4 2 4 2 3 Q1 2.5V CMRR= (21) REF192 1kΩ 2N2222 6 2R R − 2R R A2 1 4 2 3 OR 4 AD8552-B EQUIVALENT In the three-op amp, instrumentation amplifier configuration 12.0kΩ 20kΩ 4.0V shown in Figure 67, the output difference amplifier is set to R R 1 2 unity gain with all four resistors equal in value. If the tolerance 17.4kΩ 100Ω of the resistors used in the circuit is given as δ, the worst-case CMRR of the instrumentation amplifier is V OUT 40mV A1 0V TO 4.0V FULL-SCALE 350Ω 1 AD8552-A LOAD CMRR = (22) MIN CELL R R 3 4 2δ 17.4kΩ 100Ω AD8554-A V2 R NOTES 1. USE 0.1% TOLERANCE RESISTORS. Figure 65. A 5 V Precision Strain Gage Amplifier R R R V G OUT 3 V INSTRUMENTATION AMPLIFIER R AD8554-C R R The high common-mode rejection, high open-loop gain, and R operation down to 3 V of supply voltage makes the AD855x an V1 TRIM AD8554-B excellent choice of op amp for discrete single-supply instrumen- tation amplifiers. The common-mode rejection ratio of the 2R V = 1 + (V1 – V2) OUT R G AD855x is greater than 120 dB, but the CMRR of the system is Figure 67. A Discrete Instrumentation Amplifier Configuration also a function of the external resistor tolerances. The gain of the difference amplifier shown in Figure 66 is given as Consequently, using 1% tolerance resistors results in a worst- case system CMRR of 0.02, or 34 dB. Therefore, either high ⎛ ⎞⎛ ⎞ ⎛ ⎞ R R R 4 1 2 ⎜ ⎟⎜ ⎟ ⎜ ⎟ V = V1 1+ −V2 (18) OUT ⎜ ⎟⎜ ⎟ ⎜ ⎟ precision resistors or an additional trimming resistor, as shown R + R R R ⎝ 3 4⎠⎝ 2⎠ ⎝ 1⎠ in Figure 67, should be used to achieve high common-mode rejection. The value of this trimming resistor should be equal to the value of R multiplied by its tolerance. For example, using 10 kΩ resistors with 1% tolerance requires a series trimming resistor equal to 100 Ω. Rev. D | Page 20 of 24 01101-065 01101-066 01101-067 AD8551/AD8552/AD8554 A HIGH ACCURACY THERMOCOUPLE AMPLIFIER ⎛ ⎞ R SENSE Monitor Output= R ×⎜ ⎟× I (23) 2 L ⎜ ⎟ Figure 68 shows a K-type thermocouple amplifier configuration R 1 ⎝ ⎠ with cold junction compensation. Even from a 5 V supply, the Using the components shown in Figure 69, the monitor output AD8551 can provide enough accuracy to achieve a resolution of transfer function is 2.5 V/A. better than 0.02°C from 0°C to 500°C. D1 is used as a tempera- ture measuring device to correct the cold junction error from Figure 70 shows the low-side monitor equivalent. In this circuit, the thermocouple and should be placed as close as possible to the input common-mode voltage to the AD8552 is at or near the two terminating junctions. With the thermocouple measuring ground. Again, a 0.1 Ω resistor provides a voltage drop propor- tip immersed in a 0°C ice bath, R6 should be adjusted until the tional to the return current. The output voltage is given as output is at 0 V. ⎛ ⎞ R 2 ⎜ ⎟ V =() V+− × R × I (24) Using the values shown in Figure 68, the output voltage tracks OUT SENSE L ⎜ ⎟ R ⎝ 1 ⎠ temperature at 10 mV/°C. For a wider range of temperature measurement, R can be decreased to 62 kΩ. This creates a 9 For the component values shown in Figure 70, the output 5 mV/°C change at the output, allowing measurements of up transfer function decreases from V+ at −2.5 V/A. to 1000°C. R SENSE I L 0.1Ω 3V V+ 5.000V REF02EZ 12V 2 6 R 3V 8 0.1µF 4 0.1µF R R 124kΩ 1 5 R 10.7kΩ 40.2kΩ 1 5V 3 8 100Ω 10µF 1N4148 + 1/2 1 D1 AD8552 0.1µF 2 R R 7 4 2 453Ω 2.74kΩ 8 2 S – K-TYPE G M1 1 THERMOCOUPLE AD8551 Si9433 40.7µV/°C R 3 D 6 + 200Ω MONITOR 4 0V TO 5.00V OUTPUT R R R 4 3 2 (0°C TO 500°C) 5.62kΩ 53.6Ω 2.49kΩ Figure 69. A High-Side Load Current Monitor Figure 68. A Precision K-Type Thermocouple Amplifier with Cold Junction Compensation V+ PRECISION CURRENT METER R 2 2.49kΩ Because of its low input bias current and superb offset voltage at V OUT single supply voltages, the AD855x is an excellent amplifier for Q1 precision current monitoring. Its rail-to-rail input allows the V+ amplifier to be used as either a high-side or low-side current monitor. Using both amplifiers in the AD8552 provides a simple R 1 1/2 AD8552 method to monitor both current supply and return paths for 100Ω load or fault detection. RETURN TO GROUND R SENSE Figure 69 shows a high-side current monitor configuration. In 0.1Ω this configuration, the input common-mode voltage of the Figure 70. A Low-Side Load Current Monitor amplifier is at or near the positive supply voltage. The rail-to- PRECISION VOLTAGE COMPARATOR rail input of the amplifier provides a precise measurement even with the input common-mode voltage at the supply voltage. The The AD855x can be operated open-loop and used as a precision CMOS input structure does not draw any input bias current, comparator. The AD855x has less than 50 μV of offset voltage ensuring a minimum of measurement error. when run in this configuration. The slight increase of offset voltage stems from the fact that the autocorrection architecture The 0.1 Ω resistor creates a voltage drop to the noninverting operates with lowest offset in a closed-loop configuration, that input of the AD855x. The output of the amplifier is corrected is, one with negative feedback. With 50 mV of overdrive, the until this voltage appears at the inverting input. This creates a device has a propagation delay of 15 μs on the rising edge and current through R1, which in turn flows through R2. The 8 μs on the falling edge. Ensure the maximum differential monitor output is given by voltage of the device is not exceeded. For more information, refer to the Input Overvoltage Protection section. Rev. D | Page 21 of 24 01101-068 01101-070 01101-069 AD8551/AD8552/AD8554 OUTLINE DIMENSIONS 5.00 (0.1968) 3.20 4.80 (0.1890) 3.00 2.80 85 6.20 (0.2441) 4.00 (0.1574) 8 5 5.15 1 5.80 (0.2284) 3.80 (0.1497) 4 3.20 4.90 3.00 4.65 2.80 1 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) PIN 1 0.25 (0.0098) 8° 0.65 BSC 0.10 (0.0040) 0° 0.95 COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.85 0.31 (0.0122) 1.10 MAX 0.25 (0.0098) SEATING 0.40 (0.0157) 0.75 PLANE 0.17 (0.0067) 0.80 8° 0.15 0.38 0.60 0.23 COMPLIANT TO JEDEC STANDARDS MS-012-AA 0° 0.00 0.22 0.40 0.08 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS SEATING COPLANARITY (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR PLANE 0.10 REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 71. 8-Lead Mini Small Outline Package [MSOP] Figure 73. 8-Lead Standard Small Outline Package [SOIC_N] (RM-8) Narrow Body (R-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) 5.10 3.10 5.00 3.00 4.90 2.90 14 8 8 5 4.50 6.40 4.50 4.40 BSC 4.40 6.40 BSC 4.30 4.30 1 7 1 4 PIN 1 PIN 1 0.65 BSC 0.65 BSC 1.05 1.20 1.00 0.15 0.20 MAX 1.20 0.80 0.09 0.05 MAX 0.75 8° 0.15 8° 0.60 SEATING 0.75 0.30 0° 0° 0.05 0.45 0.30 COPLANARITY SEATING PLANE 0.20 0.60 0.19 COPLANARITY 0.10 PLANE 0.19 0.09 0.10 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AA COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 72. 8-Lead Thin Shrink Small Outline Package [TSSOP] Figure 74. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) (RU-14) Dimensions shown in millimeters Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 8 14 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 75. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. D | Page 22 of 24 060606-A 061908-A 012407-A AD8551/AD8552/AD8554 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8551AR −40°C to +125°C 8-Lead SOIC_N R-8 AD8551AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8551AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8551ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8551ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8551ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8551ARM-R2 −40°C to +125°C 8-Lead MSOP RM-8 AHA AD8551ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 AHA 1 AD8551ARMZ −40°C to +125°C 8-Lead MSOP RM-8 AHA# 1 AD8551ARMZ-R2 −40°C to +125°C 8-Lead MSOP RM-8 AHA# 1 AD8551ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 AHA# AD8552AR −40°C to +125°C 8-Lead SOIC_N R-8 AD8552AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8552AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8552ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8552ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8552ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8552ARU −40°C to +125°C 8-Lead TSSOP RU-8 AD8552ARU-REEL −40°C to +125°C 8-Lead TSSOP RU-8 1 AD8552ARUZ −40°C to +125°C 8-Lead TSSOP RU-8 1 AD8552ARUZ-REEL −40°C to +125°C 8-Lead TSSOP RU-8 AD8554AR −40°C to +125°C 14-Lead SOIC_N R-14 AD8554AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14 AD8554AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 1 AD8554ARZ −40°C to +125°C 14-Lead SOIC_N R-14 1 AD8554ARZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14 1 AD8554ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 AD8554ARU −40°C to +125°C 14-Lead TSSOP RU-14 AD8554ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14 1 AD8554ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 1 AD8554ARUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked. Rev. D | Page 23 of 24 AD8551/AD8552/AD8554 NOTES ©1999–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01101-0-9/08(D) Rev. D | Page 24 of 24