ANALOG DEVICES AD8553

1.8 V to 5 V Auto-Zero, In-Amp with Shutdown AD8553 FEATURES PIN CONFIGURATION Low offset voltage: 20 μV max RGA 1 10 RGB Low input offset drift: 0.1 μV/°C max VINP 2 9 VINN AD8553 High CMR: 120 dB min @ G = 100 VCC 3 8 GND TOP VIEW (Not to Scale) VO 4 7 V REF Low noise: 0.7 μV p-p from 0.01 Hz to 10 Hz VFB 5 6 ENABLE Wide gain range: 0.1 to 10,000 Single-supply operation: 1.8 V to 5.5 V Figure 1. 10-Lead MSOP Rail-to-rail output Shutdown capability APPLICATIONS Strain gauge Weigh scales Pressure sensors Laser diode control loops Portable medical instruments Thermocouple amplifiers GENERAL DESCRIPTION The AD8553 is a precision instrumentation amplifier featuring The small package and low power consumption allow low noise, rail-to-rail output and a power-saving shutdown maximum channel density and minimum board size for mode. The AD8553 also features low offset voltage and drift space-critical equipment and portable systems. coupled with high common-mode rejection. In shutdown The AD8553 is specified over the industrial temperature range mode, the total supply current is reduced to less than 4 μA. from −40°C to +85°C. The AD8553 is available in a Pb-free, The AD8553 is capable of operating from 1.8 V to 5.5 V. 10-lead MSOP. With a low offset voltage of 20 μV, an offset voltage drift of 0.1 μV/°C, and a voltage noise of only 0.7 μV p-p (0.01 Hz to 10 Hz), the AD8553 is ideal for applications where error sources cannot be tolerated. Precision instrumentation, position and pressure sensors, medical instrumentation, and strain gauge amplifiers benefit from the low noise, low input bias current, and high common-mode rejection. The small footprint and low cost are ideal for high volume applications. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05474-001 AD8553 TABLE OF CONTENTS Features .............................................................................................. 1  Gain Selection (Gain-Setting Resistors).................................. 12  Applications....................................................................................... 1  Reference Connection ............................................................... 12  Pin Configuration............................................................................. 1  Disable Function ........................................................................ 12  General Description ......................................................................... 1  Output Filtering.......................................................................... 12  Revision History ............................................................................... 2  Clock Feedthrough..................................................................... 12  Specifications..................................................................................... 3  Low Impedance Output............................................................. 12  Electrical Characteristics............................................................. 3  Maximizing Performance Through Proper Layout............... 13  Absolute Maximum Ratings............................................................ 5  Power Supply Bypassing............................................................ 13  Thermal Resistance ...................................................................... 5  Input Overvoltage Protection ................................................... 13  ESD Caution.................................................................................. 5  Capacitive Load Drive ............................................................... 13  Typical Performance Characteristics ............................................. 6  Circuit Diagrams/Connections ................................................ 14  Theory of Operation ...................................................................... 11  Outline Dimensions....................................................................... 18  High PSR and CMR ................................................................... 11  Ordering Guide............................................................................... 18  1/f Noise Correction .................................................................. 11  Applications..................................................................................... 12  REVISION HISTORY 8/10—Rev. 0 to Rev. A Changes to Figure 30...................................................................... 13 10/05—Revision 0: Initial Version Rev. A | Page 2 of 20 AD8553 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 5.0 V, V = 2.5 V, V = V /2, V = V − V , R = 10 kΩ, T = 25°C, G = 100, unless specified. See Table 5 for gain setting CC CM REF CC IN INP INN LOAD A resistor values. Temperature specifications guaranteed by characterization. Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Input Offset Voltage VOS G = 1000 4 20 μV G = 100 4 20 μV G = 10 15 50 μV G = 1 120 375 μV vs. Temperature ΔV /ΔT G = 1000, −40°C ≤ T ≤ +85°C 0.02 0.1 μV/°C OS A G = 100, −40°C ≤ TA ≤ +85°C 0.02 0.1 μV/°C G = 10, −40°C ≤ T ≤ +85°C 0.1 0.3 μV/°C A G = 1, −40°C ≤ TA ≤ +85°C 1 3 μV/°C Input Bias Current IB 0.4 1 nA −40°C ≤ T ≤ +85°C 2 nA A Input Offset Current IOS 2 nA VREF Pin Current I 0.01 1 nA REF Input Operating Impedance Differential 50||1 MΩ||pF Common Mode 10||10 GΩ||pF Input Voltage Range 0 3.3 V Common-Mode Rejection CMR G = 100, V = 0 V to 3.3 V, −40°C ≤ T ≤ +85°C 120 140 dB CM A G = 10, V = 0 V to 3.3 V, −40°C ≤ T ≤ +85°C 100 120 dB CM A Gain Error G = 100, VCM = 12.125 mV, VO = 0.075 V to 4.925 V 0.10 0.3 % G = 10, V = 121.25 mV , V = 0.075 V to 4.925 V 0.15 0.4 % CM O Gain Drift G = 10, 100, 1000, −40°C ≤ TA ≤ +85°C 5 25 ppm/°C G = 1, −40°C ≤ TA ≤ +85°C 30 50 ppm/°C Nonlinearity G = 100, V = 12.125 mV, V = 0.075 V to 4.925 V 0.001 0.003 % FS CM O G = 10, VCM = 121.25 mV, VO = 0.075 V to 4.925 V 0.040 0.060 % FS V Range 0.8 4.2 V REF OUTPUT CHARACTERISITICS Output Voltage High V 4.925 V OH Output Voltage Low VOL 0.075 V Short-Circuit Current I ±35 mA SC POWER SUPPLY Power Supply Rejection PSR G = 100, V = 1.8 V to 5.5 V, V = 0 V 100 120 dB S CM G = 10, VS = 1.8 V to 5.5 V, VCM = 0 V 90 110 dB Supply Current I I = 0 mA, V = 0 V 1.1 1.3 mA SY O IN −40°C ≤ TA ≤ +85°C 1.5 mA Supply Current Shutdown Mode ISD 2 4 μA ENABLE INPUTS Logic High Voltage 2.40 V Logic Low Voltage 0.80 V NOISE PERFORMANCE Voltage Noise en p-p f = 0.01 Hz to 10 Hz 0.7 μV p-p Voltage Noise Density e G = 100, f = 1 kHz 30 nV/√Hz n G = 10, f = 1 kHz 150 nV/√Hz Internal Clock Frequency 60 kHz 1 Signal Bandwidth G = 1 to 1000 1 kHz 1 Higher bandwidths result in higher noise. Rev. A | Page 3 of 20 AD8553 V = 1.8 V, V = -0 V, V = V /2, V = V − V , R = 10 kΩ, T = 25°C, G = 100, unless specified. See Table 5 for gain setting S CM REF S IN INP INN LOAD A resistor values. Temperature specifications guaranteed by characterization. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Input Offset Voltage VOS G = 1000 3 20 μV G = 100 3 20 μV G = 10 14 50 μV G = 1 130 375 μV Vs. Temperature ΔV /ΔT G = 1000, −40°C ≤ T ≤ +85°C 0.02 0.25 μV/°C OS A G = 100, −40°C ≤ TA ≤ +85°C 0.02 0.25 μV/°C G = 10, −40°C ≤ T ≤ +85°C 0.1 3 μV/°C A G = 1, −40°C ≤ T ≤ +85°C 1 10 μV/°C A Input Bias Current IB 0.05 1 nA −40°C ≤ T ≤ +85°C 2 nA A Input Offset Current IOS 2 nA VREF Pin Current IREF 0.02 1 nA Input Operating Impedance Differential 50||1 MΩ||pF Common Mode 10||10 GΩ||pF Input Voltage Range 0 0.15 V Common-Mode Rejection CMR G = 100, VCM = 0 V to 0.15 V, −40°C ≤ TA ≤ +85°C 100 110 dB G = 10, V = 0 V to 0.15 V, −40°C ≤ T ≤ +85°C 90 110 dB CM A Gain Error G = 100, VCM =4.125 mV, VO = 0.075 V to 1.725 V 0.2 0.4 % G = 10, V = 41.25 mV, V = 0.075 V to 1.725 V 0.2 0.4 % CM O Gain Drift G = 10, 100, 1000, −40°C ≤ T ≤ +85°C 25 ppm/°C A G = 1, −40°C ≤ TA ≤ +85°C 50 ppm/°C Nonlinearity G = 100, V = 4.125 mV, V = 0.075 V to 1.725 V 0.003 % FS CM O G = 10, VCM = 41.25 mV, VO = 0.075 V to 1.725 V 0.010 % FS VREF Range 0.8 1.0 V OUTPUT CHARACTERISITICS Output Voltage High V 1.725 V OH Output Voltage Low VOL 0.075 V Short-Circuit Current I ±5 mA SC POWER SUPPLY Power Supply Rejection PSR G = 100, V = 1.8 V to 5.5 V, V = 0 V 100 120 dB S CM Supply Current ISY IO = 0 mA, VIN = 0 V 0.8 1.2 mA −40°C ≤ T ≤ +85°C 1.4 mA A Supply Current Shutdown Mode I 2 4 μA SD ENABLE INPUTS Logic High Voltage 1.4 V Logic Low Voltage 0.5 V NOISE PERFORMANCE Voltage Noise e f = 0.01 Hz to 10 Hz 0.7 μV p-p n p-p Voltage Noise Density en G = 100, f = 1 kHz 30 nV/√Hz G = 10, f = 1 kHz 150 nV/√Hz Internal Clock Frequency 60 kHz 1 Signal Bandwidth G = 1 to 1000 1 kHz 1 Higher bandwidths result in higher noise. Rev. A | Page 4 of 20 AD8553 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Ratings may cause permanent damage to the device. This is a stress Supply Voltage 6 V rating only; functional operation of the device at these or any Input Voltage +V SUPPLY other conditions above those indicated in the operational 1 Differential Input Voltage ±VSUPPLY section of this specification is not implied. Exposure to absolute Output Short-Circuit Duration to GND Indefinite maximum rating conditions for extended periods may affect Storage Temperature Range (RM Package) −65°C to +150°C device reliability. Operating Temperature Range −40°C to +85°C THERMAL RESISTANCE Junction Temperature Range (RM Package) −65°C to +150°C Lead Temperature Range (Soldering, 10 sec) 300°C θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. 1 Differential input voltage is limited to ±5.0 V, the supply voltage, or whichever is less. Table 4. 1 Package Type θ θ Unit JA JC 10-Lead MSOP (RM) 110 32.2 °C/W 1 θJA is specified for the nominal conditions, that is, θJA is specified for the device soldered on a circuit board. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 20 AD8553 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, G = 100, unless specified, see Table 5 for gain setting resistor values. Filters as noted are the combination of R2/C2 and R3/C3 as in Figure 31. 80 80 V = 1.8V AND 5V V = 1.8V AND 5V CC CC FILTER = 1kHz FILTER = 10kHz GAIN = 1000 GAIN = 1000 60 60 GAIN = 100 GAIN = 100 40 40 GAIN = 10 GAIN = 10 20 20 GAIN = 1 GAIN = 1 0 0 –20 –20 –40 –40 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 5. Gain vs. Frequency Figure 2. Gain vs. Frequency 180 180 V = 5V V = 5V CC CC FILTER = 1kHz FILTER = 10kHz 160 160 GAIN = 100 GAIN = 100 140 140 GAIN = 10 GAIN = 10 120 120 GAIN = 1 GAIN = 1 100 100 80 80 60 60 40 40 20 20 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Common-Mode Rejection (CMR) vs. Frequency Figure 3. Common-Mode Rejection (CMR) vs. Frequency 10k 160 GAIN = 100 140 GAIN = 1 GAIN = 10 120 1k GAIN = 1 100 GAIN = 10 80 100 GAIN = 100, 1000 60 10 40 20 FILTER = 10kHz FILTER = 1kHz V =5VAND1.8V CC 1 10 0.01 0.1 1 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 4. Power Supply Rejection vs. Frequency Figure 7. Voltage Noise Density Rev. A | Page 6 of 20 PSR (dB) CMR (dB) GAIN (dB) 05474-006 05474-004 05474-002 NOISE (nV/√Hz) CMR (dB) GAIN (dB) 05474-007 05474-005 05474-003 AD8553 80 V =5V GAIN = 100 CC GAIN = 100 TURN ON TIME = 10µs FILTER = 1kHz FILTER = 10kHz 70 60 50 40 FILTER SETTLING 30 V =5V FILTER SETTLING CC 20 V =5V CC V =1.8V CC 10 0 V =1.8V –10 CC TURN ON TIME = 15µs V =1.8V CC –20 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 03 50 100 150 200 250 30050 TIME (ms) TIME (µs) Figure 11. Input Offset Voltage vs. Turn-On Time Figure 8. Input Offset Voltage vs. Turn-On Time V = 5V, G = 1, 10, 100, 1000 CC V = 5V, G = 1, 10, 100, 1000 CC V = 1.8V, G = 1, 10, 100, 1000 CC 10kHz FILTER 10kHz FILTER 1kHz FILTER 1kHz FILTER 500µs/DIV 500µs/DIV Figure 9. Small Signal Step Response Figure 12. Large Signal Step Response V =5V V =5V CC CC GAIN = 100, 1000 GAIN = 100, 1000 0 2 4 6 8 101214 16 18 20 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 Figure 10. Input Offset Voltage (μV) Figure 13. Input Offset Voltage Drift (μV/°C) Rev. A | Page 7 of 20 POPULATION 20µV/DIV 50mV/DIV 05474-010 05474-017 05474-008 POPULATION INPUT OFFSET VOLTAGE (µV) 1V/DIV 05474-011 05474-014 05474-009 AD8553 V = 5V CC V = 5V CC GAIN = 10 GAIN = 10 0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.30 Figure 17. Input Offset Voltage Drift (μV/°C) Figure 14. Input Offset Voltage (μV) V = 5V V = 5V CC CC GAIN = 1 GAIN = 1 0 0.30 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00 –50 –10 30 70 110 150 190 230 270 310 350 Figure 15. Input Offset Voltage (μV) Figure 18. Input Offset Voltage Drift (μV/°C) V = 5V V = 5V CC CC GAIN = 100 GAIN = 100 V = 12.125mV V = 12.125mV CM CM –250 –225 –200 –175 –150 –125 –100 –75 –50 –25 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 Figure 16. Gain Error (m%) Figure 19. Nonlinearity (m%) Rev. A | Page 8 of 20 POPULATION POPULATION POPULATION 05474-020 05474-015 05474-016 POPULATION POPULATION POPULATION 05474-019 05474-012 05474-013 AD8553 180 180 V = 1.8V V = 1.8V CC CC FILTER = 1kHz FILTER = 10kHz 160 160 GAIN = 100 GAIN = 100 140 140 GAIN = 10 GAIN = 10 120 120 GAIN = 1 GAIN = 1 100 100 80 80 60 60 40 40 20 20 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Common-Mode Rejection (CMR) vs. Frequency Figure 20. Common-Mode Rejection (CMR) vs. Frequency V =1.8V V = 1.8V CC CC GAIN = 100, 1000 GAIN = 100, 1000 –2 0 2 4 6 8 10 12 14 16 18 20 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 Figure 21. Input Offset Voltage (μV) Figure 24. Input Offset Voltage Drift (μV/°C) V = 1.8V V = 1.8V CC CC GAIN = 10 GAIN = 10 0 0.03 0.060.090.120.150.180.210.240.270.30 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 Figure 22. Input Offset Voltage (μV) Figure 25. Input Offset Voltage Drift (μV/°C) Rev. A | Page 9 of 20 POPULATION POPULATION CMR (dB) 05474-025 05474-024 05474-021 POPULATION POPULATION CMR (dB) 05474-027 05474-028 05474-022 AD8553 V = 1.8V V = 1.8V CC CC GAIN = 1 GAIN = 1 040 80 120 160 200 240 280 320 360 0 0.40.8 1.2 1.62.02.42.83.23.6 4.04.44.8 Figure 26. Input Offset Voltage (μV) Figure 28. Input Offset Voltage Drift (μV/°C) V = 5.0V V =1.8V, CC CC GAIN = 100 G = 10, 100, 1000 10kHz FILTER 1kHz FILTER 500µs/DIV 10SEC/DIV Figure 27. 0.01 Hz to 10 Hz Voltage Noise Figure 29. Large Signal Step Response Rev. A | Page 10 of 20 POPULATION 200nV/DIV 05474-036 05474-023 POPULATION 500mV/DIV 05474-029 05474-033 AD8553 THEORY OF OPERATION The AD8553 is a precision current-mode correction HIGH PSR AND CMR instrumentation amplifier capable of single-supply operation. Common-mode rejection and power supply rejection indicate The current-mode correction topology results in excellent the amount that the offset voltage of an amplifier changes when accuracy without the need for trimmed resistors on the die. its common-mode input voltage or power supply voltage changes. The autocorrection architecture of the AD8553 continuously Figure 30 shows a simplified diagram illustrating the basic corrects for offset errors, including those induced by changes in operation of the AD8553 (without correction). The circuit input or supply voltage, resulting in exceptional rejection consists of a voltage-to-current amplifier (M1 to M6), followed performance. The continuous autocorrection provides great by a current-to-voltage amplifier (R2 and A1). Application of a CMR and PSR performances over the entire operating differential input voltage forces a current through External temperature range (−40°C to +85°C). Resistor R1, resulting in conversion of the input voltage to a signal current. Transistor M3 to Transistor M6 transfer twice The parasitic resistance in series with R2 does not degrade this signal current to the inverting input of the op amp A1. CMR but causes a small gain error and a very small offset error. Amplifier A1 and External Resistor R2 form a current-to- Therefore, an external buffer amplifier is not required to drive voltage converter to produce a rail-to-rail output voltage at the VREF pin to maintain excellent CMR performance. This V . OUT helps reduce system costs over conventional instrumentation amplifiers. Op amp A1 is a high precision auto-zero amplifier. This amplifier preserves the performance of the autocorrecting, 1/f NOISE CORRECTION current-mode amplifier topology while offering the user a true Flicker noise, also known as 1/f noise, is noise inherent in the voltage-in, voltage-out instrumentation amplifier. Offset errors physics of semiconductor devices and decreases 10 dB per are corrected internally. decade. The 1/f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the An external reference voltage is applied to the noninverting amplifier. At lower frequencies, flicker noise dominates causing input of A1 to set the output reference level. External Capacitor large errors in low frequency or dc applications. C2 is used to filter out correction noise. Flicker noise is seen effectively as a slowly varying offset error, The pinout of the AD8553 allows the user to access the signal which is reduced by the autocorrection topology of the AD8553. current from the output of the voltage-to-current converter This allows the AD8553 to have lower noise near dc than (Pin 5). The user can choose to use the AD8553 as a current- standard low noise instrumentation amplifiers. output device instead of a voltage-output device. See Figure 35 for circuit connections. Rev. A | Page 11 of 20 AD8553 APPLICATIONS DISABLE FUNCTION GAIN SELECTION (GAIN-SETTING RESISTORS) The AD8553 provides a shutdown function to conserve power The gain of the AD8553 is set according to when the device is not needed. Although there is a 1 μA pull-up G = 2 × (R2/R1) (1) current on the ENABLE pin, Pin 6 should be connected to the positive supply for normal operation and to the negative supply Table 5 lists the recommended resistor values. Resistor R1 must to turn the device off. It is not recommended to leave Pin 6 be at least 3.92 kΩ for proper operation. Use of resistors larger floating. than the recommended values results in higher offset and higher noise. Turn-on time upon switching Pin 6 high is dominated by the output filters. When the device is disabled, the output becomes Gain accuracy depends on the matching of R1 and R2. Any high impedance enabling muxing application of multiple mismatch in resistor values results in a gain error. Resistor AD8553 instrumentation amplifiers. value errors due to drift affect gain by the amount indicated by Equation 1. However, due to the current-mode operation of the OUTPUT FILTERING AD8553, a mismatch in R1 and R2 does not degrade the CMR. Filter Capacitor C2 is required to limit the amount of switching Care should be taken when selecting and positioning the gain noise present at the output. The recommended bandwidth of setting resistors. The resistors should be made of the same the filter created by C2 and R2 is 1.4 kHz. The user should first material and package style. Surface-mount resistors are select R1 and R2 based on the desired gain, then select C2 based on recommended. They should be positioned as close together C2 = 1/(1400 × 2 × π × R2) (2) as possible to minimize TC errors. Addition of another single-pole RC filter of 1.4 kHz on the To maintain good CMR vs. frequency, the parasitic capacitance output (R3 and C3 in Figure 31 to Figure 33) is required for on the R1 gain setting pins should be minimized and matched. bandwidths greater than 10 Hz. These two filters produce an This also helps maintain a low gain error at G < 10. overall bandwidth of 1 kHz. If resistor trimming is required to set a precise gain, trim When driving an ADC, the recommended values for the second Resistor R2 only. Using a potentiometer for R1 degrades the filter are R3 = 100 Ω and C3 = 1 μF. This filter is required to amplifier’s performance. achieve the specified performance. It also acts as an antialiasing filter for the ADC. If a sampling ADC is not being driven, the REFERENCE CONNECTION value of the capacitor can be reduced, but the filter frequency Unlike traditional three op amp instrumentation amplifiers, should remain unchanged. parasitic resistance in series with VREF (Pin 7) does not degrade CMR performance. This allows the AD8553 to attain its extremely For applications with low bandwidths (<10 Hz), only the first high CMR performance without the use of an external buffer filter is required. In this case, the high frequency noise from the amplifier to drive the V pin, which is required by industry- REF auto-zero amplifier (output amplifier) is not filtered before the standard instrumentation amplifiers. This helps save valuable following stage. printed circuit board space and minimizes system costs. CLOCK FEEDTHROUGH For optimal performance in single-supply applications, VREF The AD8553 uses two synchronized clocks to perform the should be set with a low noise precision voltage reference. autocorrection. The input voltage-to-current amplifiers are However, for a lower system cost, the reference voltage can be corrected at 60 kHz. set with a simple resistor voltage divider between the supply and ground (see Figure 31). This configuration results in degraded Trace amounts of these clock frequencies can be observed at the output offset performance if the resistors deviate from their output. The amount of feedthrough is dependent upon the gain, ideal values. In dual-supply applications, V can simply be REF because the autocorrection noise has an input and output connected to ground. referred term. The correction feedthrough is also dependent upon the values of the external filters R2/C2, and R3/C3. The VREF pin current is approximately 20 pA, and as a result, an external buffer is not required. LOW IMPEDANCE OUTPUT For applications where a low output impedance is required, the circuit in Figure 33 should be used. This provides the same filtering performance as shown in the configuration in Figure 34. Rev. A | Page 12 of 20 AD8553 MAXIMIZING PERFORMANCE THROUGH PROPER For single-supply operation, a 0.1 μF surface-mount capacitor LAYOUT should be connected from the supply line to ground. To achieve the maximum performance of the AD8553, care All bypass capacitors should be positioned as close to the DUT should be taken in the circuit board layout. The PC board supply pins as possible, especially the bypass capacitor between surface must remain clean and free of moisture to avoid leakage the supplies. Placement of the bypass capacitor on the back of currents between adjacent traces. Surface coating of the circuit the board directly under the DUT is preferred. board reduces surface moisture and provides a humidity barrier, reducing parasitic resistance on the board. INPUT OVERVOLTAGE PROTECTION All terminals of the AD8553 are protected against ESD. In the Care must be taken to minimize parasitic capacitance on Pin 1 case of a dc overload voltage beyond either supply, a large and Pin 10 (Resistor R1 connections). Traces from Pin 1 and current would flow directly through the ESD protection diodes. Pin 10 to R1 should be kept short and symmetric. Excessive If such a condition should occur, an external resistor should be capacitance on these pins will result in a gain error. This effect used in series with the inputs to limit current for voltages is most prominent at low gains (G < 10). beyond the supply rails. The AD8553 can safely handle 5 mA of For high impedance sources, the PC board traces from the continuous current, resulting in an external resistor selection of AD8553 inputs should be kept to a minimum to reduce input R = (V − V )/5 mA. EXT IN S bias current errors. CAPACITIVE LOAD DRIVE POWER SUPPLY BYPASSING The output buffer, Pin 4, can drive capacitive loads up to 100 pF. The AD8553 uses internally generated clock signals to perform the autocorrection. As a result, proper bypassing is necessary to achieve optimum performance. Inadequate or improper bypassing of the supply lines can lead to excessive noise and offset voltage. A 0.1 μF surface-mount capacitor should be connected between the supply lines. This capacitor is necessary to minimize ripple from the correction clocks inside the IC. For dual-supply operation (see Figure 33), a 0.1 μF (ceramic) surface-mount capacitor should be connected from each supply pin to ground. V CC C2 M5 M6 I R2 I R1 I– I R1 2I R1 I– I R1 2R2 V –V I+I V =V + INP INN R1 OUT REF (V –V ) R1 INP INN I = R1 A1 R1 V BIAS V V V INP REF INN M3 M4 M1 M2 2I 2I EXTERNAL Figure 30. Simplified AD8553 Schematic Rev. A | Page 13 of 20 05474-030 AD8553 CIRCUIT DIAGRAMS/CONNECTIONS V S+ 0.1µF GND 3 2 V + IN+ 6 1 R3 100Ω 4 V R1 OUT AD8553 C3 1µF 10 5 7 GND R2 V – IN– 9 8 R3 AND C3 VALUES ARE RECOMMENDED TO DRIVE C2 AN A/D CONVERTER GND 100kΩ 100kΩ 0.1µF V S+ GND Figure 31. Single-Supply Connection Diagram Using Voltage Divider Reference V S+ 0.1µF 0.1µF V S– GND 2 3 V IN+ + 6 1 R3 100Ω 4 V R1 OUT AD8553 C3 1µF 10 5 7 GND R2 V – IN– 9 8 R3 AND C3 VALUES ARE RECOMMENDED TO DRIVE C2 AN A/D CONVERTER 0.1µF V – S GND Figure 32. Dual-Supply Connection Diagram Rev. A | Page 14 of 20 05474-031 05474-032 AD8553 V S+ 0.1µF 0.1µF V S– GND 3 2 V IN+ + 6 1 R3 100Ω 4 V R1 AD8553 OUT C3 1µF 10 5 C2 7 GND R2 V – IN– 9 8 GND R3 AND C3 VALUES ARE RECOMMENDED TO DRIVE 0.1µF AN A/D CONVERTER V – S GND Figure 33. Dual-Supply Connection Diagram with Low Impedance Output V S+ 0.1µF GND 2 3 V IN+ + 6 1 R3 100Ω 4 V R1 OUT AD8553 C3 1µF 10 5 7 GND R2 V – IN– 9 8 R3 AND C3 VALUES ARE RECOMMENDED TO DRIVE C2 AN A/D CONVERTER V S– V CC 1.0µF 0.1µF V IN V OUT GND Figure 34. Dual-Supply Connection Diagram Using IC Voltage Reference Rev. A | Page 15 of 20 05474-034 05474-035 AD8553 V S+ 6 2 3 + 7 1 V IN 4 NC (NO CONNECT) R1 AD8553 V IN I = 5 O R1 10kΩ 10 8 A 9 _ 0.1µF AMMETER V S– Figure 35. Voltage-to-Current Converter, 0 μA to 30 μA Source V S+ 6 2 3 + V = 2.5V REF 1 7 100Ω 4 A/A/ DD CONVERTER AD8553 R1 C2 1µF 5 10 R2 8 9 _ Figure 36. Example of an AD8553 Driving a Converter at V = 5 V S+ Rev. A | Page 16 of 20 05474-037 05474-038 AD8553 V S+ LOGIC 6 2 3 + 1 V REF 7 R3 4 R1 AD8553 100Ω C2 5 10 8 9 _ R2 V S– V S+ 6 2 3 + 1 V REF 7 R8 4 V OUT AD8553 R6 100Ω 1µF C3 5 10 8 9 _ R7 V S+ 6 2 3 + 1 V REF 7 R13 4 R11 AD8553 100Ω C4 5 10 8 9 _ R12 Figure 37. Multiplexed Output Table 5. Recommended External Component Values for Selected Gains Desired Gain (V/V) R1 (Ω) R2 || C2 (Ω || F) Calculated Gain 1 200 k 100 k || 1200p 1 2 100 k 100 k || 1200p 2 5 40.2 k 100 k || 1200p 4.975 10 20 k 100 k || 1200p 10 50 4.02 k 100 k || 1200p 49.75 100 3.92 k 196 k || 560p 100 500 3.92 k 976 k || 120p 497.95 1000 3.92 k 1.96 M || 56p 1000 Rev. A | Page 17 of 20 05474-039 AD8553 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 38. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8553ARMZ −40°C to +85°C 10-Lead MSOP RM-10 A09 AD8553ARMZ-REEL −40°C to +85°C 10-Lead MSOP RM-10 A09 1 Z = RoHS Compliant Part. Rev. A | Page 18 of 20 091709-A AD8553 NOTES Rev. A | Page 19 of 20 AD8553 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05474-0-8/10(A) Rev. A | Page 20 of 20