ANALOG DEVICES AD8534

Low Cost, 250 mA Output, Single-Supply Amplifiers AD8531/AD8532/AD8534 FEATURES PIN CONFIGURATIONS Single-supply operation: 2.7 V to 6 V AD8531 OUT A 1 5 V+ High output current: ±250 mA V– 2 Low supply current: 750 μA/amplifier Wide bandwidth: 3 MHz +IN A 3 4 –IN A Slew rate: 5 V/μs No phase reversal Figure 1. 5-Lead SC70 and 5-Lead SOT-23 (KS and RJ Suffixes) Low input currents Unity gain stable Rail-to-rail input and output NC 1 8 NC AD8531 –IN A 2 7 V+ APPLICATIONS +IN A 3 6 OUT A V– 4 5 NC Multimedia audio LCD drivers NC = NO CONNECT ASIC input or output amplifiers Figure 2. 8-Lead SOIC Headphone drivers (R Suffix) GENERAL DESCRIPTION OUT A 1 8 V+ The AD8531, AD8532, and AD8534 are single, dual, and quad –IN A 2 7 OUT B rail-to-rail input/output single-supply amplifiers featuring +IN A 3 6 –IN B 250 mA output drive current. This high output current makes V– 4 5 +IN B these amplifiers excellent for driving either resistive or capacitive loads. AC performance is very good with 3 MHz bandwidth, AD8532 5 V/μs slew rate, and low distortion. All are guaranteed to operate Figure 3. 8-Lead SOIC, 8-Lead TSSOP, and 8-Lead MSOP (R, RU, and RM Suffixes) from a 3 V single supply as well as a 5 V supply. The very low input bias currents enable the AD853x to be used for integrators, diode amplification, and other applications requiring OUT A 1 14 OUT D low input bias current. Supply current is only 750 μA per –IN A 2 13 –IN D amplifier at 5 V, allowing low current applications to control +IN A 3 12 +IN D high current loads. V+ 4 AD8534 11 V– Applications include audio amplification for computers, sound +IN B 5 10 +IN C ports, sound cards, and set-top boxes. The AD853x family is 6 –IN B 9 –IN C very stable, and it is capable of driving heavy capacitive loads OUT B 7 8 OUT C such as those found in LCDs. Figure 4. 14-Lead SOIC and 14-Lead TSSOP The ability to swing rail-to-rail at the inputs and outputs enables (R and RU Suffixes) designers to buffer CMOS DACs, ASICs, or other wide output swing devices in single-supply systems. The AD8531/AD8532/AD8534 are specified over the extended industrial temperature range (−40°C to +85°C). The AD8531 is available in 8-lead SOIC, 5-lead SC70, and 5-lead SOT-23 packages. The AD8532 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead TSSOP surface-mount packages. The AD8534 is available in narrow 14-lead SOIC and 14-lead TSSOP surface-mount packages. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 01099-001 01099-002 01099-003 01099-004 AD8531/AD8532/AD8534 TABLE OF CONTENTS Features .............................................................................................. 1 Calculating Power by Measuring Ambient and Case Temperature ................................................................................ 12 Applications....................................................................................... 1 Calculating Power by Measuring Supply Current ................. 12 General Description ......................................................................... 1 Input Overvoltage Protection ................................................... 12 Pin Configurations ........................................................................... 1 Output Phase Reversal............................................................... 13 Revision History ............................................................................... 2 Capacitive Load Drive ............................................................... 13 Specifications..................................................................................... 3 Applications Information .............................................................. 14 Electrical Characteristics............................................................. 3 High Output Current, Buffered Reference/Regulator........... 14 Absolute Maximum Ratings............................................................ 5 Single-Supply, Balanced Line Driver ....................................... 14 Thermal Resistance ...................................................................... 5 Single-Supply Headphone Amplifier....................................... 15 ESD Caution.................................................................................. 5 Single-Supply, 2-Way Loudspeaker Crossover Network....... 15 Typical Performance Characteristics ............................................. 6 Direct Access Arrangement for Telephone Line Interface ... 16 Theory of Operation ...................................................................... 11 Outline Dimensions ....................................................................... 17 Short-Circuit Protection............................................................ 11 Ordering Guide .......................................................................... 20 Power Dissipation....................................................................... 11 Power Calculations for Varying or Unknown Loads............. 12 REVISION HISTORY 1/08—Rev. E to Rev. F Changes to Layout ............................................................................ 5 Changes to Figure 12 and Figure 13............................................... 7 Changes to Figure 38...................................................................... 11 Changes to Input Overvoltage Protection Section..................... 12 Changes to Figure 43...................................................................... 14 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 20 4/05—Rev. D to Rev. E Updated Format..................................................................Universal Changes to Pin Configurations....................................................... 1 Changes to Table 4............................................................................ 5 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 10/02—Rev. C to Rev. D Deleted 8-Lead PDIP (N-8) .............................................. Universal Deleted 14-Lead PDIP (N-14) .......................................... Universal Edits to Figure 34...............................................................................9 Updated Outline Dimensions ........................................................15 8/96—Revision 0: Initial Version Rev. F | Page 2 of 20 AD8531/AD8532/AD8534 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 3.0 V, V = 1.5 V, T = 25°C, unless otherwise noted. S CM A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 25 mV −40°C ≤ T ≤ +85°C 30 mV A Input Bias Current I 5 50 pA B −40°C ≤ TA ≤ +85°C 60 pA Input Offset Current IOS 1 25 pA −40°C ≤ TA ≤ +85°C 30 pA Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR V = 0 V to 3 V 38 45 dB CM Large Signal Voltage Gain A R = 2 kΩ, V = 0.5 V to 2.5 V 25 V/mV VO L O Offset Voltage Drift ΔVOS/ΔT 20 μV/°C Bias Current Drift ΔIB/ΔT 50 fA/°C Offset Current Drift ΔIOS/ΔT 20 fA/°C OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 10 mA 2.85 2.92 V −40°C ≤ T ≤ +85°C 2.8 V A Output Voltage Low V I = 10 mA 60 100 mV OL L −40°C ≤ T ≤ +85°C 125 mV A Output Current IOUT ±250 mA Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 60 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 3 V to 6 V 45 55 dB Supply Current/Amplifier ISY VO = 0 V 0.70 1 mA −40°C ≤ TA ≤ +85°C 1.25 mA DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ 3.5 V/μs Settling Time tS To 0.01% 1.6 μs Gain Bandwidth Product GBP 2.2 MHz Phase Margin фo 70 Degrees Channel Separation CS f = 1 kHz, RL = 2 kΩ 65 dB NOISE PERFORMANCE Voltage Noise Density e f = 1 kHz 45 nV/√Hz n f = 10 kHz 30 nV/√Hz Current Noise Density in f = 1 kHz 0.05 pA/√Hz Rev. F | Page 3 of 20 AD8531/AD8532/AD8534 V = 5.0 V, V = 2.5 V, T = 25°C, unless otherwise noted. S CM A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 25 mV OS −40°C ≤ T ≤ +85°C 30 mV A Input Bias Current I 5 50 pA B −40°C ≤ TA ≤ +85°C 60 pA Input Offset Current IOS 1 25 pA −40°C ≤ TA ≤ +85°C 30 pA Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V = 0 V to 5 V 38 47 dB CM Large Signal Voltage Gain A R = 2 kΩ, V = 0.5 V to 4.5 V 15 80 V/mV VO L O Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 20 μV/°C Bias Current Drift ΔIB/ΔT 50 fA/°C Offset Current Drift ΔIOS/ΔT 20 fA/°C OUTPUT CHARACTERISTICS Output Voltage High VOH IL = 10 mA 4.9 4.94 V −40°C ≤ T ≤ +85°C 4.85 V A Output Voltage Low V I = 10 mA 50 100 mV OL L −40°C ≤ T ≤ +85°C 125 mV A Output Current IOUT ±250 mA Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 40 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 3 V to 6 V 45 55 dB Supply Current/Amplifier ISY VO = 0 V 0.75 1.25 mA −40°C ≤ TA ≤ +85°C 1.75 mA DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ 5 V/μs Full-Power Bandwidth BWp 1% distortion 350 kHz Settling Time t To 0.01% 1.4 μs S Gain Bandwidth Product GBP 3 MHz Phase Margin фo 70 Degrees Channel Separation CS f = 1 kHz, RL = 2 kΩ 65 dB NOISE PERFORMANCE Voltage Noise Density en f = 1 kHz 45 nV/√Hz f = 10 kHz 30 nV/√Hz Current Noise Density in f = 1 kHz 0.05 pA/√Hz Rev. F | Page 4 of 20 AD8531/AD8532/AD8534 ABSOLUTE MAXIMUM RATINGS Table 3. 2.5 Parameter Rating –V OL Supply Voltage (V) 7 V S +V OH Input Voltage GND to V 2.0 S 1 Differential Input Voltage ±6 V Storage Temperature Range −65°C to +150°C 1.5 Operating Temperature Range −40°C to +85°C Junction Temperature Range −65°C to +150°C 1.0 Lead Temperature (Soldering, 60 sec) 300°C 1 For supplies less than 6 V, the differential input voltage is equal to ±VS. 0.5 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress 0 rating only; the functional operation of the device at these or 0 20 40 60 80 100 120 140 160 180 200 R (Ω) LOAD any other conditions above those indicated in the operational Figure 5. Output Voltage vs. Load, VS = ±2.5 V, sections of this specification is not implied. Exposure to absolute RLOAD Is Connected to GND (0 V) maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE ESD CAUTION θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Package Type θJA θJC Unit 5-Lead SC70 (KS) 376 126 °C/W 5-Lead SOT-23 (RJ) 230 146 °C/W 8-Lead SOIC (R) 158 43 °C/W 8-Lead MSOP (RM) 210 45 °C/W 8-Lead TSSOP (RU) 240 43 °C/W 14-Lead SOIC (R) 120 36 °C/W 14-Lead TSSOP (RU) 240 43 °C/W Rev. F | Page 5 of 20 ±V OUT 01099-005 AD8531/AD8532/AD8534 TYPICAL PERFORMANCE CHARACTERISTICS V = 2.7V V = 5V, 3V S S V = 1.35V V = V /2 CM CM S 8 T = 25°C 500 A 7 400 6 300 5 4 200 3 100 2 –12 –10 –8 –6 –4 –2 0 2 4 –35 –15 5 25 45 65 85 INPUT OFFSET VOLTAGE (mV) TEMPERATURE (°C) Figure 6. Input Offset Voltage Distribution Figure 9. Input Bias Current vs. Temperature V = 5V S V = 5V S T = 25°C A V = 2.5V CM T = 25°C A 500 8 7 400 6 5 300 4 200 3 2 100 –12 –10 –8 –6 –4 –2 0 2 4 01 2 3 4 5 INPUT OFFSET VOLTAGE (mV) COMMON-MODE VOLTAGE (V) Figure 7. Input Offset Voltage Distribution Figure 10. Input Bias Current vs. Common-Mode Voltage 6 V = 5V V = 5V, 3V S S V = 2.5V V = V /2 CM CM S –2 5 –3 4 –4 3 –5 2 –6 1 –7 0 –8 –1 –2 –35 –15 5 25 45 65 85 –35 –15 5 25 45 65 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Input Offset Voltage vs. Temperature Figure 11. Input Offset Current vs. Temperature Rev. F | Page 6 of 20 INPUT OFFSET VOLTAGE (mV) QUANTITY (Amplifiers) QUANTITY (Amplifiers) 01099-008 01099-007 01099-006 INPUT OFFSET CURRENT (pA) INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (pA) 01099-011 01099-010 01099-009 AD8531/AD8532/AD8534 V = 2.7V S V = 5V S T = 25°C A R = NO LOAD L 1000 T = 25°C A 100 80 SOURCE SINK 60 45 10 40 90 20 135 1 0 180 0.1 0.01 1k 10k 100k 1M 10M 100M 0.001 0.01 0.1 1 10 100 FREQUENCY (Hz) LOAD CURRENT (mA) Figure 15. Open-Loop Gain and Phase Shift vs. Frequency Figure 12. Output Voltage to Supply Rail vs. Load Current 5 1000 V = 2.7V V = 5V S S T = 25°C T = 25°C A A R = 2kΩ L V = 2.5V p-p 4 IN 100 3 10 SOURCE SINK 2 1 1 0.1 0 0.01 1k 10k 100k 1M 10M 0.001 0.01 0.1 1 10 100 FREQUENCY (Hz) LOAD CURRENT (mA) Figure 16. Closed-Loop Output Swing vs. Frequency Figure 13. Output Voltage to Supply Rail vs. Load Current 5 V = 5V V = 2.7V S S T = 25°C R = NO LOAD A L R = 2kΩ T = 25°C L A V = 4.9V p-p 4 IN 80 45 3 60 40 90 20 135 2 0 180 1 0 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. Open-Loop Gain and Phase Shift vs. Frequency Figure 17. Closed-Loop Output Swing vs. Frequency Rev. F | Page 7 of 20 GAIN (dB) ΔOUTPUT VOLTAGE (mV) ΔOUTPUT VOLTAGE (mV) 01099-013 01099-012 PHASE SHIFT (Degrees) 01099-014 GAIN (dB) OUTPUT SWING (V p-p) OUTPUT SWING (V p-p) 01099-015 01099-017 01099-016 PHASE SHIFT (Degrees) AD8531/AD8532/AD8534 200 1 V = 5V V = 5V S S T = 25°C T = 25°C 180 A A 160 140 120 100 0.1 80 A = 10 V 60 A = 1 V 40 20 0 0.01 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k LOAD CURRENT (mA) FREQUENCY (Hz) Figure 18. Closed-Loop Output Impedance vs. Frequency Figure 21. Current Noise Density vs. Frequency 110 V = 5V V = 5V S S T = 25°C A = 1000 A V 100 100 T = 25°C A 90 FREQUENCY = 1kHz 90 80 70 60 10 0% 50 40 MARKER 41µV/√Hz 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 19. Voltage Noise Density vs. Frequency (1 kHz) Figure 22. Common-Mode Rejection vs. Frequency 140 V = 5V V = 2.7V S S A = 1000 120 T = 25°C V A 100 T = 25°C A 90 FREQUENCY = 10kHz 100 80 60 PSSR– 40 20 PSSR+ 0 10 0% –20 –40 –60 MARKER 25.9µV/√Hz 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 20. Voltage Noise Density vs. Frequency (10 kHz) Figure 23. Power Supply Rejection vs. Frequency Rev. F | Page 8 of 20 IMPEDANCE (Ω) 200µV/DIV 100µV/DIV 01099-020 01099-019 01099-018 POWER SUPPLY REJECTION (dB) COMMON-MODE REJECTION (dB) CURRENT NOISE DENSITY (pA/√Hz) 01099-023 01099-022 01099-021 AD8531/AD8532/AD8534 140 50 V = 5V V = 5V S S = 25°C T = 25°C T 120 A A R = 600Ω L 100 40 80 PSSR– 60 30 –OS PSSR+ +OS 40 20 20 0 –20 10 –40 –60 0 100 1k 10k 100k 1M 10M 10 100 1000 10000 FREQUENCY (Hz) CAPACITANCE (pF) Figure 24. Power Supply Rejection vs. Frequency Figure 27. Small Signal Overshoot vs. Load Capacitance 50 50 V = 2.7V V = 2.7V S S T = 25°C T = 25°C A A = 600Ω R = 2kΩ R L L 40 40 30 30 –OS 20 20 –OS +OS 10 10 +OS 0 0 10 100 1000 10000 10 100 1000 10000 CAPACITANCE (pF) CAPACITANCE (pF) Figure 25. Small Signal Overshoot vs. Load Capacitance Figure 28. Small Signal Overshoot vs. Load Capacitance 0.90 60 V = 5V S T = 25°C A 0.85 R = 2kΩ L 50 0.80 40 0.75 –OS 30 0.70 V = 5V S +OS 0.65 20 0.60 V = 3V S 10 0.55 0.50 0 10 100 1000 10000 –40 –20 0 20 40 60 80 CAPACITANCE (pF) TEMPERATURE (°C) Figure 26. Small Signal Overshoot vs. Load Capacitance Figure 29. Supply Current per Amplifier vs. Temperature Rev. F | Page 9 of 20 SMALL SIGNAL OVERSHOOT (%) SMALL SIGNAL OVERSHOOT (%) POWER SUPPLY REJECTION (dB) 01099-026 01099-025 01099-024 SMALL SIGNAL OVERSHOOT (%) SMALL SIGNAL OVERSHOOT (%) SUPPLY CURRENT/AMPLIFIER (mA) 01099-028 01099-027 01099-029 AD8531/AD8532/AD8534 0.8 T = 25°C A V = ±2.5V S A = 1 V 0.7 100 R = 2kΩ L 90 T = 25°C A 0.6 0.5 0.4 0.3 10 0.2 0% 0.1 500mV 500ns 0 0.75 1.00 1.50 2.00 2.50 3.00 SUPPLY VOLTAGE (±V) Figure 30. Supply Current per Amplifier vs. Supply Voltage Figure 33. Large Signal Transient Response V = 1.35V S V = ±1.35V S V = 50mV IN A = 1 V 100 A = 1Ω V R = 2kΩ L R = 2kΩ 90 L T = 25°C A C = 300pF L T = 25°C A 0V 10 0% 500mV 500ns 500 ns/DIV Figure 31. Small Signal Transient Response Figure 34. Large Signal Transient Response 1V 10µs 100 90 V = 2.5V 0V S V = 50mV IN A = 1Ω V R = 2kΩ L C = 300pF L T = 25°C A 10 0% 1V 500ns/DIV Figure 32. Small Signal Transient Response Figure 35. No Phase Reversal Rev. F | Page 10 of 20 SUPPLY CURRENT/AMPLIFIER (mA) 20mV/DIV 20mV/DIV 01099-032 01099-031 01099-030 01099-035 01099-034 01099-033 AD8531/AD8532/AD8534 THEORY OF OPERATION The AD8531/AD8532/AD8534 are all CMOS, high output SHORT-CIRCUIT PROTECTION current drive, rail-to-rail input/output operational amplifiers. As a result of the design of the output stage for the maximum Their high output current drive and stability with heavy capacitive load current capability, the AD8531/AD8532/AD8534 do not loads make the AD8531/AD8532/AD8534 excellent choices as have any internal short-circuit protection circuitry. Direct drive amplifiers for LCD panels. connection of the output of the AD8531/AD8532/AD8534 to Figure 36 illustrates a simplified equivalent circuit for the the positive supply in single-supply applications destroys the AD8531/AD8532/AD8534. Like many rail-to-rail input amplifier device. In applications where some protection is needed, but not configurations, it comprises two differential pairs, one N-channel at the expense of reduced output voltage headroom, a low value (M1 to M2) and one P-channel (M3 to M4). These differential resistor in series with the output, as shown in Figure 37, can be pairs are biased by 50 μA current sources, each with a compliance used. The resistor, connected within the feedback loop of the limit of approximately 0.5 V from either supply voltage rail. The amplifier, has very little effect on the performance of the amplifier differential input voltage is then converted into a pair of other than limiting the maximum available output voltage differential output currents. These differential output currents swing. For single 5 V supply applications, resistors less than are then combined in a compound folded-cascade second gain 20 Ω are not recommended. stage (M5 to M9). The outputs of the second gain stage at M8 5V and M9 provide the gate voltage drive to the rail-to-rail output R V IN X 20Ω stage. Additional signal current recombination for the output V AD8532 OUT stage is achieved using M11 to M14. To achieve rail-to-rail output swings, the AD8531/AD8532/ Figure 37. Output Short-Circuit Protection AD8534 design employs a complementary, common source output stage (M15 to M16). However, the output voltage swing POWER DISSIPATION is directly dependent on the load current because the difference Although the AD8531/AD8532/AD8534 are capable of between the output voltage and the supply is determined by providing load currents to 250 mA, the usable output load the AD8531/AD8532/AD8534’s output transistors on channel current drive capability is limited to the maximum power resistance (see Figure 12 and Figure 13). The output stage also dissipation allowed by the device package used. In any exhibits voltage gain by virtue of the use of common source application, the absolute maximum junction temperature amplifiers; as a result, the voltage gain of the output stage (thus, for the AD8531/AD8532/AD8534 is 150°C. The maximum the open-loop gain of the device) exhibits a strong dependence junction temperature should never be exceeded because the on the total load resistance at the output of the AD8531/ device could suffer premature failure. Accurately measuring AD8532/AD8534. power dissipation of an integrated circuit is not always a V+ straightforward exercise; therefore, Figure 38 is provided as a design aid for either setting a safe output current drive 50µA 20µA 100µA 100µA level or selecting a heat sink for the package options available M11 on the AD8531/AD8532/AD8534. M12 M5 1.5 V B2 M8 T MAX = 150°C J FREE AIR M1 M3 M4 M2 M15 NO HEAT SINK IN– OUT SOIC M6 M16 θ = 158°C/W IN+ 1.0 JA V M9 SOT-23 B3 M14 θ = 230°C/W JA MSOP 20µA θ = 210°C/W JA M13 M7 M10 50µA SC70 0.5 θ = 376°C/W JA V– Figure 36. Simplified Equivalent Circuit TSSOP θ = 240°C/W JA 0 0 25 50 75 85 100 TEMPERATURE (°C) Figure 38. Maximum Power Dissipation vs. Ambient Temperature Rev. F | Page 11 of 20 01099-036 POWER DISSIPATION (W) 01099-037 01099-038 AD8531/AD8532/AD8534 The thermal resistance curves were determined using the T = T + P θ J C DISS JA AD8531/AD8532/AD8534 thermal resistance data for each where: package and a maximum junction temperature of 150°C. The T is the case temperature. C following formula can be used to calculate the internal junction θJA and θJC are given in the data sheet. temperature of the AD8531/AD8532/AD8534 for any application: The two equations can be solved for P (power) TJ = PDISS × θJA + TA TA + PDISS θJA = TC + PθJC where: PDISS = (TA − TC)/(θJC − θJA) T is the junction temperature. J P is the power dissipation. Once power is determined, it is necessary to go back and calculate DISS θ is the package thermal resistance, junction-to-case. the junction temperature to ensure that it has not been exceeded. JA TA is the ambient temperature of the circuit. The temperature measurements should be directly on the package To calculate the power dissipated by the AD8531/AD8532/ and on a spot on the board that is near the package but not AD8534, the following equation can be used: touching it. Measuring the package could be difficult. A very small bimetallic junction glued to the package can be used, or PDISS = ILOAD × (VS − VOUT) measurement can be done using an infrared sensing device if where: the spot size is small enough. I is the output load current. LOAD CALCULATING POWER BY MEASURING SUPPLY V is the supply voltage. S CURRENT VOUT is the output voltage. Power can be calculated directly, knowing the supply voltage The quantity within the parentheses is the maximum voltage and current. However, supply current may have a dc component developed across either output transistor. As an additional with a pulse into a capacitive load, which can make rms current design aid in calculating available load current from the very difficult to calculate. It can be overcome by lifting the supply AD8531/AD8532/AD8534, Figure 5 illustrates the output pin and inserting an rms current meter into the circuit. For this voltage of the AD8531/AD8532/AD8534 as a function of to work, be sure the current is being delivered by the supply pin load resistance. being measured. This is usually a good method in a single-supply POWER CALCULATIONS FOR VARYING OR system; however, if the system uses dual supplies, both supplies UNKNOWN LOADS may need to be monitored. Often, calculating power dissipated by an integrated circuit to INPUT OVERVOLTAGE PROTECTION determine if the device is being operated in a safe range is not As with any semiconductor device, whenever the condition as simple as it may seem. In many cases, power cannot be directly exists for the input to exceed either supply voltage, the input measured, which may be the result of irregular output waveforms overvoltage characteristic of the device must be considered. or varying loads; indirect methods of measuring power are When an overvoltage occurs, the amplifier can be damaged, required. depending on the magnitude of the applied voltage and the There are two methods to calculate power dissipated by an magnitude of the fault current. Although not shown here, when integrated circuit. The first can be done by measuring the the input voltage exceeds either supply by more than 0.6 V, pn package temperature and the board temperature, and the junctions internal to the AD8531/AD8532/AD8534 energize, other is to directly measure the supply current of the circuit. allowing current to flow from the input to the supplies. As illustrated in the simplified equivalent input circuit (see Figure 36), CALCULATING POWER BY MEASURING AMBIENT the AD8531/AD8532/AD8534 do not have any internal current AND CASE TEMPERATURE limiting resistors; therefore, fault currents can quickly rise to Given the two equations for calculating junction temperature damaging levels. T = T + P θ J A DISS JA This input current is not inherently damaging to the device, as where: long as it is limited to 5 mA or less. For the AD8531/AD8532/ TJ is the junction temperature. AD8534, once the input voltage exceeds the supply by more than TA is the ambient temperature. 0.6 V, the input current quickly exceeds 5 mA. If this condition θJA is the junction to ambient thermal resistance. continues to exist, an external series resistor should be added. The size of the resistor is calculated by dividing the maximum overvoltage by 5 mA. For example, if the input voltage could reach 10 V, the external resistor should be (10 V/5 mA) = 2 kΩ. This resistance should be placed in series with either or both inputs if they are exposed to an overvoltage condition. Rev. F | Page 12 of 20 AD8531/AD8532/AD8534 5V OUTPUT PHASE REVERSAL Some operational amplifiers designed for single-supply operation AD8532 V OUT exhibit an output voltage phase reversal when their inputs are R S V IN 5Ω driven beyond their useful common-mode range. The AD8531/ 100mV p-p C C S L AD8532/AD8534 are free from reasonable input voltage range 1µF 47nF restrictions, provided that input voltages no greater than the Figure 40. Snubber Network Compensates for Capacitive Loads supply voltage rails are applied. Although the output of the device does not change phase, large currents can flow through The first step is to determine the value of the resistor, R . A good S internal junctions to the supply rails, which was described in the starting value is 100 Ω. This value is reduced until the small signal Input Overvoltage Protection section. Without limit, these fault transient response is optimized. Next, C is determined; 10 μF is a S currents can easily destroy the amplifier. The technique good starting point. This value is reduced to the smallest value recommended in the Input Overvoltage Protection section for acceptable performance (typically, 1 μF). For the case of a should therefore be applied in those applications where the 47 nF load capacitor on the AD8531/AD8532/AD8534, the possibility of input voltages exceeding the supply voltages exists. optimal snubber network is 5 Ω in series with 1 μF. The benefit is immediately apparent, as seen in Figure 41. The top trace was CAPACITIVE LOAD DRIVE taken with a 47 nF load, and the bottom trace was taken with The AD8531/AD8532/AD8534 exhibit excellent capacitive load the 5 Ω in series with a 1 μF snubber network in place. The driving capabilities. They can drive up to 10 nF directly, as amount of overshoot and ringing is dramatically reduced. Table 5 shown in Figure 25 through Figure 28. However, even though illustrates a few sample snubber networks for large load the device is stable, a capacitive load does not come without a capacitors. penalty in bandwidth. As shown in Figure 39, the bandwidth is reduced to less than 1 MHz for loads greater than 10 nF. A snubber Table 5. Snubber Networks for Large Capacitive Loads network on the output does not increase the bandwidth, but it Load Capacitance (CL) Snubber Network (RS, CS) does significantly reduce the amount of overshoot for a given 0.47 nF 300 Ω, 0.1 μF capacitive load. A snubber consists of a series RC network (R , S 4.7 nF 30 Ω, 1 μF C ), as shown in Figure 40, connected from the output of the S 47 nF 5 Ω, 1 μF device to ground. This network operates in parallel with the load capacitor, CL, to provide phase lag compensation. The 50mV actual value of the resistor and capacitor is best determined 100 47nF LOAD empirically. 90 ONLY 4.0 V = ±2.5V S R = 1kΩ L 3.5 T = 25°C A 3.0 2.5 SNUBBER 10 2.0 IN CIRCUIT 0% 1.5 50mV 10µs 1.0 Figure 41. Overshoot and Ringing Are Reduced by Adding a Snubber Network in Parallel with the 47 nF Load 0.5 0 0.01 0.1 1 10 100 CAPACITIVE LOAD (nF) Figure 39. Unity-Gain Bandwidth vs. Capacitive Load Rev. F | Page 13 of 20 BANDWIDITH (MHz) 01099-039 01099-040 01099-041 AD8531/AD8532/AD8534 APPLICATIONS INFORMATION for optimizing the transient response, any changes to the R5 to HIGH OUTPUT CURRENT, BUFFERED C5 network should be verified by experiment to preclude the REFERENCE/REGULATOR possibility of excessive ringing with some capacitor types. Many applications require stable voltage outputs relatively close To scale VOUT2 to another (higher) output level, the optional in potential to an unregulated input source. This low dropout resistor R3 (shown dotted in Figure 42) is added, causing the type of reference/regulator is readily implemented with a rail- new V to become to-rail output op amp and is particularly useful when using a OUT1 higher current device, such as the AD8531/AD8532/AD8534. R2 ⎛ ⎞ V = V ×1 + A typical example is the 3.3 V or 4.5 V reference voltage developed ⎜ ⎟ OUT1 OUT2 ⎝ R3⎠ from a 5 V system source. Generating these voltages requires a The circuit can either be used as shown, as a 5 V to 3.3 V three terminal reference, such as the REF196 (3.3 V) or the reference/regulator, or with on/off control. By driving Pin 3 of REF194 (4.5 V), both of which feature low power, with sourcing U1 with a logic control signal as noted, the output is switched outputs of 30 mA or less. Figure 42 shows how such a reference on/off. Note that when on/off control is used, R4 must be used can be outfitted with an AD8531/AD8532/AD8534 buffer for with U1 to speed on/off switching. higher currents and/or voltage levels, plus sink and source load capability. SINGLE-SUPPLY, BALANCED LINE DRIVER V S The circuit in Figure 43 is a unique line driver circuit topology U2 5V AD8531 used in professional audio applications. It was modified for C1 V = OUT1 0.1µF 3.3V @ 100mA automotive and multimedia audio applications. On a single 5 V supply, the line driver exhibits less than 0.7% distortion into a R2 10kΩ 1% 600 Ω load from 20 Hz to 15 kHz (not shown) with an input R1 10kΩ signal level of 4 V p-p. In fact, the output drive capability of the 1% C2 AD8531/AD8532/AD8534 maintains this level for loads as 0.1µF R3 C3 small as 32 Ω. For input signals less than 1 V p-p, the THD is 2 (See Text) C5 0.1µF 100µF/16V 6 less than 0.1%, regardless of load. The design is a transformer- 3 U1 TANTALUM V C REF196 less, balanced transmission system where output common- V = ON/OFF OUT2 R5 CONTROL 3.3V 4 mode rejection of noise is of paramount importance. As with 0.2Ω C4 INPUT CMOS HI 1µF (OR OPEN) = ON the transformer-based system, either output can be shorted LO = OFF R4 to ground for unbalanced line driver applications without changing 3.3kΩ the circuit gain of 1. Other circuit gains can be set according to the V V S OUT COMMON COMMON equation in the diagram. This allows the design to be easily Figure 42. High Output Current Reference/Regulator configured for inverting, noninverting, or differential operation. R3 The low dropout performance of this circuit is provided by 10kΩ C3 stage U2, an AD8531 connected as a follower/buffer for the R5 2 47µF 50Ω 1 basic reference voltage produced by U1. The low voltage A2 V OUT1 3 R6 saturation characteristic of the AD8531/AD8532/AD8534 10kΩ R2 allows up to 100 mA of load current in the illustrated use, R7 10kΩ 10kΩ 5V as a 5 V to 3.3 V converter with good dc accuracy. In fact, 5V 12V the dc output voltage change for a 100 mA load current delta 2 6 C1 R8 R 22µF 1 7 measures less than 1 mV. This corresponds to an equivalent 100kΩ L A1 A1 3 5 600Ω V IN output impedance of < 0.01 Ω. In this application, the stable R9 C2 1µF 100kΩ 3.3 V from U1 is applied to U2 through a noise filter, R1 to C1. R1 R11 R12 10kΩ 10kΩ U2 replicates the U1 voltage within a few millivolts, but at a 10kΩ A1, A2 = 1/2 AD8532 C4 R10 R14 higher current output at V , with the ability to both sink and OUT1 6 47µF 10kΩ R3 50Ω 7 GAIN = source output current(s), unlike most IC references. R2 and C2 R2 A2 V OUT2 5 R13 SET: R7, R10, R11 = R2 10kΩ in the feedback path of U2 provide additional noise filtering. SET: R6, R12, R13 = R3 Transient performance of the reference/regulator for a 100 mA Figure 43. Single-Supply, Balanced Line Driver for Multimedia and step change in load current is also quite good and is largely Automotive Applications determined by the R5 to C5 output network. With values as shown, the transient is about 20 mV peak and settles to within 2 mV in less than 10 μs for either polarity. Although room exists Rev. F | Page 14 of 20 01099-042 01099-043 AD8531/AD8532/AD8534 This active crossover exhibits less than 0.4% THD+N at output SINGLE-SUPPLY HEADPHONE AMPLIFIER levels of 1.4 V rms using general-purpose, unity-gain HP/LP stages. Because of its speed and large output drive, the AD8531/ In this 2-way example, the LO signal is a dc-to-500 Hz LP woofer AD8532/AD8534 make an excellent headphone driver, as illustrated in Figure 44. Its low supply operation and rail-to-rail output, and the HI signal is the HP (>500 Hz) tweeter output. inputs and outputs give a maximum signal swing on a single U1B forms an LP section at 500 Hz, while U1A provides an HP 5 V supply. To ensure maximum signal swing available to drive section, covering frequencies ≥500 Hz. the headphone, the amplifier inputs are biased to V+/2, which 500Hz C1 R1 R3 AND UP 270µF 0.01µF 31.6kΩ 49.9Ω in this case is 2.5 V. The 100 kΩ resistor to the positive supply + HI V S is equally split into two 50 kΩ resistors, with their common C2 100kΩ 0.01µF U1A point bypassed by 10 μF to prevent power supply noise from AD8532 3 contaminating the audio signal. V 1 IN 2 R IN R2 The audio signal is then ac-coupled to each input through a 100kΩ 4 31.6kΩ 10 μF capacitor. A large value is needed to ensure that the 20 Hz C IN DC – audio information is not blocked. If the input already has the R5 R6 R4 10µF 500Hz 270µF 31.6kΩ 31.6kΩ 49.9Ω + proper dc bias, the ac coupling and biasing resistors are not LO C3 R7 required. A 270 μF capacitor is used at the output to couple the 0.01µF 100kΩ 15.8kΩ V S amplifier to the headphone. This value is much larger than that 6 C4 used for the input because of the low impedance of the head- 100kΩ 7 0.02µF 5 phones, which can range from 32 Ω to 600 Ω. An additional 16 Ω U1B resistor is used in series with the output capacitor to protect the 100kΩ AD8532 10µF output stage of the op amp by limiting the capacitor discharge current. When driving a 48 Ω load, the circuit exhibits less V 5V than 0.3% THD+N at output drive levels of 4 V p-p. S 0.1µF 100µF/25V V 5V TO U1 COM V5V 1µF/0.1µF 50kΩ Figure 45. A Single-Supply, 2-Way Active Crossover 270µF 10µF 16Ω 1/2 LEFT The crossover example frequency of 500 Hz can be shifted 50kΩ AD8532 HEADPHONE LEFT lower or higher by frequency scaling of either resistors or 50kΩ INPUT 10µF capacitors. In configuring the circuit for other frequencies, 100kΩ complementary LP/HP action must be maintained between sections, and component values within the sections must be in the same ratio. Table 6 provides a design aid to adaptation, with V suggested standard component values for other frequencies. 50kΩ For additional information on the active filters and active crossover networks, refer to the data sheet for the OP279, a dual rail-to- 270µF 10µF 16Ω 1/2 50kΩ RIGHT rail, high output current, operational amplifier. AD8532 HEADPHONE RIGHT INPUT 50kΩ Table 6. RC Component Selection for Various Crossover 10µF 100kΩ 1 Frequencies 2 3 Crossover Frequency (Hz) R1/C1 (U1A) , R5/C3 (U1B) Figure 44. Single-Supply, Stereo Headphone Driver 100 160 kΩ/0.01 μF 200 80.6 kΩ/0.01 μF SINGLE-SUPPLY, 2-WAY LOUDSPEAKER 319 49.9 kΩ/0.01 μF CROSSOVER NETWORK 500 31.6 kΩ/0.01 μF Active filters are useful in loudspeaker crossover networks 1 k 16 kΩ/0.01 μF because of small size, relative freedom from parasitic effects, the 2 k 8.06 kΩ/0.01 μF ease of controlling low/high channel drive, and the controlled 5 k 3.16 kΩ/0.01 μF driver damping provided by a dedicated amplifier. Both Sallen- 10 k 1.6 kΩ/0.01 μF Key (SK) and multiple-feedback (MFB) filter architectures are 1 useful in implementing active crossover networks. The circuit Applicable for Filter A = 2. 2 For Sallen-Key stage U1A: R1 = R2, and C1 = C2, and so on. shown in Figure 45 is a single-supply, 2-way active crossover 3 For multiple feedback stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3. that combines the advantages of both filter topologies. Rev. F | Page 15 of 20 01099-044 01099-045 AD8531/AD8532/AD8534 DIRECT ACCESS ARRANGEMENT FOR TELEPHONE P1 LINE INTERFACE Tx GAIN ADJUST R2 Figure 46 illustrates a 5 V only transmit/receive telephone line 9.09kΩ C1 interface for 600 Ω transmission systems. It allows full duplex R1 TRANSMIT TOTELEPHONE 0.1µF 2kΩ R3 TxA 10kΩ 2 LINE transmission of signals on a transformer-coupled 600 Ω line in 360Ω 1 1:1 A1 3 a differential manner. A1 provides gain that can be adjusted to R5 6.2V Z O 10kΩ meet the modem output drive requirements. Both A1 and A2 600Ω 6.2V are configured to apply the largest possible signal on a single 5V DC T1 R6 supply to the transformer. Because of the high output current 6 MIDCOM 10kΩ R7 7 671-8005 10kΩ drive and low dropout voltage of the AD8531/AD8532/AD8534, A2 5 the largest signal available on a single 5 V supply is approximately R8 10µF 10kΩ 4.5 V p-p into a 600 Ω transmission system. A3 is configured as R9 R10 a difference amplifier for two reasons: it prevents the transmit 10kΩ 10kΩ P2 Rx GAIN signal from interfering with the receive signal, and it extracts ADJUST R13 R14 RECEIVE 2 R11 10kΩ 14.3kΩ RxA 1 the receive signal from the transmission line for amplification A3 10kΩ 3 2kΩ by A4. The gain of A4 can be adjusted in the same manner as 6 C2 R12 0.1µF 7 that of A1 to meet the input signal requirements of the modem. A4 10kΩ 5 A1, A2 = 1/2 AD8532 Standard resistor values permit the use of single in-line package A3, A4 = 1/2 AD8532 (SIP) format resistor arrays. Figure 46. Single-Supply Direct Access Arrangement for Modems Rev. F | Page 16 of 20 01099-046 0.10 MAX AD8531/AD8532/AD8534 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 5 4 2.40 1.25 2.10 12 3 1.15 1.80 PIN 1 0.65 BSC 1.00 0.40 1.10 0.90 0.10 0.80 0.70 0.46 0.36 0.30 0.22 0.26 SEATING 0.15 0.08 PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 47. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters 2.90 BSC 5 4 2.80 BSC 1.60 BSC 12 3 PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 10° 0.15 MAX 5° 0.50 0.60 SEATING 0° 0.30 PLANE 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 48. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 49. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. F | Page 17 of 20 012407-A AD8531/AD8532/AD8534 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.38 0.23 0° 0.40 0.00 0.22 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 50. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 3.10 3.00 2.90 8 5 4.50 4.40 6.40 BSC 4.30 1 4 PIN 1 0.65 BSC 0.15 1.20 0.05 MAX 8° 0.75 0.30 0° COPLANARITY SEATING 0.20 0.60 0.19 0.10 PLANE 0.09 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AA Figure 51. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 1.05 BSC 1.00 0.20 1.20 0.80 0.75 0.09 MAX 8° 0.60 0.15 0.30 0° 0.45 0.05 SEATING 0.19 COPLANARITY PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. F | Page 18 of 20 AD8531/AD8532/AD8534 8.75 (0.3445) 8.55 (0.3366) 8 14 6.20 (0.2441) 4.00 (0.1575) 1 5.80 (0.2283) 3.80 (0.1496) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 53. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. F | Page 19 of 20 060606-A AD8531/AD8532/AD8534 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8531AKS-R2 −40°C to +85°C 5-Lead SC70 KS-5 A7B AD8531AKS-REEL7 −40°C to +85°C 5-Lead SC70 KS-5 A7B 1 AD8531AKSZ-R2 −40°C to +85°C 5-Lead SC70 KS-5 A0Q 1 AD8531AKSZ-REEL7 −40°C to +85°C 5-Lead SC70 KS-5 A0Q AD8531ART-REEL −40°C to +85°C 5-Lead SOT-23 RJ-5 A7A AD8531ART-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 A7A 1 AD8531ARTZ-REEL −40°C to +85°C 5-Lead SOT-23 RJ-5 A0P 1 AD8531ARTZ-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 A0P AD8531AR −40°C to +85°C 8-Lead SOIC_N R-8 AD8531AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8531ARZ −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8531ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD8532AR −40°C to +85°C 8-Lead SOIC_N R-8 AD8532AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD8532AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8532ARZ −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8532ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8532ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8532ARM-R2 −40°C to +85°C 8-Lead MSOP RM-8 ARA AD8532ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 ARA 1 AD8532ARMZ-R2 −40°C to +85°C 8-Lead MSOP RM-8 A0R 1 AD8532ARMZ-REEL −40°C to +85°C 8-Lead MSOP RM-8 A0R AD8532ARU −40°C to +85°C 8-Lead TSSOP RU-8 AD8532ARU-REEL −40°C to +85°C 8-Lead TSSOP RU-8 1 AD8532ARUZ −40°C to +85°C 8-Lead TSSOP RU-8 1 AD8532ARUZ-REEL −40°C to +85°C 8-Lead TSSOP RU-8 AD8534AR −40°C to +85°C 14-Lead SOIC_N R-14 AD8534AR-REEL −40°C to +85°C 14-Lead SOIC_N R-14 1 AD8534ARZ −40°C to +85°C 14-Lead SOIC_N R-14 1 AD8534ARZ-REEL −40°C to +85°C 14-Lead SOIC_N R-14 AD8534ARU −40°C to +85°C 14-Lead TSSOP RU-14 AD8534ARU-REEL −40°C to +85°C 14-Lead TSSOP RU-14 1 AD8534ARUZ −40°C to +85°C 14-Lead TSSOP RU-14 1 AD8534ARUZ-REEL −40°C to +85°C 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part. ©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01099-0-1/08(F) Rev. F | Page 20 of 20