ANALOG DEVICES AD8522

+5 Volt, Serial Input, a Dual 12-Bit DAC AD8522 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete Dual 12-Bit DAC V DD No External Components +5 V Single-Supply Operation 610% CS OP CLK DAC A AMP V 4.095 V Full Scale (1 mV/LSB) LATCH OUTA CLK DAC A 12 A REGISTER Buffered Voltage Outputs D Low Power: 5 mW/DAC SDI BANDGAP REF Space Saving 1.5 mm Height SO-14 Package (DATA) 12 REFERENCE BUF SHIFT REGISTER V REF APPLICATIONS Digitally Controlled Calibration REF BUF Servo Controls D DAC B SDO Process Control Equipment REGISTER 12 OP Computer Peripherals DAC B V AMP OUTB LDA CONTROL B Portable Instrumentation LOGIC LDB Cellular Base Stations Voltage Adjustment AD8522 DGND MSB AGND RS GENERAL DESCRIPTION inputs. A serial data output allows the user to easily daisy-chain The AD8522 is a complete dual 12-bit, single-supply, voltage multiple devices in conjunction with a chip select input. A reset output DAC in a 14-pin DIP, or SO-14 surface mount package. RS input sets the outputs to zero scale or midscale, as deter- Fabricated in a CBCMOS process, features include a serial digi- mined by the input MSB. tal interface, onboard reference, and buffered voltage output. The output 4.095 V full scale is laser trimmed to maintain accu- Ideal for +5 V-only systems, this monolithic device offers low racy over the operating temperature range of the device, and cost and ease of use, and requires no external components to gives the user an easy-to-use one-millivolt-per-bit resolution. A realize the full performance of the device. 2.5 V reference output is also available externally for other data The serial digital interface allows interfacing directly to numer- acquisition circuitry, and for ratiometric applications. The out- ous microcontroller ports, with a simple high speed, three-wire put buffers are capable of driving ±5 mA. data, clock, and load strobe format. The 16-bit serial word con- The AD8522 is available in the 14-pin plastic DIP and low pro- tains the 12-bit data word and DAC select address, which is de- file 1.5 mm SOIC-14 packages. coded internally or can be decoded externally using LDA, LDB 0.6 PACKAGE TYPES AVAILABLE V = +4.5V DD 0.4 T = –55°C, +25°C, +85°C, +125°C A +25°C 0.2 –55°C 0 –0.2 –0.4 PDIP-14 –0.6 +85°C SO-14 +125°C –0.8 –1.0 0 1024 2048 3072 4096 DIGITAL INPUT CODE – Decimal Figure 1. Linearity Error vs. Digital Code & Temperature REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 LINEARITY ERROR – LSB AD8522–SPECIFICATIONS (@ V = +5.0 V 6 10%, R = No Load, –408C ≤ T ≤ +858C, both DACs tested, unless DD L A otherwise noted) ELECTRICAL CHARACTERISTICS Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE 1 Resolution N 12 Bits Relative Accuracy INL -1.5 ±0.5 +1.5 LSB Differential Nonlinearity DNL Monotonic -1 ±0.5 +1 LSB Zero-Scale Error V Data = 000 +0.5 +3 mV ZSE H 2 Full-Scale Voltage V Data = FFF 4.079 4.095 4.111 Volts FS H 2, 3 Full-Scale Tempco TCV ±15 ppm/°C FS MATCHING PERFORMANCE Linearity Matching Error ΔV A/B ±1 LSB FS ANALOG OUTPUT Output Current I Data = 800 , ΔV ≤ 3 LSB ±5mA OUT H OUT Load Regulation at Half-Scale LD R = 402 Ω to ∞, Data = 800 1 3 LSB REG L H 3 Capacitive Load C No Oscillation 500 pF L REFERENCE OUTPUT Output Voltage V 2.484 2.500 2.516 V REF 4 Output Source Current I ΔV < 18 mV 5 mA REF REF Line Rejection LN 0.025 0.08 %/V REJ Load Regulation LD I = 0 to 5 mA, Data = 800 0.025 0.1 %/mA REG REF H LOGIC INPUTS & OUTPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 10 μA IL 3 Input Capacitance C 10 pF IL Logic Output Voltage Low V I = 1.6 mA 0.4 V OL OL Logic Output Voltage High V I = 400 μA 3.5 V OH OH 3, 5 TIMING SPECIFICATIONS Clock Width High t 35 ns CH Clock Width Low t 35 ns CL Load Pulse Width t 25 ns LDW Data Setup t 10 ns DS Data Hold t 20 ns DH Clear Pulse Width t 20 ns CLRW Load Setup t 10 ns LD1 Load Hold t 10 ns LD2 Select t 30 ns CSS Deselect t 30 ns CSH Clock to SDO Propagation Delay t 20 45 80 ns PD 3, 5 AC CHARACTERISTICS 6 Voltage Output Settling Time t To ±1 LSB of Final Value 16 μs S Crosstalk C Signal Measured at DAC Output, T While Changing Opposite LDA/B 38 dB DAC Glitch Q Half-Scale Transition 13 nV s Digital Feedthrough D Signal Measured at DAC Output, FT While Changing Data Without LDA/B 2 nV s SUPPLY CHARACTERISTICS Positive Supply Current I V = 5.5 V, V = 2.4 V or V = 0.8 V 3 5 mA DD DD IH IL V = 5 V, V = 0 V 1 2 mA DD IL 7 Power Dissipation P V = 5 V, V = 2.4 V or V = 0.8 V 15 25 mW DISS DD IH IL V = 5 V, V = 0 V 5 10 mW DD IL Power Supply Sensitivity PSS ΔV = ±5% 0.002 0.004 %/% DD NOTES 1 1 LSB = 1 mV for 0 V to +4.095 V output range. 2 Includes internal voltage reference error. 3 These parameters are guaranteed by design and not subject to production testing. 4 Very little sink current is available at the V pin. Use external buffer if setting up a virtual ground. REF 5 All input control signals are specified with t = t = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. r f 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. 7 Power Dissipation is calculated I × 5 V. DD Specifications subject to change without notice. –2– REV. A AD8522 SDI Sf/Hd B A NC DB11 DB10 DB4 DB3 DB2 DB1 DB0 CLK t t CSS CSH CS t t LD1 LD2 LD t LDW t PD SDO SDI t t DS DH t CH t CL CLK t LD2 t LDW LD t CLRW RS t S t S FS ±1 LSB V OUT ERROR BAND ZS Figure 2. Timing Diagram SERIAL INPUT REGISTER DATA FORMAT Last First D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 NC A B Sf/Hd Table I. Truth Table Data Word Ext Pins Sf/Hd BA LDA LDB DAC Register Hardware Load: LX X ↓↓ Loads DACA + DACB with Data from SR LX X ↓ H Loads DACA with Data from SR L XXH ↓ Loads DACB with Data from SR L X X H H No Load Software Decode Load: H L L X X No Load HH L ↓↓ Loads DACB with Data from SR, See Note 1 Below H H L H H No Load HL H ↓↓ Loads DACA with Data from SR, See Note 1 Below H L H H H No Load HH H ↓↓ Loads DACA + DACB with Data from SR, See 1 Note Below H H H H H No Load NOTES 1 In software mode LDA and LDB perform the same function. They can be tied together or the unused pin should be tied high. 2 External Pins LDA and LDB should always be high when shifting Data into the shift register. 3 ↓ symbol denotes negative transition. 1.6mA SDO 1.6 VOLT 200µA Figure 3. AC Timing SDO Pin Load Circuit REV. A –3– AD8522 PIN DESCRIPTION Pin Function SDI Serial Data Input, input data loads directly into the shift register. CLK Clock input, positive edge clocks data into shift register. CS Chip Select, active low input. Prevents shift register loading when high. Does not affect LDA and LDB operation. LDA/B Load DAC register strobes, active low. Transfers shift register data to DAC register. See truth table for operation. Software decode feature only requires one LD strobe. Tie LDA and LDB together or use one of them with the other pin tied high. SDO Serial Data Output. Output of shift register, always active. RS Resets DAC registers to condition determined by MSB pin. Active low input. MSB Digital input: High presets DAC registers to half scale (800 ); Low clears all registers to zero (000 ), when RS is H H strobed to active low. V Positive +5 V power supply input. Tolerance ±10%. DD AGND Analog Ground Input. DGND Digital Ground Input. V Reference Voltage Output, 2.5 V nominal. REF V DAC A/B voltage outputs, 4.095 V full scale, ±5 mA output. OUT A/B PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS* V to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V DD 14-Pin Plastic DIP 14-Lead SO-14 Logic Inputs and Output to DGND . . . . .–0.3 V, V + 0.3 V DD V to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V + 0.3 V OUT DD V to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V + 0.3 V REF DD V 1 14 V OUTA OUTB AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V DD AGND 2 13 V REF I Short Circuit to GND or V . . . . . . . . . . . . . . . . 50 mA OUT DD 12 DGND 3 V DD Package Power Dissipation . . . . . . . . . . . . . . .(T max–T )/θ AD8522 J A JA (Not To Scale) CS 4 11 MSB 1 Thermal Resistance, θ JA CLK 5 10 RS 14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . . . 83°C/W 9 SDI 6 LDA 14-Lead SOIC Package (SO-14) . . . . . . . . . . . . . . 120°C/W SDO 7 8 LDB Maximum Junction Temperature (T max) . . . . . . . . . . 150°C J Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Table II. Truth Tables *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional DAC Register Preset operation of the device at these or any other conditions above those indicated in the RS MSB Register Activity operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 0 0 Asynchronously Resets DAC Registers to Zero Scale ORDERING GUIDE 0 1 Asynchronously Presets DAC Registers to Half Scale (800 ) H Temperature Package Package 1 X None Model Range Description Option AD8522AN –40°C to +85°C 14-Pin P-DIP N-14 Shift Register AD8522AR –40°C to +85°C 14-Lead SOIC SO-14 CS CLK Shift Register 1 X No Effect The AD8522 contains 1482 transistors. 0 ↑ Shifts Register One Bit, SDO Outputs Data from 16 Clocks Earlier CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8522 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. A AD8522 OPERATION V DD The AD8522 is a complete ready-to-use dual 12-bit digital-to- analog converter. Only one +5 V power supply is necessary for P-CH operation. It contains two voltage-switched, 12-bit, laser- trimmed digital-to-analog converters, a curvature-corrected V bandgap reference, rail-to-rail output op amps, input registers, OUT and DAC registers. The serial data interface consists of a serial N-CH data input (SDI), clock (CLK), and two load strobe pins (LDA, LDB) with an active low CS strobe. In addition, an asynchro- nous RS pin will set all DAC register bits to zero causing the AGND V to become zero volts, or to midscale for trimming applica- OUT tions when the MSB pin is programmed to Logic 1. This func- tion is useful for power on reset or system failure recovery to a Figure 5. Equivalent Analog Output Circuit known state. Figures 6 and 7 in the typical performance characteristics sec- tion provide information on output swing performance near D/A CONVERTER SECTION ground and full scale as a function of load. In addition to resis- The internal DAC is a 12-bit voltage-mode device with an out- tive load driving capability the amplifier has also been carefully put that swings from AGND potential to the 2.5 V internal designed and characterized for up to 500 pF capacitive load bandgap voltage. It uses a laser-trimmed R-2R ladder which is driving capability. switched by N channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input REFERENCE SECTION code. The DAC output is internally connected to the rail-to-rail The internal 2.5 V curvature-corrected bandgap voltage refer- output op amp. ence is laser trimmed for both initial accuracy and low tempera- ture coefficient. The voltage generated by the reference is AMPLIFIER SECTION available at the V pin. Since V is not intended to drive REF REF The internal DAC’s output is buffered by a low power con- heavy external loads, it must be buffered. The equivalent emit- sumption precision amplifier. This low power amplifier contains ter follower output circuit of the V pin is shown in Figure 4. REF a differential PNP pair input stage that provides low offset volt- Bypassing the V pin will improve noise performance; how- age and low noise, as well as the ability to amplify the zero-scale REF ever, bypassing is not required for proper operation. Figure 10 DAC output voltages. The rail-to-rail amplifier is configured in shows broad band noise performance. a gain of 1.638 (= 4.095 V/2.5 V) in order to set the 4.095 V full-scale output (1 mV/LSB). See Figure 4 for an equivalent POWER SUPPLY circuit schematic of the analog section. The very low power consumption of the AD8522 is a direct RAIL-TO-RAIL VOLTAGE SWITCHED 12-BIT BANDGAP result of a circuit design optimizing use of a CBCMOS process. OUTPUT R-2R D/A CONVERTER REFERENCE AMPLIFIER By using the low power characteristics of the CMOS for the 2R V REF 2.5V logic, and the low noise, tight matching of the complementary V BUFFER OUT R bipolar transistors good analog accuracy is achieved. 2R R2 For power consumption sensitive applications it is important to R note that the internal power consumption of the AD8522 is 2R R1 strongly dependent on the actual input voltage levels present on the SDI, CLK, CS, MSB, LDA, LDB and RS pins. Since these in- A = 4.096/2.5 V puts are standard CMOS logic structures, they contribute static 2R = 1.638V/V SPDT power dissipation dependent on the actual driving logic V and N CH FET OH 2R SWITCHES V voltage levels. Consequently for optimum dissipation use of OL CMOS logic versus TTL provides minimal dissipation in the static state. A V = 0 V on the logic input pins provides the lowest INL Figure 4. Equivalent AD8522 Schematic of Analog Portion standby dissipation of 1 mA with a +5 V power supply. The op amp has a 16 μs typical settling time to 0.01%. There As with any analog system, it is recommended that the AD8522 are slight differences in settling time for negative slewing signals power supply be bypassed on the same PC card that contains versus positive. See the oscilloscope photos in the “Typical Per- the chip. Figure 12 shows the power supply rejection versus fre- formance Characteristics” section of this data sheet. quency performance. This should be taken into account when using higher frequency switched-mode power supplies with OUTPUT SECTION ripple frequencies of 100 kHz and higher. The rail-to-rail output stage of this amplifier has been designed One advantage of the rail-to-rail output amplifiers used in the to provide precision performance while operating near either AD8522 is the wide range of usable supply voltage. The part is power supply. Figure 5 shows an equivalent output schematic of fully specified and tested over temperature for operation from the rail-to-rail amplifier with its N channel pull-down FETs that +4.5 V to +5.5 V. If reduced linearity and source current capa- will pull an output load directly to GND. The output sourcing bility near full scale can be tolerated, operation of the AD8522 current is provided by a P channel pull-up device that can sup- ply GND terminated loads, especially important at the –10% supply tolerance value of 4.5 V. REV. A –5– AD8522 is possible down to +4.3 V. The minimum operating supply input register and transferring the 12 bits of data into the de- voltage versus load current plot, in Figure 7, provides informa- coded address determined by the address bits A and B in the se- tion for operation below V = +4.5 V. rial input register. DD Unipolar Output Operation TIMING AND CONTROL This is the basic mode of operation for the AD8522. The The AD8522 has a 16-bit serial input register that accepts AD8522 has been designed to drive loads as low as 820 Ω in clocked in data when the CS pin is active low. The DAC regis- parallel with 500 pF. The code table for this operation is shown ters are updated by the Load Enable (LDA and LDB) pins. in Table III. The AD8522 offers two modes of data loading. The first mode, hardware-load, directs the data currently clocked into the serial Table III. Unipolar Code Table shift register into either the DAC A or the DAC B register or Hexadecimal Decimal Analog both depending on the external active low strobing of the LDA Number in Number in Output or LDB pin. Serial data register bit Sf/Hd must be low for this DAC Register DAC Register Voltage (V) mode to be in effect. The second mode of operation is software-load which is de- FFF 4095 +4.095 signed to minimize the number of control lines connected to 801 2049 +2.049 the AD8522. In this mode of operation the LDA and LDB pins 800 2048 +2.048 act as one control input taking the present contents of the serial 7FF 2047 +2.047 000 0 0 Typical Performance Characteristics 5 5.2 100 V = +5V DD ΔV ≤ 1 LSB FS T = +25°C A V = +5V DATA = FFF DD 5.0 H 4 DATA = 000 TA = +25°C H R TIED TO AGND L VIH = 5.0V 10 DATA = FFF H V = 0.0V IL 4.8 3 PROPER OPERATION +85°C V H = +5V IN 4.6 WHEN V SUPPLY 1 DD V L = 0V IN VOLTAGE IS ABOVE 2 CURVE 4.4 –55°C 0.1 1 4.2 R TIED TO +5V L +25°C DATA = 000 H 0 4.0 0.01 10 100 1k 10k 100k 0.01 0.1 1.0 10 100 1 10 100 1000 LOAD RESISTANCE – Ω OUTPUT LOAD CURRENT – mA OUTPUT SINK CURRENT – µA Figure 6. Output Swing vs. Load Figure 7. Minimum Supply Voltage Figure 8. Pull-Down Voltage vs. Out- vs. Load Current put Sink Current Capability 80 9 8 60 POSITIVE T = +25°C CURRENT A NBW = 1MHz T = +25°C A 7 LIMIT 40 100 90 6V = +4.5V DD 20 DATA = 800 H 5 0 V = +5V DD 4 –20 3 10 –40 0% 2 NEGATIVE CURRENT –60 1 LIMIT 0 –80 100µs/DIV 123 01 2 3 4 5 OUTPUT VOLTAGE – Volts LOGIC INPUT VOLTAGE V H – Volts IN Figure 9. I vs. V Figure 11. Supply Current vs. Logic OUT OUT Figure 10. Broadband Noise Input Voltage –6– REV. A OUTPUT VOLTAGE – Volts OUTPUT CURRENT – mA 200µV/DIV V MIN – Volts DD OUTPUT PULL-DOWN VOLTAGE – mV SUPPLY CURRENT I – mA DD AD8522 140 V = +5V ± 200mV DD AC 5V 2048 TO 2047 RS 10 10 T = +25°C A 120 5V DATA = FFF H 100 100 LD 90 90 0V 100 V OUT 4V 80 T = +25°C V A OUT T = +25°C A V = +5V 60 100mV/ DD V = +5V DD DIV 10 10 0% 40 0% #299, DAC A 0V V H = +5V 100mV 500ns IN 20 V L = 0V IN –SR +SR TIME – 500ns/DIV TIME – 20µs/DIV 0 10 100 1k 10k 100k 1M FREQUENCY – Hz Figure 13. Midscale Transition Figure 14. Large Signal Settling Time Figure 12. Power Supply Rejection Performance vs. Frequency 4.11 1.6 40 TUE = ∑ (INL+ZS+FS) V = +4.5V DD 1.4 V = +4.5V DD 35 SSZ = 300 UNITS 4.105 NO LOAD NO LOAD V = +4.5V DD SSZ = 300 UNITS T = +25°C 1.2 SSZ = 300 UNITS A 30 4.1 AVG +1σ 1.0 25 4.095 0.8 20 AVG +1σ 4.09 AVG 0.6 15 AVG –1σ 4.085 AVG 0.4 10 4.08 0.2 5 AVG –1σ 4.075 0.0 0 –55 –35 –15 5 25 45 65 85 105 125 –5 –4 –3 –2 –1 0 1 2 3 4 5 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE – °C TOTAL UNADJUSTED ERROR – mV TEMPERATURE – °C Figure 15. Total Unadjusted Error Figure 16. Full-Scale Voltage vs. Figure 17. Zero-Scale Voltage vs. Histogram Temperature Temperature 4.096 4.0 100 V = +4.5V DD 4.095 SSZ = 135 UNITS 3.5 V = +5V 4.094 DD DATA = FFF H DATA = FFFHm4.093 3.0 V = +5.5V T = +25°C DD A AVG +1σ 4.092 10 2.5 V = +5V DD 4.091 4.090 V = +4.5V DD 2.0 AVG 4.089 1.5 4.088 1.0 V = +2.4V IN 4.087 1.0 NO LOAD AVG –1σ 4.086 0.5 4.085 4.084 0.1 0 0 100 200 300 400 500 600 –55 –35 –15 5 25 45 65 85 105 125 10 100 1k 10k 100k HOURS OF OPERATION AT +150°C TEMPERATURE – °C FREQUENCY – Hz Figure 19. Long Term Drift Acceler- Figure 20. Supply Current vs. Figure 18. Output Voltage Noise ated by Burn-In Temperature Density vs. Frequency REV. A –7– POWER SUPPLY REJECTION – dB FREQUENCY OUTPUT NOISE DENSITY – V/√Hz FULL SCALE VOLTAGE – Volts FULL-SCALE OUTPUT VOLTAGE – Volts ZERO-SCALE VOLTAGE – mV OUTPUT INPUT SUPPLY CURRENT – mA AD8522 2.504 2V V = +4.5V DD AVG +1σ 5V 2.502 SSZ = 300 UNITS 100 CLK V DD 90 0V AVG T = +25°C A 2.500 NO LOAD 0V V = +5V DD AVG –1σ 2.498 V OUT 20mV/ DIV V REF 2.496 10 0% 0V 1µs 2.494 1V TIME – 5µs/DIV TIME – 1µs/DIV 2.492 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE – °C Figure 23. Reference Voltage vs. Figure 22. Digital Feedthrough vs. Figure 21. Reference Startup vs. Temperature Time Time 0.05 0 Δ V = +4.5V TO +5.5V DD V = +4.5V DD SSZ = 300 UNITS –0.01 SSZ = 300 UNITS 0.04 Δ I = 5mA L –0.02 0.03 AVG +3σ AVG +3σ AVG –0.03 AVG 0.02 AVG –3σ –0.04 AVG –3σ 0.01 –0.05 0 –0.06 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE – °C TEMPERATURE – °C Figure 25. Reference Line Regulation vs. Figure 24. Reference Load Regulation Temperature vs. Temperature OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Narrow Body SOIC (SO-14) 14-Lead Epoxy DIP (N-14) 14 8 14 8 0.1574 (4.00) 0.280 (7.11) PIN 1 0.240 (6.10) 0.1497 (3.80) PIN 1 0.2440 (6.20) 1 7 7 1 0.2284 (5.80) 0.325 (8.25) 0.795 (20.19) 0.300 (7.62) 0.725 (18.42) 0.3444 (8.75) 0.0196 (0.50) 0.060 (1.52) x 45 ° 0.3367 (8.55) 0.210 0.195 (4.95) 0.0099 (0.25) 0.015 (0.38) (5.33) 0.115 (2.93) 0.0688 (1.75) MAX 0.0532 (1.35) 0.130 8° 0.160 (4.06) 0.015 (0.381) (3.30) 0.0098 (0.25) 0° 0.0500 (1.27) 0.008 (0.204) 0.0500 0.0192 (0.49) 0.115 (2.93) MIN 0.0098 (0.25) (1.27) 0.0040 (0.10) 0.0160 (0.41) 0.0138 (0.35) 0.0075 (0.19) BSC SEATING 0.022 (0.558) 0.070 (1.77) 0.100 PLANE 0.014 (0.356) (2.54) 0.045 (1.15) BSC –8– REV. A V LOAD REGULATION – %/mA REF V LINE REGULATION – %/Volts REF V – Volts REF PRINTED IN U.S.A. C1942–18–94