ANALOG DEVICES AD8510

Precision, Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifiers AD8510/AD8512/AD8513 FEATURES PIN CONFIGURATIONS Fast settling time: 500 ns to 0.1% NULL 1 8 NC NULL 1 8 NC Low offset voltage: 400 μV maximum AD8510 AD8510 –IN 2 7 V+ –IN 2 7 V+ TOP VIEW Low T V : 1 μV/°C typical TOP VIEW C OS +IN 3 6 OUT +IN 3 6 OUT (Not to Scale) (Not to Scale) V– NULL Low input bias current: 25 pA typical at V = ±15 V 45 V–45 NULL S Dual-supply operation: ±5 V to ±15 V NC = NO CONNECT NC = NO CONNECT Low noise: 8 nV/√Hz typical at f = 1 kHz Figure 1. 8-Lead MSOP (RM Suffix) Figure 2. 8-Lead SOIC_N (R Suffix) Low distortion: 0.0005% No phase reversal OUT A 1 8 V+ OUT A 1 8 V+ AD8512 Unity gain stable AD8512 –IN A 2 7 OUT B –IN A 2 7 OUT B TOP VIEW TOP VIEW +IN A 3 6 –IN B +IN A –IN B 3 6 (Not to Scale) (Not to Scale) APPLICATIONS V–45 +IN B V–45 +IN B Instrumentation Figure 3. 8-Lead MSOP (RM Suffix) Figure 4. 8-Lead SOIC_N (R Suffix) Multipole filters Precision current measurement OUT A 1 14 OUT D OUT A 1 14 OUT D Photodiode amplifiers –IN A 2 13 –IN D –IN A 2 13 –IN D Sensors +IN A 3 12 +IN D +IN A 3 12 +IN D AD8513 AD8513 Audio V+ 4 11 V– V+ 4 11 V– TOP VIEW TOP VIEW (Not to Scale) (Not to Scale) +IN B 5 10 +IN C +IN B 5 10 +IN C –IN B 6 9 –IN C –IN B 6 9 –IN C OUT B 7 8 OUT C OUT B 7 8 OUT C Figure 5. 14-Lead SOIC_N (R Suffix) Figure 6. 14-Lead TSSOP (RU Suffix) GENERAL DESCRIPTION The AD8510/AD8512/AD8513 are single-, dual-, and quad- Fast slew rate and great stability with capacitive loads make the precision JFET amplifiers that feature low offset voltage, input AD8510/AD8512/AD8513 a perfect fit for high performance bias current, input voltage noise, and input current noise. filters. Low input bias currents, low offset, and low noise result in a wide dynamic range of photodiode amplifier circuits. Low The combination of low offsets, low noise, and very low input noise and distortion, high output current, and excellent speed bias currents makes these amplifiers especially suitable for high make the AD8510/AD8512/AD8513 great choices for audio impedance sensor amplification and precise current measurements applications. using shunts. The combination of dc precision, low noise, and fast settling time results in superior accuracy in medical The AD8510/AD8512 are both available in 8-lead narrow SOIC_N instruments, electronic measurement, and automated test and 8-lead MSOP packages. MSOP-packaged parts are only equipment. Unlike many competitive amplifiers, the AD8510/ available in tape and reel. The AD8513 is available in 14-lead AD8512/AD8513 maintain their fast settling performance even SOIC_N and TSSOP packages. with substantial capacitive loads. Unlike many older JFET The AD8510/AD8512/AD8513 are specified over the −40°C to amplifiers, the AD8510/AD8512/AD8513 do not suffer from +125°C extended industrial temperature range. output phase reversal when input voltages exceed the maximum common-mode voltage range. Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02729-003 02729-001 02729-005 02729-004 02729-002 02729-006 AD8510/AD8512/AD8513 TABLE OF CONTENTS Features .............................................................................................. 1 Output Phase Reversal ............................................................... 13 Applications ....................................................................................... 1 Total Harmonic Distortion (THD) + Noise .............................. 13 Pin Configurations ........................................................................... 1 Total Noise Including Source Resistors ................................... 13 General Description ......................................................................... 1 Settling Time ............................................................................... 14 Revision History ............................................................................... 2 Overload Recovery Time .......................................................... 14 Specif ica t ions ..................................................................................... 3 Capacitive Load Drive ............................................................... 14 Electrical Characteristics ............................................................. 4 Open-Loop Gain and Phase Response .................................... 15 Absolute Maximum Ratings ............................................................ 6 Precision Rectifiers ..................................................................... 16 ESD Caution .................................................................................. 6 I-V Conversion Applications .................................................... 17 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 19 General Application Information ................................................. 13 Ordering Guide .......................................................................... 20 Input Overvoltage Protection ................................................... 13 REVISION HISTORY 2/09—Rev. H to Rev. I 9/03—Rev. B to Rev. C Changes to Ordering Guide ............................................................ 4 Changes to Figure 25 ...................................................................... 10 Updated Figure 2 ............................................................................ 10 Changes to Ordering Guide .......................................................... 20 Changes to Input Overvoltage Protection Section .................... 10 10/07—Rev. G to Rev. H Changes to Figure 10 and Figure 11............................................. 12 Changes to Crosstalk Section ........................................................ 18 Changes to Photodiode Circuits Section .................................... 13 Added Figure 58 .............................................................................. 18 Changes to Figure 13 and Figure 14............................................. 13 Deleted Precision Current Monitoring Section ......................... 14 6/07—Rev. F to Rev. G Updated Outline Dimensions ....................................................... 15 Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Table 1 and Table 2 ....................................................... 3 3/03—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 19 Updated Figure 5 ............................................................................ 11 Changes to Ordering Guide .......................................................... 20 Updated Outline Dimensions ....................................................... 15 6/06—Rev. E to Rev. F 8/02—Rev. 0 to Rev. A Changes to Figure 23 ........................................................................ 9 Added AD8510 Model ....................................................... Universal Updated Outline Dimensions ....................................................... 19 Added Pin Configurations ............................................................... 1 Changes to Ordering Guide .......................................................... 20 Changes to Specifications ................................................................. 2 Changes to Ordering Guide ............................................................. 4 6/04—Rev. D to Rev. E Changes to TPC 2 and TPC 3 .......................................................... 5 Changes to Format ............................................................. Universal Added TPC 10 and TPC 12 .............................................................. 6 Changes to Specifications ................................................................ 3 Replaced TPC 20 ............................................................................... 8 Updated Outline Dimensions ....................................................... 19 Replaced TPC 27 ............................................................................... 9 10/03—Rev. C to Rev. D Changes to General Application Information Section .............. 10 Added AD8513 Model ....................................................... Universal Changes to Figure 5 ........................................................................ 11 Changes to Specifications ................................................................ 3 Changes to I-V Conversion Applications Section ..................... 13 Added Figure 36 through Figure 40 ............................................. 10 Changes to Figure 13 and Figure 14............................................. 13 Added Figure 55 and Figure 57..................................................... 17 Changes to Figure 17 ...................................................................... 14 Changes to Ordering Guide .......................................................... 20 Rev. I | Page 2 of 20 AD8510/AD8512/AD8513 SPECIFICATIONS @ VS = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS 1 Offset Voltage (B Grade) V 0.08 0.4 mV OS −40°C < TA < +125°C 0.8 mV Offset Voltage (A Grade) VOS 0.1 0.9 mV −40°C < TA < +125°C 1.8 mV Input Bias Current I 21 75 pA B −40°C < T < +85°C 0.7 nA A −40°C < T < +125°C 7.5 nA A Input Offset Current IOS 5 50 pA −40°C < TA < +85°C 0.3 nA −40°C < T < +125°C 0.5 nA A Input Capacitance Differential 12.5 pF Common Mode 11.5 pF Input Voltage Range −2.0 +2.5 V Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +2.5 V 86 100 dB Large-Signal Voltage Gain A R = 2 kΩ, V = −3 V to +3 V 65 107 V/mV VO L O 1 Offset Voltage Drift (B Grade) ΔV/ΔT 0.9 5 μV/°C OS Offset Voltage Drift (A Grade) ΔV/ΔT 1.7 12 μV/°C OS OUTPUT CHARACTERISTICS Output Voltage High V R = 10 kΩ 4.1 4.3 V OH L Output Voltage Low V R = 10 kΩ, −40°C < T < +125°C −4.9 −4.7 V OL L A Output Voltage High VOH RL = 2 kΩ 3.9 4.2 V Output Voltage Low VOL RL = 2 kΩ, −40°C < TA < +125°C −4.9 −4.5 V Output Voltage High V R = 600 Ω 3.7 4.1 V OH L Output Voltage Low V R = 600 Ω, −40°C < T < +125°C −4.8 −4.2 V OL L A Output Current I ±40 ±54 mA OUT POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 86 130 dB S Supply Current/Amplifier I SY AD8510/AD8512/AD8513 VO = 0 V 2.0 2.3 mA AD8510/AD8512 −40°C < TA < +125°C 2.5 mA AD8513 −40°C < TA < +125°C 2.75 mA DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ 20 V/μs Gain Bandwidth Product GBP 8 MHz Settling Time t To 0.1%, 0 V to 4 V step, G = +1 0.4 μs S Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, G = +1, R = 2 kΩ 0.0005 % L Phase Margin φM 44.5 Degrees NOISE PERFORMANCE Voltage Noise Density e f = 10 Hz 34 nV/√Hz n f = 100 Hz 12 nV/√Hz f = 1 kHz 8.0 10 nV/√Hz f = 10 kHz 7.6 nV/√Hz Peak-to-Peak Voltage Noise e p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 μV p-p n 1 AD8510/AD8512 only. Rev. I | Page 3 of 20 AD8510/AD8512/AD8513 ELECTRICAL CHARACTERISTICS @ VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS 1 Offset Voltage (B Grade) VOS 0.08 0.4 mV −40°C < TA < +125°C 0.8 mV Offset Voltage (A Grade) V 0.1 1.0 mV OS −40°C < T < +125°C 1.8 mV A Input Bias Current IB 25 80 pA −40°C < TA < +85°C 0.7 nA −40°C < TA < +125°C 10 nA Input Offset Current I 6 75 pA OS −40°C < T < +85°C 0.3 nA A −40°C < T < +125°C 0.5 nA A Input Capacitance Differential 12.5 pF Common Mode 11.5 pF Input Voltage Range −13.5 +13.0 V Common-Mode Rejection Ratio CMRR V = −12.5 V to +12.5 V 86 108 dB CM Large-Signal Voltage Gain A 115 196 V/mV VO RL = 2 kΩ, VCM = 0 V, VO = −13.5 V to +13.5 V 1 Offset Voltage Drift (B Grade) ΔVOS/ΔT 1.0 5 μV/°C Offset Voltage Drift (A Grade) ΔV /ΔT 1.7 12 μV/°C OS OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 10 kΩ +14.0 +14.2 V Output Voltage Low V R = 10 kΩ, −40°C < T < +125°C −14.9 −14.6 V OL L A Output Voltage High V R = 2 kΩ +13.8 +14.1 V OH L Output Voltage Low V R = 2 kΩ, −40°C < T < +125°C –14.8 −14.5 V OL L A Output Voltage High VOH RL = 600 Ω +13.5 +13.9 V RL = 600 Ω, −40°C < TA < +125°C +11.4 V Output Voltage Low VOL RL = 600 Ω −14.3 −13.8 V R = 600 Ω, −40°C < T < +125°C −12.1 V L A Output Current I ±70 mA OUT POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 86 dB S Supply Current/Amplifier I SY AD8510/AD8512/AD8513 VO = 0 V 2.2 2.5 mA AD8510/AD8512 −40°C < TA < +125°C 2.6 mA AD8513 −40°C < TA < +125°C 3.0 mA DYNAMIC PERFORMANCE Slew Rate SR RL = 2 kΩ 20 V/μs Gain Bandwidth Product GBP 8 MHz Settling Time t To 0.1%, 0 V to 10 V step, G = +1 0.5 μs S To 0.01%, 0 V to 10 V step, G = +1 0.9 μs Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, G = +1, R = 2 kΩ 0.0005 % L Phase Margin φM 52 Degrees Rev. I | Page 4 of 20 AD8510/AD8512/AD8513 Parameter Symbol Conditions Min Typ Max Unit NOISE PERFORMANCE Voltage Noise Density en f = 10 Hz 34 nV/√Hz f = 100 Hz 12 nV/√Hz f = 1 kHz 8.0 10 nV/√Hz f = 10 kHz 7.6 nV/√Hz Peak-to-Peak Voltage Noise e p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 μV p-p n 1 AD8510/AD8512 only. Rev. I | Page 5 of 20 AD8510/AD8512/AD8513 ABSOLUTE MAXIMUM RATINGS Table 4. Thermal Resistance Table 3. 1 Package Type θ θ Unit JA JC Parameter Rating 8-Lead MSOP (RM) 210 45 °C/W Supply Voltage ±18 V 8-Lead SOIC_N (R) 158 43 °C/W Input Voltage ±V S 14-Lead SOIC_N (R) 120 36 °C/W Output Short-Circuit Duration to GND Observe derating curves 14-Lead TSSOP (RU) 180 35 °C/W Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C 1 θJA is specified for worst-case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages. Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Electrostatic Discharge 2000 V ESD CAUTION (Human Body Model) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. I | Page 6 of 20 AD8510/AD8512/AD8513 TYPICAL PERFORMANCE CHARACTERISTICS 120 100k V = ±15V SY V = ±5V, ±15V SY T = 25°C A 100 10k 80 1k 60 100 40 10 20 0 1 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 –40 –25 –10 5 20 35 50 65 80 95 110 125 INPUT OFFSET VOLTAGE (mV) TEMPERATURE (°C) Figure 7. Input Offset Voltage Distribution Figure 10. Input Bias Current vs. Temperature 30 1000 V = ±15V SY B GRADE 25 100 20 ±15V 15 10 ±5V 10 1 5 0 0.1 0 1 23 4 5 6 –40 –25 –10 5 20 35 50 65 80 95 110 125 T V (µV/°C) C OS TEMPERATURE (°C) Figure 11. Input Offset Current vs. Temperature Figure 8. AD8510/AD8512 TCVOS Distribution 30 40 V = ±15V T = 25°C SY A A GRADE 35 25 30 20 25 20 15 15 10 10 5 5 0 0 8 13 18 23 28 30 0 1 23 4 5 6 SUPPLY VOLTAGE (V+ – V– ) T V (µV/°C) C OS Figure 9. AD8510/AD8512 TCVOS Distribution Figure 12. Input Bias Current vs. Supply Voltage Rev. I | Page 7 of 20 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 02729-009 02729-008 02729-007 INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (pA) INPUT OFFSET CURRENT (pA) 02729-012 02729-011 02729-010 AD8510/AD8512/AD8513 2.0 2.8 T = 25°C A T = 25°C A 1.9 2.6 1.8 2.4 1.7 2.2 1.6 2.0 1.5 1.8 1.4 1.6 1.3 1.4 1.2 1.1 1.2 1.0 1.0 8 13 18 23 28 30 8 13 18 23 28 33 SUPPLY VOLTAGE (V+ – V–) SUPPLY VOLTAGE (V+ – V–) Figure 13. AD8512 Supply Current per Amplifier vs. Supply Voltage Figure 16. AD8510 Supply Current vs. Supply Voltage 16 70 315 V V = ±15V OL SY V = ±15V SY 60 270 14 R = 2.5kΩ L C = 20pF SCOPE V OH 225 50 Φ = 52° M 12 180 40 10 30 135 8 20 90 10 45 6 V OL V = ±5V SY 0 0 4 V –45 OH –10 2 –20 –90 0 –135 –30 0 10 20 30 40 50 60 70 80 10k 100k 1M 10M 50M LOAD CURRENT (mA) FREQUENCY (Hz) Figure 14. AD8510/AD8512 Output Voltage vs. Load Current Figure 17. Open-Loop Gain and Phase vs. Frequency 2.50 2.50 2.25 ±15V 2.25 2.00 2.00 ±15V ±5V 1.75 1.75 ±5V 1.50 1.50 1.25 1.25 1.00 1.00 –40 –25 –10 520 35 50 65 80 95 110 125 –40 –25 –10 520 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. AD8510 Supply Current vs. Temperature Figure 15. AD8512 Supply Current per Amplifier vs. Temperature Rev. I | Page 8 of 20 SUPPLY CURRENT PER AMPLIFIER (mA) SUPPLY CURRENT PER AMPLIFIER (mA) OUTPUT VOLTAGE (V) 02729-014 02729-013 02729-015 GAIN (dB) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 02729-016 02729-018 PHASE (Degrees) 02729-017 AD8510/AD8512/AD8513 70 300 V = ±15V SY V = ±15V, ±5V 60 SY 270 V = 50mV IN 240 50 210 40 A = 100 V 180 30 150 20 A = 1 V A = 10 V 120 10 A = 100 90 V 0 A = 1 V 60 –10 A = 10 V 30 –20 0 –30 1k 100M 1k 10k 100k 50M 100 10k 100k 1M 10M 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. Closed-Loop Gain vs. Frequency Figure 22. Output Impedance vs. Frequency 1k 120 V = ±5V TO ±15V SY V = ±15V SY 100 100 80 60 40 10 20 1 0 1 10 100 1k 10k 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Voltage Noise Density vs. Frequency Figure 20. CMRR vs. Frequency 120 V = ±15V V = ±5V, ±15V SY SY 100 80 –PSRR 60 40 +PSRR 20 0 –20 100 1k 10k 100k 1M 10M 100M TIME (1s/DIV) FREQUENCY (Hz) Figure 21. PSRR vs. Frequency Figure 24. 0.1 Hz to 10 Hz Input Voltage Noise Rev. I | Page 9 of 20 PSRR (dB) CMRR (dB) CLOSED-LOOP GAIN (dB) 02729-020 02729-019 02729-021 OUTPUT IMPEDANCE (Ω) VOLTAGE (1µV/DIV) VOLTAGE NOISE DENSITY (nV/ Hz) 02729-024 02729-023 02729-022 AD8510/AD8512/AD8513 280 90 V = ±5V TO ±15V SY V = ±15V SY 80 R = 2kΩ 245 L 70 210 60 175 50 +OS 140 40 –OS 105 30 70 20 35 10 0 0 0 127 346 5 8 9 10 1 10 100 1k 10k LOAD CAPACITANCE (pF) FREQUENCY (Hz) Figure 25. Voltage Noise Density vs. Frequency Figure 28. Small-Signal Overshoot vs. Load Capacitance 70 315 V = ±5V V = ±15V SY SY 60 270 R = 2kΩ R = 2.5kΩ L L C = 100pF C = 20pF SCOPE L 50 Φ = 44.5° 225 A = 1 M V 40 180 30 135 20 90 10 45 0 0 –10 –45 –20 –90 –30 –135 10k 100k 1M 10M 50M TIME (1µs/DIV) FREQUENCY (Hz) Figure 26. Large-Signal Transient Response Figure 29. Open-Loop Gain and Phase vs. Frequency 120 V = ±5V SY V = ±15V SY R = 2kΩ L 100 C = 100pF L A = 1 V 80 60 40 20 0 100k 100 1k 10k 1M 10M 100M FREQUENCY (Hz) TIME (100ns/DIV) Figure 27. Small-Signal Transient Response Figure 30. CMRR vs. Frequency Rev. I | Page 10 of 20 VOLTAGE NOISE DENSITY (nV Hz) VOLTAGE (5V/DIV) VOLTAGE (50mV/DIV) 02729-027 02729-026 02729-025 OPEN-LOOP GAIN (dB) CMRR (dB) SMALL-SIGNAL OVERSHOOT (%) 02729-028 02729-030 PHASE (Degrees) 02729-029 AD8510/AD8512/AD8513 300 V = ±5V SY V = ±5V 270 V = 50mV SY IN R = 2kΩ L C = 100pF 240 L A = 1 V 210 180 A = 1 V 150 120 A = 100 V 90 60 A = 10 V 30 0 100 1k 10k 100k 1M 10M 100M TIME (100ns/DIV) FREQUENCY (Hz) Figure 31. Output Impedance vs. Frequency Figure 34. Small-Signal Transient Response 100 V = ±5V V = ±5V SY SY 90 R = 2kΩ L 80 70 60 +OS 50 –OS 40 30 20 10 0 1 10 100 1k 10k TIME (1s/DIV) LOAD CAPACITANCE (pF) Figure 32. 0.1 Hz to 10 Hz Input Voltage Noise Figure 35. Small-Signal Overshoot vs. Load Capacitance 100 V = ±15V S 90 V = ±5V SY R = 2kΩ L 80 C = 100pF L A = 1 V 70 60 50 40 30 20 10 0 0 125 34 6 T V (µV/°C) TIME (1µs/DIV) C OS Figure 33. Large-Signal Transient Response Figure 36. AD8513 T V Distribution C OS Rev. I | Page 11 of 20 OUTPUT IMPEDANCE (Ω) VOLTAGE (1µV/DIV) VOLTAGE (2V/DIV) 02729-033 02729-032 02729-031 NUMBER OF AMPLIFIERS SMALL-SIGNAL OVERSHOOT (%) VOLTAGE (50mV/DIV) 02729-034 02729-035 02729-036 AD8510/AD8512/AD8513 120 16 V = ±5V S V V = ±15V OL SY 14 100 V OH 12 80 10 60 8 6 40 V = ±5V V SY OL 4 V OH 20 2 0 0 0 125 34 6 0 10 20 30 40 50 60 70 80 T V (µV/°C) C OS LOAD CURRENT (mA) Figure 37. AD8513 T V Distribution C OS Figure 39. AD8513 Output Voltage vs. Load Current 3.0 2.5 T = 25°C A 2.4 2.5 ±15V 2.3 2.2 2.0 ±5V 2.1 1.5 2.0 1.9 1.0 1.8 1.7 0.5 1.6 0 1.5 –40 –25 –10 5 20 35 50 65 80 95 110 125 8 18 23 28 33 13 SUPPLY VOLTAGE (V+ – V–) TEMPERATURE (°C) Figure 38. AD8513 Supply Current per Amplifier vs. Supply Voltage Figure 40. AD8513 Supply Current per Amplifier vs. Temperature Rev. I | Page 12 of 20 SUPPLY CURRENT PER AMPLIFIER (mA) NUMBER OF AMPLIFIERS 02729-038 02729-037 SUPPLY CURRENT PER AMPLIFIER (mA) OUTPUT VOLTAGE (V) 02729-039 02729-040 AD8510/AD8512/AD8513 GENERAL APPLICATION INFORMATION 0.01 INPUT OVERVOLTAGE PROTECTION V = ±5V SY R = 100kΩ L The AD8510/AD8512/AD8513 have internal protective BW = 22kHz circuitry that allows voltages as high as 0.7 V beyond the supplies to be applied at the input of either terminal without causing damage. For higher input voltages, a series resistor is 0.001 necessary to limit the input current. The resistor value can be determined from the formula V − V IN S ≤ 5 mA R S With a very low offset current of <0.5 nA up to 125°C, higher 0.0001 resistor values can be used in series with the inputs. A 5 kΩ 20 100 1k 10k 20k FREQUENCY (Hz) resistor protects the inputs from voltages as high as 25 V Figure 42. THD + N vs. Frequency beyond the supplies and adds less than 10 μV to the offset. TOTAL NOISE INCLUDING SOURCE RESISTORS OUTPUT PHASE REVERSAL The low input current noise and input bias current of the Phase reversal is a change of polarity in the transfer function of AD8510/AD8512/AD8513 make them the ideal amplifiers for the amplifier. This can occur when the voltage applied at the circuits with substantial input source resistance. Input offset input of an amplifier exceeds the maximum common-mode voltage increases by less than 15 nV per 500 Ω of source voltage. resistance at room temperature. The total noise density of the Phase reversal can cause permanent damage to the device and circuit is can result in system lockups. The AD8510/AD8512/AD8513 do 2 2 not exhibit phase reversal when input voltages are beyond the e = e +(i R ) + 4kTR n n nTOTAL S S supplies. where: V = ±5V SY en is the input voltage noise density of the parts. A = 1 V R = 10kΩ L in is the input current noise density of the parts. R is the source resistance at the noninverting terminal. S V OUT –23 k is Boltzmann’s constant (1.38 × 10 J/K). T is the ambient temperature in Kelvin (T = 273 + °C). For RS < 3.9 kΩ, en dominates and enTOTAL ≈ en. The current noise V IN of the AD8510/AD8512/AD8513 is so low that its total density does not become a significant term unless RS is greater than 165 MΩ, an impractical value for most applications. The total equivalent rms noise over a specific bandwidth is expressed as TIME (20µs/DIV) e = e BW nTOTAL nTOTAL Figure 41. No Phase Reversal where BW is the bandwidth in hertz. TOTAL HARMONIC DISTORTION (THD) + NOISE Note that the previous analysis is valid for frequencies larger The AD8510/AD8512/AD8513 have low THD and excellent gain than 150 Hz and assumes flat noise above 10 kHz. For lower linearity, making these amplifiers great choices for precision frequencies, flicker noise (1/f) must be considered. circuits with high closed-loop gain and for audio application circuits. Figure 42 shows that the AD8510/AD8512/AD8513 have approximately 0.0005% of total distortion when configured in positive unity gain (the worst case) and driving a 100 kΩ load. Rev. I | Page 13 of 20 VOLTAGE (2V/DIV) 02729-057 DISTORTION (%) 02729-056 AD8510/AD8512/AD8513 SETTLING TIME V = ±15V SY A = –100 V Settling time is the time it takes the output of the amplifier to R = 10kΩ L +15V reach and remain within a percentage of its final value after a pulse is applied at the input. The AD8510/AD8512/AD8513 0V settle to within 0.01% in less than 900 ns with a step of 0 V to 10 V in unity gain. This makes each of these parts an excellent choice as a buffer at the output of DACs whose settling time is 0V typically less than 1 μs. –200mV In addition to the fast settling time and fast slew rate, low offset voltage drift and input offset current maintain the full accuracy of 12-bit converters over the entire operating temperature range. TIME (2µs/DIV) OVERLOAD RECOVERY TIME Figure 44. Negative Overload Recovery Overload recovery, also known as overdrive recovery, is the CAPACITIVE LOAD DRIVE time it takes the output of an amplifier to recover to its linear region from a saturated condition. This recovery time is par- The AD8510/AD8512/AD8513 are unconditionally stable at all ticularly important in applications where the amplifier must gains in inverting and noninverting configurations. Each device amplify small signals in the presence of large transient voltages. is capable of driving a capacitive load of up to 1000 pF without oscillation in unity gain using the worst-case configuration. Figure 43 shows the positive overload recovery of the AD8510/ AD8512/AD8513. The output recovers in approximately 200 ns However, as with most amplifiers, driving larger capacitive from a saturated condition. loads in a unity gain configuration may cause excessive overshoot and ringing, or even oscillation. A simple snubber V = ±15V SY network significantly reduces the amount of overshoot and V = 200mV IN 0V A = –100 V ringing. The advantage of this configuration is that the output R = 10kΩ L swing of the amplifier is not reduced, because R is outside the S –15V feedback loop. V+ 200mV 0V 2 7 V AD8510 6 OUT 4 3 200mV R S TIME (2µs/DIV) C C S L Figure 43. Positive Overload Recovery V– Figure 45. Snubber Network Configuration The negative overdrive recovery time shown in Figure 44 is less than 200 ns. In addition to the fast recovery time, the AD8510/AD8512/ AD8513 show excellent symmetry of the positive and negative recovery times. This is an important feature for transient signal rectification because the output signal is kept equally undistorted throughout any given period. Rev. I | Page 14 of 20 VOLTAGE INPUT OUTPUT 02729-053 VOLTAGE INPUT OUTPUT 02729-055 02729-054 AD8510/AD8512/AD8513 Figure 46 shows a scope plot of the output of the AD8510/AD8512/ OPEN-LOOP GAIN AND PHASE RESPONSE AD8513 in response to a 400 mV pulse. The circuit is configured in In addition to their impressive low noise, low offset voltage, and positive unity gain (worst case) with a load experience of 500 pF. offset current, the AD8510/AD8512/AD8513 have excellent loop gain and phase response even when driving large resistive V = ±15V SY C = 500pF L and capacitive loads. R =10kΩ L Compared with Competitor A (see Figure 49) under the same conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/ AD8513 have more than 8 MHz of bandwidth and a phase margin of more than 52°. Competitor A, on the other hand, has only 4.5 MHz of band- width and 28° of phase margin under the same test conditions. Even with a 1 nF capacitive load in parallel with the 2 kΩ load at the output, the AD8510/AD8512/AD8513 show much better response than Competitor A, whose phase margin is degraded to less than 0, indicating oscillation. TIME (1µs/DIV) 70 315 Figure 46. Capacitive Load Drive Without Snubber V = ±15V SY 60 R = 2.5kΩ 270 L When the snubber circuit is used, the overshoot is reduced from C = 0pF L 50 225 55% to less than 3% with the same load capacitance. Ringing is 40 180 virtually eliminated, as shown in Figure 47. 30 135 V = ±15V SY R = 10kΩ 20 L 90 C = 500pF L R = 100Ω 10 45 S C = 1nF S 0 0 –45 –10 –20 –90 –30 –135 10k 100k 1M 10M 50M FREQUENCY (Hz) Figure 48. Frequency Response of the AD8510/AD8512/AD8513 70 315 V = ±15V SY TIME (1µs/DIV) 60 R = 2.5kΩ 270 L C = 0pF L Figure 47. Capacitive Load with Snubber Network 225 50 Optimum values for RS and CS depend on the load capacitance 180 40 and input stray capacitance and are determined empirically. 30 135 Table 5 shows a few values that can be used as starting points. 20 90 Table 5. Optimum Values for Capacitive Loads 10 45 C R (Ω) C LOAD S S 0 0 500 pF 100 1 nF –45 –10 2 nF 70 100 pF –20 –90 5 nF 60 300 pF –135 –30 10k 100k 1M 10M 50M FREQUENCY (Hz) Figure 49. Frequency Response of Competitor A Rev. I | Page 15 of 20 VOLTAGE (200mV/DIV) VOLTAGE (200mV/DIV) 02729-042 02729-041 GAIN (dB) GAIN (dB) PHASE (Degrees) PHASE (Degrees) 02729-043 02729-044 AD8510/AD8512/AD8513 PRECISION RECTIFIERS Rectifying circuits are used in a multitude of applications. One of the most popular uses is in the design of regulated power supplies, where a rectifier circuit is used to convert an input sinusoid to a unipolar output voltage. However, there are some potential problems with amplifiers used in this manner. When the input voltage (V ) is negative, IN the output is zero, and the magnitude of VIN is doubled at the inputs of the op amp. If this voltage exceeds the power supply voltage, it may permanently damage some amplifiers. In addition, the op amp must come out of saturation when VIN is negative. This delays the output signal because the amplifier requires time to enter its linear region. TIME (1ms/DIV) Although the AD8510/AD8512/AD8513 have a very fast Figure 51. Half-Wave Rectifier Signal (OUT A in Figure 50) overdrive recovery time, which makes them great choices for the rectification of transient signals, the symmetry of the positive and negative recovery times is also important to keep the output signal undistorted. Figure 50 shows the test circuit of the rectifier. The first stage of the circuit is a half-wave rectifier. When the sine wave applied at the input is positive, the output follows the input response. During the negative cycle of the input, the output tries to swing negative to follow the input, but the power supply restrains it to zero. In a similar fashion, the second stage is a follower during the positive cycle of the sine wave and an inverter during the negative cycle. R2 R3 10kΩ 10kΩ TIME (1ms/DIV) Figure 52. Full-Wave Rectifier Signal (OUT B in Figure 50) 10V V IN 6 4 2/2 3V p-p 7 3 AD8512 8 1/2 OUT B R1 8 1 5 AD8512 (FULL WAVE) 1kΩ 4 2 10V OUT A (HALF WAVE) Figure 50. Half-Wave and Full-Wave Rectifiers Rev. I | Page 16 of 20 02729-045 VOLTAGE (1V/DIV) VOLTAGE (1V/DIV) 02729-047 02729-046 AD8510/AD8512/AD8513 A typical value for Rd is 1000 MΩ. Because Rd >> R2, the I-V CONVERSION APPLICATIONS circuit behavior is not impacted by the effect of the junction Photodiode Circuits resistance. The maximum signal bandwidth is Common applications for I-V conversion include photodiode circuits where the amplifier is used to convert a current emitted ft f = MAX by a diode placed at the positive input terminal into an output 2πR2Ct voltage. where ft is the unity gain frequency of the amplifier. The AD8510/AD8512/AD8513’s low input bias current, wide Cf can be calculated by bandwidth, and low noise make them each an excellent choice for various photodiode applications, including fax machines, Ct Cf= fiber optic controls, motion sensors, and bar code readers. 2πR2 ft The circuit shown in Figure 53 uses a silicon diode with zero where ft is the unity gain frequency of the op amp, and it achieves bias voltage. This is known as a photovoltaic mode; this a phase margin, φM, of approximately 45°. configuration limits the overall noise and is suitable for A higher phase margin can be obtained by increasing the value instrumentation applications. of Cf. Setting Cf to twice the previous value yields approximately Cf φ = 65° and a maximal flat frequency response, but it reduces the M maximum signal bandwidth by 50%. R2 Using the previous parameters with a Cf ≈ 1 pF, the signal V EE bandwidth is approximately 2.6 MHz. Signal Transmission Applications 4 2 One popular signal transmission method uses pulse-width 6 AD8510 modulation. High data rates may require a fast comparator 3 Rd Ct 7 rather than an op amp. However, the need for sharp, undistorted signals may favor using a linear amplifier. V CC The AD8510/AD8512/AD8513 make excellent voltage Figure 53. Equivalent Preamplifier Photodiode Circuit comparators. In addition to a high slew rate, the AD8510/ AD8512/AD8513 have a very fast saturation recovery time. In A larger signal bandwidth can be attained at the expense of the absence of feedback, the amplifiers are in open-loop mode additional output noise. The total input capacitance (Ct) (very high gain). In this mode of operation, they spend much of consists of the sum of the diode capacitance (typically 3 pF to their time in saturation. 4 pF) and the amplifier’s input capacitance (12 pF), which includes external parasitic capacitance. Ct creates a pole in the The circuit shown in Figure 54 was used to compare two signals frequency response that can lead to an unstable system. To of different frequencies, namely a 100 Hz sine wave and a 1 kHz ensure stability and optimize the bandwidth of the signal, a triangular wave. Figure 55 shows a scope plot of the resulting capacitor is placed in the feedback loop of the circuit shown in output waveforms. A pull-up resistor (typically 5 kΩ) can be Figure 53. It creates a zero and yields a bandwidth whose corner connected from the output to V if the output voltage needs to CC frequency is 1/(2π(R2Cf)). reach the positive rail. The trade-off is that power consumption is higher. The value of R2 can be determined by the ratio +15V V/I D where: 3 7 6 V is the desired output voltage of the op amp. V OUT ID is the diode current. 2 4 V1 For example, if ID is 100 μA and a 10 V output voltage is desired, R2 should be 100 kΩ. Rd (see Figure 53) is a junction resistance –15V V2 that drops typically by a factor of 2 for every 10°C increase in temperature. Figure 54. Pulse-Width Modulator Rev. I | Page 17 of 20 02729-048 02729-049 AD8510/AD8512/AD8513 The AD8510 single has two additional active terminals that are not present on the AD8512 dual or AD8513 quad parts. These pins are labeled “null” and are used for fine adjustment of the input offset voltage. Although the guaranteed maximum offset voltage at room temperature is 400 μV and over the −40°C to +125°C range is 800 mV maximum, this offset voltage can be reduced by adding a potentiometer to the null pins as shown in Figure 58. With the 20 kΩ potentiometer shown, the adjustment range is approximately ±3.5 mV. The potentiometer parallels low value resistors in the drain circuit of the JFET differential input pair and allows unbalancing of the drain currents to change the offset voltage. If offset adjustment is not required, TIME (2ms/DIV) these pins should be left unconnected. Caution should be used when adding adjusting potentiometers to Figure 55. Pulse-Width Modulation any op amp with this capability for several reasons. First, there is Crosstalk gain from these nodes to the output; therefore, capacitive coupling Crosstalk, also known as channel separation, is a measure of from noisy traces to these nodes will inject noise into the signal signal feedthrough from one channel to another on the same path. Second, the temperature coefficient of the potentiometer IC. The AD8512/AD8513 have a channel separation of better will not match the temperature coefficient of the internal resistors, than −90 dB for frequencies up to 10 kHz and of better than so the offset voltage drift with temperature will be slightly affected. −50 dB for frequencies up to 10 MHz. Figure 57 shows the Third, this provision is for adjusting the offset voltage of the typical channel separation behavior between Amplifier A op amp, not for adjusting the offset of the overall system. Although (driving amplifier) and each of the following: Amplifier B, it is tempting to decrease the value of the potentiometer to attain Amplifier C, and Amplifier D. more range, this will adversely affect the dc and ac parameters. V OUT Instead, increase the potentiometer to 50 kΩ to decrease the range if needed. 20kΩ 2.2kΩ 20kΩ +V S V+ 2 6 8 1 1 7 18V p-p 5 2 – 3 5 7 INPUT AD8510 6 OUTPUT 5kΩ 5kΩ 4 V IN + 3 –V V S OUT 4 CROSSTALK = 20 log V TRIM RANGE IS OS 10V IN TYPICALLY ±3.5mV Figure 56. Crosstalk Test Circuit V– 0 Figure 58. Optional Offset Nulling Circuit –20 –40 –60 CH B CH C CH D –80 –100 –120 –140 –160 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 57. Channel Separation Rev. I | Page 18 of 20 CHANNEL SEPARATION (dB) VOLTAGE (5V/DIV) 02729-050 02729-052 02729-051 02729-058 AD8510/AD8512/AD8513 OUTLINE DIMENSIONS 5.10 5.00 (0.1968) 5.00 4.80 (0.1890) 4.90 85 6.20 (0.2441) 14 8 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 4.50 6.40 4.40 BSC 4.30 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 1 7 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° PIN 1 0.10 (0.0040) 0° 1.05 0.65 0.51 (0.0201) COPLANARITY 1.27 (0.0500) BSC 1.00 0.10 0.31 (0.0122) 0.25 (0.0098) 0.20 SEATING 0.40 (0.0157) 1.20 0.80 0.17 (0.0067) PLANE 0.75 0.09 MAX 8° 0.60 0.15 0.30 0° COMPLIANT TO JEDEC STANDARDS MS-012-AA 0.45 SEATING 0.05 0.19 COPLANARITY PLANE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.10 (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 59. 8-Lead Standard Small Outline Package [SOIC_N] Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] Narrow Body (R-8) (RU-14) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters 3.20 3.00 2.80 8.75 (0.3445) 8 5 5.15 8.55 (0.3366) 3.20 4.90 3.00 4.65 14 8 6.20 (0.2441) 2.80 1 4.00 (0.1575) 4 1 3.80 (0.1496) 5.80 (0.2283) 7 PIN 1 1.27 (0.0500) 0.65 BSC 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.95 0.25 (0.0098) 1.35 (0.0531) 8° 0.85 1.10 MAX 0.10 (0.0039) 0° 0.75 COPLANARITY SEATING 0.80 1.27 (0.0500) 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 8° 0.15 0.38 0.60 0.40 (0.0157) 0.23 0.31 (0.0122) 0.17 (0.0067) 0° 0.00 0.22 0.40 0.08 SEATING COPLANARITY COMPLIANT TO JEDEC STANDARDS MS-012-AB PLANE 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR COMPLIANT TO JEDEC STANDARDS MO-187-AA REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 60. 8-Lead Mini Small Outline Package [MSOP] Figure 62. 14-Lead Standard Small Outline Package [SOIC_N] (RM-8) Narrow Body (R-14) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) Rev. I | Page 19 of 20 012407-A 060606-A AD8510/AD8512/AD8513 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD8510ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 B7A# 1 AD8510ARMZ −40°C to +125°C 8-Lead MSOP RM-8 B7A# AD8510AR −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8510ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8510ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8510ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8510BR −40°C to +125°C 8-Lead SOIC_N R-8 AD8510BR-REEL −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8510BRZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8510BRZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8510BRZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8512ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 B8A# 1 AD8512ARMZ −40°C to +125°C 8-Lead MSOP RM-8 B8A# AD8512AR −40°C to +125°C 8-Lead SOIC_N R-8 AD8512AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8512AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8512ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8512ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8512ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8512BR −40°C to +125°C 8-Lead SOIC_N R-8 AD8512BR-REEL −40°C to +125°C 8-Lead SOIC_N R-8 AD8512BR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8512BRZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8512BRZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8512BRZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 AD8513AR −40°C to +125°C 14-Lead SOIC_N R-14 AD8513AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14 AD8513AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 1 AD8513ARZ −40°C to +125°C 14-Lead SOIC_N R-14 1 AD8513ARZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14 1 AD8513ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 AD8513ARU −40°C to +125°C 14-Lead TSSOP RU-14 AD8513ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14 1 AD8513ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 1 AD8513ARUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02729-0-2/09(I) Rev. I | Page 20 of 20