ANALOG DEVICES AD8505

20 μA Maximum, Rail-to-Rail I/O, Zero Input Crossover Distortion Amplifiers AD8505/AD8506/AD8508 FEATURES PIN CONFIGURATIONS PSRR: 100 dB minimum BALL A1 INDICATOR CMRR: 105 dB typical OUT V+ Very low supply current: 20 μA per amplifier maximum A1 A2 1.8 V to 5 V single supply or ±0.9 V to ±2.5 V dual supply V– NC Rail-to-rail input/output B1 B2 Low noise: 45 nV/√Hz at 1 kHz +IN –IN 2.5 mV offset voltage maximum C1 C2 Very low input bias current: 1 pA typical OUT 1 5 V+ AD8505 APPLICATIONS AD8505 V– 2 TOP VIEW TOP VIEW (Not to Scale) Pressure and position sensors (BALL SIDE DOWN) +IN 3 4 –IN Not to Scale Remote security NC = NO CONNECT Bio sensors Figure 1. 5-Lead SOT-23 (RJ-5) Figure 2. 6-Ball WLCSP (CB-6-7) IR thermometers BALL A1 Battery-powered consumer equipment CORNER Hazard detectors OUT B V+ OUT A GENERAL DESCRIPTION A1 A2 A3 –IN B –IN A The AD8505/AD8506/AD8508 are single, dual, and quad micro- B1 B3 power amplifiers featuring rail-to-rail input/output swings while +IN B V– +IN A operating from a single 1.8 V to 5 V power supply or from dual C1 C2 C3 ±0.9 V to ±2.5 V power supplies. Using a new circuit technology, OUT A 1 8 V+ these amplifiers offer zero input crossover distortion (excellent AD8506 –IN A 2 7 OUT B AD8506 TOP VIEW PSRR and CMRR performance) and low bias current while +IN A 3 6 –IN B (Not to Scale) TOP VIEW (BALL SIDE DOWN) operating with a supply current of less than 20 μA per amplifier. V– 4 5 +IN B Not to Scale This amplifier family offers the lowest noise in its power class. Figure 3. 8-Lead MSOP (RM-8) Figure 4. 8-Ball WLCSP (CB-8-2) This combination of features makes the AD8505/AD8506/AD8508 BALL A1 CORNER amplifiers ideal choices for battery-powered applications because OUTD OUTA –INA they minimize errors due to power supply voltage variations over A1 A2 A3 the lifetime of the battery and maintain high CMRR even for a rail- –IND V– +INA B1 B2 B3 to-rail input op amp. Remote battery-powered sensors, handheld +IND +INB instrumentation, consumer equipment, hazard detection (for OUT A 1 14 OUT D C1 C3 example, smoke, fire, and gas), and patient monitors can benefit –IN A 2 13 –IN D +INC V+ –INB D1 D2 D3 from the features of the AD8505/AD8506/AD8508 amplifiers. +IN A 3 12 +IN D AD8508 –INC OUTC OUTB V+ 4 TOP VIEW 11 V– E1 E2 E3 The AD8505/AD8506/AD8508 are specified for both the industrial (Not to Scale) +IN B 5 10 +IN C temperature range of −40°C to +85°C and the extended industrial –IN B 6 9 –IN C AD8508 TOP VIEW temperature range of −40°C to +125°C. The AD8505 single ampli- OUT B 7 8 OUT C (BALL SIDE DOWN) Not to Scale fier is available in a tiny 5-lead SOT-23 and a 6-ball WLCSP Figure 5. 14-Lead TSSOP (RU-14) Figure 6. 14-Ball WLCSP (CB-14-1) packages. The AD8506 dual amplifier is available in 8-lead MSOP and 8-ball WLCSP packages. The AD8508 quad amplifier is available in 14-lead TSSOP and 14-ball WLCSP packages. The AD8505/AD8506/AD8508 are members of a growing series of zero crossover distortion op amps offered by Analog Devices, Inc., including the ADA4505-1/ADA4505-2/ADA4505-4, that operate from a single 1.8 V to 5 V supply or from dual ±0.9 V to ±2.5 V power supplies. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06900-051 06900-002 06900-045 06900-100 06900-001 06900-104 AD8505/AD8506/AD8508 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Pin Configurations ........................................................................... 1 Applications Information .............................................................. 15 Revision History ............................................................................... 2 Pulse Oximeter Current Source ............................................... 15 Specif ica t ions ..................................................................................... 3 Four-Pole, Low-Pass Butterworth Filter for Glucose Monitor ........................................................................................ 16 Electrical Characteristics—1.8 V Operation ............................ 3 Outline Dimensions ....................................................................... 17 Electrical Characteristics—5 V Operation................................ 4 Ordering Guide .......................................................................... 20 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 REVISION HISTORY Changes to Table 4 ............................................................................. 5 5/10—Rev. D to Rev. E Added AD8505, 6-Ball WLCSP Package ......................... Universal Changes to Figure 46 ...................................................................... 16 Changes to Large-Signal Voltage Gain Parameter (Table 1) ....... 4 Updated Outline Dimensions ....................................................... 17 Changes to Large-Signal Voltage Gain Parameter (Table 2) ....... 5 Added Figure 49 ............................................................................. 17 Changes to Table 4 ............................................................................ 6 Changes to Ordering Guide .......................................................... 18 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 21 7/08—Rev. 0 to Rev. A Added AD8508 ................................................................... Universal 10/09—Rev. C to Rev. D Added TSSOP Package ...................................................... Universal Added AD8505, 5-Lead SOT-23 Package ....................... Universal Changes to Features Section and General Description Section .. 1 Changes to General Description, Added Figure 1 ....................... 1 Added Figure 2; Renumbered Sequentially ................................... 1 Moved Electrical Characteristics—1.8 V Operation Section, Changed Electrical Characteristics Heading to Electrical Changes to Supply Current per Amplifier Parameter, Table 1 ..... 3 Characteristics—5 V Operation ...................................................... 3 Moved Electrical Characteristics—5 V Operation Section, Changes to Table 1 ............................................................................. 3 Changes to Supply Current per Amplifier Parameter, Table 2 ..... 4 Added Electrical Characteristics—1.8 V Operation Heading ..... 4 Changes to Table 2 ............................................................................. 4 Changes to Thermal Resistance Section and Table 4 ................... 5 Changes to Figure 20 and Figure 23 ............................................... 8 Changes to Table 3, Thermal Resistance Section, and Table 4 .... 5 Updated Outline Dimensions ....................................................... 16 Added TA = 25°C Condition to Typical Performance Changes to Ordering Guide .......................................................... 17 Characteristics Section ..................................................................... 6 Changes to Figure 3, Figure 4, Figure 6, and Figure 7 .................. 6 3/09—Rev. B to Rev. C Added Figure 11 and Figure 14 ....................................................... 7 Added AD8508, 14-Ball WLCSP Package ....................... Universal Changes to Figure 17 Through Figure 20....................................... 8 Updated Outline Dimensions ....................................................... 17 Changes to Figure 21 Through Figure 26....................................... 9 Changes to Ordering Guide .......................................................... 18 Changes to Figure 27, Figure 28, Figure 30, and Figure 31....... 10 Changes to Figure 34, Figure 37, and Figure 38 ......................... 11 10/08—Rev. A to Rev. B Added Figure 39 and Figure 40 .................................................... 12 Added WLCSP Package ..................................................... Universal Added Theory of Operation Section, Figure 41, and Added Figure 2; Renumbered Sequentially .................................. 1 Figure 42 .......................................................................................... 13 Added Input Resistance Parameter ................................................ 3 Added Figure 43 and Figure 44 .................................................... 14 Changes to Input Capacitance Differential Mode Parameter Added Applications Information Section and Figure 45 .......... 15 Symbol and Input Capacitance Common Mode Parameter Added Figure 46 ............................................................................. 16 Symbol ................................................................................................ 3 Updated Outline Dimensions ....................................................... 17 Added Input Resistance Parameter ................................................ 4 Added Figure 48 ............................................................................. 17 Changes to Input Capacitance Differential Mode Parameter Changes to Ordering Guide .......................................................... 17 Symbol and Input Capacitance Common Mode Parameter Symbol ................................................................................................ 4 11/07—Revision 0: Initial Version Rev. E | Page 2 of 20 AD8505/AD8506/AD8508 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—1.8 V OPERATION V = 1.8 V, V = V /2, T = 25°C, R = 100 kΩ to GND, unless otherwise noted. SY CM SY A L Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 0 V ≤ VCM ≤ 1.8 V 0.5 2.5 mV −40°C ≤ T ≤ +125°C 3.5 mV A Input Bias Current I 1 10 pA B −40°C ≤ TA ≤ +85°C 100 pA −40°C ≤ TA ≤ +125°C 600 pA Input Offset Current IOS 0.5 5 pA −40°C ≤ T ≤ +85°C 50 pA A −40°C ≤ T ≤ +125°C 100 pA A Input Voltage Range −40°C ≤ T ≤ +125°C 0 1.8 V A Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 1.8 V 85 100 dB −40°C ≤ TA ≤ +85°C 85 dB −40°C ≤ TA ≤ +125°C 80 dB Large-Signal Voltage Gain A 0.05 V ≤ V ≤ 1.75 V, 95 115 dB VO OUT R = 100 kΩ to V L CM −40°C ≤ TA ≤ +125°C 95 dB Offset Voltage Drift −40°C ≤ TA ≤ +125°C 2.5 μV/°C ΔVOS/ΔT Input Resistance R 220 GΩ IN Input Capacitance, Differential Mode C 3 pF INDM Input Capacitance, Common Mode C 4.2 pF INCM OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND 1.78 1.79 V OH L −40°C ≤ T ≤ +125°C 1.78 V A RL = 10 kΩ to GND 1.65 1.75 V −40°C ≤ TA ≤ +125°C 1.65 V Output Voltage Low VOL RL = 100 kΩ to VSY 2 5 mV −40°C ≤ T ≤ +125°C 5 mV A R = 10 kΩ to V 12 25 mV L SY −40°C ≤ TA ≤ +125°C 25 mV Short-Circuit Limit ISC VOUT = VSY or GND ±4.5 mA POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = 1.8 V to 5 V 100 110 dB −40°C ≤ TA ≤ +85°C 100 dB −40°C ≤ TA ≤ +125°C 95 dB Supply Current per Amplifier I SY AD8506/AD8508 V = V/2 16.5 20 μA OUT SY −40°C ≤ T ≤ +125°C 25 μA A AD8505 VOUT = VSY/2 16.5 24 μA −40°C ≤ TA ≤ +125°C 27.5 μA DYNAMIC PERFORMANCE Slew Rate SR RL = 100 kΩ, CL = 10 pF, G = 1 13 mV/μs Gain Bandwidth Product GBP RL = 1 MΩ, CL = 20 pF, G = 1 95 kHz Phase Margin ΦM RL = 1 MΩ, CL = 20 pF, G = 1 60 Degrees NOISE PERFORMANCE Voltage Noise en p-p f = 0.1 Hz to 10 Hz 2.8 μV p-p Voltage Noise Density en f = 1 kHz 45 nV/√Hz Current Noise Density i f = 1 kHz 15 fA/√Hz n Rev. E | Page 3 of 20 AD8505/AD8506/AD8508 ELECTRICAL CHARACTERISTICS—5 V OPERATION VSY = 5 V, VCM = VSY/2, TA = 25°C, RL = 100 kΩ to GND, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 0 V ≤ VCM ≤ 5 V 0.5 2.5 mV −40°C ≤ TA ≤ +125°C 3.5 mV Input Bias Current IB 1 10 pA −40°C ≤ T ≤ +85°C 100 pA A −40°C ≤ T ≤ +125°C 600 pA A Input Offset Current IOS 0.5 5 pA −40°C ≤ TA ≤ +85°C 50 pA −40°C ≤ TA ≤ +125°C 130 pA Input Voltage Range −40°C ≤ T ≤ +125°C 0 5 V A Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 5 V 90 105 dB CM −40°C ≤ T ≤ +85°C 90 dB A −40°C ≤ TA ≤ +125°C 85 dB Large-Signal Voltage Gain AVO 0.05 V ≤ VOUT ≤ 4.95 V, 105 120 dB R = 100 kΩ to V L CM −40°C ≤ T ≤ +125°C 100 dB A Offset Voltage Drift −40°C ≤ T ≤ +125°C 2 μV/°C ΔV /ΔT A OS Input Resistance RIN 220 GΩ Input Capacitance, Differential Mode CINDM 3 pF Input Capacitance, Common Mode CINCM 4.2 pF OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 100 kΩ to GND 4.98 4.99 V −40°C ≤ T ≤ +125°C 4.98 V A R = 10 kΩ to GND 4.9 4.95 V L −40°C ≤ T ≤ +125°C 4.9 V A Output Voltage Low VOL RL = 100 kΩ to VSY 2 5 mV −40°C ≤ TA ≤ +125°C 5 mV RL = 10 kΩ to VSY 10 25 mV −40°C ≤ T ≤ +125°C 30 mV A Short-Circuit Limit I V = V or GND ±45 mA SC OUT SY POWER SUPPLY Power Supply Rejection Ratio PSRR V = 1.8 V to 5 V 100 110 dB SY −40°C ≤ T ≤ +85°C 100 dB A −40°C ≤ T ≤ +125°C 95 dB A Supply Current per Amplifier ISY AD8506/AD8508 VOUT = VSY/2 15 20 μA −40°C ≤ T ≤ +125°C 25 μA A AD8505 −40°C ≤ T ≤ +125°C 25.5 μA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 10 pF, G = 1 13 mV/μs L L Gain Bandwidth Product GBP R = 1 MΩ, C = 20 pF, G = 1 95 kHz L L Phase Margin Φ R = 1 MΩ, C = 20 pF, G = 1 60 Degrees M L L NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz 2.8 μV p-p n Voltage Noise Density e f = 1 kHz 45 nV/√Hz n Current Noise Density in f = 1 kHz 15 fA/√Hz Rev. E | Page 4 of 20 AD8505/AD8506/AD8508 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages with its Supply Voltage 5.5 V exposed paddle soldered to a pad, if applicable. Table 4 shows Input Voltage ±V ± 0.1 V SY 1 Input Current ±10 mA simulated thermal values for a 4-layer (2S2P) JEDEC standard 2 thermal test board, unless otherwise specified. Differential Input Voltage ±VSY Output Short-Circuit Duration to GND Indefinite Table 4. Storage Temperature Range −65°C to +150°C Package Type θJA θJC Unit Operating Temperature Range −40°C to +125°C 5-Lead SOT-23 (RJ-5) 190 92 °C/W Junction Temperature Range −65°C to +150°C 6-Ball WLCSP (CB-6-7) 105 N/A °C/W Lead Temperature (Soldering, 60 sec) 300°C 8-Lead MSOP (RM-8) 142 45 °C/W 1 Input pins have clamp diodes to the supply pins. The input current should 8-Ball WLCSP (CB-8-2) 82 N/A °C/W be limited to 10 mA or less whenever the input signal exceeds the power 14-Lead TSSOP (RU-14) 112 35 °C/W supply rail by 0.5 V. 2 The differential input voltage is limited to 5 V or the supply voltage, whichever 14-Ball WLCSP (CB-14-1) 64 N/A °C/W is less. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. E | Page 5 of 20 AD8505/AD8506/AD8508 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 250 250 V = 1.8V SY V = 5V SY V = V /2 CM SY V = V /2 CM SY 200 200 150 150 100 100 50 50 0 0 –4 –3 –2 –1 0 1 2 3 4 –4 –3 –2 –1 0 1 2 3 4 V (mV) V (mV) OS OS Figure 7. Input Offset Voltage Distribution Figure 10. Input Offset Voltage Distribution 16 12 V = 1.8V V = 5V SY SY –40°C ≤ T ≤ +125°C –40°C ≤ T ≤ +125°C A A 14 10 12 8 10 8 6 6 4 4 2 2 0 0 012 34 567 89 10 11 12 13 012 34 567 89 10 11 12 13 TCV (µV/°C) TCV (µV/°C) OS OS Figure 8. Input Offset Voltage Drift Distribution Figure 11. Input Offset Voltage Drift Distribution 2000 2000 V = 1.8V SY V = 5V SY 1500 1500 1000 1000 500 500 0 0 –500 –500 –1000 –1000 –1500 –1500 –2000 –2000 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0123 45 V (V) V (V) CM CM Figure 9. Input Offset Voltage vs. Input Common-Mode Voltage Figure 12. Input Offset Voltage vs. Input Common-Mode Voltage Rev. E | Page 6 of 20 V (µV) OS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 06900-004 06900-003 06900-005 V (µV) OS NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 06900-007 06900-006 06900-008 AD8505/AD8506/AD8508 T = 25°C, unless otherwise noted. A –115 –120 V = 1.8V V = 5V SY SY –125 –120 –130 –125 –135 –130 –140 –135 –145 –140 –150 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 05 1 2 3 4 V (V) V (V) CM CM Figure 13. Input Offset Voltage vs. Input Common-Mode Voltage Figure 16. Input Offset Voltage vs. Input Common-Mode Voltage 600 600 V = 1.8V V = 5V SY SY 550 550 500 500 450 450 400 400 350 350 300 300 250 250 200 200 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V (V) V (V) CM CM Figure 14. Input Bias Current vs. Input Common-Mode Voltage at 125°C Figure 17. Input Bias Current vs. Input Common-Mode Voltage at 125°C 1000 1000 V = 1.8V SY V = 5V SY V = V /2 CM SY V = V /2 CM SY 100 100 10 10 1 1 0.1 0.1 0.01 0.01 25 35 45 55 65 75 85 95 105 115 125 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Input Bias Current vs. Temperature Figure 18. Input Bias Current vs. Temperature Rev. E | Page 7 of 20 V (µV) OS I (pA) I (pA) B B 06900-018 06900-009 06900-037 I (pA) V (µV) I (pA) B OS B 06900-019 06900-012 06900-038 AD8505/AD8506/AD8508 T = 25°C, unless otherwise noted. A 10k 10k V = 1.8V V = 5V SY SY 1k 1k V – V DD OH 100 100 V OL 10 V OL V – V DD OH 10 1 1 0.1 0.1 0.01 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 100 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 19. Output Voltage to Supply Rail vs. Load Current Figure 22. Output Voltage to Supply Rail vs. Load Current 14 14 V = 1.8V V = 5V SY SY 12 12 V – V @ R = 10kΩ V – V @ R = 10kΩ DD OH L DD OH L 10 10 8 8 V @ R = 10kΩ V @ R = 10kΩ OL L OL L 6 6 4 4 V – V @ R = 100kΩ DD OH L V – V @ R = 100kΩ DD OH L 2 2 V @ R = 100kΩ V @ R = 100kΩ OL L OL L 0 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 20. Output Voltage to Supply Rail vs. Temperature Figure 23. Output Voltage to Supply Rail vs. Temperature 90 90 AD8508 V = V /2 V = V /2 CM SY CM SY AD8506 80 80 AD8505 70 70 60 60 AD8508, 1.8V AD8508, 5V 50 50 AD8506, 1.8V AD8606, 5V AD8505, 1.8V 40 40 AD8505, 5V 30 30 20 20 10 10 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 21. Total Supply Current vs. Supply Voltage Figure 24. Total Supply Current vs. Temperature Rev. E | Page 8 of 20 TOTAL SUPPLY CURRENT (µA) OUTPUT VOLTAGE TO SUPPLY RAIL (mV) OUTPUT VOLTAGE TO SUPPLY RAIL (mV) 06900-011 06900-010 06900-052 TOTAL SUPPLY CURRENT (µA) OUTPUT VOLTAGE TO SUPPLY RAIL (mV) OUTPUT VOLTAGE TO SUPPLY RAIL (mV) 06900-014 06900-013 06900-053 AD8505/AD8506/AD8508 T = 25°C, unless otherwise noted. A 120 120 120 120 V = 1.8V V = 5V SY SY 100 PHASE 100 100 100 PHASE 80 80 80 80 60 60 60 60 40 40 GAIN 40 40 GAIN 20 20 20 20 0 0 0 0 –20 –20 –20 –20 GAIN, C = 0pF GAIN, C = 0pF –40 L –40 L PHASE, C = 0pF PHASE, C = 0pF L –40 L –40 –60 –60 GAIN, C = 50pF GAIN, C = 50pF L L PHASE, C = 50pF –60 PHASE, C = 50pF –60 –80 L –80 L GAIN, C = 100pF GAIN, C = 100pF L L –80 –80 –100 –100 PHASE, C = 100pF PHASE, C = 100pF L L –120 –120 –100 –100 100 1k 10k 100k 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 25. Open-Loop Gain and Phase vs. Frequency Figure 28. Open-Loop Gain and Phase vs. Frequency 50 50 V = 5V V = 1.8V SY SY G= –100 G= –100 40 40 30 30 G= –10 G= –10 20 20 10 10 G= –1 G= –1 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 100 1k 10k 100k 1M 1k 10k 100k 100 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. Closed-Loop Gain vs. Frequency Figure 29. Closed-Loop Gain vs. Frequency 10k 10k V = 5V V = 1.8V SY SY 1k 1k G = 100 G = 100 G = 10 G = 1 100 G = 10 G = 1 100 10 10 1 1 0.1 0.1 0.01 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 27. Z vs. Frequency Figure 30. ZOUT vs. Frequency OUT Rev. E | Page 9 of 20 OPEN-LOOP GAIN (dB) Z (Ω) CLOSED-LOOP GAIN (dB) OUT 06900-028 06900-017 PHASE (Degrees) 06900-022 OPEN-LOOP GAIN (dB) Z (Ω) OUT CLOSED-LOOP GAIN (dB) 06900-031 06900-020 PHASE (Degrees) 06900-025 AD8505/AD8506/AD8508 T = 25°C, unless otherwise noted. A 100 100 V = 1.8V V = 5V SY SY 90 90 80 80 70 70 60 60 50 50 40 40 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 31. CMRR vs. Frequency Figure 34. CMRR vs. Frequency 100 100 V = 5V V = 1.8V SY SY 90 90 80 80 70 70 60 60 50 50 40 40 30 30 PSRR+ 20 PSRR+ 20 10 10 PSRR– PSRR– 0 0 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 32. PSRR vs. Frequency Figure 35. PSRR vs. Frequency 80 80 V = 1.8V V = 5V SY SY R = 100kΩ R = 100kΩ L L 70 70 60 60 50 50 40 40 30 30 –OVERSHOOT –OVERSHOOT 20 20 +OVERSHOOT +OVERSHOOT 10 10 0 0 10 100 600 10 100 600 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 36. Small-Signal Overshoot vs. Load Capacitance Figure 33. Small-Signal Overshoot vs. Load Capacitance Rev. E | Page 10 of 20 PSRR (dB) OVERSHOOT (%) CMRR (dB) 06900-029 06900-027 06900-023 PSRR (dB) OVERSHOOT (%) CMRR (dB) 06900-030 06900-032 06900-026 AD8505/AD8506/AD8508 T = 25°C, unless otherwise noted. A V = 1.8V V = 5V SY SY R = 100kΩ R = 100kΩ L L C = 200pF C = 200pF L L G = 1 G = 1 TIME (100µs/DIV) TIME (100µs/DIV) Figure 37. Large-Signal Transient Response Figure 40. Large-Signal Transient Response V = 1.8V V = 5V SY SY R = 100kΩ R = 100kΩ L L C = 200pF C = 200pF L L G = 1 G = 1 TIME (100µs/DIV) TIME (100µs/DIV) Figure 38. Small-Signal Transient Response Figure 41. Small-Signal Transient Response 1k V = 1.8V AND 5V SY V = 1.8V AND 5V SY 2.78µV p-p 100 10 1 TIME (4s/DIV) 1 10 100 1k 10k FREQUENCY (Hz) Figure 42. Voltage Noise Density vs. Frequency Figure 39. Input Voltage Noise 0.1 Hz to 10 Hz Rev. E | Page 11 of 20 INPUT VOLTAGE NOISE (0.5µV/DIV) VOLTAGE (5mV/DIV) VOLTAGE (500mV/DIV) 06900-034 06900-036 06900-033 VOLTAGE NOISE DENSITY (nV/√Hz) VOLTAGE (5mV/DIV) VOLTAGE (1V/DIV) 06900-046 06900-035 06900-047 AD8505/AD8506/AD8508 T = 25°C, unless otherwise noted. A –40 –40 V = 1.8V V = 5V 100kΩ SY SY 100kΩ V = 1.5V p-p V = 4V p-p IN IN –50 –50 10kΩ 10kΩ –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 100 1k 10k 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 43. Channel Separation vs. Frequency Figure 44. Channel Separation vs. Frequency Rev. E | Page 12 of 20 CHANNEL SEPARATION (dB) 06900-049 CHANNEL SEPARATION (dB) 06900-048 AD8505/AD8506/AD8508 THEORY OF OPERATION V DD The AD8505/AD8506/AD8508 are unity-gain, stable, CMOS, rail- to-rail input/output operational amplifiers designed to optimize performance in current consumption, PSRR, CMRR, and zero V BIAS crossover distortion, all embedded in a small package. The typical offset voltage is 500 μV, with a low peak-to-peak voltage noise of 2.8 μV from 0.1 Hz to 10 Hz and a voltage noise density of 45 nV/√Hz at 1 kHz. V V IN+ IN– Q3 Q1 Q2 Q4 The AD8505/AD8506/AD8508 amplifiers are designed to solve I I B two key problems in low voltage battery-powered applications: B the battery voltage decrease over time and the rail-to-rail input stage distortion. V SS In battery-powered applications, the supply voltage available to Figure 45. A Typical Dual Differential Pair Input Stage Op Amp the IC is the voltage of the battery. Unfortunately, the voltage of (Dual PMOS Q1 and Q2 Transistors Form the Lower End of the Input Voltage a battery decreases as it discharges itself through the load. This Range, Whereas Dual NMOS Q3 and Q4 Compose the Upper End) voltage drop over the lifetime of the battery causes an error in 300 the output of the op amps. Some applications requiring precision V = 5V SY 250 T = 25°C A measurements during the entire lifetime of the battery use voltage 200 regulators to power up the op amps as a solution. If a design 150 uses standard battery cells, the op amps experience a supply 100 voltage change from roughly 3.2 V to 1.8 V during the lifetime 50 of the battery. This means that for a PSRR of 70 dB minimum in 0 a typical op amp, the input-referred offset error is approximately –50 440 μV. If the same application uses the AD8505/AD8506/ –100 AD8508 amplifiers with a 100 dB minimum PSRR, the error is –150 only 14 μV. It is possible to calibrate out this error or to use an –200 external voltage regulator to power the op amp, but these solutions –250 can increase system cost and complexity. The AD8505/AD8506/ –300 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 AD8508 amplifiers solve the impasse with no additional cost or V (V) CM error-nullifying circuitry. Figure 46. Typical Input Offset Voltage vs. Common-Mode Voltage The second problem with battery-powered applications is the Response in a Dual Differential Pair Input Stage Op Amp (Powered by 5 V Supply; Results of Approximately 100 Units per Graph Are Displayed) distortion caused by the standard rail-to-rail input stage. Using a CMOS non-rail-to-rail input stage (that is, a single differential This distortion forces the designer to devise impractical ways pair) limits the input voltage to approximately one VGS (gate- to avoid the crossover distortion areas, therefore narrowing the source voltage) away from one of the supply lines. Because VGS common-mode dynamic range of the operational amplifier. The for normal operation is commonly over 1 V, a single differential AD8505/AD8506/AD8508 amplifiers solve this crossover dis- pair input stage op amp greatly restricts the allowable input tortion problem by using an on-chip charge pump to power the voltage range when using a low supply voltage. This limitation input differential pair. The charge pump creates a supply voltage restricts the number of applications where the non-rail-to-rail higher than the voltage of the battery, allowing the input stage to input op amp was originally intended to be used. To solve this handle a wide range of input signal voltages without using a second problem, a dual differential pair input stage is usually implemented differential pair. With this solution, the input voltage can vary from (see Figure 45); however, this technique has its own drawbacks. one supply extreme to the other with no distortion, thereby restoring the full common-mode dynamic range of the op amp. One differential pair amplifies the input signal when the common- mode voltage is on the high end, whereas the other pair amplifies the input signal when the common-mode voltage is on the low end. This method also requires control circuitry to operate the two differential pairs appropriately. Unfortunately, this topology leads to a very noticeable and undesirable problem: if the signal level moves through the range where one input stage turns off and the other one turns on, noticeable distortion occurs (see Figure 46). Rev. E | Page 13 of 20 V (µV) OS 06900-040 06900-039 AD8505/AD8506/AD8508 The charge pump has been carefully designed so that switching Figure 48, the input offset voltage vs. input common-mode voltage noise components at any frequency, both within and beyond the response, shows the typical response of 12 devices. Figure 48 is amplifier bandwidth, are much lower than the thermal noise floor. expanded to make it easier to compare with Figure 46, the typical Therefore, the spurious-free dynamic range (SFDR) is limited only input offset voltage vs. common-mode voltage response in a by the input signal and the thermal or flicker noise. There is no dual differential pair input stage op amp. intermodulation between the input signal and the switching noise. 300 250 Figure 47 displays a typical front-end section of an operational V = 5V, T = 25°C SY A 200 amplifier with an on-chip charge pump. 150 V = POSITIVE PUMPED VOLTAGE = V + 1.8V PP DD 100 V PP V DD 50 V BIAS 0 –50 CASCODE –100 STAGE Q1 Q2 –IN +IN AND –150 RAIL-TO-RAIL OUT OUTPUT –200 STAGE –250 –300 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V (V) CM V SS Figure 48. Input Offset Voltage vs. Input Common-Mode Voltage Response Figure 47. Typical Front-End Section of an Op Amp (Powered by a 5 V Supply; Results of 12 Units Are Displayed) with Embedded Charge Pump This solution improves the CMRR performance tremendously. For instance, if the input varies from rail to rail on a 2.5 V supply rail, using a part with a CMRR of 70 dB minimum, an input-referred error of 790 μV is introduced. Another part with a CMRR of 52 dB minimum generates a 6.3 mV error. The AD8505/AD8506/AD8508 CMRR of 90 dB minimum causes only a 79 μV error. As with the PSRR error, there are complex ways to minimize this error, but the AD8505/AD8506/AD8508 amplifiers solve this problem without incurring unnecessary circuitry complexity or increased cost. Rev. E | Page 14 of 20 06900-041 V (µV) OS 06900-042 AD8505/AD8506/AD8508 APPLICATIONS INFORMATION drift of the total design need to be improved, then a more accurate PULSE OXIMETER CURRENT SOURCE and low temperature coefficient drift voltage reference and current A pulse oximeter is a noninvasive medical device used for con- source resistor should be utilized. C3 and C4 are used to improve tinuously measuring the percentage of hemoglobin (Hb) saturated stabilization of U1; R3 and R7 are used to provide some current with oxygen and the pulse rate of a patient. Hemoglobin that is limit into the U1 inverting pin; and R2 and R6 are used to slow carrying oxygen (oxyhemoglobin) absorbs light in the infrared down the rise time of the N-MOSFET when it turns on. These (IR) region of the spectrum; hemoglobin that is not carrying elements may not be needed, or some bench adjustments may oxygen (deoxyhemoglobin) absorbs visible red (R) light. In be required. pulse oximetry, a clip containing two LEDs (sometimes more, +5V depending on the complexity of the measurement algorithm) and C2 CONNECT TO RED LED the light sensor (photodiode) is placed on the finger or earlobe 0.1µF +5V U2 of the patient. One LED emits red light (600 nm to 700 nm) and C1 U1 ADG733 0.1µF 16 the other emits light in the near IR (800 nm to 900 nm) region. 1/2 +5V 62.5mA AD8506 V DD The clip is connected by a cable to a processor unit. The LEDs S1A 12 R4 are rapidly and sequentially excited by two current sources (one 8 14 D1 R2 V 5 53.6kΩ OUT1 S1B 13 22Ω V+ for each LED), whose dc levels depend on the LED being driven, 7 V = 1.25V REF V– S2A 2 based on manufacturer requirements, and the detector is synchro- 6 Q1 U3 4 15 D2 IRLMS2002 ADR1581 nized to capture the light from each LED as it is transmitted S2B 1 C3 22pF through the tissue. S3A 5 R3 4 D3 1kΩ An example design of a dc current source driving the red and S3B 3 R1 RED CURRENT 9 infrared LEDs is shown in Figure 49. These dc current sources 20Ω A2 SOURCE 10 0.1% A1 allow 62.5 mA and 101 mA to flow through the red and infrared 1/4W MIN 11 8 A0 GND LEDs, respectively. First, to prolong battery life, the LEDs are 6 EN driven only when needed. One-third of the ADG733 SPDT V SS analog switch is used to disconnect or connect the 1.25 V voltage CONNECT TO INFRARED LED 7 reference from or to each current circuit. When driving the LEDs, +5V U1 the ADR1581 1.25 V voltage reference is buffered by half of the 101mA 1/2 AD8506; the presence of this voltage on the noninverting input AD8506 8 R6 I_BIT2 forces the output of the op amp (due to the negative feedback) 3 V OUT2 22Ω V+ I_BIT1 1 I_BIT0 to maintain a level that causes its inverting input to track the V– I_ENA 2 Q2 noninverting pin. Therefore, the 1.25 V appears in parallel with 4 IRLMS2002 C4 the 20 Ω R1 or 12.4 Ω R5 current source resistor, creating the flow 22pF of 62.5 mA or 101 mA current through the red or infrared LED R7 1kΩ as the output of the op amp turns on the Q1 or Q2 N-MOSFET R5 INFRARED CURRENT IRLMS2002. 12.4Ω SOURCE 0.1% The maximum total quiescent currents for the AD8506 (that is, 1/2W MIN half of the AD8506), ADR1581, and ADG733 are 25 μA, 70 μA, Figure 49. Pulse Oximeter Red and Infrared Current Sources Using the and 1 μA, respectively, resulting in a total of 96 μA current con- AD8506 as a Buffer to the Voltage Reference Device sumption (480 μW power consumption) per circuit, which is good for a system powered by a battery. If the accuracy and temperature Rev. E | Page 15 of 20 06900-043 AD8505/AD8506/AD8508 the I-to-V converter requires low input bias current. The FOUR-POLE, LOW-PASS BUTTERWORTH FILTER AD8505/AD8506/AD8508 are excellent choices because these FOR GLUCOSE MONITOR amplifiers provide 1 pA typical and 10 pA maximum of input There are several methods of glucose monitoring: spectroscopic bias current at ambient temperature. absorption of infrared light in the 2 μm to 2.5 μm range, reflec- A low-pass filter with a cutoff frequency of 80 Hz to 100 Hz is tance spectrophotometry, and the amperometric type using desirable in a glucose meter device to remove extraneous noise; electrochemical strips with glucose oxidase enzymes. The this can be a simple two-pole or four-pole Butterworth filter. Low amperometric type generally uses three electrodes: a reference power op amps with bandwidths of 50 kHz to 500 kHz should electrode, a control electrode, and a working electrode. Although be adequate. The AD8505/AD8506/AD8508 amplifiers with their this is a well established and widely used technique, signal-to-noise 95 kHz GBP and 15 μA typical current consumption meet these ratio and repeatability can be improved using the AD8505/ requirements. A circuit design of a four-pole Butterworth filter AD8506/AD8508 amplifiers with their low peak-to-peak voltage (preceded by a one-pole, low-pass filter) is shown in Figure 50. noise of 2.8 μV from 0.1 Hz to 10 Hz and voltage noise density With a 3.3 V battery, the total power consumption of this design of 45 nV/√Hz at 1 kHz. is 297 μW typical at ambient temperature. Another consideration is operation from a 3.3 V battery. Glucose signal currents are usually less than 3 μA full scale; therefore, C1 1000pF R1 5MΩ +3.3V WORKING +3.3V U1 1/2 8 CONTROL 3 R2 R3 AD8506 +3.3V U2 V+ 22.6kΩ 22.6kΩ 1/2 1 5 8 R4 R5 AD8506 V– C3 V+ 22.6kΩ 22.6kΩ REFERENCE 8 2 U1 0.047µF 7 3 4 1/2 V– C5 V+ AD8506 6 0.047µF 1 V 4 OUT V– C2 2 4 0.1µF C4 0.1µF DUPLICATE OF CIRCUIT ABOVE Figure 50. A Four-Pole Butterworth Filter That Can Be Used in a Glucose Meter Rev. E | Page 16 of 20 06900-044 AD8505/AD8506/AD8508 OUTLINE DIMENSIONS 3.00 2.90 2.80 5 4 3.00 1.70 2.80 1.60 2.60 1.50 12 3 0.95 BSC 1.90 BSC 1.30 1.15 0.90 0.20 MAX 1.45 MAX 0.08 MIN 0.95 MIN 0.55 0.15 MAX 10° 0.45 SEATING 0.20 0.05 MIN 5° 0.50 MAX 0.35 PLANE BSC 0° 0.35 MIN COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 51. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 0.645 0.600 0.945 0.415 0.555 0.905 0.400 SEATING 0.865 0.385 PLANE 2 1 A 0.287 BALL A1 1.425 0.80 0.267 IDENTIFIER BSC 1.385 0.247 B 1.345 0.40 BSC C TOP VIEW 0.05 NOM 0.40 BSC (BALL SIDE DOWN) 0.230 COPLANARITY BOTTOM VIEW 0.200 (BALL SIDE UP) 0.170 Figure 52. 6-Ball Wafer Level Chip Scale Package [WLCSP] (CB-6-7) Dimensions shown in millimeters Rev. E | Page 17 of 20 121608-A 081709-A AD8505/AD8506/AD8508 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 53. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 0.650 0.595 1.460 0.540 1.420 SQ SEATING 1.380 3 2 1 PLANE 0.340 A BALL 1 0.320 IDENTIFIER 0.300 B 0.50 C BALL PITCH TOP VIEW BOTTOM VIEW 0.380 (BALL SIDE UP) 0.355 0.270 0.330 0.240 0.210 COPLANARITY 0.075 Figure 54. 8-Ball Wafer Level Chip Scale Package [WLCSP] (CB-8-2) Dimensions shown in millimeters Rev. E | Page 18 of 20 100709-B 011008-B AD8505/AD8506/AD8508 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 55. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 0.650 0.25 0.595 1.50 BSC 0.25 0.540 BSC 1.46 0.25 0.25 1.42 BSC SEATING BSC 3 2 1 PLANE A BALL 1 0.50 BSC IDENTIFIER B 3.00 0.50 BSC 2.96 2.00 0.340 C BSC 2.92 0.320 0.50 BSC 0.300 D E 0.50 BSC TOP VIEW BOTTOM VIEW 0.10 MAX 0.380 (BALL SIDE UP) (BALL SIDE DOWN) COPLANARITY 0.355 1.00 0.270 0.330 BSC 0.240 0.210 Figure 56. 14-Ball Wafer Level Chip Scale Package [WLCSP] (CB-14-1) Dimensions shown in millimeters Rev. E | Page 19 of 20 061908-A 061208-A AD8505/AD8506/AD8508 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8505ARJZ-R2 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A2E AD8505ARJZ-R7 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A2E AD8505ARJZ-RL −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A2E AD8505ACBZ-R7 −40°C to +125°C 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-7 A2H AD8505ACBZ-RL −40°C to +125°C 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-7 A2H AD8506ACBZ-REEL −40°C to +125°C 8-Ball Wafer Level Chip Scale Package [WLCSP] CB-8-2 A1X AD8506ACBZ-REEL7 −40°C to +125°C 8-Ball Wafer Level Chip Scale Package [WLCSP] CB-8-2 A1X AD8506ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1X AD8506ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1X AD8506ARMZ-REEL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1X AD8508ARUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 AD8508ARUZ-REEL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 AD8508ACBZ-REEL −40°C to +125°C 14-Ball Wafer Level Chip Scale Package [WLCSP] CB-14-1 A27 AD8508ACBZ-REEL7 −40°C to +125°C 14-Ball Wafer Level Chip Scale Package [WLCSP] CB-14-1 A27 1 Z = RoHS Compliant Part. ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06900-0-5/10(E) Rev. E | Page 20 of 20