ANALOG DEVICES AD847

High Speed, Low Power a Monolithic Op Amp AD847 FEATURES CONNECTION DIAGRAM Superior Performance Plastic DIP (N), High Unity Gain BW: 50 MHz Small Outline (R) and Low Supply Current: 5.3 mA Cerdip (Q) Packages High Slew Rate: 300 V/ms Excellent Video Specifications 0.04% Differential Gain (NTSC and PAL) 0.198 Differential Phase (NTSC and PAL) Drives Any Capacitive Load Fast Settling Time to 0.1% (10 V Step): 65 ns Excellent DC Performance High Open-Loop Gain 5.5 V/mV (R = 1 kV) LOAD Low Input Offset Voltage: 0.5 mV Specified for 65 V and 615 V Operation Available in a Wide Variety of Options Plastic DIP and SOIC Packages Cerdip Package Die Form specifications which include an open-loop gain of 3500 V/V MIL-STD-883B Processing (500 Ω load) and low input offset voltage of 0.5 mV. Common- Tape & Reel (EIA-481A Standard) mode rejection is a minimum of 78 dB. Output voltage swing is Dual Version Available: AD827 (8 Lead) ±3 V into loads as low as 150 Ω. Analog Devices also offers Enhanced Replacement for LM6361 over 30 other high speed amplifiers from the low noise AD829 Replacement for HA2544, HA2520/2/5 and EL2020 (1.7 nV/√Hz) to the ultimate video amplifier, the AD811, which APPLICATIONS features 0.01% differential gain and 0.01° differential phase. Video Instrumentation Imaging Equipment APPLICATION HIGHLIGHTS Copiers, Fax, Scanners, Cameras 1. As a buffer the AD847 offers a full-power bandwidth of High Speed Cable Driver 12.7 MHz (5 V p-p with ±5 V supplies) making it outstand- High Speed DAC and Flash ADC Buffers ing as an input buffer for flash A/D converters. 2. The low power and small outline package of the AD847 make it very well suited for high density applications such as PRODUCT DESCRIPTION multiple pole active filters. The AD847 represents a breakthrough in high speed amplifiers offering superior ac & dc performance and low power, all at low 3. The AD847 is internally compensated for unity gain opera- cost. The excellent dc performance is demonstrated by its ±5 V tion and remains stable when driving any capacitive load. 6 5.5 5 4.5 4 02 5 10 150 SUPPLY VOLTAGE – – Volts Quiescent Current vs. Supply Voltage AD847 Driving Capacitive Loads REV. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 QUIESCENT CURRENT – mA (@ T = +258C, unless otherwise noted) AD847–SPECIFICATIONS A Model AD847J AD847AR Conditions V Min Typ Max Min Typ Max Units S 1 INPUT OFFSET VOLTAGE ±5 V 0.5 1 0.5 1 mV T to T 3.5 4 mV MIN MAX Offset Drift 15 15 μV/°C INPUT BIAS CURRENT ±5 V, ±15 V 3.3 6.6 3.3 6.6 μA T to T 7.2 10 μA MIN MAX INPUT OFFSET CURRENT ±5 V, ±15 V 50 300 50 300 nA T to T 400 500 nA MIN MAX Offset Current Drift 0.3 0.3 nA/°C OPEN-LOOP GAIN V = ±2.5 V ±5 V OUT R = 500 Ω 2 3.5 2 3.5 V/mV LOAD T to T 1 1 V/mV MIN MAX R = 150 Ω 1.6 1.6 V/mV LOAD V = ±10 V ±15 V OUT R = 1 kΩ 3 5.5 3 5.5 V/mV LOAD T to T 1.5 1.5 V/mV MIN MAX DYNAMIC PERFORMANCE Unity Gain Bandwidth ±5 V 35 35 MHz ±15 V 50 50 MHz 2 Full Power Bandwidth V = 5 V p-p OUT R = 500 Ω, ±5 V 12.7 12.7 MHz LOAD V = 20 V p-p, OUT R = 1 kΩ±15 V 4.7 4.7 MHz LOAD 3 Slew Rate R = 1 kΩ±5 V 200 200 V/μs LOAD ±15 V 225 300 225 300 V/μs Settling Time to 0.1%, R = 250 Ω –2.5 V to +2.5 V ±5 V 65 65 ns LOAD 10 V Step, A = –1 ±15 V 65 65 ns V to 0.01%, R = 250 Ω –2.5 V to +2.5 V ±5 V 140 140 ns LOAD 10 V Step, A = –1 ±15 V 120 120 ns V Phase Margin C = 10 pF ±15 V LOAD R = 1 kΩ 50 50 Degree LOAD Differential Gain f ≈ 4.4 MHz, R = 1 kΩ±15 V 0.04 0.04 % LOAD Differential Phase f ≈ 4.4 MHz, R = 1 kΩ±15 V 0.19 0.19 Degree LOAD COMMON-MODE REJECTION V = ±2.5 V ±5 V 78 95 78 95 dB CM V = ±12 V ±15 V 78 95 78 95 dB CM T to T 75 75 dB MIN MAX POWER SUPPLY REJECTION V = ±5 V to ±15 V 75 86 75 86 dB S T to T 72 72 dB MIN MAX INPUT VOLTAGE NOISE f = 10 kHz ±15 V 15 15 nV/√Hz INPUT CURRENT NOISE f = 10 kHz ±15 V 1.5 1.5 pA/√Hz INPUT COMMON-MODE VOLTAGE RANGE ±5 V +4.3 +4.3 V –3.4 –3.4 V ±15 V +14.3 +14.3 V –13.4 –13.4 V OUTPUT VOLTAGE SWING R = 500 Ω±5 V 3.0 3.6 3.0 3.6 ±V LOAD R = 150 Ω±5 V 2.5 3 2.5 3 ±V LOAD R = 1 kΩ±15 V 12 12 ±V LOAD R = 500 Ω±15 V 10 10 ±V LOAD Short-Circuit Current ±15 V 32 32 mA INPUT RESISTANCE 300 300 kΩ INPUT CAPACITANCE 1.5 1.5 pF OUTPUT RESISTANCE Open Loop 15 15 Ω POWER SUPPLY Operating Range 64.5 618 64.5 618 V Quiescent Current ±5 V 4.8 6.0 4.8 6.0 mA T to T 7.3 7.3 mA MIN MAX ±15 V 5.3 6.3 5.3 6.3 mA T to T 7.6 7.6 mA MIN MAX NOTES l Input Offset Voltage Specifications are guaranteed after 5 minutes at T = +25°C. A 2 Full Power Bandwidth = Slew Rate/2 π V . PEAK 3 Slew Rate is measured on rising edge. All min and max specifications are guaranteed. Specifications in boldface are 100% tested at final electrical test. Specifications subject to change without notice. –2– REV. F AD847 Model AD847AQ AD847S Conditions V Min Typ Max Min Typ Max Units S 1 INPUT OFFSET VOLTAGE ±5 V 0.5 1 0.5 1 mV T to T 44 mV MIN MAX Offset Drift 15 15 μV/°C INPUT BIAS CURRENT ±5 V, ±15 V 3.3 5 3.3 5 μA T to T 7.5 7.5 μA MIN MAX INPUT OFFSET CURRENT ±5 V, ±15 V 50 300 50 300 nA T to T 400 400 nA MIN MAX Offset Current Drift 0.3 0.3 nA/°C OPEN-LOOP GAIN V = ±2.5 V ±5 V OUT R = 500 Ω 2 3.5 2 3.5 V/mV LOAD T to T 11 V/mV MIN MAX R = 150 Ω 1.6 1.6 V/mV LOAD V = = ±10 V ±15 V OUT R = 1 kΩ 3 5.5 3 5.5 V/mV LOAD T to T 1.5 1.5 V/mV MIN MAX DYNAMIC PERFORMANCE Unity Gain Bandwidth ±5 V 35 35 MHz ±15 V 50 50 MHz 2 Full Power Bandwidth V = 5 V p-p OUT R = 500 Ω, ±5 V 12.7 12.7 MHz LOAD V = 20 V p-p, OUT R = 1 kΩ±15 V 4.7 4.7 MHz LOAD 3 Slew Rate R = 1 kΩ±5 V 200 200 V/μs LOAD ±15 V 225 300 225 300 V/μs Settling Time to 0.1%, R = 250 Ω –2.5 V to +2.5 V ±5 V 65 65 ns LOAD 10 V Step, A = –1 ±15 V 65 65 ns V to 0.01%, R = 250 Ω –2.5 V to +2.5 V ±5 V 140 140 ns LOAD 10 V Step, A = –1 ±15 V 120 120 ns V Phase Margin C = 10 pF ±15 V LOAD R = 1 kΩ 50 50 Degree LOAD Differential Gain f ≈ 4.4 MHz, R = 1 kΩ±15 V 0.04 0.04 % LOAD Differential Phase f ≈ 4.4 MHz, R = 1 kΩ±15 V 0.19 0.19 Degree LOAD COMMON-MODE REJECTION V = ±2.5 V ±5 V 80 95 80 95 dB CM V = ±12 V ±15 V 80 95 80 95 dB CM T to T 75 75 dB MIN MAX POWER SUPPLY REJECTION V = ±5 V to ±15 V 75 86 75 86 dB S T to T 72 72 dB MIN MAX INPUT VOLTAGE NOISE f = 10 kHz ±15 V 15 15 nV/√Hz INPUT CURRENT NOISE f = 10 kHz ±15 V 1.5 1.5 pA/√Hz INPUT COMMON-MODE VOLTAGE RANGE ±5 V +4.3 +4.3 V –3.4 –3.4 V ±15 V +14.3 +14.3 V –13.4 –13.4 V OUTPUT VOLTAGE SWING R = 500 Ω±5 V 3.0 3.6 3.0 3.6 ±V LOAD R = 150 Ω±5 V 2.5 3 2.5 3 ±V LOAD R = 1 kΩ±15 V 12 12 ±V LOAD R = 500 Ω±15 V 10 10 ±V LOAD Short-Circuit Current ±15 V 32 32 mA INPUT RESISTANCE 300 300 kΩ INPUT CAPACITANCE 1.5 1.5 pF OUTPUT RESISTANCE Open Loop 15 15 Ω POWER SUPPLY Operating Range 64.5 618 64.5 618 V Quiescent Current ±5 V 4.8 5.7 4.8 5.7 mA T to T 7.0 7.8 mA MIN MAX ±15 V 5.3 6.3 5.3 6.3 mA T to T 7.6 8.4 mA MIN MAX REV. F –3– AD847 1 ABSOLUTE MAXIMUM RATINGS ESD SUSCEPTIBILITY Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V ESD (electrostatic discharge) sensitive device. Electrostatic 2 Internal Power Dissipation charges as high as 4000 volts, which readily accumulate on the Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Watts human body and on test equipment, can discharge without de- Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts tection. Although the AD847 features proprietary ESD protec- Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts tion circuitry, permanent damage may still occur on these Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V devices if they are subjected to high energy electrostatic dis- S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V charges. Therefore, proper ESD precautions are recommended Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C to avoid any performance degradation or loss of functionality. (N, R) . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Mini-DIP Package: θ = 100°C/Watt; θ = 33°C/Watt JA JC Cerdip Package: θ = 110°C/Watt; θ = 30°C/Watt JA JC Small Outline Package: θ = 155°C/Watt; θ = 33°C/Watt JA JC METALIZATION PHOTOGRAPH Contact factory for latest dimensions. Dimensions shown in inches and (mm). ORDERING GUIDE Temperature Package Package Models* Range – 8C Description Option AD847JN 0 to +70 Plastic N-8 AD847JR 0 to +70 SOIC R-8 AD847AQ –40 to +85 Cerdip Q-8 AD847AR –40 to +85 SOIC R-8 AD847SQ –55 to +125 Cerdip Q-8 AD847SQ/883B –55 to +125 Cerdip Q-8 5962-8964701PA –55 to +125 Cerdip Q-8 *AD847 also available in J and S grade chips, and AD847JR and AD847AR are available *in tape and reel. –4– REV. F AD847 (@ +258C and V = 615 V, unless otherwise noted) Typical Characteristics S 20 20 – 15 15 +V IN +V OUT 10 10 –V –V IN OUT 5 5 R = 500WLOAD 0 0 02 5 10 15002 5 10 150 SUPPLY VOLTAGE – – Volts SUPPLY VOLTAGE – – Volts Figure 1. Input Common-Mode Range vs. Supply Voltage Figure 2. Output Voltage Swing vs. Supply Voltage 30 6 25 5.5 20 –15 V SUPPLIES 15 5 10 4.5 –5V SUPPLIES 5 0 4 10 100 1k 10k 02 5 10 150 LOAD RESISTANCE – WSUPPLY VOLTAGE – – Volts Figure 3. Output Voltage Swing vs. Load Resistance Figure 4. Quiescent Current vs. Supply Voltage 5 100 m10W 4 V = – 5V 1 S 3 0.1 2 0.01 –60 –40 –20 0 20 40 60 80 100 120 140 10k 100k 1M 10M 100M TEMPERATURE – °C FREQUENCY – Hz Figure 5. Input Bias Current vs. Temperature Figure 6. Output Impedance vs. Frequency REV. F –5– OUTPUT VOLTAGE SWING – Volts p-p INPUT BIAS CURRENT – A INPUT COMMON-MODE RANGE – Volts OUTPUT IMPEDANCE – QUIESCENT CURRENT – mA OUTPUT VOLTAGE SWING – Volts AD847–Typical Characteristics (@ +258C and V = 615 V, unless otherwise noted) S 7 35 6 30 5 25 4 20 V = – 5V S 3 15 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE – °C TEMPERATURE – °C Figure 8. Short-Circuit Current Limit vs. Temperature Figure 7. Quiescent Current vs. Temperature 52 100 +100° 80 +80° 51–15V SUPPLIES 1kW LOAD 60 +60° –5V SUPPLIES 500W LOAD 50 40 +40° 20 +20° 49 0 0 –20 48 100 1k 10k 100k 1M 10M 100M –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY – Hz TEMPERATURE – °C Figure 10. Open-Loop Gain and Phase Margin Figure 9. Gain Bandwidth Product vs. Temperature vs. Frequency 80 100 V = –15V S +SUPPLY 75 80 70 60 V = – 5V S 65 –SUPPLY 40 60 20 55 50 0 10 100 1k 10k 1k 10k 100k 1M 10M 100M LOAD RESISTANCE – WFREQUENCY – Hz Figure 11. Open-Loop Gain vs. Load Resistance Figure 12. Power Supply Rejection vs. Frequency –6– REV. F OPEN-LOOP GAIN – dB QUIESCENT CURRENT – mA UNITY – GAIN BANDWIDTH – MHz OPEN -LOOP GAIN – dB POWER SUPPLY REJECTION – dB SHORT CIRCUIT CURRENT LIMIT – mA PHASE MARGIN – DEGREES AD847 100 30 25 80 V = –1V p-p CM 20 60 R = 1kW L 15 40 10 20 5 0 0 1M 10M 100M 1k 10k 100k 1M 10M 100M INPUT FREQUENCY – Hz FREQUENCY – Hz Figure 14. Large Signal Frequency Response Figure 13. Common-Mode Rejection vs. Frequency –70 10 8 –80 6 3V RMS– R =1kWL 4 –90 2ND HARMONIC 2 1% 0.1% –100 0 1% 0.1% –2 –110 –4 3RD HARMONIC –6 –120 –8 –130 –10 0 20 40 60 80 100 120 140 160 100 1k 10k 100k SETTLING TIME – ns FREQUENCY – Hz Figure 15. Output Swing and Error vs. Settling Time Figure 16. Harmonic Distortion vs. Frequency 50 450 400 40 m350 30 300 20 250 10 200 150 0 –60 –40 –20 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1M 10M TEMPERATURE – °C FREQUENCY – Hz Figure 18. Slew Rate vs. Temperature Figure 17. Input Voltage Noise Spectral Density REV. F –7– CMR – dB OUTPUT SWING FROM 0 TO V INPUT VOLTAGE NOISE – nV/ Hz HARMONIC DISTORTION – dB SLEW RATE – V/ s OUTPUT VOLTAGE – Volts p–p AD847 Figure 19. Inverting Amplifier Configuration Figure 19a. Inverter Large Figure 19b. Inverter Small Signal Pulse Response Signal Pulse Response Figure 20. Noninverting Amplifier Configuration Figure 20a. Noninverting Figure 20b. Noninverting Large Signal Pulse Response Small Signal Pulse Response –8– REV. F AD847 +V OFFSET NULLING S The input offset voltage of the AD847 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in Figure 21 can be used. C F OUTPUT –IN +IN –V S Figure 21. Offset Nulling NULL 1 NULL 8 INPUT CONSIDERATIONS An input resistor (R in Figure 20) is required in circuits where Figure 22. AD847 Simplified Schematic IN the input to the AD847 will be subjected to transient or con- tinuous overload voltages exceeding the ±6 V maximum differ- GROUNDING AND BYPASSING ential limit. This resistor provides protection for the input In designing practical circuits with the AD847, the user must transistors by limiting the maximum current that can be forced remember that whenever high frequencies are involved, some into their bases. special precautions are in order. Circuits must be built with short interconnect leads. A large ground plane should be used For high performance circuits it is recommended that a resistor whenever possible to provide a low resistance, low inductance (R in Figures 19 and 20) be used to reduce bias current errors B circuit path, as well as minimizing the effects of high frequency by matching the impedance at each input. The offset voltage er- coupling. Sockets should be avoided because the increased ror will be reduced by more than an order of magnitude. interlead capacitance can degrade bandwidth. THEORY OF OPERATION Feedback resistors should be of low enough value to assure that The AD847 is fabricated on Analog Devices’ proprietary the time constant formed with the capacitance at the amplifier complementary bipolar (CB) process which enables the con- summing junction will not limit the amplifier performance. struction of pnp and npn transistors with similar f s in the Resistor values of less than 5 kΩ are recommended. If a larger T 600 MHz to 800 MHz region. The AD847 circuit (Figure 22) resistor must be used, a small (<10 pF) feedback capacitor in includes an npn input stage followed by fast pnps in the folded parallel with the feedback resistor, R , may be used to compen- F cascode intermediate gain stage. The CB pnps are also used in sate for the input capacitances and optimize the dynamic perfor- the current amplifying output stage. The internal compensation mance of the amplifier. capacitance that makes the AD847 unity gain stable is provided Power supply leads should be bypassed to ground as close as by the junction capacitances of transistors in the gain stage. possible to the amplifier pins. Ceramic disc capacitors of The capacitor, C , in the output stage mitigates the effect of ca- 0.1 μF are recommended. F pacitive loads. At low frequencies and with low capacitive loads, the gain from the compensation node to the output is very close to unity. In this case C is bootstrapped and does not F contribute to the compensation capacitance of the part. As the capacitive load is increased, a pole is formed with the output impedance of the output stage. This reduces the gain, and therefore, C is incompletely bootstrapped. Some fraction of C F F contributes to the compensation capacitance, and the unity gain bandwidth falls. As the load capacitance is increased, the band- width continues to fall, and the amplifier remains stable. REV. F –9– AD847 VIDEO LINE DRIVER Figure 24 shows the AD847 driving 100 pF and 1000 pF loads. The AD847 functions very well as a low cost, high speed line driver for either terminated or unterminated cables. Figure 23 shows the AD847 driving a doubly terminated cable in a fol- lower configuration. The termination resistor, R , (when equal to the cable’s charac- T teristic impedance) minimizes reflections from the far end of the cable. While operating from ±5 V supplies, the AD847 main- tains a typical slew rate of 200 V/μs, which means it can drive a ±1 V, 30 MHz signal into a terminated cable. +V S 75WR IN 0.1 mF COAX Figure 24. AD847 Driving Capacitive Loads 100W75W V COAX IN AD847 V OUT FLASH ADC INPUT BUFFER 75WR BT R T The 35 MHz unity gain bandwidth of the AD847 makes it an 75W75W excellent choice for buffering the input of high speed flash A/D 0.1 mF converters, such as the AD9048. 500W –V S Figure 25 shows the AD847 as a unity inverter for the input to the AD9048. 500WC C 0.1 SEE TABLE I –5.2V AD589 2k 10kW Figure 23. Video Line Driver 27 100 Table I. Video Line Driver Performance Chart 0.1 2N3906 AD741 Over- 5 1k 1k V*V C –3 dB B shoot IN SUPPLY C W 1.5kW0.1mF 0 dB or ±500 mV Step ±15 20 pF 23 MHz 4% ANALOG 1.5kWR R B T 0 dB or ±500 mV Step ±15 15 pF 21 MHz 0% INPUT 43W D1 (0V TO +2V) 0 dB or ±500 mV Step ±15 0 pF 13 MHz 0% V AD847 50WIN (MSB) 0 dB or ±500 mV Step ±5 20 pF 18 MHz 2% AD9048 0 dB or ±500 mV Step ±5 15 pF 16 MHz 0% TTL 0 dB or ±500 mV Step ±5 0 pF 11 MHz 0% D8 CONVERT CONVERT (LSB) SIGNAL V V *–3 dB bandwidth numbers are for the 0 dBm signal input. Overshoot numbers EE CC are the percent overshoot of the 1 volt step input. 0.1mF 0.1mF A back-termination resistor (R , also equal to the characteristic BT impedance of the cable) may be placed between the AD847 out- –5.2V +5.0V put and the cable input, in order to damp any reflected signals Figure 25. Flash ADC Input Buffer caused by a mismatch between R and the cable’s characteristic T impedance. This will result in a flatter frequency response, al- though this requires that the op amp supply ±2 V to the output in order to achieve a ±1 V swing at resistor R . T –10– REV. F AD847 A High Speed, Three Op-Amp In-Amp The input amplifier (A1 and A2) is an AD827, which is a dual The circuit of Figure 26 lends itself well to CCD imaging and version of the AD847. This circuit has the optional flexibility of other video speed applications. It uses two high speed CB pro- both dc and ac trims for common-mode rejection, plus the abil- cess op-amps: Amplifier A3, the output amplifier, is an AD847. ity to adjust for minimum settling time. EACH AMPLIFIER PIN 7 AD847, +15V +V S PIN 8 AD827 10mF 0.1mF 1mF 0.1mF COMM 10mF 0.1mF 1mF 0.1mF PIN 4 –15V –V S AD847 & AD827 1/2 2–8pF SETTLING TIME AD827 AC CMR ADJUST –V 3 IN INPUT A1 1 FREQUENCY CMRR 2 2kW 1kW100Hz 88.3dB 1kHz 87.4dB 2kW 2 V 10kHz 86.2dB OUT 100kHz 67.4dB A3 6 R G 2kW1MHz 47.1dB 3 1kWR AD847 L 2kW 1.87kW 5pF 6 7 A2 DC CMR +V 5 IN ADJUST 1/2 200W 2000WAD827 CIRCUIT GAIN = + 1 R G BANDWIDTH, SETTLING TIME AND TOTAL HARMONIC DISTORTION VS. GAIN THD + NOISE SMALL SETTLING BELOW INPUT C SIGNAL TIME LEVEL ADJ GAIN R (pF) BANDWIDTH TO 0.1% @ 10kHz G 1 OPEN 2–8 16.1MHz 200ns 82dB 2 2kW2–8 14.7MHz 200ns 82dB 10 226W2–8 4.5MHz 370ns 81dB 100 20W2–8 660kHz 2.5ms 71dB Figure 26. A High Speed In-Amp Circuit for Data Acquisition REV. F –11– AD847 HIGH SPEED DAC BUFFER (10.24 V for a 1 kΩ resistor). Note that since the DAC gener- The wide bandwidth and fast settling time of the AD847 makes ates a positive current to ground, the voltage at the amplifier it a very good output buffer for high speed current-output D/A output will be negative. A 100 Ω series resistor between the converters like the AD668. As shown in Figure 27, the op amp noninverting amplifier input and ground minimizes the offset establishes a summing node at ground for the DAC output. The effects of op amp input bias currents. output voltage is determined by the amplifier’s feedback resistor +15V 10mF TO ANALOG GROUND PLANE 0.1mF 1 MSB V 24 CC – 2 REFCOM 23 1V NOMINAL REFERENCE INPUT 3 REFIN1 22 + 10k 4 REFIN2 21 1k 5 I 20 OUT DIGITAL AD668 100WANALOG 6 R INPUTS 19 LOAD OUTPUT AD847 7 ACOM 18 ANALOG GROUND PLANE ANALOG 8 17 SUPPLY LCOM GROUND 9 IBPO 16 10mF 0.1mF –15V 10 15 V EE 11 THCOM 14 100pF 12 LSB +5V VTH 13 1kW Figure 27. High Speed DAC Buffer OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Small Outline (R-8) Package Mini-DIP (N-8) Package Cerdip (Q-8) Package 0.150 (3.81) 0.005 (0.13) MIN 0.055 (1.40) MAX 8 5 0.25 (6.35) 0.31 8 5 PIN 1 8 5 (7.87) 0.244 (6.20) 0.157 (3.99) 0.310 (7.87) 1 4 0.228 (5.79) PIN 1 0.150 (3.81) 0.220 (5.59) PIN 1 1 4 1 4 0.39 (9.91) MAX 0.035±0.01 0.405 (10.29) MAX (0.89±0.25) 0.165±0.01 (4.19±0.25) 0.060 (1.52) 0.197 (5.01) 0.200 0.015 (0.38) (5.08) 0.189 (4.80) 0.18±0.03 0.125 MAX 0.102 (2.59) (4.57±0.76) (3.18) 0.010 (0.25) 0.094 (2.39) 0.150 MIN 0.004 (0.10) 0.200 (5.08) (3.81) MIN 0.125 (3.18) 0.050 0.019 (0.48) 0.018±0.003 0.10 0.033 SEATING (1.27) 0.014 (0.36) (0.46±0.08) (2.54) (0.84) PLANE BSC NOM BSC 0.023 (0.58) 0.100 0.070 (1.78) 0.020 (0.051) x 45° SEATING (2.54) 0.30 (7.62) 0.014 (0.36) 0.030 (0.76) CHAMF PLANE REF BSC 0.190 (4.82) 0.320 (8.13) 0.170 (4.32) 8° 0.290 (7.37) 0.090 0° (2.29) 10° 0.011±0.003 0° 0.030 (0.76) (0.28±0.08) 0.098 (0.2482) 0.018 (0.46) 0.075 (0.1905) 15° 0.015 (0.38) 0° 0.008 (0.20) 15° 0° All brand or product names mentioned are trademarks or registered trademarks of their respective holders. –12– REV. F PRINTED IN U.S.A. C1191f–10–9/92