ANALOG DEVICES AD8432

Dual-Channel Ultralow Noise Amplifier with Selectable Gain and Input Impedance AD8432 FEATURES FUNCTIONAL BLOCK DIAGRAM ENB VPS1 VPS2 COMM Low noise Input voltage noise: 0.85 nV/√Hz BIAS Current noise: 2.0 pA/√Hz AD8432 High speed INH1 OPH1 200 MHz bandwidth (G = 12.04 dB) IND1 LNA1 295 V/µs slew rate OPL1 GMH1 Selectable gain GOH1 G = 12.04 dB (×4) GOL1 INL1 G = 18.06 dB (×8) GML1 G = 21.58 dB (×12) INH2 OPH2 G = 24.08 dB (×16) IND2 LNA2 OPL2 Active input impedance matching GMH2 Integrated input clamp diodes GOH2 Single-ended input, differential output INL2 GOL2 GML2 Supply range: 4.5 V to 5.5 V Low power: 60 mW/channel Figure 1. APPLICATIONS CW Doppler ultrasound front ends Low noise preamplification Predriver for I/Q demodulators and phase shifters Wideband analog-to-digital drivers GENERAL DESCRIPTION The AD8432 is a dual-channel, low power, ultralow noise The AD8432 achieves 0.85 nV/√Hz input-referred voltage noise for amplifier with selectable gain and active impedance matching. a gain of 12.04 dB. The AD8432’s ultralow noise, low distortion, Each channel has a single-ended input, differential output, and gain accuracy, and channel-to-channel matching are ideal for integrated input clamps. By pin strapping the gain setting pins, four high performance ultrasound systems and for processing I/Q accurate gains of G = 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB demodulator signals. (×4, ×8, ×12, and ×16, respectively) are possible. A bandwidth of The AD8432 operates on a single supply of 5 V at 24 mA. It is 200 MHz at G = 12.04 dB makes this amplifier well suited for many available in a 4 mm × 4 mm, 24-lead LFSCP. The LFCSP features high speed applications. an exposed paddle that provides a low thermal resistance path to The exceptional noise performance of the AD8432 is made the PCB, which enables more efficient heat transfer and increases possible by the active impedance matching. Using a feedback reliability. The operating temperature range is −40°C to +85°C. network, the input impedance of the amplifiers can be adjusted to match the signal source impedance without compromising the noise performance. Impedance matching and low noise in the AD8432 allow designers to create wider dynamic range systems that are able to detect even very low level signals. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009-2011 Analog Devices, Inc. All rights reserved. 08341-001 AD8432 TABLE OF CONTENTS Features .............................................................................................. 1 Gain Setting Technique ............................................................. 18 Applications ....................................................................................... 1 Active Input Resistance Matching............................................ 19 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 21 General Description ......................................................................... 1 Typical Setup ............................................................................... 21 Revision History ............................................................................... 2 I/Q Demodulation Front End ................................................... 23 Specifications ..................................................................................... 3 Differential-to-Single-Ended Conversion ............................... 24 Absolute Maximum Ratings ............................................................ 5 Evaluation Board ............................................................................ 25 Thermal Resistance ...................................................................... 5 Gain Setting ................................................................................. 25 Maximum Power Dissipation ..................................................... 5 Schematic..................................................................................... 26 ESD Caution .................................................................................. 5 Power Supply ............................................................................... 27 Pin Configuration and Function Descriptions ............................. 6 Input Termination ...................................................................... 27 Typical Performance Characteristics ............................................. 7 Output .......................................................................................... 27 Test Circuits ..................................................................................... 16 Outline Dimensions ....................................................................... 28 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 28 Low Noise Amplifier (LNA) ..................................................... 18 REVISION HISTORY 3/11—Rev. A to Rev. B Changes to Format ......................................................................... 21 2/10—Rev. 0 to Rev. A Changes to General Description .................................................... 1 Changes to Figure 5, Figure 6, Figure 7, Figure 8 ......................... 7 Added Figure 27, Figure 29, and Figure 31, Renumbered Sequentially ..................................................................................... 11 Added Figure 33 and Figure 35..................................................... 12 Changes to Figure 58 ...................................................................... 16 10/09—Revision 0: Initial Version Rev. B | Page 2 of 28 AD8432 SPECIFICATIONS V = 5 V, T = 25°C, R = R = 50 Ω, R =150 Ω, C = 47 pF, R = 15 Ω, R = 500 Ω (per SE output), C = 5 pF (per SE output), S A S IN FB SH SH L L G = 12.04 dB (single-ended input to differential output), f = 1 MHz, unless otherwise specified. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Gain Range Input to differential output (selectable gain) 12.04 24.08 dB Input to single output (selectable gain) 6.02 18.06 dB Gain Error 0.1 1 dB −3 dB Small Signal Bandwidth R unterminated, R = ∞, C = 0 pF, R = 0 Ω IN FB SH SH G = 12.04 dB 200 MHz G = 18.06 dB 90 MHz G = 21.58 dB 50 MHz G = 24.08 dB 32 MHz −3 dB Large Signal Bandwidth V = 2 V p-p 42 MHz OUT Slew Rate (Rising Edge) V = 2 V p-p, f = 10 MHz 295 V/µs OUT Slew Rate (Falling Edge) V = 2 V p-p, f = 10 MHz 170 V/µs OUT Overdrive Recovery Time 10 ns DISTORTION/NOISE PERFORMANCE Input Voltage Noise R = ∞ 0.85 nV/√Hz FB Input Current Noise R = ∞ 2.0 pA/√Hz FB Noise Figure Unterminated R = 50 Ω, R = ∞ 2.8 dB S FB Active Termination R = R = 50 Ω, R = 150 Ω 4.8 dB S IN FB R = 50 Ω, R = 226 Ω, R = 75 Ω 4.2 dB S FB IN R = 50 Ω, R = 301 Ω, R = 100 Ω 3.2 dB S FB IN R = 50 Ω, R = 619 Ω, R = 200 Ω 2.1 dB S FB IN R = 50 Ω, R = 3.57 kΩ, R = 1 kΩ 2.3 dB S FB IN Output Referred Noise G = 12.04 dB, R = ∞ 3.4 nV/√Hz FB G = 18.06 dB, R = ∞ 6.8 nV/√Hz FB G = 21.58 dB, R = ∞ 10.2 nV/√Hz FB G = 24.08 dB, R = ∞ 13.6 nV/√Hz FB Harmonic Distortion 1 MHz (V = 1 V p-p) HD2 −67 dBc OUT HD2, R = 50 Ω, R unterminated −74 dBc S IN HD3 −103 dBc HD3, R = 50 Ω, R unterminated −106 dBc S IN 1 MHz (V = 2 V p-p) HD2 −65 dBc OUT HD2, R = 50 Ω, R unterminated −72 dBc S IN HD3 −103 dBc HD3, R = 50 Ω, R unterminated −92 dBc S IN 10 MHz (V = 1 V p-p) HD2 −66 dBc OUT HD2, R = 50 Ω, R unterminated −62 dBc S IN HD3 −78 dBc HD3, R = 50 Ω, R unterminated −73 dBc S IN 10 MHz (V = 2 V p-p) HD2 −60 dBc OUT HD2, R = 50 Ω, R unterminated −56 dBc S IN HD3 −72 dBc HD3, R = 50 Ω, R unterminated −65 dBc S IN Rev. B | Page 3 of 28 AD8432 Parameter Conditions Min Typ Max Unit Two-Tone IMD3 Distortion R = 50 Ω, R unterminated S IN 10 MHz V = 1 V p-p, f1 = 9.5 MHz, f2 = 10.5 MHz −89.1 dBc OUT V = 2 V p-p, f1 = 9.5 MHz, f2 = 10.5 MHz −66.0 dBc OUT 1 MHz V = 1 V p-p, f1 = 0.9 MHz, f2 = 1.1 MHz −88.9 dBc OUT V = 2 V p-p, f1 = 0.9 MHz, f2 = 1.1 MHz −73.7 dBc OUT Input 1dB Compression Point f = 1 MHz 7.5 dBm f = 10 MHz 7.7 dBm Output Third-Order Intercept 1 MHz V = 1 V p-p of composite tones 29.7 dBV rms OUT V = 2 V p-p of composite tones 28.2 dBV rms OUT 10 MHz V = 1 V p-p of composite tones 23.2 dBV rms OUT V = 2 V p-p of composite tones 24.2 dBV rms OUT 1 MHz V = 1 V p-p of composite tones, reference to 50 Ω 42.7 dBm OUT V = 2 V p-p of composite tones, reference to 50 Ω 41.2 dBm OUT 10 MHz V = 1 V p-p of composite tones, reference to 50 Ω 36.2 dBm OUT V = 2 V p-p of composite tones, reference to 50 Ω 37.2 dBm OUT Crosstalk V = 1 V p-p, f = 1 MHz 102 dB OUT DC PERFORMANCE Input Offset Voltage −6.25 +1 +6.25 mV Input Offset Voltage Drift 300 µV/°C INPUT CHARACTERISTICS Input Voltage Range AC-coupled 1.2 V p-p Input Resistance R = 150 Ω 50 Ω FB R = 226 Ω 75 Ω FB R = 301 Ω 100 Ω FB R = 619 Ω 200 Ω FB R = 3.57 kΩ 1 kΩ FB R = ∞, f = 100 kHz 6.2 kΩ FB Input Capacitance 6 pF Input Common-Mode Voltage 3.25 V OUTPUT CHARACTERISTCS Output Common-Mode Voltage 2.5 V Output Offset Voltage −25 +4 +25 mV Output Voltage Swing 4.8 V p-p Output Resistance Single-ended, either output <0.1 Ω Output Resistance in Shutdown Mode Single-ended, either output 2.5 kΩ Output Short-Circuit Current R = 10 Ω differential 77 mA L Enable Response Time ENB (enable high to output on) 200 µs ON ENB (enable low to output off) 200 µs OFF POWER SUPPLY Supply Voltage 4.5 5 5.5 V Quiescent Current ENB = 5 V 24 mA Over Temperature T = −40°C 21 mA A T = +85°C 27 mA A Supply Current in Shutdown Mode ENB = GND 50 100 µA Power Dissipation 120 mW PSRR G = 24.08 dB, f = 100 kHz, no bypass capacitors −82 dB Rev. B | Page 4 of 28 AD8432 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 2. The maximum safe power dissipation for the AD8432 is limited Parameter Rating by the associated rise in junction temperature (T ) on the die. At J Voltage approximately 150°C, which is the glass transition temperature, Supply Voltage 5.5 V the properties of the plastic change. Even temporarily exceeding Input Voltage 0 V to VPS this temperature limit may change the stresses that the package Power Dissipation 120 mW exerts on the die, permanently shifting the parametric performance Temperature of the amplifiers. Exceeding a temperature of 150°C for an Operating Temperature –40°C to +85°C extended period can cause changes in silicon devices, potentially Storage Temperature –65°C to +150°C resulting in a loss of functionality. Package Glass Transition Temperature (T ) 150°C G Lead Temperature (Soldering, 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings ESD CAUTION may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. The θ JA value in Table 3 assumes a 4-layer JEDEC standard board with zero airflow. 1 Table 3. Thermal Resistance Parameter θ θ θ Ψ Unit JA JC JB JT 40-Lead LFCSP 57.9 11.2 35.9 1.1 °C/W 1 4-layer JEDEC board (2S2P). Rev. B | Page 5 of 28 AD8432 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 18 INH1 GOL1 INL1 2 17 OPL1 AD8432 IND1 3 16 COM1 TOP VIEW 15 COMM 4 COM2 (Not to Scale) INL2 5 14 OPL2 INH2 6 13 GOL2 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 INH1 LNA1 Noninverting Input. 2 INL1 LNA1 Inverting Input (AC-Coupled to Ground). 3, 7 IND1, IND2 Integrated Input Clamping Back-to-Back Diodes. 4 COMM Input Ground. 5 INL2 LNA2 Inverting Input (AC-Coupled to Ground). 6 INH2 LNA2 Noninverting Input. 8 VPS2 5 V Supply. 9 OPH2 Noninverting Output of LNA2. 10 GOH2 Gain Setting Pin for LNA2. 11 GMH2 Gain Setting Pin for LNA2. 12 GML2 Gain Setting Pin for LNA2. 13 GOL2 Gain Setting Pin for LNA2. 14 OPL2 Inverting Output of LNA2. 15 COM2 LNA2 Output Ground. 16 COM1 LNA1 Output Ground. 17 OPL1 Inverting Output of LNA1. 18 GOL1 Gain Setting Pin for LNA1. 19 GML1 Gain Setting Pin for LNA1. 20 GMH1 Gain Setting Pin for LNA1. 21 GOH1 Gain Setting Pin for LNA1. 22 OPH1 Noninverting Output of LNA1. 23 VPS1 5 V Supply. 24 ENB Enable. EPAD Exposed pad must be connected to ground. Rev. B | Page 6 of 28 08341-002 24 IND2 7 ENB VPS2 8 23 VPS1 OPH2 9 22 OPH1 GOH2 10 21 GOH1 GMH2 11 20 GMH1 GML2 12 19 GML1 AD8432 TYPICAL PERFORMANCE CHARACTERISTICS V = 5 V, T = 25°C, R = R = 50 Ω, R =150 Ω, C = 47 pF, R = 15 Ω, R =500 Ω (per SE output), C = 5 pF (per SE output), S A S IN FB SH SH L L G = 12.04 dB (single-ended input to differential output), f = 1 MHz, unless otherwise specified. 24 30 24 18 18 12 12 6 6 0 0 –6 –6 –12 –12 –18 G = 24.08dB R UNTERMINATED IN G = 21.58dB R = 200Ω –18 IN –24 G = 18.06dB R = 100Ω IN G = 12.04dB R = 50Ω IN –30 –24 1 10 100 1k 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 3. Small Signal Differential Gain vs. Frequency, R Unterminated Figure 6. Small Signal Frequency Response vs. R , G = 21.58 dB IN IN 24 30 21 24 18 18 15 12 12 9 6 6 0 3 0 –6 –3 –12 –6 R UNTERMINATED IN R UNTERMINATED IN R = 200Ω IN R = 200Ω IN –18 –9 R = 100Ω R = 100Ω IN IN R = 50Ω R = 50Ω IN IN –12 –24 1 10 100 500 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Small Signal Frequency Response vs. R , G = 12.04 dB Figure 7. Small Signal Frequency Response vs. R , G = 24.08 dB IN IN 24 30 18 24 18 12 12 6 6 0 0 –6 –6 –12 –12 R UNTERMINATED IN G = 24.08dB R = 200Ω –18 IN G = 21.58dB –18 R = 100Ω IN G = 18.06dB R = 50Ω IN G = 12.04dB –24 –24 1 10 100 1k 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Small Signal Frequency Response vs. R , G = 18.06 dB Figure 8. Differential Gain vs. Frequency, V = 1 V p-p, R = 50 Ω IN OUT IN Rev. B | Page 7 of 28 GAIN (dB) GAIN (dB) GAIN (dB) 08341-003 08341-055 08341-004 GAIN (dB) GAIN (dB) GAIN (dB) 08341-058 08341-057 08341-056 AD8432 30 240 24 230 18 220 12 210 6 200 0 190 –6 180 –12 G = 24.08dB G = 24.08dB G = 21.58dB 170 G = 21.58dB –18 G = 18.06dB G = 18.06dB G = 12.04dB G = 12.04dB –24 160 1 10 100 1k 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Differential Gain vs. Frequency, V = 2 V p-p, R = 50 Ω Figure 12. Input Impedance R vs. Frequency, 200 Ω Active Termination OUT IN IN 55 10 54 53 52 51 50 1 49 48 47 G = 24.08dB G = 24.08dB G = 21.58dB G = 21.58dB 46 G = 18.06dB G = 18.06dB G = 12.04dB G = 12.04dB 45 0.1 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Input Impedance R vs. Frequency, 50 Ω Active Termination Figure 13. Input Impedance R vs. Frequency, Unterminated IN IN 115 3.5 3.0 110 2.5 105 2.0 100 1.5 95 1.0 90 G = 24.08dB 0.5 G = 21.58dB G = 18.06dB G = 12.04dB 85 0 0.1 1 10 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Input Impedance R vs. Frequency, 100 Ω Active Termination Figure 14. Output Impedance vs. Frequency IN Rev. B | Page 8 of 28 GAIN (dB) INPUT IMPEDANCE (Ω) INPUT IMPEDANCE (Ω) 08341-029 08341-030 08341-011 OUTPUT IMPEDANCE (Ω) INPUT IMPEDANCE (kΩ) INPUT IMPEDANCE (Ω) 08341-032 08341-031 08341-033 AD8432 100 1.00 0.95 10 0.90 0.85 1 0.80 0.75 0.1 0.70 0.1 1 10 100 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) FREQUENCY (MHz) Figure 15. Output Impedance vs. Frequency in Disable Mode Figure 18. Input Voltage Noise vs. Temperature 10 16 f = 1MHz G = 24.08dB 14 12 G = 21.58dB 10 1 R THERMAL S 8 NOISE ALONE G = 18.06dB 6 4 G = 12.04dB 0.1 2 1 10 100 1k –50 –30 –10 10 30 50 70 90 SOURCE RESISTANCE (Ω) TEMPERATURE (°C) Figure 16. Input-Referred Voltage Noise vs. Source Resistance (R ) Figure 19. Output Voltage Noise vs. Temperature S 100 1.6 f = 1MHz 1.4 1.2 1.0 G = 24.08dB G = 21.58dB 10 0.8 G = 18.06dB 0.6 G = 12.04dB 0.4 G = 24.08dB 0.2 G = 21.58dB G = 18.06dB G = 12.04dB 0 1 1 10 100 1k 0.01 0.1 1 10 100 SOURCE RESISTANCE (Ω) FREQUENCY (MHz) Figure 17. Output-Referred Voltage Noise vs. Source Resistance (R ) Figure 20. Input Voltage Noise vs. Frequency S Rev. B | Page 9 of 28 OUTPUT-REFERRED VOLTAGE NOISE (nV/√Hz) INPUT-REFERRED VOLTAGE NOISE (nV/√Hz) OUTPUT IMPEDANCE (kΩ) 08341-034 08341-035 08341-036 INPUT VOLTAGE NOISE (nV/√Hz) INPUT VOLTAGE NOISE (nV/√Hz) OUTPUT VOLTAGE NOISE (nV/√Hz) 08341-038 08341-221 08341-037 AD8432 20 –40 G = 24.08dB HD2, 10MHz G = 21.58dB HD2, 1MHz 18 G = 18.06dB HD3, 10MHz –50 G = 12.04dB HD3, 1MHz 16 MEASUREMENT LIMIT –60 14 12 –70 10 –80 8 6 –90 4 –100 2 –110 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.01 0.1 1 10 100 V (V p-p) FREQUENCY (MHz) OUT Figure 21. Output Voltage Noise vs. Frequency Figure 24. Harmonic Distortion vs. Differential Output Voltage, G = 12.04 dB 0 –40 LOW TONE HIGH TONE –10 –50 –20 –60 –30 –40 –70 HD2, 10MHz –50 HD2, 1MHz –80 HD3, 10MHz –60 HD3, 1MHz MEASUREMENT –70 –90 LIMIT –80 –100 –90 –100 –110 1 10 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 FREQUENCY (MHz) V (V p-p) OUT Figure 22. IMD3 vs. Frequency Figure 25. Harmonic Distortion vs. Differential Output Voltage, G = 24.08 dB 50 –50 G = 24.08dB G = 12.04dB 45 40 –60 35 30 25 –70 20 15 –80 10 HD2, 10MHz, 2V p-p HD2, 10MHz, 1V p-p 5 HD3, 10MHz, 2V p-p HD3, 10MHz, 1V p-p 0 –90 1 10 100 0 5 10 15 20 25 FREQUENCY (MHz) C (pF) L Figure 23. Output Third-Order Intercept vs. Frequency Figure 26. Harmonic Distortion at 10 MHz vs. Capacitive Load (C ), L G = 12.04 dB Rev. B | Page 10 of 28 OIP3 (dBm) IMD3 (dBc) OUTPUT VOLTAGE NOISE (nV/√Hz) 08341-223 08341-222 08341-224 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 08341-227 08341-226 08341-225 AD8432 –50 –50 HD2, 10MHz, 2V p-p HD2, 1MHz, 2V p-p HD2, 10MHz, 1V p-p HD2, 1MHz, 1V p-p HD3, 10MHz, 2V p-p HD3, 1MHz, 2V p-p HD3, 10MHz, 1V p-p –60 HD3, 1MHz, 1V p-p –55 –70 –60 –80 –65 –90 –70 –100 –110 –75 0 5 10 15 20 25 0 200 400 600 800 1000 1200 1400 1600 1800 2000 C (pF) R (Ω) L L Figure 27. Harmonic Distortion at 1 MHz vs. Capacitive Load (C ), Figure 30. Harmonic Distortion at 10 MHz vs. Resistive Load (R ), L L G = 12.04 dB G = 12.04 dB –40 –60 HD2, 1MHz, 1V p-p HD2, 1MHz, 2V p-p –50 HD3, 1MHz, 2V p-p –65 HD3, 1MHz, 1V p-p –60 –70 –70 –75 –80 –80 –90 –85 HD2, 10MHz, 2V p-p –90 HD2, 10MHz, 1V p-p HD3, 10MHz, 2V p-p HD3, 10MHz, 1V p-p –100 –95 0 5 10 15 20 25 30 35 0 200 400 600 800 1000 1200 1400 1600 1800 2000 C (pF) R (Ω) L L ), Figure 31. Harmonic Distortion at 1 MHz vs. Resistive Load (R ), Figure 28. Harmonic Distortion at 10 MHz vs. Capacitive Load (C L L G = 24.08 dB G = 12.04 dB –50 –60 –55 –70 –60 –65 –80 –70 –90 –75 –80 –100 –85 –110 HD2, 1MHz, 1V p-p HD2, 10MHz, 2V p-p HD2, 1MHz, 2V p-p HD2, 10MHz, 1V p-p –90 HD3, 1MHz, 2V p-p HD3, 10MHz, 2V p-p HD3, 1MHz, 1V p-p HD3, 10MHz, 1V p-p –120 –95 0 5 10 15 20 25 30 35 0 200 400 600 800 1000 1200 1400 1600 1800 2000 C (pF) R (Ω) L L Figure 29. Harmonic Distortion at 1 MHz vs. Capacitive Load (C ), Figure 32. Harmonic Distortion at 10 MHz vs. Resistive Load (R ), L L G = 24.08 dB G = 24.08 dB Rev. B | Page 11 of 28 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 08341-269 08341-270 08341-228 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 08341-230 08341-271 08341-229 AD8432 –60 –70 HD2, 1MHz, 1V p-p HD2, 1MHz, 2V p-p –75 HD3, 1MHz, 2V p-p –65 HD3, 1MHz, 1V p-p –80 –70 –85 –90 –75 –95 –80 –100 –105 –85 –110 –90 –115 –95 –120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0.1 1 10 100 FREQUENCY (MHz) R (Ω) L Figure 33. Harmonic Distortion at 1 MHz vs. Resistive Load (R ), Figure 36. Channel Crosstalk vs. Frequency L G = 24.08 dB –50 –60 –70 –80 –90 HD2, 10MHz, 2V p-p HD2, 10MHz, 1V p-p HD3, 10MHz, 2V p-p HD3, 10MHz, 1V p-p –100 100ns/DIV 2 4 6 8 10 12 14 16 18 GAIN (V/V) Figure 34. Harmonic Distortion at 10 MHz vs. Gain Figure 37. Overdrive Recovery, G = 12.04 dB –50 HD2, 1MHz, 2V p-p HD2, 1MHz, 1V p-p HD3, 1MHz, 2V p-p HD3, 1MHz, 1V p-p –60 –70 –80 –90 –100 –110 100ns/DIV 2 4 6 8 10 12 14 16 18 GAIN (V/V) Figure 35. Harmonic Distortion at 1 MHz vs. Gain Figure 38. Overdrive Recovery, G = 24.08 dB Rev. B | Page 12 of 28 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 08341-273 08341-231 08341-272 CROSSTALK (dB) 1V/DIV 1V/DIV 08341-013 08341-132 08341-232 AD8432 C = 5pF L G = 24.08dB C = 10pF L C = 15pF L C = 20pF L C = 30pF L G = 21.58dB G = 18.06dB G = 12.04dB 10ns/DIV 10ns/DIV Figure 39. Small Signal Transient Response vs. Gain, V = 100 mV p-p Figure 42. Small Signal Transient Response vs. Capacitive Load (C ), IN L G = 24.08 dB R = 499Ω L R = 249Ω L R = 24.9Ω L R = 15Ω L R = 10Ω L 10ns/DIV 10ns/DIV Figure 40. Small Signal Transient Response, G = 12.04 dB Figure 43. Small Signal Transient Response vs. Resistive Load (R ), L G = 12.04 dB C = 15pF L R = 499Ω L C = 10pF R = 249Ω L L C = 5pF R = 24.9Ω L L R = 15Ω L R = 10Ω L 10ns/DIV 10ns/DIV Figure 41. Small Signal Transient Response vs. Capacitive Load (C ), Figure 44. Small Signal Transient Response vs. Resistive Load (R ), L L G = 12.04 dB G = 24.08 dB Rev. B | Page 13 of 28 100mV/DIV 50mV/DIV 200mV/DIV 08341-016 08341-015 08341-014 50mV/DIV 50mV/DIV 50mV/DIV 08341-018 08341-017 08341-019 AD8432 C = 30pF L G = 18.06dB C = 20pF G = 12.04dB L C = 15pF L G = 21.58dB C = 10pF L G = 24.08dB C = 5pF L 10ns/DIV 10ns/DIV Figure 45. Small Signal Transient Response vs. Gain, V = 200 mV p-p Figure 48. Large Signal Transient Response vs. Capacitive Load (C ), OUT L G = 24.08 dB R = 499Ω L R = 249Ω L R = 24.9Ω G = 24.08dB L R = 15Ω L G = 21.58dB G = 18.06dB G = 12.04dB 10ns/DIV 10ns/DIV = 125 mV p-p Figure 46. Large Signal Transient Response vs. Gain, V Figure 49. Large Signal Transient Response vs. Resistive Load (R ), IN L G = 12.04 dB R = 499Ω C = 20pF L L R = 249Ω C = 15pF L L R = 24.9Ω C = 10pF L L R = 15Ω C = 5pF L L R = 10Ω L 10ns/DIV 10ns/DIV Figure 47. Large Signal Transient Response vs. Capacitive Load (C ), Figure 50. Large Signal Transient Response vs. Resistive Load (R ), L L G = 12.04 dB G = 24.08 dB Rev. B | Page 14 of 28 500mV/DIV 500mV/DIV 50mV/DIV 08341-020 08341-021 08341-022 500mV/DIV 500mV/DIV 500mV/DIV 08341-025 08341-024 08341-023 AD8432 140 G = 12.04dB G = 21.58dB G = 18.06dB G = 24.08dB 120 100 80 60 40 20 0 –60 –40 –20 0 20 40 60 80 100 10ns/DIV TEMPERATURE (°C) Figure 51. Large Signal Transient Response vs. Gain, V = 2 V p-p Figure 54. Supply Current vs. Temperature in Disable Mode OUT –20 ENB –30 5V/DIV 1 –40 –50 –60 OUTPUT 50mV/DIV –70 2 –80 G = 24.08dB NO BYPASS CAPS –90 –100 0.01 0.1 1 10 100 TIME (100µs/DIV) FREQUENCY (MHz) Figure 52. PSRR vs. Frequency Figure 55. Small Signal Enable Response 30 ENB 5V/DIV 1 28 26 OUTPUT 24 500mV/DIV 2 22 20 TIME (100µs/DIV) –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 56. Large Signal Enable Response Figure 53. Supply Current vs. Temperature Rev. B | Page 15 of 28 SUPPLY CURRENT (mA) PSRR (dB) 500mV/DIV 08341-026 08341-248 08341-027 SUPPLY CURRENT (µA) 08341-252 08341-251 08341-028 AD8432 TEST CIRCUITS 0.1µF R FB 1MHz SPECTRUM (10MHz LPF) DUAL FILTER ANALZYER 0.1µF 0.1µF INH INH OPL HP 475Ω R L R INL OPH SH 50Ω LP INL 56.2Ω 0.1µF AD8432 0.1µF 1MHz LNA1 (10MHz) C AD8130 SH 1.7MHz 50Ω G = 1 (10.7MHz) R L Figure 57. Harmonic Distortion vs. Resistive Load (R ) Measurements L 0.1µF DUAL FILTER R FB 50Ω SPECTRUM LP ANALYZER 1MHz (10MHz LPF) 0.1µF 0.1µF 50Ω 487Ω HP IN INH OPL 1:1 C 26.1Ω L 487Ω R INL OPH 1.7MHz SH (10.7MHz) 0.1µF 0.1µF 1MHz C AD8432 (10MHz) SH LNA1 26.1Ω C L R L Figure 58. Harmonic Distortion vs. Capacitive Load (C ) Measurements L NETWORK ANALYZER 50Ω OUT 50Ω IN 5pF 499Ω 0.1µF R FB DIFF PROBE 0.1µF 0.1µF INH OPL R INL OPH SH AD8432 0.1µF 499Ω LNA1 C SH 0.1µF 5pF Figure 59. Frequency Response Measurements SPECTRUM ANALYZER 0.1µF 0.1µF INH OPL 50Ω 1kΩ INL OPH AD8432 AD8129 1kΩ 0.1µF 0.1µF LNA1 G = 10 Figure 60. Voltage Noise Measurements Rev. B | Page 16 of 28 08341-048 08341-047 08341-049 08341-046 AD8432 5pF 0.1µF R FB 10MHz 499Ω DIFF X MULTIPLIER 0.1µF 0.1µF OSCILLOSCOPE PROBE INH OPL CH1 R Y SH INL OPH C SH AD8432 0.1µF 499Ω 5pF LNA1 1MHz 0.1µF Figure 61. Overdrive Recovery Measurements 499Ω 5pF 0.1µF R FB NETWORK ANALYZER 0.1µF 0.1µF 50Ω OUT INH OPL 0.1µF R SH INL OPH C SH 499Ω 5pF AD8432 0.1µF LNA1 Figure 62. Input Impedance vs. Frequency Measurements R 0.1µF FB NETWORK ANALYZER 0.1µF 0.1µF 50Ω INH OPL 0.1µF R SH INL OPH C SH 499Ω AD8432 LNA1 0.1µF Figure 63. Output Impedance vs. Frequency Measurements R 0.1µF FB SPECTRUM ANALYZER 0.1µF 0.1µF +IN OPL1 INH1 50Ω R 1kΩ OUT S –IN OPH1 AD8129 INL1 1kΩ AD8432 G = 10 0.1µF 0.1µF LNA1 Figure 64. Noise Figure Measurements Rev. B | Page 17 of 28 08341-052 08341-054 08341-051 08341-050 AD8432 THEORY OF OPERATION differential gain of G = 12.04 dB, the maximum input voltage LOW NOISE AMPLIFIER (LNA) allowed is 1.2 V p-p. The AD8432 is a dual-channel, ultralow noise amplifier with integrated pin-strappable, gain-setting resistors. The resistors Clamping the inputs ensures quick recovery from large input voltages. The input back-to-back diodes, which are integrated can be externally connected to achieve differential gains of inside the die (IND1 and IND2), should be used for the lowest gain 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (×4, ×8, ×12, and configuration (12.04 dB) to protect the input from overdriving. ×16, respectively). A simplified schematic of an LNA is shown They should be connected after the source resistance or before in Figure 65. the INH coupling capacitor. The LNA is driven with a single-ended input and measured The use of a fully differential topology and negative feedback differentially at the output. The inverting input INL must be ac-coupled to ground through a capacitor for proper operation. minimizes distortion. A differential signal enables smaller swings at The LNA cannot be driven differentially due to the asymmetry each output, which results in reduction of third-order distortion. of the internal gain setting resistors. The gain from the inverting The AD8432 is a voltage feedback amplifier. Due to gain band- input INL to the single-ended output (OPH or OPL) does not width product (GBW), a decrease in bandwidth should be match the gain from the noninverting input INH to the single- expected as the gain increases. Table 5 displays the values of the ended output. −3 dB bandwidth for each gain with unterminated input impedance. The AD8432 inputs have a dc bias voltage of 3.25 V, which is generated internally. The inputs must be ac-coupled through a GAIN SETTING TECHNIQUE series capacitor to maintain the dc bias level of the inputs. Likewise, Pin strapping is used to set the gain of the amplifier. Gain setting the AD8432 outputs have a dc bias voltage of 2.5 V. An ac coupling resistors are integrated in the LNA and are accessible externally capacitor in series with each single-ended output is recommended through the GOH, GMH, GML, and GOL pins. By externally to prevent improper loading of the outputs. The AD8432 inputs shorting these pins, and thereby shorting or connecting the have a dc bias voltage of 3.25 V, which is generated internally. internal resistors, the AD8432 can be configured for four different The inputs must be ac-coupled through a series capacitor to gains. Table 5 shows which pins must be connected to achieve maintain the dc bias level of the inputs (see CINL and CINH the desired gain. in Figure 65). The AD8432 supports a differential output voltage of 4.8 V p-p for the common-mode output voltage of 2.5 V. Therefore, for a C R FB FB VPS I I OPL OPH INL Q1 Q2 CINH RG4 RG3 RG2 RG1 RG5 RG6 RG7 R CINL SH INH 48Ω 24Ω 12Ω 12Ω 24Ω 24Ω 48Ω C SH GND I I R S GOH GMH GML GOL GND V S GND Figure 65. Simplified Schematic of LNA Rev. B | Page 18 of 28 08341-039 AD8432 Table 5. Gain Setting Using a Pin-Strapping Technique and −3 dB Bandwidth for Each Gain Configuration Differential Single −3 dB Gain (dB) Gain (dB) BW (MHz) RG1 (Ω) RG2 (Ω) RG3 (Ω) RG4 (Ω) RG5 (Ω) RG6 (Ω) RG7 (Ω) 12.04 6.02 200 12 12 Connect Connect 24 Connect Connect GMH to GOH GOH to OPH GML to GOL GOL to OPL 18.06 12.04 90 12 12 24 Connect 24 24 Connect GOH to OPH GOL to OPL 21.58 15.56 50 12 12 Connect 48 24 Connect 48 GMH to GOH GML to GOL 24.08 18.06 32 12 12 24 48 24 24 48 The single-ended gain from INH to OPH (see Figure 65) is R IN R S INH defined as V LNA OUT V R +R +R +R IN G1 G2 G3 G4 G = UNTERMINATED OPH−INH R G1 R IN The single-ended gain from INH to OPL is defined as R S INH V LNA OUT R +R +R G5 G6 G7 R S V G =− IN OPL−INH RESISTIVE R G1 TERMINATION The values of the seven gain resistors were chosen so that both R FB single-ended gains are equal. For example, to set a gain of R IN 12.04 dB (G = ×4) differentially, the gain from INH to each R INH S V LNA OUT output (OPH, OPL) should be 6.02 dB (G = ×2). V IN INH to OPH: For R = R = R , then ACTIVE G1 G2 G IMPEDANCE MATCH 2×R R +R G G1 G2 Figure 66. Input Resistance Matching G = = = 2 OPH−INH R R G1 G To achieve this active impedance match, connect a feedback resistor, R , between the INH and OPL (see Figure 66). R is INH to OPL: For R = R and R = 2 × R , then FB IN G1 G G5 G given in Equation 1, where G/2 is the single-ended gain. R 2×R G G5 G =− =− =−2 OPL−INH R FB R R G1 G R = (1) IN G 1+ ACTIVE INPUT RESISTANCE MATCHING 2 The AD8432 reduces noise and optimizes signal power transfer In addition, to further reduce the input resistance, there is an by using active input termination to perform signal source internal resistance of 6.2 kΩ in parallel with the source resistance, resistance matching. such that The primary purpose of input impedance matching is to optimize R FB R = R (2) IN INTERNAL the input signal power transfer. With resistive termination, the G 1+ input noise increases due to the thermal noise of the terminating 2 resistor and the increased contribution of the input voltage Equation 3 should be used to calculate R accurately for a desired FB noise generator of the LNA. With active impedance matching, input resistance and single-ended gain. Refer to Table 6 for however, the contributions of both are smaller than they are for calculated results for R for several input resistance and gain FB resistive termination by a factor of 1/(1 + ½ LNA) gain. The combinations. noise figure (NF) for the three terminating schemes is shown in G Figure 67.   R 1+   IN  2 ⇒R = , R = 6.2 kΩ (3) FB INTERNAL R IN 1− R INTERNAL Rev. B | Page 19 of 28 08341-009 AD8432 8 The user must determine the level of matching accuracy desired and adjust R accordingly. The R and C network presents a FB FB FB 7 load to OPL that OPH does not see. The user can add an identical 6 load on OPH to improve slightly the distortion caused by this RESISTIVE TERMINATION imbalance. 5 (R = R ) S IN There is a feedback capacitor (CFB) in series with RFB (see 4 ACTIVE IMPEDANCE Figure 65) because the dc levels of the positive output and the MATCH 3 positive input are different. At higher frequencies, the value of the feedback capacitor must be considered. 2 UNTERMINATED The unterminated bandwidth (R = ∞) is 200 MHz. The AD8432 FB 1 has a low input-referred voltage noise of 0.85 nV/√Hz at the (SIMULATED RESULTS) 0 lowest gain, 12.04 dB (unterminated configuration). To achieve 50 100 1k such low noise, the dual amplifier consumes 24 mA, resulting in R (Ω) S a power consumption of 120 mW. Figure 67. Noise Figure vs. R for Resistive, Active Match, and S Unterminated Inputs 18 R = 1kΩ IN R = 200Ω IN 16 = 100Ω R IN R = 75Ω IN R = 50Ω 14 IN R = UNTERMINATED IN 12 10 8 6 4 2 (SIMULATED RESULTS) 0 50 100 1k R (Ω) S Figure 68. Noise Figure vs. RS for Various Values of RIN, Actively Matched Table 6. Feedback Resistance for Several RIN and Gain Combinations Single-Ended Gain, Exact RFB (Ω), Actual RIN (Ω), Desired RIN (Ω) Differential Gain (V/V) G/2 (V/V) Equation 2 RFB (Ω), 1% Standard Value Equation 2 50 4 2 151.2 150 49.6 75 4 2 227.8 226 74.4 100 4 2 304.9 301 98.7 200 4 2 620 619 199.7 1 k 4 2 3.58 k 3.57 k 998.4 50 8 4 252 250 49.6 100 8 4 508.2 511 100.5 50 12 6 352.9 357 50.6 100 12 6 711.5 715 100.5 50 16 8 453.7 453 49.9 100 16 8 914.8 909 99.4 Rev. B | Page 20 of 28 NOISE FIGURE (dB) NOISE FIGURE (dB) 08341-268 08341-267 AD8432 APPLICATIONS INFORMATION The AD8432 LNA provides precision gain and ultralow noise The unterminated input impedance of the AD8432 is 6.2 kΩ. performance with minimal external components. Because it is Any input resistance between 50 Ω and 6.2 kΩ can be synthesized a high performance part, care must be taken to ensure that it is using active impedance matching. configured optimally to attain the best performance and dynamic At the lowest gain (12.04 dB), the gain response exhibits some range for the system. peaking at higher frequencies. A resistor-capacitor shunt net- work (RC) at the input (see RSHx and CSHx in Figure 69) is TYPICAL SETUP recommended to reduce gain peaking and enhance stability at The internal bias circuitry of the AD8432 sets the input bias higher frequencies. voltage at 3.25 V and the output bias voltage at 2.5 V. It is important to ac couple the inputs through a capacitor to maintain the internal Table 7 shows the recommended values of RFB, CSH, and RSH for dc bias levels. When active input termination is used (R ), a all four gains and several input impedance combinations. The FB decoupling capacitor (C ) is required to isolate the input and values for the CSH and RSH network are determined empirically FB output bias voltages of the LNA. A typical value for C is 0.1 μF, but and can be customized as needed to optimize performance. As FB R increases, the value of C diminishes, and for higher input a smaller value capacitor is more appropriate at higher frequencies. IN SH impedance values, no capacitor may be required. C FB1 0.1µF R FB1 FB G = 12dB 120nH 0.1µF 0.1µF ENB VPS1 COMM VPS2 BIAS FB 0.1µF 120nH 0.1µF INH1 OPH1 IN1 OUT1+ IND1 R SH1 R C LNA1 L L 15Ω OPL1 OUT1– C SH1 0.1µF 47pF GMH1 GOH1 INL1 GOL1 0.1µF GML1 FB 120nH 0.1µF 0.1µF INH2 OPH2 IN2 OUT2+ IND2 R SH2 R C LNA2 L L 15Ω OPL2 OUT2– C SH2 0.1µF 47pF GMH2 GOH2 INL2 GOL2 0.1µF GML2 AD8432 C FB2 0.1µF R FB2 Figure 69. Typical AD8432 Setup, G = 12.04 dB Rev. B | Page 21 of 28 08341-040 AD8432 Table 7. External Component Selections for Common Input Impedance R (Ω) Gain (dB) R (Ω) C (pF) R (Ω) −3 dB BW (MHz) IN FB SH SH 50 12 150 47 15 176 18 249 30 15 116 21 357 None None 117 24 453 None None 87 75 12 226 36 15 167 18 383 None None 144 21 536 None None 100 24 681 None None 72 100 12 301 30 15 164 18 511 None None 134 21 715 None None 90 24 909 None None 63 200 12 619 18 15 164 18 1.02 k None None 116 21 1.43 k None None 74 24 1.87 k None None 51 1 k 12 3.57 k 10 10 160 18 5.9 k None None 99 21 8.25 k None None 61 24 10.7 k None None 43 Unterminated, R = 50 Ω 12 ∞ None None 178 S 18 ∞ None None 95 21 ∞ None None 59 24 ∞ None None 40 Unterminated, R = 0 Ω 12 ∞ None None 210 S 18 ∞ None None 96 21 ∞ None None 55 24 ∞ None None 38 Rev. B | Page 22 of 28 AD8432 4LOP and 4LON pins of the AD8339, has a frequency 4× that of I/Q DEMODULATION FRONT END the RF inputs. The AD8339 downconverts the RF signals, The AD8432 low noise amplifiers can be used to drive the generates quadrature, and phase-shifts the resultant I and Q differential RF inputs of the dual AD8333 or the quad AD8339 signals. I/Q demodulators. The primary application for the AD8339 is phased array beamforming in medical ultrasound, specifically The I and Q outputs of the AD8339 are current outputs. A in CW Doppler processing. Other applications include phased transimpedance amplifier, such as the AD8021, processes the array radar and smart antennas for mobile communications. outputs and performs several functions, including the following: AD8021 • Current-to-voltage conversion Q1 • Summation amplifier for multiple channels 0.1µF 20Ω 787Ω • Active low-pass filter RF1P Q1OP 2.2nF AD8339 AD8432 In beamforming applications, the I and Q outputs of a number 2.2nF RF1N I1OP of receiver channels are summed, which increases the system 20Ω 787Ω 0.1µF 4LO dynamic range by 10 log (N), where N is the number of 10 I1 0.1µF channels being summed. The external RC feedback network of the AD8021 is a 100 kHz low-pass filter as shown in Figure 70. AD8021 See the AD8333 and AD8339 datasheets for more details on Figure 70. Block Diagram of AD8432 and AD8339 Application for implementing I/Q demodulators. Ultrasound Beamforming Evaluation boards are available for the AD8432 and the AD8339 Because of its low output noise and low distortion, the AD8432 to facilitate system level design and testing. A detailed reference ensures minimal degradation in dynamic range while amplifying schematic of the setup is shown in Figure 71. The AD8432 is the RF input signal. At the lowest gain of 12.04 dB, the AD8432 shown in this configuration with a gain of 12.04 dB, with contributes only 3.4 nV/√Hz output voltage noise. unterminated inputs. If active termination is preferred, use an Figure 70 shows a simplified block diagram of one channel of R and C network as discussed in the Theory of Operation FB FB the AD8432 driving the AD8339. The AD8432 outputs can be section. The IND1/IND2 clamping diodes can be connected to connected directly to the AD8339 RF inputs through 20 Ω IN1/IN2 to protect the LNA input from being overdriven. resistors. A differential clock signal, 4LO, which is applied to the 4LO 0.1µF +5V −5V +5V 0.1µF 787Ω 0.1µF 0.1µF 0.1µF 2.2nF ENB VPS1 VPS2 COMM VPOS VNEG 4LOP 2 7 BIAS – 0Ω 6 0.1µF IN1 Q1 + Q2 INH1 AD8021 20Ω RF1P Q1OP OPH1 + IND1 R 3 SH1 LNA1 20Ω OPL1 RF1N I1OP 4 15Ω C GMH1 0.1µF SH1 47pF GOH1 INL1 −5V GOL1 +5V 0.1µF GML1 IN2 INH2 787Ω 20Ω OPH2 RF2P Q2OP IND2 0.1µF 0.1µF 2.2nF LNA2 R 20Ω SH2 OPL2 RF2N I2OP 15Ω 2 7 GMH2 – C SH2 0Ω GOH2 6 47pF I1 + I2 INL2 AD8339 AD8021 GOL2 + GML2 G = –1.3dB 0.1µF 3 4 AD8432 LPF 0.1µF f = 100kHz C G = 12dB −5V Figure 71. Schematic of the AD8432 (G = 12.04 dB) and AD8339 Application for Ultrasound Beamforming Rev. B | Page 23 of 28 08341-041 08341-043 AD8432 A transformer or balun can also be used to convert the differential DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION output of the AD8432 to a single-ended output. Transformers Some applications require the low noise and high dynamic have lower distortion; however, care must be taken to properly range of the AD8432; however, they may also require a single- match the impedance of the transformer. The test circuit for ended output, rather than a differential output. The AD8129 distortion measurements in Figure 58 uses an ADTT1-1 or AD8130 differential receiver amplifier can be used for the transformer to perform differential-to-single-ended conversion. differential-to-single-ended conversion of the AD8432 output, as shown in Figure 72. The AD8129 is a low noise, high gain (10 or greater) amplifier intended for applications over very long cables, where signal attenuation is significant. The AD8130 is stable at a gain of 1 and can be used for applications where lower gains are required. The AD8129 and AD8130 have user-adjustable gain, set by the ratio of two resistors, to help compensate for losses in the transmission line. 0.1µF 0.1µF ENB VPS1 VPS2 COMM +V S AC-COUPLING CAPS SERIES 20Ω BIAS (AD8432 HAS 2.5V RESISTORS IF DRIVING HIGH CAP LOAD OUTPUT BIAS) 0.1µF IN1 INH1 20Ω 0.1µF OPH1 1 + 7 IND1 R 8 – SH1 LNA1 20Ω 0.1µF V OPL1 OUT1 6 15Ω 4 C GMH1 SH1 499Ω 499Ω + 5 2 47pF – GOH1 INL1 AD8130 GOL1 0.1µF GML1 499Ω RESISTORS PROVIDE BIAS CURRENT PATH AND G = 12 dB TERMINATION IF NECESSARY –V S Figure 72. AD8432 Differential-to-Single-Ended Conversion Using the AD8129/AD8130 with Unity Gain Rev. B | Page 24 of 28 08341-044 AD8432 EVALUATION BOARD Figure 73 shows the AD8432 evaluation board, and the schematic Table 8 outlines the resistors or headers that must be installed or diagram is shown in Figure 74. Using the board is a convenient shorted for each gain configuration. and fast way to verify system design and assess the performance of Table 8. Gain Setting Using Resistors or Headers the AD8432 under user-specific operating conditions. The Gain (V/V) board provides access to all LNA inputs, outputs, and gain setting LNA1 LNA2 4 8 12 16 pins. The board is shipped in a typical G = 12.04 dB configuration 1 1 R1 W5 R9 W9 X X but is designed to allow customization of the setup as required. 1 1 R2 W6 R10 W10 X X The AD8432-EVALZ requires a single 5 V power supply. An 1 1 R3 W7 R11 W11 X X on-board switch (S1) allows VPS to drive the enable (ENB) input. 1 1 R4 W8 R12 W12 X X GAIN SETTING 1 X = shorting the indicated header or resistor. Headers (W5 to W12) are provided across the gain setting pins and can be shorted using jumpers to allow gain setting quickly and easily. Alternately, it is recommended to short the gain setting pins using surface-mount (0402), 0 Ω resistors (R1 to R4, R9 to R12) that eliminate the small parasitic capacitances from longer trace lengths to the headers. As shipped, the evaluation board is configured for G = 12.04 dB with these 0 Ω resistors. Figure 73. Evaluation Board Rev. B | Page 25 of 28 08341-045 AD8432 SCHEMATIC GML1 19 12 GML2 GMH1 20 11 GMH2 GOH1 21 10 GOH2 OPH1 22 9 OPH2 VPS1 23 8 VPS2 ENB 24 7 IND2 Figure 74. Schematic Rev. B | Page 26 of 28 BANANA BANANA VPOS GND JACK JACK VPOS AD8432 EVALUATION BOARD GND C FB1 SCHEMATIC W3 0.1µF R FB 1 DNI DNI TEST POINT GND1 GND2 GND3 OPH1 L3 120nH FB GOH1 GMH1 VPS1 W5 W7 W6 GML1 +5V C9 R7 OPH1 C3 0.1µF R5 453Ω ENB R1 R2 R3 0.1µF DNI DNI DNI ENABLE 0Ω 0Ω 0Ω DISABLE S1 RL1 DNI C7 CL1 PRB3 0.1µF T1 DNI 4 1 C5 L1 GOL1 PIN 1 DNI R17 2 0.1µF INH1 IN1 120nH FB IDENTIFIER 0Ω VOUT1 C8 DNI CL2 3 0.1µF C10 6 R 1 18 INH1 GOL1 DNI SH1 R4 DNI 0.1µF INL1 W8 PRB1 RL2 15Ω 0Ω C DNI SH1 DNI 2 17 47pF INL1 OPL1 C1 R6 R8 0.1µF OPL1 OPL1 DNI 453Ω IND1 3 16 W1 AD8432 COM1 COM1 DNI TOP VIEW COMM C14 (Not to Scale) R16 COMM 4 15 COM2 OPL2 0.1µF R14 INL2 OPL2 453Ω DNI DNI DNI PIN 0 INL2 5 14 OPL2 C2 EXPOSED PADDLE INH2 RL4 0.1µF (TIED TO GND) L2 R12 W12 DNI C12 IN2 CL4 120nH FB INH2 6 13 GOL2 0Ω PRB4 0.1µF T2 DNI 4 1 DNI R18 R 2 SH2 C6 0Ω PRB2 15Ω VOUT2 C11 0.1µF GOL2 DNI CL3 3 C 0.1µF C13 6 SH 2 DNI DNI 0.1µF 47pF RL3 DNI DNI W2 R11 R9 R10 0Ω R13 R15 C4 0Ω 0Ω OPH2 453Ω DNI 0.1µF DNI GML2 W9 W10 W11 GOH2 VPS2 GMH2 L4 C FB2 GND4 GND5 GND6 120nH FB 0.1µF R FB2 DNI DNI OPH2 W4 VPOS 08341-042 AD8432 OUTPUT POWER SUPPLY The AD8432 evaluation board provides the space to configure The AD8432 should be powered by a single 5 V supply connected the output loading conditions required by the user, by populating to the VPOS terminal. Separate supplies can be used for VPS1, the given footprints (for example, RL1, RL2, C7, and C8). SMA VPS2, and ENB, or they can all be tied to VPOS by shorting connectors are available at the outputs, and space for a transformer the W3 and W4 headers and the S1 switch. Ferrite beads and is also available for differential-to-single-ended conversion. decoupling capacitors are installed for isolation, protection, and power supply noise reduction. The 4-pin headers, PRB3 and PRB4, are placed close to the AD8432, and they provide a way for monitoring the differential output or INPUT TERMINATION the single-ended output using a high impedance differential probe. Active input impedance matching can be realized by installing The two inner pins of the headers are connected to OPL/OPH, a feedback resistor (R ), the value of which is determined by FB and the two outer pins of the headers are connected to ground. the gain and source impedance, as described in the Theory of There are several footprints provided to install ac coupling Operation section. C provides the necessary ac coupling FB capacitors at the outputs (C7 to C14). The AD8432 outputs are between the input and output when using active termination; biased internally at 2.5 V. To maintain the dc bias level, use coupling a 0.1 µF capacitor value is recommended. The R and C network FB FB capacitors between the outputs and the load. presents a load to OPL, and an equivalent load at OPH can be used to balance the differential output. Input clamping diodes (IND1 and IND2) can be connected to the inputs by shorting the connection on the W1 and W2 headers. The diodes provide overvoltage protection to the input and enable faster overdrive recovery times, especially at the lowest gain (12.04 dB). Rev. B | Page 27 of 28 AD8432 OUTLINE DIMENSIONS 4.10 0.30 4.00 SQ 0.25 3.90 0.18 PIN 1 INDICATOR 19 24 0.50 18 1 BSC EXPOSED 2.65 PAD 2.50 SQ 2.45 13 6 12 7 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. Figure 75. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm, Very Very Thin Quad (CP-24-7) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8432ACPZ-R7 −40°C to +85°C 24-Lead LFCSP_WQ, 7” Tape and Reel CP-24-7 AD8432ACPZ-RL −40°C to +85°C 24-Lead LFCSP_WQ, 13” Tape and Reel CP-24-7 AD8432ACPZ-WP −40°C to +85°C 24-Lead LFCSP_WQ, Waffle Pack CP-24-7 AD8432-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08341-0-3/11(B) Rev. B | Page 28 of 28 PIN 1 INDICATOR 112108-A