ANALOG DEVICES AD8429

1 nV/√Hz Low Noise Instrumentation Amplifier AD8429 FEATURES PIN CONNECTION DIAGRAM Low noise AD8429 –IN 1 8 +V S 1 nV/√Hz input noise R 2 7 V G OUT 45 nV/√Hz output noise R 3 6 REF G High accuracy dc performance (AD8429BRZ) +IN 4 5 –V S 90 dB CMRR minimum (G = 1) 50 μV maximum input offset voltage TOP VIEW (Not to Scale) 0.02% maximum gain accuracy (G = 1) Figure 1. Excellent ac specifications 80 dB CMRR to 5 kHz (G = 1) 15 MHz bandwidth (G = 1) 1.2 MHz bandwidth (G = 100) 22 V/μs slew rate THD: −130 dBc (1 kHz, G = 1) Versatile ±4 V to ±18 V dual supply Gain set with a single resistor (G = 1 to 10,000) Temperature range for specified performance −40°C to +125°C APPLICATIONS Medical instrumentation Precision data acquisition Microphone preamplification Vibration analysis GENERAL DESCRIPTION The AD8429 is an ultralow noise, instrumentation amplifier be useful to shift the output level when interfacing to a single designed for measuring extremely small signals over a wide supply signal chain. temperature range (−40°C to +125°C). The AD8429 performance is specified over the extended industrial The AD8429 excels at measuring tiny signals. It delivers ultralow temperature range of −40°C to +125°C. It is available in an 8-lead input noise performance of 1 nV/√Hz. The high CMRR of the plastic SOIC package. 1000 AD8429 prevents unwanted signals from corrupting the acqui- sition. The CMRR increases as the gain increases, offering high rejection when it is most needed. The high performance pin 100 configuration of the AD8429 allows it to reliably maintain high G = 1 CMRR at frequencies well beyond those of typical instrumentation amplifiers. 10 The AD8429 reliably amplifies fast changing signals. Its current G = 10 feedback architecture provides high bandwidth at high gain, for example, 1.2 MHz at G = 100. The design includes circuitry to im- G = 100 1 G = 1k prove settling time after large input voltage transients. The AD8429 was designed for excellent distortion performance, allowing use in demanding applications such as vibration analysis. 0.1 1 10 100 1k 10k 100k Gain is set from 1 to 10,000 with a single resistor. A reference FREQUENCY (Hz) pin allows the user to offset the output voltage. This feature can Figure 2. RTI Voltage Noise Spectral Density vs. Frequency Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. NOISE (nV/√Hz) 09730-001 09730-002 AD8429 TABLE OF CONTENTS Features .............................................................................................. 1 Architecture ................................................................................ 15 Applications....................................................................................... 1 Gain Selection............................................................................. 15 Pin Connection Diagram ................................................................ 1 Reference Terminal .................................................................... 15 General Description ......................................................................... 1 Input Voltage Range................................................................... 16 Revision History ............................................................................... 2 Layout .......................................................................................... 16 Specifications..................................................................................... 3 Input Bias Current Return Path ............................................... 17 Absolute Maximum Ratings............................................................ 6 Input Protection ......................................................................... 17 Thermal Resistance ...................................................................... 6 Radio Frequency Interference (RFI)........................................ 17 ESD Caution.................................................................................. 6 Calculating the Noise of the Input Stage................................. 18 Pin Configuration and Function Descriptions............................. 7 Outline Dimensions....................................................................... 19 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 19 Theory of Operation ...................................................................... 15 REVISION HISTORY 4/11—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD8429 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted. Table 1. A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ V = ±10 V CM Source Imbalance G = 1 80 90 dB G = 10 100 110 dB G = 100 120 130 dB G = 1000 134 140 dB CMRR at 5 kHz V = ±10 V CM G = 1 76 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 90 90 dB VOLTAGE NOISE, RTI VIN+, VIN− = 0 V 1 Spectral Density : 1 kHz Input Voltage Noise, e 1.0 1.0 nV/√Hz ni Output Voltage Noise, e 45 45 nV/√Hz no Peak to Peak: 0.1 Hz to 10 Hz G = 1 2 2 μV p-p G = 1000 100 100 nV p-p CURRENT NOISE Spectral Density: 1 kHz 1.5 1.5 pA/√Hz Peak to Peak: 0.1 Hz to 10 Hz 100 100 pA p-p 2 VOLTAGE OFFSET Input Offset, VOSI 150 50 μV Average TC 0.1 1 0.1 0.3 μV/°C Output Offset, V 1000 500 μV OSO Average TC 3 10 3 10 μV/°C Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V G = 1 90 100 dB G = 10 110 120 dB G = 100 130 130 dB G = 1000 130 130 dB INPUT CURRENT Input Bias Current 300 150 nA Average TC 250 250 pA/°C Input Offset Current 100 30 nA Average TC 15 15 pA/°C DYNAMIC RESPONSE Small Signal Bandwidth: –3 dB G = 1 15 15 MHz G = 10 4 4 MHz G = 100 1.2 1.2 MHz G = 1000 0.15 0.15 MHz Rev. 0 | Page 3 of 20 AD8429 A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit Settling Time 0.01% 10 V step G = 1 0.75 0.75 μs G = 10 0.65 0.65 μs G = 100 0.85 0.85 μs G = 1000 5 5 μs Settling Time 0.001% 10 V step G = 1 0.9 0.9 μs G = 10 0.9 0.9 μs G = 100 1.2 1.2 μs G = 1000 7 7 μs Slew Rate G = 1 to 100 22 22 V/μs THD First five harmonics, f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p G = 1 −130 −130 dBc G = 10 −116 −116 dBc G = 100 −113 −113 dBc G = 1000 −111 −111 dBc THD + N f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p G = 100 0.0005 0.0005 % 3 GAIN G = 1 + (6 kΩ/R) G Gain Range 1 10000 1 10000 V/V Gain Error VOUT = ±10 V G = 1 0.05 0.02 % G > 1 0.3 0.15 % Gain Nonlinearity VOUT = −10 V to +10 V G = 1 to 1000 RL = 10 kΩ 2 2 ppm Gain vs. Temperature G = 1 2 5 2 5 ppm/°C G > 1 −100 −100 ppm/°C INPUT 4 Impedance (Pin to Ground) 1.5||3 1.5||3 GΩ||pF Input Operating Voltage VS = ±4 V to ±18 V −VS + 2.8 +VS − 2.5 −VS + 2.8 +VS − 2.5 V 5 Range OUTPUT Output Swing R = 2 kΩ −V + 1.8 +Vs − 1.2 −V + 1.8 +Vs − 1.2 V L S S Over Temperature −VS + 1.9 +Vs − 1.3 −VS + 1.9 +Vs − 1.3 V Output Swing R = 10 kΩ −V + 1.7 +Vs − 1.1 −V + 1.7 +Vs − 1.1 V L S S Over Temperature −V + 1.8 +Vs − 1.2 −V + 1.8 +Vs − 1.2 V S S Short-Circuit Current 35 35 mA REFERENCE INPUT RIN 10 10 kΩ IIN VIN+, VIN− = 0 V 70 70 μA Voltage Range −V +V V S S Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.05 0.01 0.05 % Rev. 0 | Page 4 of 20 AD8429 A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit POWER SUPPLY Operating Range ±4 ±18 ±4 ±18 V Quiescent Current 6.7 7 6.7 7 mA T = 125°C 9 9 mA TEMPERATURE RANGE For Specified Performance −40 +125 −40 +125 °C 1 2 2 2 Total voltage noise = √(eni + (eno/G) + eRG ). See the Theory of Operation section for more information. 2 Total RTI VOS = (VOSI) + (VOSO/G). 3 These specifications do not include the tolerance of the external gain setting resistor, R . For G > 1, add R errors to the specifications given in this table. G G 4 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 5 Input voltage range of the AD8429 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more details. Rev. 0 | Page 5 of 20 AD8429 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. θ is specified for a device in free air using a 4-layer JEDEC JA Parameter Rating printed circuit board (PCB). Supply Voltage ±18 V Output Short-Circuit Current Duration Indefinite Table 3. 1 Maximum Voltage at –IN, +IN ±V S Package θ Unit JA 1 Differential Input Voltage 8-Lead SOIC 121 °C/W Gain ≤ 4 ±VS 4 > Gain > 50 ±50 V/gain Gain ≥ 50 ±1 V ESD CAUTION Maximum Voltage at REF ±V S Storage Temperature Range −65°C to +150°C Specified Temperature Range −40°C to +125°C Maximum Junction Temperature 140°C ESD Human Body Model 3.0 kV Charge Device Model 1.5 kV Machine Model 0.2 kV 1 For voltages beyond these limits, use input protection resistors. See the Theory of Operation section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 20 AD8429 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8429 –IN 1 8 +V S 2 7 R V G OUT R 3 6 REF G 4 5 +IN –V S TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input Terminal. 2, 3 RG Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (6 kΩ/RG). 4 +IN Positive Input Terminal. 5 −V Negative Power Supply Terminal. S 6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level shift the output. 7 V Output Terminal. OUT 8 +VS Positive Power Supply Terminal. Rev. 0 | Page 7 of 20 09730-003 AD8429 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, VS = ±15, VREF = 0, RL = 10 kΩ, unless otherwise noted. 15 160 GAIN = 1000 V = ±15V S G = 1 GAIN = 100 GAIN = 10 140 10 GAIN = 1 V = ±12V 120 S 5 100 V = ±5V 0 80 S 60 –5 40 –10 20 –15 0 –15 –10 –5 0 5 10 15 1 10 100 1k 10k 100k 1M OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 4. Input Common-Mode Voltage vs. Output Voltage, Figure 7. Positive PSRR vs. Frequency Dual Supply, V = ±5 V, ±12 V, ±15 V (G = 1) S 160 15 GAIN = 1000 V = ±15V G = 100 S GAIN = 100 GAIN = 10 140 GAIN = 1 10 120 V = ±12V S 5 100 0 V = ±5V 80 S 60 –5 40 –10 20 –15 0 1 10 100 1k 10k 100k 1M –15 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 5. Input Common-Mode Voltage vs. Output Voltage, Figure 8. Negative PSRR vs. Frequency Dual Supply, V = ±5 V, ±12 V, ±15 V (G = 100) S 0 70 V = ±15V S GAIN = 1000 –5 60 –10 50 GAIN = 100 –15 40 –12.28V –20 30 GAIN = 10 –25 20 +12.60V –30 10 GAIN = 1 –35 0 –40 –10 –45 –20 –50 –30 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 100 1k 10k 100k 1M 10M 100M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 6. Input Bias Current vs. Common-Mode Voltage Figure 9. Gain vs. Frequency Rev. 0 | Page 8 of 20 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) INPUT BIAS CURRENT (nA) 09730-068 09730-011 09730-010 GAIN (dB) POSITIVE PSRR (dB) NEGATIVE PSRR (dB) 09730-070 09730-069 09730-017 AD8429 160 40 3.0 I + B G = 1k I – B 140 I G = 100 OS 30 2.5 G = 10 120 20 2.0 G = 1 100 BANDWIDTH LIMITED 10 1.5 80 60 0 1.0 40 –10 0.5 20 –20 0 0 1 10 100 1k 10k 100k 1M –45 –30 –15 0 15 30 45 60 75 90 105 120 135 TEMPERATURE (°C) FREQUENCY (Hz) Figure 13. Input Bias Current and Input Offset Current vs. Temperature Figure 10. CMRR vs. Frequency 40 140 G = 100 GAIN = 1 G = 1k 30 120 G = 10 20 100 10 G = 1 0 80 BANDWIDTH –10 LIMITED 60 –20 –30 40 –40 20 –50 NORMALIZED AT 25°C –60 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 1 10 100 1k 10k 100k 1M TEMPERATURE (°C) FREQUENCY (Hz) Figure 11. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 14. CMRR vs. Temperature (G = 1), Normalized at 25°C 12 10.0 9.5 10 9.0 8.5 8 8.0 6 7.5 7.0 4 6.5 6.0 2 5.5 0 5.0 0 100 200 300 400 500 600 700 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) WARM-UP TIME (s) Figure 12. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time Figure 15. Supply Current vs. Temperature (G = 1) Rev. 0 | Page 9 of 20 CHANGE IN INPUT OFFSET VOLTAGE (µV) CMRR (dB) CMRR (dB) 09730-112 09730-111 09730-110 INPUT BIAS CURRENT (nA) SUPPLY CURRENT (mA) CMRR (µV/V) INPUT OFFSET CURRENT (nA) 09730-114 09730-022 09730-019 AD8429 50 +V S +125°C –0.5 +85°C 40 I SHORT+ +25°C –1.0 –40°C 30 –1.5 20 –2.0 10 –2.5 0 +2.5 –10 +2.0 –20 I +1.5 SHORT– –30 +1.0 –40 +0.5 –V –50 S –40 –25 –10 5 20 35 50 65 80 95 110 125 41 6 8 10 12 14 168 SUPPLY VOLTAGE (±V ) TEMPERATURE (°C) S Figure 16. Short-Circuit Current vs. Temperature (G = 1) Figure 19. Input Voltage Limit vs. Supply Voltage 30 +V S –0.4 25 –0.8 –SR –1.2 20 +SR 15 +2.0 +1.6 10 +1.2 +0.8 +125°C 5 +85°C +0.4 +25°C –40°C 0 –V S –40 –25 –10 5 20 35 50 65 80 95 110 125 41 6 8 10 12 14 168 TEMPERATURE (°C) SUPPLY VOLTAGE (±V ) S Figure 17. Slew Rate vs. Temperature, VS = ±15 V (G = 1) Figure 20. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ 25 +V S –0.4 –SR 20 –0.8 –1.2 +SR 15 +2.0 10 +1.6 +1.2 5 +0.8 +125°C +85°C +0.4 +25°C –40°C –V 0 S 41 6 8 10 12 14 168 –40 –25 –10 5 20 35 50 65 80 95 110 125 SUPPLY VOLTAGE (±V ) TEMPERATURE (°C) S Figure 21. Output Voltage Swing vs. Supply Voltage, R = 2 kΩ Figure 18. Slew Rate vs. Temperature, V = ±5 V (G = 1) L S Rev. 0 | Page 10 of 20 SLEW RATE (V/µs) SLEW RATE (V/µs) SHORT-CIRCUIT CURRENT (mA) 09730-025 09730-024 09730-023 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 09730-028 09730-027 09730-026 AD8429 15 10 V = ±15V S GAIN = 1000 8 10 6 4 5 2 +125°C +85°C 0 0 +25°C –40°C –2 –5 –4 –6 –10 –8 –15 –10 –10 –8 –6 –4 –2 0246 8 10 100 1k 10k 100k LOAD (Ω) OUTPUT VOLTAGE (V) Figure 25. Gain Nonlinearity (G = 1000), R = 10 kΩ Figure 22. Output Voltage Swing vs. Load Resistance L +V 1000 S V = ±15V S –0.4 –0.8 100 –1.2 G = 1 –1.6 10 +2.0 G = 10 +1.6 G = 100 +1.2 1 G = 1k +125°C +0.8 +85°C +25°C +0.4 –40°C –V 0.1 S 1 10 100 1k 10k 100k 10µ 100µ 1m 10m OUTPUT CURRENT (A) FREQUENCY (Hz) Figure 23. Output Voltage Swing vs. Output Current Figure 26. RTI Voltage Noise Spectral Density vs. Frequency 10 GAIN = 1 8 GAIN = 1000, 100nV/DIV 6 4 2 GAIN = 1, 2μV/DIV 0 –2 –4 –6 –8 1s/DIV –10 –10 –8 –6 –4 –2 0246 8 10 OUTPUT VOLTAGE (V) Figure 24. Gain Nonlinearity (G = 1), R = 10 kΩ Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1, G = 1000) L Rev. 0 | Page 11 of 20 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) NONLINEARITY (ppm/DIV) REFERRED TO SUPPLY VOLTAGES 09730-083 09730-029 09730-030 NOISE (nV/√Hz) NONLINEARITY (ppm/DIV) 09730-086 09730-084 09730-126 AD8429 16 15 14 13 12 5V/DIV 11 10 750ns TO 0.01% 9 872ns TO 0.001% 8 7 6 0.002%/DIV 5 4 3 2µs/DIV 2 1 TIME (µs) 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 28. Current Noise Spectral Density vs. Frequency Figure 31. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step, V = ±15 V S 5V/DIV 640ns TO 0.01% 896ns TO 0.001% 0.002%/DIV 50pA/DIV 2µs/DIV 1s/DIV TIME (µs) Figure 29. 0.1 Hz to 10 Hz Current Noise Figure 32. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step, V = ±15 V S 30 G = 1 V = ±15V S 25 20 5V/DIV 840ns TO 0.01% 15 1152ns TO 0.001% 10 0.002%/DIV V = ±5V S 5 2µs/DIV 0 100 1k 10k 100k 1M 10M TIME (µs) FREQUENCY (Hz) Figure 30. Large Signal Frequency Response Figure 33. Large Signal Pulse Response and Settling Time (G = 100), 10 V Step, V = ±15 V S Rev. 0 | Page 12 of 20 OUTPUT VOLTAGE (V p-p) NOISE (pA/√Hz) 09730-088 09730-089 09730-087 09730-040 09730-091 09730-090 AD8429 G = 100 5V/DIV 5.04µs TO 0.01% 6.96µs TO 0.001% 0.002%/DIV 20mV/DIV 1µs/DIV 10µs/DIV TIME (µs) Figure 37. Small Signal Response (G = 100), R = 10 kΩ, C = 100 pF Figure 34. Large Signal Pulse Response and Settling Time (G = 1000), L L 10 V Step, VS = ±15 V G = 1000 G = 1 20mV/DIV 10µs/DIV 50mV/DIV 1µs/DIV Figure 35. Small Signal Response (G = 1), R = 10 kΩ, C = 100 pF L L Figure 38. Small Signal Response (G = 1000), R = 10 kΩ, C = 100 pF L L G = 10 G = 1 NO LOAD C = 100pF L C = 147pF L 20mV/DIV 1µs/DIV 50mV/DIV 1µs/DIV Figure 36. Small Signal Response (G = 10), R = 10 kΩ, C = 100 pF Figure 39. Small Signal Response with Various Capacitive Loads (G = 1), L L R = Infinity L Rev. 0 | Page 13 of 20 09730-043 09730-042 09730-041 09730-093 09730-045 09730-044 AD8429 1400 1 NO LOAD G = 1000, SECOND HARMONIC 2kΩ LOAD V = 10V p-p OUT 600Ω LOAD 1200 0.1 1000 SETTLED TO 0.001% 800 0.01 SETTLED TO 0.01% 600 400 0.001 200 0 0.0001 2 4 6 8 10 12 14 16 18 20 10 100 1k 10k 100k STEP SIZE (V) FREQUENCY (Hz) Figure 40. Settling Time vs. Step Size (G = 1) Figure 43. Second Harmonic Distortion vs. Frequency (G = 1000) 1 1 NO LOAD NO LOAD G = 1, SECOND HARMONIC G = 1000, THIRD HARMONIC 2kΩ LOAD 2kΩ LOAD V = 10V p-p V = 10V p-p OUT OUT 600Ω LOAD 600Ω LOAD 0.1 0.1 0.01 0.01 0.001 0.001 0.0001 0.0001 0.00001 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 41. Second Harmonic Distortion vs. Frequency (G = 1) Figure 44. Third Harmonic Distortion vs. Frequency (G = 1000) 1 1 NO LOAD G = 1, THIRD HARMONIC V = 10V p-p OUT 2kΩ LOAD V = 10V p-p OUT R ≥ 2kΩ L 600Ω LOAD 0.1 0.1 0.01 0.01 GAIN = 100 0.001 0.001 GAIN = 1000 GAIN = 10 0.0001 0.0001 GAIN = 1 0.00001 0.00001 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 42. Third Harmonic Distortion vs. Frequency (G = 1) Figure 45. THD vs. Frequency Rev. 0 | Page 14 of 20 AMPLITUDE (Percentage of Fundamental) AMPLITUDE (Percentage of Fundamental) SETTLING TIME (ns) 09730-092 09730-097 09730-096 THD (%) AMPLITUDE (Percentage of Fundamental) AMPLITUDE (Percentage of Fundamental) 09730-099 09730-098 09730-100 AD8429 THEORY OF OPERATION II V B I B I B COMPENSATION COMPENSATION R3 A1 A2 5kΩ +V C1 C2 S R4 5kΩ NODE 1 V A3 OUT NODE 2 +V R5 S +V +V S S R1 R2 5kΩ –V R6 S 3kΩ 3kΩ 5kΩ +V +V S S REF Q1 Q2 –IN +IN R G –V S –V –V S S RG– RG+ –V –V S S Figure 46. Simplified Schematic ARCHITECTURE Table 5. Gains Achieved Using 1% Resistors The AD8429 is based on the classic 3-op-amp topology. This 1% Standard Table Value of R Calculated Gain G topology has two stages: a preamplifier to provide differential 6.04 kΩ 1.993 amplification followed by a difference amplifier that removes 1.5 kΩ 5.000 the common-mode voltage and provides additional amplifica- 665 Ω 10.02 tion. Figure 46 shows a simplified schematic of the AD8429. 316 Ω 19.99 121 Ω 50.59 The first stage works as follows. To keep its two inputs matched, 60.4 Ω 100.3 Amplifier A1 must keep the collector of Q1 at a constant voltage. 30.1 Ω 200.3 It does this by forcing RG− to be a precise diode drop from –IN. 12.1 Ω 496.9 Similarly, A2 forces RG+ to be a constant diode drop from +IN. 6.04 Ω 994.4 Therefore, a replica of the differential input voltage is placed 3.01 Ω 1994 across the gain setting resistor, R . The current that flows through G this resistance must also flow through the R1 and R2 resistors, The AD8429 defaults to G = 1 when no gain resistor is used. creating a gained differential signal between the A2 and A1 Add the tolerance and gain drift of the R resistor to the G outputs. specifications of the AD8429 to determine the total gain accu- The second stage is a G = 1 difference amplifier, composed of racy of the system. When the gain resistor is not used, gain Amplifier A3 and the R3 through R6 resistors. This stage removes error and gain drift are minimal. the common-mode signal from the amplified differential signal. R Power Dissipation G The transfer function of the AD8429 is The AD8429 duplicates the differential voltage across its inputs V = G × (V − V ) + V OUT IN+ IN− REF onto the R resistor. Choose an R resistor size sufficient to G G where: handle the expected power dissipation. 6 kΩ REFERENCE TERMINAL G= 1+ R The output voltage of the AD8429 is developed with respect to G the potential on the reference terminal. This is useful when the GAIN SELECTION output signal must be offset to a precise midsupply level. For Placing a resistor across the R terminals sets the gain of the G example, a voltage source can be tied to the REF pin to level AD8429, which can be calculated by referring to Table 5 or by shift the output, allowing the AD8429 to drive a single-supply using the following gain equation: ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V. 6 kΩ R = G G−1 Rev. 0 | Page 15 of 20 09730-058 AD8429 For best performance, maintain a source impedance to the REF source resistance in the input path (for example, for input terminal that is well below 1 Ω. As shown in Figure 46, the protection) close to the in-amp inputs, which minimizes their reference terminal, REF, is at one end of a 5 kΩ resistor. interaction with parasitic capacitance from the PCB traces. Additional impedance at the REF terminal adds to this 5 kΩ Parasitic capacitance at the gain setting pins can also affect CMRR resistor and results in amplification of the signal connected to over frequency. If the board design has a component at the gain the positive input. The amplification from the additional RREF setting pins (for example, a switch or jumper), choose a component can be calculated as follows: such that the parasitic capacitance is as small as possible. 2(5 kΩ + R )/(10 kΩ + R ) REF REF Power Supplies and Grounding Only the positive signal path is amplified; the negative path Use a stable dc voltage to power the instrumentation amplifier. is unaffected. This uneven amplification degrades CMRR. Noise on the supply pins can adversely affect performance. See INCORRECT CORRECT the PSRR performance curves in Figure 9 and Figure 10 for more information. Place a 0.1 μF capacitor as close as possible to each supply pin. AD8429 AD8429 Because the length of the bypass capacitor leads is critical at REF REF V high frequency, surface-mount capacitors are recommended. A V parasitic inductance in the bypass ground trace works against + the low impedance created by the bypass capacitor. As shown in OP1177 Figure 49, a 10 μF capacitor can be used farther away from the – device. For larger value capacitors, intended to be effective at lower frequencies, the current return path distance is less critical. Figure 47. Driving the Reference Pin In most cases, this capacitor can be shared by other precision INPUT VOLTAGE RANGE integrated circuits. +V S Figure 4 and Figure 5 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. 0.1µF 10µF The 3-op-amp architecture of the AD8429 applies gain in the first stage before removing common-mode voltage with the +IN difference amplifier stage. Internal nodes between the first and V second stages (Node 1 and Node 2 in Figure 46) experience a OUT R G AD8429 combination of a gained signal, a common-mode signal, and a LOAD diode drop. This combined signal can be limited by the voltage REF –IN supplies even when the individual input and output signals are not limited. 0.1µF 10µF LAYOUT –V S To ensure optimum performance of the AD8429 at the PCB Figure 49. Supply Decoupling, REF, and Output Referred to Local Ground level, care must be taken in the design of the board layout. The A ground plane layer is helpful to reduce parasitic inductances. pins of the AD8429 are arranged in a logical manner to aid in This minimizes voltage drops with changes in current. The area this task. of the current path is directly proportional to the magnitude of 1 8 +V parasitic inductances and, therefore, the impedance of the path –IN S R 2 7 V at high frequency. Large changes in currents in an inductive G OUT R 3 6 REF decoupling path or ground return create unwanted effects, due G +IN 4 5 –V to the coupling of such changes into the amplifier inputs. S AD8429 TOP VIEW Because load currents flow from the supplies, the load should (Not to Scale) be connected at the same physical location as the bypass capa- Figure 48. Pinout Diagram citor grounds. Common-Mode Rejection Ratio over Frequency Reference Pin Poor layout can cause some of the common-mode signals to be The output voltage of the AD8429 is developed with respect to converted to differential signals before reaching the in-amp. the potential on the reference terminal. Ensure that REF is tied Such conversions occur when one input path has a frequency to the appropriate local ground. response that is different from the other. To maintain high CMRR over frequency, closely match the input source impedance and capacitance of each path. Place additional Rev. 0 | Page 16 of 20 09730-060 09730-059 09730-061 AD8429 Noise sensitive applications may require a lower protection resis- INPUT BIAS CURRENT RETURN PATH tance. Low leakage diode clamps, such as the BAV199, can be used The input bias current of the AD8429 must have a return path to at the inputs to shunt current away from the AD8429 inputs, ground. When using a floating source without a current return thereby allowing smaller protection resistor values. To ensure path, such as a thermocouple, create a current return path, as current flows primarily through the external protection diodes, shown in Figure 50. place a small value resistor, such as a 33 Ω, between the diodes and INCORRECT CORRECT the AD8429. +V +V S S +V S +V +V S S R R PROTECT PROTECT 33Ω I + + I V V IN+ IN+ –V – S – AD8429 AD8429 AD8429 AD8429 +V S R REF REF R PROTECT PROTECT 33Ω + + –V –V V S V S IN– IN– –V – – S –V –V S S SIMPLE METHOD LOW NOISE METHOD TRANSFORMER TRANSFORMER Figure 51. Protection for Voltages Beyond the Rails +V +V S S Large Differential Input Voltage at High Gain If large differential voltages at high gain are expected, use an external resistor in series with each input to limit current during AD8429 AD8429 overload conditions. The limiting resistor at each input can be REF REF computed by using the following equation: 10MΩ ⎛ V −1V⎞ 1 DIFF ⎜ ⎟ R ≥ − R PROTECT G –V –V ⎜ ⎟ S S 2 I MAX ⎝ ⎠ THERMOCOUPLE THERMOCOUPLE Noise sensitive applications may require a lower protection resis- +V +V S S tance. Low leakage diode clamps, such as the BAV199, can be used across the inputs to shunt current away from the AD8429 inputs C C and, therefore, allow smaller protection resistor values. 1 R R R f = PROTECT PROTECT HIGH-PASS AD8429 2πRC AD8429 C C I I + + REF REF V V DIFF DIFF AD8429 AD8429 – R – R PROTECT R PROTECT –V –V S S CAPACITIVELY COUPLED CAPACITIVELY COUPLED SIMPLE METHOD LOW NOISE METHOD Figure 50. Creating an Input Bias Current Return Path Figure 52. Protection for Large Differential Voltages INPUT PROTECTION I MAX Do not allow the inputs of the AD8429 to exceed the ratings The maximum current into the AD8429 inputs, IMAX, depends stated in the Absolute Maximum Ratings section of this data on time and temperature. At room temperature, the device can sheet. If this cannot be done, protection circuitry can be added withstand a current of 10 mA for at least one day. This time is in front of the AD8429 to limit the current into the inputs to a cumulative over the life of the device. maximum current, I . MAX RADIO FREQUENCY INTERFERENCE (RFI) Input Voltages Beyond the Rails RF rectification is often a problem when amplifiers are used in If voltages beyond the rails are expected, use an external resistor applications that have strong RF signals. The disturbance can in series with each input to limit current during overload condi- appear as a small dc offset voltage. High frequency signals can tions. The limiting resistor at the input can be computed from be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 53. |V − V | IN SUPPLY R ≥ PROTECT I MAX Rev. 0 | Page 17 of 20 09730-062 09730-067 09730-066 AD8429 +V S at the amplifier input. To calculate the noise referred to the amplifier output (RTO), simply multiply the RTI noise by the 0.1µF 10µF gain of the instrumentation amplifier. C C 1nF Source Resistance Noise R +IN Any sensor connected to the AD8429 has some output resistance. 4.02kΩ V C OUT D There may also be resistance placed in series with inputs for pro- R G AD8429 10nF tection from either overvoltage or radio frequency interference. R REF –IN This combined resistance is labeled R1 and R2 in Figure 54. Any 4.02kΩ C C resistor, no matter how well made, has an intrinsic level of noise. 1nF This noise is proportional to the square root of the resistor value. 0.1µF 10µF At room temperature, the value is approximately equal to –V 4 nV/√Hz × √(resistor value in kΩ). S Figure 53. RFI Suppression For example, assuming that the combined sensor and protec- tion resistance on the positive input is 4 kΩ, and on the negative The filter limits the input signal bandwidth, according to the input is 1 kΩ, the total noise from the input resistance is following relationship: 2 2 1 (4× 4) +(4× 1) = 64+16= 8.9 nV/√Hz FilterFrequency = DIFF 2πR(2C +C ) D C Voltage Noise of the Instrumentation Amplifier 1 FilterFrequency = CM 2πRC The voltage noise of the instrumentation amplifier is calculated C using three parameters: the device input noise, output noise, where C ≥ 10 C . D C and the RG resistor noise. It is calculated as follows: C affects the difference signal, and C affects the common-mode D C Total Voltage Noise = signal. Choose values of R and CC that minimize RFI. A mismatch 2 2 2 between R × CC at the positive input and R × CC at the negative ( ) ( )( ) Output Noise /G + Input Noise + Noise of R Resistor G input degrades the CMRR of the AD8429. By using a value of CD that is one magnitude larger than CC, the effect of the For example, for a gain of 100, the gain resistor is 60.4 Ω. There- mismatch is reduced, and performance is improved. fore, the voltage noise of the in-amp is Resistors add noise; therefore, the choice of resistor and capacitor 2 2 2 () 45/100 + 1 +(4× 0.0604) = 1.5 nV/√Hz values depends on the desired tradeoff between noise, input impedance at high frequencies, and RFI immunity. The resistors Current Noise of the Instrumentation Amplifier used for the RFI filter can be the same as those used for input Current noise is calculated by multiplying the source resistance protection. by the current noise. CALCULATING THE NOISE OF THE INPUT STAGE SENSOR For example, if the R1 source resistance in Figure 54 is 4 kΩ, and the R2 source resistance is 1 kΩ, the total effect from the current noise is calculated as follows: R 2 2 R1 G AD8429 (() 4×1.5 +(1×1.5) ) = 6.2 nV/√Hz Total Noise Density Calculation R2 To determine the total noise of the in-amp, referred to input, Figure 54. Source Resistance from Sensor and Protection Resistors combine the source resistance noise, voltage noise, and current The total noise of the amplifier front end depends on much noise contribution by the sum of squares method. more than the 1 nV/√Hz specification of this data sheet. There For example, if the R1 source resistance in Figure 54 is 4 kΩ, the are three main contributors: the source resistance, the voltage R2 source resistance is 1 kΩ, and the gain of the in-amps is 100, noise of the instrumentation amplifier, and the current noise of the total noise, referred to input, is the instrumentation amplifier. 2 2 2 In the following calculations, noise is referred to the input 8.9 +1.5 + 6.2 = 11.0 nV/√Hz (RTI). In other words, everything is calculated as if it appeared Rev. 0 | Page 18 of 20 09730-064 09730-063 AD8429 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8429ARZ −40°C to +125°C 8-Lead SOIC_N R-8 AD8429ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7” Tape and Reel R-8 AD8429BRZ −40°C to +125°C 8-Lead SOIC_N R-8 AD8429BRZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7” Tape and Reel R-8 1 Z = RoHS Compliant Part. Rev. 0 | Page 19 of 20 012407-A AD8429 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09730-0-4/11(0) Rev. 0 | Page 20 of 20