ANALOG DEVICES AD8426

Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier AD8426 FEATURES CONNECTION DIAGRAM 2 channels in a small, 4 mm × 4 mm LFCSP LFCSP package has no metal pad 16 15 14 13 More routing room AD8426 No current leakage to pad 12 –IN2 –IN1 1 Gain set with 1 external resistor RG1 2 11 RG2 Gain range: 1 to 1000 RG1 3 10 RG2 Input voltage goes below ground +IN2 +IN1 4 9 Inputs protected beyond supplies Very wide power supply range 5 678 Single supply: 2.2 V to 36 V Dual supply: ±1.35 V to ±18 V Bandwidth (G = 1): 1 MHz Figure 1. CMRR (G = 1): 80 dB minimum 1 Input noise: 24 nV/√Hz Table 1. Instrumentation Amplifiers by Category Typical supply current (per amplifier): 350 μA General- Zero Military Low High Speed Specified temperature range: −40°C to +125°C Purpose Drift Grade Power PGA AD8220 AD8231 AD620 AD627 AD8250 APPLICATIONS AD8221 AD8290 AD621 AD623 AD8251 Industrial process controls AD8222 AD8293 AD524 AD8235 AD8253 Bridge amplifiers AD8224 AD8553 AD526 AD8236 Medical instrumentation AD8228 AD8556 AD624 AD8426 Portable data acquisition AD8295 AD8557 AD8226 Multichannel systems AD8227 1 See www.analog.com for the latest instrumentation amplifiers. GENERAL DESCRIPTION The AD8426 is a dual-channel, low cost, wide supply range The AD8426 is designed to make PCB routing easy and efficient. The two amplifiers are arranged in a logical way so that typical instrumentation amplifier that requires only one external resistor to set any gain from 1 to 1000. application circuits have short routes and few vias. Unlike most chip scale packages, the AD8426 does not have an exposed metal The AD8426 is designed to work with a variety of signal pad on the bottom of the part, which frees additional space for voltages. A wide input range and rail-to-rail output allow the routing and vias. The AD8426 offers two in-amps in the equivalent signal to make full use of the supply rails. Because the input board space of a typical MSOP package. range can also go below the negative supply, small signals near ground can be amplified without requiring dual supplies. The The AD8426 is ideal for multichannel, space-constrained industrial AD8426 operates on supplies ranging from ±1.35 V to ±18 V applications. Unlike other low cost, low power instrumentation for dual supplies and 2.2 V to 36 V for a single supply. amplifiers, the AD8426 is designed with a minimum gain of 1 and can easily handle ±10 V signals. With its space-saving LFCSP The robust AD8426 inputs are designed to connect to real- package and 125°C temperature rating, the AD8426 thrives in world sensors. In addition to its wide operating range, the tightly packed, zero airflow designs. AD8426 can handle voltages beyond the rails. For example, with a ±5 V supply, the part is guaranteed to withstand ±35 V The AD8226 is the single-channel version of the AD8426. at the input with no damage. Minimum and maximum input bias currents are specified to facilitate open-wire detection. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. +V +V S S REF1 OUT1 REF2 OUT2 –V –V S S 09490-001 AD8426 TABLE OF CONTENTS Features .............................................................................................. 1  Gain Selection ............................................................................. 21  Applications ....................................................................................... 1  Reference Terminal .................................................................... 22  Connection Diagram ....................................................................... 1  Input Voltage Range ................................................................... 22  General Description ......................................................................... 1  Layout .......................................................................................... 23  Revision History ............................................................................... 2  Input Bias Current Return Path ............................................... 24  Specif ica t ions ..................................................................................... 3  Input Protection ......................................................................... 24  Dual-Supply Operation ............................................................... 3  Radio Frequency Interference (RFI) ........................................ 24  Single-Supply Operation ............................................................. 6  Applications Information .............................................................. 25  Absolute Maximum Ratings ............................................................ 9  Precision Strain Gage ................................................................. 25  Thermal Resistance ...................................................................... 9  Differential Drive ....................................................................... 25  ESD Caution .................................................................................. 9  Driving a Cable ........................................................................... 26  Pin Configuration and Function Descriptions ........................... 10  Driving an ADC ......................................................................... 27  Typical Performance Characteristics ........................................... 11  Outline Dimensions ....................................................................... 28  Theory of Operation ...................................................................... 21  Ordering Guide .......................................................................... 28  Architec ture ................................................................................. 21  REVISION HISTORY 7/11—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD8426 SPECIFICATIONS DUAL-SUPPLY OPERATION +V = +15 V, −V = −15 V, V = 0 V, T = 25°C, G = 1, R = 10 kΩ, specifications referred to input, unless otherwise noted. S S REF A L Table 2. A Grade B Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION V = −10 V to +10 V CM RATIO (CMRR) CMRR, DC to 60 Hz G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB CMRR at 5 kHz G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB NOISE Total noise: 2 2 e = √(e + (e /G) ) N NI NO Voltage Noise f = 1 kHz Input Voltage Noise, e 24 27 24 27 nV/√Hz NI Output Voltage Noise, eNO 120 125 120 125 nV/√Hz RTI Noise f = 0.1 Hz to 10 Hz G = 1 2 2 μV p-p G = 10 0.5 0.5 μV p-p G = 100 to 1000 0.4 0.4 μV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p VOLTAGE OFFSET Total offset voltage: VOS = VOSI + (VOSO/G) Input Offset, VOSI VS = ±5 V to ±15 V 200 100 μV Average Temperature TA = −40°C to +125°C 0.5 2 0.5 1 μV/°C Coefficient Output Offset, V V = ±5 V to ±15 V 1000 500 μV OSO S Average Temperature T = −40°C to +125°C 2 10 1 5 μV/°C A Coefficient Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB INPUT CURRENT 1 Input Bias Current T = +25°C 5 20 27 5 20 27 nA A TA = +125°C 5 15 25 5 15 25 nA TA = −40°C 5 30 35 5 30 35 nA Average Temperature TA = −40°C to +125°C 70 70 pA/°C Coefficient Input Offset Current T = +25°C 1.5 0.5 nA A T = +125°C 1.5 0.5 nA A TA = −40°C 2 0.5 nA Average Temperature TA = −40°C to +125°C 5 5 pA/°C Coefficient Rev. 0 | Page 3 of 28 AD8426 A Grade B Grade Test Conditions/ Parameter M Comments in Typ Max Min Typ Max Unit REFERENCE INPUT R 100 100 kΩ IN I 7 7 μA IN Voltage Range −V +V −V +V V S S S S Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 % GAIN G = 1 + (49.4 kΩ/R) G Gain Range 1 1000 1 1000 V/V Gain Error VOUT ± 10 V G = 1 0.04 0.01 % G = 5 to 1000 0.3 0.1 % Gain Nonlinearity V = −10 V to +10 V OUT G = 1 to 10 RL ≥ 2 kΩ 20 20 ppm G = 100 RL ≥ 2 kΩ 75 75 ppm G = 1000 RL ≥ 2 kΩ 750 750 ppm 2 Gain vs. Temperature G = 1 T = −40°C to +85°C 5 1 ppm/°C A T = +85°C to +125°C 5 2 ppm/°C A G > 1 TA = −40°C to +125°C −100 −100 ppm/°C INPUT V = ±1.35 V to +36 V S Input Impedance Differential 0.8||2 0.8||2 GΩ||pF Common Mode 0.4||2 0.4||2 GΩ||pF Input Operating Voltage TA = +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V 3 Range T = +125°C −V − 0.05 +V − 0.6 −V − 0.05 +V − 0.6 V A S S S S TA = −40°C −VS − 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V OUTPUT Output Swing RL = 2 kΩ to Ground TA = +25°C −VS + 0.4 +VS − 0.7 −VS + 0.4 +VS − 0.7 V TA = +125°C −VS + 0.4 +VS − 1.0 −VS + 0.4 +VS − 1.0 V T = −40°C −V + 1.2 +V − 1.1 −V + 1.2 +V − 1.1 V A S S S S R = 10 kΩ to Ground T = +25°C −V + 0.2 +V − 0.2 −V + 0.2 +V − 0.2 V L A S S S S T = +125°C −V + 0.3 +V − 0.3 −V + 0.3 +V − 0.3 V A S S S S TA = −40°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V RL = 100 kΩ to Ground TA = −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V Short-Circuit Current 13 13 mA POWER SUPPLY Operating Range Dual-supply operation ±1.35 ±18 ±1.35 ±18 V Quiescent Current T = +25°C 350 425 350 425 μA A (Per Amplifier) T = −40°C 250 325 250 325 μA A TA = +85°C 450 525 450 525 μA TA = +125°C 525 600 525 600 μA TEMPERATURE RANGE −40 +125 −40 +125 °C 1 The input stage uses PNP transistors; therefore, input bias current always flows into the part. 2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG. 3 Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage. See the Input Voltage Range section for more information. Rev. 0 | Page 4 of 28 AD8426 Dynamic Performance Specifications +VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted. Table 3. Single-Ended Output Configuration (Both Amplifiers) A Grade B Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 1000 1000 kHz G = 10 160 160 kHz G = 100 20 20 kHz G = 1000 2 2 kHz Settling Time 0.01% 10 V step G = 1 25 25 μs G = 10 15 15 μs G = 100 40 40 μs G = 1000 750 750 μs Slew Rate G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs Table 4. Differential Output Configuration A Grade B Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 850 850 kHz G = 10 300 300 kHz G = 100 30 30 kHz G = 1000 2 2 kHz Settling Time 0.01% 10 V step G = 1 25 25 μs G = 10 15 15 μs G = 100 80 80 μs G = 1000 300 300 μs Slew Rate G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs Rev. 0 | Page 5 of 28 AD8426 SINGLE-SUPPLY OPERATION +VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted. Table 5. A Grade B Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION V = 0 V to 1.7 V CM RATIO (CMRR) CMRR, DC to 60 Hz G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB CMRR at 5 kHz G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB NOISE Total noise: 2 2 e = √(e + (e /G) ) N NI NO Voltage Noise f = 1 kHz Input Voltage Noise, e 24 27 24 27 nV/√Hz NI Output Voltage Noise, eNO 120 125 120 125 nV/√Hz RTI Noise f = 0.1 Hz to 10 Hz G = 1 2 2 μV p-p G = 10 0.5 0.5 μV p-p G = 100 to 1000 0.4 0.4 μV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p VOLTAGE OFFSET Total offset voltage: VOS = VOSI + (VOSO/G) Input Offset, VOSI 300 150 μV Average Temperature TA = −40°C to +125°C 0.5 3 0.5 1.5 μV/°C Coefficient Output Offset, V 1000 500 μV OSO T = −40°C to +125°C 2 12 1 8 μV/°C Average Temperature A Coefficient Offset RTI vs. Supply (PSR) VS = 2.7 V to 36 V G = 1 80 90 dB G = 10 100 105 dB G = 100 105 110 dB G = 1000 105 110 dB INPUT CURRENT 1 Input Bias Current T = +25°C 5 20 30 5 20 30 nA A TA = +125°C 5 15 28 5 15 28 nA TA = −40°C 5 30 38 5 30 38 nA Average Temperature TA = −40°C to +125°C 70 70 pA/°C Coefficient Input Offset Current T = +25°C 2 1 nA A T = +125°C 2 1 nA A TA = −40°C 3 1 nA Average Temperature TA = −40°C to +125°C 5 5 pA/°C Coefficient Rev. 0 | Page 6 of 28 AD8426 A Grade B Grade Test Conditions/ Parameter M Comments in Typ Max Min Typ Max Unit REFERENCE INPUT RIN 100 100 kΩ IIN 7 7 μA Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 % GAIN G = 1 + (49.4 kΩ/RG) Gain Range 1 1000 1 1000 V/V Gain Error G = 1 VOUT = 0.8 V to 1.8 V 0.05 0.05 % G = 5 to 1000 VOUT = 0.2 V to 2.5 V 0.3 0.1 % 2 Gain vs. Temperature G = 1 T = −40°C to +85°C 5 1 ppm/°C A T = +85°C to +125°C 5 2 ppm/°C A G > 1 T = −40°C to +125°C −100 −100 ppm/°C A INPUT −V = 0 V, +V = 2.7 V S S to 36 V Input Impedance Differential 0.8||2 0.8||2 GΩ||pF Common Mode 0.4||2 0.4||2 GΩ||pF Input Operating Voltage TA = +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V 3 Range T = +125°C −0.05 +V − 0.6 −0.05 +V − 0.6 V A S S TA = −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V Input Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V OUTPUT Output Swing RL = 10 kΩ to 1.35 V TA = −40°C to +125°C 0.1 +VS − 0.1 0.1 +VS − 0.1 V Short-Circuit Current 13 13 mA POWER SUPPLY Operating Range Single-supply operation 2.2 36 2.2 36 V Quiescent Current −VS = 0 V, +VS = 2.7 V (Per Amplifier) T = +25°C 325 400 325 400 μA A T = −40°C 250 325 250 325 μA A TA = +85°C 425 500 425 500 μA TA = +125°C 475 550 475 550 μA TEMPERATURE RANGE −40 +125 −40 +125 °C 1 The input stage uses PNP transistors; therefore, input bias current always flows into the part. 2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG. 3 Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage. See the Input Voltage Range section for more information. Rev. 0 | Page 7 of 28 AD8426 Dynamic Performance Specifications +VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted. Table 6. Single-Ended Output Configuration (Both Amplifiers) A Grade B Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 1000 1000 kHz G = 10 160 160 kHz G = 100 20 20 kHz G = 1000 2 2 kHz Settling Time 0.01% 2 V step G = 1 6 6 μs G = 10 6 6 μs G = 100 35 35 μs G = 1000 750 750 μs Slew Rate G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs Table 7. Differential Output Configuration A Grade B Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 850 850 kHz G = 10 300 300 kHz G = 100 30 30 kHz G = 1000 2 2 kHz Settling Time 0.01% 2 V step G = 1 25 25 μs G = 10 15 15 μs G = 100 80 80 μs G = 1000 300 300 μs Slew Rate G = 1 0.4 0.4 V/μs G = 5 to 100 0.6 0.6 V/μs Rev. 0 | Page 8 of 28 AD8426 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Rating The θ value in Table 9 assumes a 4-layer JEDEC standard JA board with zero airflow. Supply Voltage ±18 V Output Short-Circuit Current Indefinite Table 9. Maximum Voltage at −INx or +INx −V + 40 V S Package θ Unit JA Minimum Voltage at −INx or +INx +VS − 40 V 16-Lead LFCSP (CP-16-19) 86 °C/W REFx Voltage ±VS Storage Temperature Range −65°C to +150°C Specified Temperature Range −40°C to +125°C ESD CAUTION Maximum Junction Temperature 130°C ESD Human Body Model 1.5 kV Charged Device Model 1.5 kV Machine Model 100 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 28 AD8426 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 15 14 13 AD8426 –IN2 –IN1 1 12 2 RG2 RG1 11 RG1 3 10 RG2 +IN1 4 9 +IN2 5 678 Figure 2. Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN1 Negative Input, In-Amp 1 2 RG1 Gain-Setting Resistor Terminal, In-Amp 1 3 RG1 Gain-Setting Resistor Terminal, In-Amp 1 4 +IN1 Positive Input, In-Amp 1 5 +VS Positive Supply 6 REF1 Reference Adjust, In-Amp 1 7 REF2 Reference Adjust, In-Amp 2 8 −V Negative Supply S 9 +IN2 Positive Input, In-Amp 2 10 RG2 Gain-Setting Resistor Terminal, In-Amp 2 11 RG2 Gain-Setting Resistor Terminal, In-Amp 2 12 −IN2 Negative Input, In-Amp 2 13 −V Negative Supply S 14 OUT2 Output, In-Amp 2 15 OUT1 Output, In-Amp 1 16 +VS Positive Supply Rev. 0 | Page 10 of 28 +V +V S S REF1 OUT1 REF2 OUT2 –V –V S S 09490-002 AD8426 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted. IN-AMP 1 IN-AMP 1 60 IN-AMP 2 IN-AMP 2 40 50 30 40 30 20 20 10 10 0 0 –100 –50 0 50 100 –21 –20 –19 –18 –17 CMRR (µV/V) I (nA) BIAS Figure 3. Typical Distribution for CMRR (G = 1) Figure 6. Typical Distribution of Input Bias Current, Inverting Input 50 IN-AMP 1 IN-AMP 1 50 IN-AMP 2 IN-AMP 2 40 40 30 30 20 20 10 10 0 0 –21 –20 –19 –18 –17 –100 –50 0 50 100 I (nA) BIAS V (µV) OSI Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Input Bias Current, Noninverting Input 60 IN-AMP 1 IN-AMP 1 70 IN-AMP 2 IN-AMP 2 50 60 50 40 40 30 30 20 20 10 10 0 0 –600 –400 –200 0 200 400 600 –0.010 –0.005 0 0.005 0.010 GAIN ERROR (%) V (µV) OSO Figure 5. Typical Distribution of Output Offset Voltage Figure 8. Typical Distribution of Gain Error (G = 1) Rev. 0 | Page 11 of 28 HITS HITS HITS 09490-305 09490-304 09490-303 HITS HITS HITS 09490-308 09490-307 09490-306 AD8426 2.5 2.5 +0.01V, +1.90V V = +1.35V +0.01V, +1.90V V = +1.35V REF +1.35V, +1.95V REF +1.35V, +1.94V 2.0 2.0 1.5 +2.61V, +1.13V 1.5 +2.60V, +1.11V +0.01V, +1.28V +0.01V, +1.19V 1.0 1.0 +2.17V, +0.90V V = 0V V = 0V REF REF +2.46V, +0.72V 0.5 0.5 +2.61V, +0.37V +0.01V, +0.31V +0.01V, +0.05V 0 0 +2.61V, +0.08V –0.5 –0.5 +1.35V, –0.41V 0.00V, –0.45V +0.01V, –0.40V +1.35V, –0.55V –1.0 –1.0 2.0 –0.5 0 0.5 1.0 1.5 2.5 3.0 2.0 –0.5 0 0.5 1.0 1.5 2.5 3.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 9. Input Common-Mode Voltage vs. Output Voltage, Figure 12. Input Common-Mode Voltage vs. Output Voltage, Single Supply, V = 2.7 V, G = 1 Single Supply, V = 2.7 V, G = 100 S S 5 5 V = +2.50V +0.02V, +4.25V +2.50V, +4.25V REF +2.49V, +4.25V +0.02V, +4.20V V = +2.5V REF 4 4 +4.90V, +3.02V +4.90V, +3.03V 3 3 +0.02V, +2.95V +0.02V, +2.89V V = 0V REF +4.64V, +2.03V 2 2 V = 0V REF +4.77V, +1.71V +0.01V, +0.87V 1 1 +0.01V, +0.69V +4.90V, +0.82V +4.90V, +0.54V 0 0 +2.49V, –0.30V +0.01V, –0.30V +2.50V, –0.40V +0.01V, –0.40V –1 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 –0.5 0 0.5 1.01.52 2.0.53 3.0.54 4.0.5 5.0 5.5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 10. Input Common-Mode Voltage vs. Output Voltage, Figure 13. Input Common-Mode Voltage vs. Output Voltage, Single Supply, V = 5 V, G = 1 Single Supply, V = 5 V, G = 100 S S 6 6 0V, +4.25V 0V, +4.24V 4 4 2 2 +4.87V, +1.79V +4.90V, +1.76V –4.93V, +1.77V –4.93V, +1.74V 0 0 –2 –2 +4.90V, –2.84V +4.90V, –3.18V –4.93V, –2.83V –4.93V, –3.15V –4 –4 0V, –5.30V –0.01V, –5.30V –6 –6 4 –6 –4 –2 0 2 4 6 –6 –4 –2 0 2 6 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 11. Input Common-Mode Voltage vs. Output Voltage, Figure 14. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, V = ±5 V, G = 1 Dual Supply, V = ±5 V, G = 100 S S Rev. 0 | Page 12 of 28 INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) 09490-105 09490-104 09490-103 INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) 09490-108 09490-107 09490-106 AD8426 20 20 V = ±15V V = ±15V S S 0V, +14.2V 0V, +14.1V 15 15 +14.8V, +6.64V 10 10 –14.9V, +6.61V –14.9V, +6.7V +14.8V, +6.8V 0V, +11.2V 0V, +11.2V 5 5 –11.9V, +5.2V +11.9V, +5.3V –11.9V, +5.22V +11.8V, +5.25V V = ±12V V = ±12V S S 0 0 –11.9V, –6.0V –11.9V, –6.71V –5 –5 +11.8V, –6.5V +11.8V, –6.63V 0V, –12.3V –0.01V, –12.3V –10 –10 –14.9V, –7.6V +14.8V, –7.9V +14.8V, –8.18V –14.9V, –8.09V –15 –15 0V, –15.3V –0.01V, –15.3V –20 –20 –20 –15 –10 –5 0 5 10 15 20 –20 –15 –10 –5 0 5 10 15 20 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 15. Input Common-Mode Voltage vs. Output Voltage, Figure 18. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±15 V and VS = ±12 V, G = 1 Dual Supply, VS = ±15 V and VS = ±12 V, G = 100 2.75 0.6 2.75 0.6 V = 2.7V V = 2.7V S S 2.50 0.5 2.50 0.5 G = 1 G = 100 –V = 0V –V = 0V IN IN 2.25 0.4 2.25 0.4 V V OUT OUT 2.00 0.3 2.00 0.3 1.75 0.2 1.75 0.2 1.50 0.1 1.50 0.1 1.25 0 1.25 0 1.00 –0.1 1.00 –0.1 0.75 –0.2 0.75 –0.2 I IN I IN 0.50 –0.3 0.50 –0.3 0.25 –0.4 0.25 –0.4 0 –0.5 0 –0.5 –0.25 –0.6 –0.25 –0.6 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 16. Input Overvoltage Performance, Figure 19. Input Overvoltage Performance, Single Supply, V = 2.7 V, G = 1 Single Supply, V = 2.7 V, G = 100 S S 16 0.8 16 0.8 V = ±15V V = ±15V S S 14 0.7 14 0.7 G = 1 G = 100 12 0.6 12 0.6 –V = 0V –V = 0V IN IN V V OUT OUT 10 0.5 10 0.5 8 0.4 8 0.4 6 6 0.3 0.3 4 4 0.2 0.2 2 2 I 0.1 0.1 IN 0 0 0 0 –2 –2 –0.1 –0.1 I –4 –0.2 –4 –0.2 IN –6 –0.3 –6 –0.3 –8 –0.4 –8 –0.4 –10 –0.5 –10 –0.5 –12 –0.6 –12 –0.6 –14 –0.7 –14 –0.7 –16 –0.8 –16 –0.8 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 17. Input Overvoltage Performance, Figure 20. Input Overvoltage Performance, Dual Supply, VS = ±15 V, G = 1 Dual Supply, VS = ±15 V, G = 100 Rev. 0 | Page 13 of 28 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) INPUT CURRENT (mA) 09490-109 INPUT CURRENT (mA) 09490-111 09490-110 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) INPUT CURRENT (mA) 09490-112 INPUT CURRENT (mA) 09490-114 09490-113 AD8426 30 50 45 28 40 35 26 –15.1V –0.12V 30 24 25 20 +4.22V +14.1V 22 15 20 10 5 18 0 16 –5 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 –16 –12 –8 –4 0 4 8 12 16 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) Figure 21. Input Bias Current vs. Common-Mode Voltage, Figure 24. Input Bias Current vs. Common-Mode Voltage, Single Supply, VS = 5 V Dual Supply, VS = ±15 V 160 160 GAIN = 1000 140 140 GAIN = 1000 GAIN = 100 120 120 GAIN = 100 GAIN = 10 GAIN = 10 GAIN = 1 100 100 GAIN = 1 80 80 60 60 40 40 20 20 0 0 0.1 1 10 100 1k 10k 100k 1M 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. Positive PSRR vs. Frequency, RTI Figure 25. Negative PSRR vs. Frequency 70 70 V = ±15V S GAIN = 1000 GAIN = 1000 60 60 50 50 GAIN = 100 40 GAIN = 100 40 30 30 GAIN = 10 20 GAIN = 10 20 10 GAIN = 1 10 0 GAIN = 1 0 –10 –10 –20 –30 –20 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Gain vs. Frequency, Dual Supply, VS = ±15 V Figure 26. Gain vs. Frequency, Single Supply, VS = 2.7 V Rev. 0 | Page 14 of 28 INPUT BIAS CURRENT (nA) GAIN (dB) POSITIVE PSRR (dB) 09490-322 09490-323 09490-115 INPUT BIAS CURRENT (nA) GAIN (dB) NEGATIVE PSRR (dB) 09490-325 09490-326 09490-118 AD8426 30 250 160 GAIN = 1000 140 GAIN = 100 25 200 BANDWIDTH GAIN = 10 120 ±I B LIMITED 20 150 GAIN = 1 100 15 100 80 I OS 60 10 50 40 5 0 20 0 –50 0 –45 –25 –5 15 35 55 75 95 115 135 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) TEMPERATURE (°C) Figure 27. CMRR vs. Frequency, RTI Figure 30. Input Bias Current and Input Offset Current vs. Temperature 120 40 GAIN = 100 GAIN = 1000 BANDWIDTH 100 20 LIMITED GAIN = 1 GAIN = 10 80 0 60 –20 40 –40 –60 20 NORMALIZED AT 25°C –80 0 0.1 1 10 100 1k 10k 100k –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY (Hz) TEMPERATURE (°C) Figure 31. Gain Error vs. Temperature, G = 1 Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance 6 10 5 4 5 3 0 2 1 0 –5 –1 –2 –10 –3 –4 –15 –5 REPRESENTATIVE DATA NORMALIZED AT 25°C –6 –20 0 10 20 30 40 50 60 70 80 90 100 110 120 –60 –40 –20 0 20 40 60 80 100 120 140 WARM-UP TIME (Seconds) TEMPERATURE (°C) Figure 29. Change in Input Offset Voltage vs. Warm-Up Time Figure 32. CMRR vs. Temperature, G = 1 Rev. 0 | Page 15 of 28 CMRR (dB) CMRR (dB) CHANGE IN INPUT OFFSET VOLTAGE (µV) 09490-329 09490-328 09490-327 INPUT BIAS CURRENT (nA) CMRR (µV/V) GAIN ERROR (µV/V) INPUT OFFSET CURRENT (pA) 09490-126 09490-125 09490-330 AD8426 +V 15 S –40°C +25°C +85°C +105°C +125°C –0.2 10 –0.4 –0.6 5 –0.8 –40°C +25°C 0 +85°C +105°C –V +125°C S –5 –0.2 –0.4 –10 –0.6 –15 –0.8 2 4 6 8 10 12 14 16 18 100 1k 10k 100k SUPPLY VOLTAGE (±V ) LOAD RESISTANCE (Ω) S Figure 33. Input Voltage Limit vs. Supply Voltage Figure 36. Output Voltage Swing vs. Load Resistance +V +V S S –0.2 –0.1 –0.4 –0.2 –40°C –40°C +25°C –0.6 +25°C –0.3 +85°C +85°C –0.8 +105°C –0.4 +105°C +125°C +125°C +0.4 +0.8 +0.3 +0.6 +0.2 +0.4 +0.1 +0.2 –V –V S S 2 4 6 8 10 12 14 16 18 0.01 0.1 1 10 SUPPLY VOLTAGE (±V ) OUTPUT CURRENT (µA) S Figure 34. Output Voltage Swing vs. Supply Voltage, R = 10 kΩ Figure 37. Output Voltage Swing vs. Output Current, G = 1 L +V S –0.2 –0.4 –40°C –0.6 +25°C –0.8 +85°C –1.0 +105°C +125°C –1.2 +1.2 +1.0 +0.8 +0.6 +0.4 +0.2 –V S OUTPUT VOLTAGE (V) 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (±V ) S Figure 35. Output Voltage Swing vs. Supply Voltage, R = 2 kΩ Figure 38. Gain Nonlinearity, R ≥ 10 kΩ, G = 1 L L Rev. 0 | Page 16 of 28 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 09490-335 09490-334 09490-333 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES LINEARITY (10ppm/DIV) 09490-338 09490-130 09490-131 AD8426 1k GAIN = 1 100 GAIN = 100 GAIN = 10 GAIN = 1000 10 OUTPUT VOLTAGE (V) 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 39. Gain Nonlinearity, R ≥ 10 kΩ, G = 10 L Figure 42. Voltage Noise Spectral Density vs. Frequency GAIN = 1000, 200nV/DIV GAIN = 1, 1µV/DIV 1s/DIV OUTPUT VOLTAGE (V) Figure 40. Gain Nonlinearity, RL ≥ 10 kΩ, G = 100 Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000 1k 100 10 OUTPUT VOLTAGE (V) 1 10 100 1k 10k FREQUENCY (Hz) Figure 44. Current Noise Spectral Density vs. Frequency Figure 41. Gain Nonlinearity, RL ≥ 10 kΩ, G = 1000 Rev. 0 | Page 17 of 28 LINEARITY (100ppm/DIV) LINEARITY (10ppm/DIV) LINEARITY (10ppm/DIV) 09490-341 09490-340 09490-339 NOISE (nV/ Hz) NOISE (fA/ Hz) 09490-343 09490-344 09490-342 AD8426 5V/DIV 17µs TO 0.01% 23µs TO 0.001% 0.002%/DIV 1.5pA/DIV 1s/DIV 50µs/DIV Figure 45. 0.1 Hz to 10 Hz Current Noise Figure 48. Large Signal Pulse Response and Settling Time, 10 V Step, Dual Supply, V = ±15 V, G = 10 S 30 V = ±15V 27 S 24 5V/DIV 21 42µs TO 0.01% 18 60µs TO 0.001% 15 12 9 0.002%/DIV 6 V = +5V S 3 100µs/DIV 0 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 46. Large Signal Frequency Response Figure 49. Large Signal Pulse Response and Settling Time, 10 V Step, Dual Supply, V = ±15 V, G = 100 S 5V/DIV 5V/DIV 580µs TO 0.01% 780µs TO 0.001% 26µs TO 0.01% 27µs TO 0.001% 0.002%/DIV 0.002%/DIV 50µs/DIV 500µs/DIV Figure 47. Large Signal Pulse Response and Settling Time, Figure 50. Large Signal Pulse Response and Settling Time, 10 V Step, Dual Supply, VS = ±15 V, G = 1 10 V Step, Dual Supply, VS = ±15 V, G = 1000 Rev. 0 | Page 18 of 28 OUTPUT VOLTAGE (V p-p) 09490-347 09490-345 09490-346 09490-350 09490-349 09490-348 AD8426 20mV/DIV 4µs/DIV 20mV/DIV 100µs/DIV Figure 51. Small Signal Pulse Response, R = 10 kΩ, C = 100 pF, G = 1 Figure 54. Small Signal Pulse Response, R = 10 kΩ, C = 100 pF, G = 1000 L L L L NO LOAD 47pF 100pF 147pF 20mV/DIV 4µs/DIV 20mV/DIV 4µs/DIV Figure 52. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 10 Figure 55. Small Signal Pulse Response with Various Capacitive Loads, G = 1, RL = Infinity 60 50 40 SETTLED TO 0.001% 30 SETTLED TO 0.01% 20 10 20mV/DIV 20µs/DIV 0 2468 10 12 14 16 18 20 STEP SIZE (V) Figure 53. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF, G = 100 Figure 56. Settling Time vs. Step Size, Dual Supply, VS = ±15 V Rev. 0 | Page 19 of 28 09490-147 09490-145 09490-146 SETTLING TIME (µs) 09490-149 09490-148 09490-356 AD8426 760 70 GAIN = 1000 60 740 50 720 GAIN = 100 40 700 30 GAIN = 10 20 680 10 660 GAIN = 1 0 640 –10 –20 620 100 1k 10k 100k 1M 062141 8 10 124618 SUPPLY VOLTAGE (±V ) FREQUENCY (Hz) S Figure 57. Supply Current vs. Supply Voltage (Both Amplifiers) Figure 59. Gain vs. Frequency, Differential Output Configuration 200 100 180 90 GAIN = 1000 160 80 140 70 LIMITED BY MEASUREMENT 120 GAIN = 1 60 SYSTEM 100 50 80 40 60 30 40 20 20 10 0 0 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 58. Channel Separation vs. Frequency, RL = 2 kΩ, Figure 60. Output Balance vs. Frequency, Differential Output Configuration Source Channel at G = 1 and G = 1000 Rev. 0 | Page 20 of 28 SUPPLY CURRENT (µA) CHANNEL SEPARATION (dB) 09490-358 09490-151 OUTPUT BALANCE (dB) GAIN (dB) 09490-360 09490-359 AD8426 THEORY OF OPERATION +V +V S S R NODE 3 G NODE 4 R3 50kΩ –V –V S S R1 R2 +V S R4 24.7kΩ 24.7kΩ 50kΩ NODE 2 A3 V OUT NODE 1 +V R5 S 50kΩ R6 –V S ESD AND ESD AND 50kΩ REF OVERVOLTAGE OVERVOLTAGE +IN Q1 Q2 –IN A1 A2 PROTECTION PROTECTION –V S V R R B BIAS B –V DIFFERENCE S GAIN STAGE AMPLIFIER STAGE Figure 61. Simplified Schematic ARCHITECTURE GAIN SELECTION The AD8426 is based on the classic 3-op-amp topology. This Placing a resistor across the RG terminals sets the gain of the topology has two stages: a gain stage (preamplifier) to provide AD8426. The gain can be calculated by referring to Table 11 differential amplification, followed by a difference amplifier stage or by using the following gain equation: to remove the common-mode voltage. Figure 61 shows a simplified 49.4 kΩ schematic of one of the instrumentation amplifiers in the AD8426. R = G G− 1 The first stage works as follows. To maintain a constant voltage across the bias resistor, RB, A1 must keep Node 3 at a constant Table 11. Gains Achieved Using 1% Resistors diode drop above the positive input voltage. Similarly, A2 keeps 1% Standard Table Value of R Calculated Gain G Node 4 at a constant diode drop above the negative input voltage. 49.9 kΩ 1.990 Therefore, a replica of the differential input voltage is placed 12.4 kΩ 4.984 across the gain setting resistor, R . The current that flows across G 5.49 kΩ 9.998 this resistance must also flow through the R1 and R2 resistors, 2.61 kΩ 19.93 creating a gained differential signal between the A2 and A1 out- 1.00 kΩ 50.40 puts. Note that, in addition to a gained differential signal, the 499 Ω 100.0 original common-mode signal, shifted up by a diode drop, is 249 Ω 199.4 also still present. 100 Ω 495.0 49.9 Ω 991.0 The second stage is a difference amplifier, composed of A3 and four 50 kΩ resistors. The purpose of this stage is to remove the The AD8426 defaults to G = 1 when no gain resistor is used. common-mode signal from the amplified differential signal. The tolerance and gain drift of the R resistor should be added G The transfer function of the AD8426 is to the AD8426 specifications to determine the total gain accu- racy of the system. When the gain resistor is not used, gain VOUT = G × (VIN+ − VIN−) + VREF error and gain drift are minimal. where: 49.4 kΩ G= 1+ RG Rev. 0 | Page 21 of 28 09490-003 AD8426 Equation 1 to Equation 3 can be used to understand the inter- REFERENCE TERMINAL action of the gain (G), common-mode input voltage (V ), CM The output voltage of the AD8426 is developed with respect differential input voltage (V ), and reference voltage (V ). DIFF REF to the potential on the reference terminal. This is useful when The values for the constants (V−LIMIT, V+LIMIT, and VREF_LIMIT) the output signal needs to be offset to a precise midsupply level. at different temperatures are shown in Table 12. These three For example, a voltage source can be tied to the REF pin to level- equations, along with the input and output voltage range speci- shift the output so that the AD8426 can drive a single-supply fications in Table 2 and Table 5, set the operating boundaries ADC. The REF pin is protected with ESD diodes and should of the part. or −V by more than 0.3 V. not exceed either +VS S V × G DIFF For the best performance, source impedance to the REF V − >−V + V (1) CM S −LIMIT 2 terminal should be kept below 2 Ω. As shown in Figure 62, the reference terminal, REF, is at one end of a 50 kΩ resistor. V × G DIFF Additional impedance at the REF terminal adds to this 50 kΩ V + <+V − V (2) CM S +LIMIT 2 resistor and results in amplification of the signal connected to the positive input. The amplification from the additional R REF V ×G ⎛ ⎞ DIFF can be computed by 2 × (50 kΩ + R )/100 kΩ + R . ⎜ + V +V ⎟ REF REF CM REF 2 ⎜ ⎟ (3) <+V − V S REF_LIMIT Only the positive signal path is amplified; the negative path is ⎜ ⎟ 2 ⎜ ⎟ unaffected. This uneven amplification degrades the CMRR of ⎝ ⎠ the amplifier. Table 12. Input Voltage Range Constants for Various INCORRECT CORRECT CORRECT Temperatures Temperature V (V) V (V) V (V) −LIMIT +LIMIT REF_LIMIT −40°C −0.55 +0.8 +1.3 AD8426 AD8426 AD8426 REF REF REF +25°C −0.35 +0.7 +1.15 V V REF REF +85°C −0.15 +0.65 +1.05 V REF +125°C −0.05 +0.6 +0.9 + + OP1177 AD8426 The common-mode input voltage range shifts upward with temp- – – erature. At cold temperatures, the part requires extra headroom from the positive supply, whereas operation near the negative supply has more margin. Conversely, at hot temperatures, the part Figure 62. Driving the Reference Pin requires less headroom from the positive supply but is subject INPUT VOLTAGE RANGE to the worst-case conditions for input voltages near the negative The 3-op-amp architecture of the AD8426 applies gain in supply. the first stage before removing common-mode voltage in the A typical part functions up to the boundaries described in this difference amplifier stage. In addition, the input transistors in section. However, for best performance, designing with a few the first stage shift the common-mode voltage up one diode hundred millivolts of extra margin is recommended. As signals drop. Therefore, internal nodes between the first and second approach the boundary, internal transistors begin to saturate, stages (Node 1 and Node 2 in Figure 61) experience a combina- which can affect frequency and linearity performance. tion of gained signal, common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. Figure 9 to Figure 15 and Figure 18 show the allowable common- mode input voltage ranges for various output voltages and supply voltages. Rev. 0 | Page 22 of 28 09490-156 AD8426 Common-Mode Rejection Ratio over Frequency LAYOUT Poor layout can cause some of the common-mode signals to be To ensure optimum performance of the AD8426 at the PCB converted to differential signals before reaching the in-amp. Such level, care must be taken in the design of the board layout. conversions occur when one input path has a frequency response The AD8426 pins are arranged in a logical manner to aid in that is different from the other. To keep CMRR over frequency this task. high, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the 16 15 14 13 input paths (for example, for input protection) should be placed close to the in-amp inputs to minimize the interaction of the AD8426 12 –IN2 –IN1 1 inputs with parasitic capacitance from the PCB traces. RG1 2 11 RG2 Parasitic capacitance at the gain setting pins can also affect CMRR RG2 RG1 3 10 over frequency. If the board design has a component at the gain 4 9 +IN2 +IN1 setting pins (for example, a switch or jumper), the component should be chosen so that the parasitic capacitance is as small as 5 678 possible. Power Supplies Figure 63. Pinout Diagram A stable dc voltage should be used to power the instrumenta- Package Considerations tion amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 22 The AD8426 is available in a 16-lead, 4 mm × 4 mm LFCSP with and Figure 25 for more information. no exposed paddle. The footprint from another 4 mm × 4 mm LFCSP part should not be copied because it may not have the A 0.1 μF capacitor should be placed as close as possible to each correct lead pitch and lead width dimensions. Refer to the supply pin. As shown in Figure 65, a 10 μF capacitor can be used Outline Dimensions section to verify that the corresponding farther away from the part. In most cases, it can be shared by dimensional symbol has the correct dimensions. other precision integrated circuits. +V S Hidden Paddle Package The AD8426 is available in an LFCSP package with a hidden 0.1µF 10µF paddle. Unlike chip scale packages where the pad limits routing capability, this package allows routes and vias directly beneath +IN the chip. In this way, the full space savings of the small LFCSP OUT R can be realized. Although the package has no metal in the center G AD8426 of the part, the manufacturing process leaves a very small section LOAD REF –IN of exposed metal at each of the package corners, as shown in Figure 64 and in Figure 73 in the Outline Dimensions section. This metal is connected to −V through the part. Because of the S 0.1µF 10µF possibility of a short, vias should not be placed beneath these –V exposed metal tabs. S Figure 65. Supply Decoupling, REF, and Output Referred to Local Ground HIDDEN References PADDLE The output voltage of the AD8426 is developed with respect to the potential on the reference terminal. Care should be taken to EXPOSED METAL tie the REFx pins to the appropriate local ground. This should TABS BOTTOM VIEW also help minimize crosstalk between the two channels. NOTES 1. EXPOSED METAL TABS AT THE FOUR CORNERS OF THE PACKAGE ARE INTERNALLY CONNECTED TO –V . S Figure 64. Hidden Paddle Package, Bottom View Rev. 0 | Page 23 of 28 +V +V S S REF1 OUT1 REF2 OUT2 –V –V S S 09490-002 09490-158 09490-006 AD8426 The other AD8426 terminals should be kept within the supplies. INPUT BIAS CURRENT RETURN PATH All terminals of the AD8426 are protected against ESD. The input bias current of the AD8426 must have a return path For applications where the AD8426 encounters voltages beyond to ground. When the source, such as a thermocouple, cannot provide a current return path, one should be created, as shown the allowed limits, external current limiting resistors and low in Figure 66. leakage diode clamps such as the BAV199L, the FJH1100, or the SP720 should be used. INCORRECT CORRECT RADIO FREQUENCY INTERFERENCE (RFI) +V +V S S RF interference is often a problem when amplifiers are used in applications where there are strong RF signals. The precision circuits in the AD8426 can rectify the RF signals so that they AD8426 AD8426 appear as a dc offset voltage error. To avoid this rectification, REF REF place a low-pass RC filter at the input of the instrumentation amplifier (see Figure 67). The filter limits both the differential and common-mode bandwidth, as shown in the following –V –V S S equations: TRANSFORMER TRANSFORMER 1 +V +V FilterFrequency = S S DIFF 2πR(2C + C ) D C 1 FilterFrequency = CM 2πRC C AD8426 AD8426 REF REF where CD ≥ 10 CC. 10MΩ +V S –V –V S S 0.1µF 10µF THERMOCOUPLE THERMOCOUPLE C C 1nF +V +V S S R +IN 4.02kΩ C C OUT C D R G AD8426 10nF R 1 R REF f = HIGH-PASS AD8426 2πRC AD8426 –IN 4.02kΩ C C REF REF C C 1nF R 0.1µF 10µF –V –V S S –V S CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 67. RFI Suppression Figure 66. Creating an Input Bias Current Return Path C affects the differential signal, and C affects the common- D C INPUT PROTECTION mode signal. Values of R and C should be chosen to minimize C The AD8426 has very robust inputs and typically does not RFI. Any mismatch between the R × C at the positive input C need additional input protection. Input voltages can be up to and the R × C at the negative input degrades the CMRR of the C 40 V from the opposite supply rail. For example, with a +5 V AD8426. By using a value of CD one order of magnitude larger positive supply and a −8 V negative supply, the part can safely than CC, the effect of the mismatch is reduced, and performance withstand voltages from −35 V to +32 V. Unlike some other is improved. instrumentation amplifiers, the part can handle large differen- tial input voltages even when the part is in high gain. Figure 16, Figure 17, Figure 19, and Figure 20 show the behavior of the part under overvoltage conditions. Rev. 0 | Page 24 of 28 09490-007 09490-008 AD8426 APPLICATIONS INFORMATION A common application sets the common-mode output voltage PRECISION STRAIN GAGE to the midscale of a differential ADC. In this case, the ADC The low offset and high CMRR over frequency of the AD8426 reference voltage is sent to the +IN2 terminal, and ground is make it an excellent candidate for bridge measurements. The connected to the REF2 terminal. This produces a common- bridge can be connected directly to the inputs of the amplifier mode output voltage of half the ADC reference voltage. (see Figure 68). 2-Channel Differential Output Using a Dual Op Amp 5V 10µF 0.1µF Another differential output topology is shown in Figure 70. Instead of a second in-amp, one-half of a dual op amp creates 350Ω 350Ω the inverted output. The recommended dual op amps (the +IN + AD8642 and the AD822) are packaged in an MSOP. This 350Ω 350Ω R AD8426 G configuration allows the creation of a dual-channel, precision – –IN 2.5V differential output in-amp with little board area. Figure 70 shows how to configure the AD8426 for differential Figure 68. Precision Strain Gage output. DIFFERENTIAL DRIVE +IN The differential output configuration of the AD8426 has the AD8426 V OUT+ same excellent dc precision specifications as the single-ended –IN output configuration. R REF V BIAS Differential Output Using Both AD8426 Amplifiers + – The circuit configuration is shown in Figure 69. The differential R OP AMP output specifications in Table 2, Table 4, Table 5, and Table 7 refer to this configuration only. The circuit includes an RC filter that maintains the stability of the loop. V OUT– RECOMMENDED OP AMPS: AD8642, AD822. +IN1 + RECOMMENDED R VALUES: 5kΩ TO 20kΩ. R V G AD8426 OUT+ Figure 70. Differential Output Using an Op Amp –IN1 – 10kΩ The differential output voltage is set by the following equation: – 100pF VDIFF_OUT = VOUT+ − VOUT− = G × (VIN+ − VIN−) AD8426 where: +INx + REF2 49.4 kΩ G =1 + V OUT– R G Figure 69. Differential Circuit Schematic The common-mode output voltage is set by the following The differential output voltage is set by the following equation: equation: VDIFF_OUT = VOUT+ − VOUT− = G × (VIN+ − VIN−) VCM_OUT = (VOUT+ − VOUT−)/2 = VBIAS where: The advantage of this circuit is that the dc differential accuracy 49.4 kΩ depends on the AD8426 and not on the op amp or the resistors. G =1 + This circuit takes advantage of the precise control of the AD8426 R G over its output voltage relative to the reference voltage. Op amp The common-mode output voltage is set by the average of +IN2 dc performance and resistor matching do affect the dc common- and REF2. The transfer function is mode output accuracy. However, because common-mode errors V = (V + V )/2 = (V + V )/2 are likely to be rejected by the next device in the signal chain, these CM_OUT OUT+ OUT− +IN2 REF2 errors typically have little effect on overall system accuracy. For best ac performance, an op amp with gain bandwidth of at least 2 MHz and a slew rate of at least 1 V/μs is recommended. Good choices for op amps are the AD8642 and the AD822. Rev. 0 | Page 25 of 28 09490-163 09490-010 09490-009 AD8426 Tips for Best Differential Output Performance DRIVING A CABLE Keep trace lengths from resistors to the inverting terminal of All cables have a certain capacitance per unit length, which varies the op amp as short as possible. Excessive capacitance at this widely with cable type. The capacitive load from the cable may node can cause the circuit to be unstable. If capacitance cannot cause peaking in the output response of the AD8426. To reduce be avoided, use lower value resistors. the peaking, use a resistor between the AD8426 outputs and the cable (see Figure 71). Because cable capacitance and desired output For best linearity and ac performance, a minimum positive supply response vary widely, this resistor is best determined empirically. voltage (+V ) is required. Table 13 shows the minimum supply S A good starting point is 50 Ω. voltage required for optimum performance, where V CM_MAX indicates the maximum common-mode voltage expected at the input of the AD8426. AD8426 Table 13. Minimum Positive Supply Voltage Temperature Equation DIFFERENTIAL OUTPUT Less than −10°C +V > (V + V )/2 + 1.4 V S CM_MAX BIAS −10°C to +25°C +V > (V + V )/2 + 1.25 V S CM_MAX BIAS More than +25°C +VS > (VCM_MAX + VBIAS)/2 + 1.1 V AD8426 SINGLE OUTPUT Figure 71. Driving a Cable The AD8426 operates at such a relatively low frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. Rev. 0 | Page 26 of 28 09490-165 AD8426 Option 2 shows a circuit for driving higher frequency signals. DRIVING AN ADC It uses a precision op amp (AD8616) with relatively high band- Figure 72 shows several different methods of driving an ADC. width and output drive. This amplifier can drive a resistor and The ADC in the ADuC7026 microcontroller was chosen for capacitor with a much higher time constant and is, therefore, this example because it has an unbuffered, charge sampling suited for higher frequency applications. architecture that is typical of most modern ADCs. This type of architecture typically requires an RC buffer stage between the Option 3 is useful for applications where the AD8426 must ADC and the amplifier to work correctly. operate from a large voltage supply but drives a single-supply ADC. In normal operation, the AD8426 output signal stays Option 1 shows the minimum configuration required to drive within the ADC range, and the AD8616 simply buffers the signal. a charge sampling ADC. The capacitor provides charge to the However, in a fault condition, the output of the AD8426 may ADC sampling capacitor, and the resistor shields the AD8426 go outside the supply range of both the AD8616 and the ADC. from the capacitance. To keep the AD8426 stable, the RC time This is not a problem in this circuit, because the 10 kΩ resistor constant of the resistor and capacitor needs to stay above 5 μs. between the two amplifiers limits the current into the AD8616 This circuit is mainly useful for lower frequency signals. to a safe level. OPTION 1: DRIVING LOW FREQUENCY SIGNALS 3.3V 3.3V AV DD 100Ω ADC0 AD8426 REF 100nF ADuC7026 OPTION 2: DRIVING HIGH FREQUENCY SIGNALS 3.3V 3.3V AD8426 10Ω REF ADC1 AD8616 10nF OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES +15V 3.3V 10kΩ AD8426 10Ω REF AD8616 ADC2 10nF AGND –15V Figure 72. Driving an ADC Rev. 0 | Page 27 of 28 09490-065 AD8426 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX 13 16 1 12 0.65 PIN 1 3.75 BSC 1.95 REF INDICATOR BCS SQ SQ 9 4 8 5 0.75 TOP VIEW BOTTOM VIEW 0.60 0.50 0.80 MAX 12° MAX 1.00 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM COPLANARITY 0.35 SEATING 0.08 PLANE 0.30 0.20 REF 0.25 COMPLIANT TO JEDEC STANDARDS MO-263-VBBC Figure 73. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle (CP-16-19) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8426ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19 AD8426ACPZ-WP −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19 AD8426BCPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19 AD8426BCPZ-WP −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-19 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09490-0-7/11(0) Rev. 0 | Page 28 of 28 062309-B