ANALOG DEVICES AD8421

3 nV/√Hz, Low Power Instrumentation Amplifier Data Sheet AD8421 FEATURES PIN CONNECTION DIAGRAM Low power AD8421 1 8 –IN +V S 2.3 mA maximum supply current R 2 7 V G OUT Low noise 3 6 R REF G 3.2 nV/√Hz maximum input voltage noise at 1 kHz +IN 4 5 –V S 200 fA/√Hz current noise at 1 kHz Excellent ac specifications TOP VIEW (Not to Scale) 10 MHz bandwidth (G = 1) Figure 1. 2 MHz bandwidth (G = 100) 0.6 μs settling time to 0.001% (G = 10) 80 dB CMRR at 20 kHz (G = 1) 35 V/μs slew rate High precision dc performance (AD8421BRZ) 10µ 94 dB CMRR minimum (G = 1) G = 100 0.2 μV/°C maximum input offset voltage drift BEST AVAILABLE 1 ppm/°C maximum gain drift (G = 1) 7mA LOW NOISE IN-AMP 1µ 500 pA maximum input bias current Inputs protected to 40 V from opposite supply ±2.5 V to ±18 V dual supply (5 V to 36 V single supply) 100n Gain set with a single resistor (G = 1 to 10,000) APPLICATIONS BEST AVAILABLE 1mA LOW POWER IN-AMP 10n Medical instrumentation AD8421 Precision data acquisition R NOISE ONLY Microphone preamplification S 1n Vibration analysis 100 1k 10k 100k 1M Multiplexed input applications SOURCE RESISTANCE, R (Ω) S ADC driver Figure 2. Noise Density vs. Source Resistance GENERAL DESCRIPTION The AD8421 is a low cost, low power, extremely low noise, ultralow The AD8421 delivers 3 nV/√Hz input voltage noise and bias current, high speed instrumentation amplifier that is ideally 200 fA/√Hz current noise with only 2 mA quiescent current, suited for a broad spectrum of signal conditioning and data making it an ideal choice for measuring low level signals. For acquisition applications. This product features extremely high applications with high source impedance, the AD8421 employs CMRR, allowing it to extract low level signals in the presence of innovative process technology and design techniques to provide high frequency common-mode noise over a wide temperature noise performance that is limited only by the sensor. range. The AD8421 uses unique protection methods to ensure robust The 10 MHz bandwidth, 35 V/μs slew rate, and 0.6 μs settling inputs while still maintaining very low noise. This protection time to 0.001% (G = 10) allow the AD8421 to amplify high speed allows input voltages up to 40 V from the opposite supply rail without damage to the part. signals and excel in applications that require high channel count, multiplexed systems. Even at higher gains, the current feedback A single resistor sets the gain from 1 to 10,000. The reference architecture maintains high performance; for example, at G = 100, pin can be used to apply a precise offset to the output voltage. the bandwidth is 2 MHz and the settling time is 0.8 μs. The The AD8421 is specified from −40°C to +85°C and has typical AD8421 has excellent distortion performance, making it suitable performance curves to 125°C. It is available in 8-lead MSOP for use in demanding applications such as vibration analysis. and SOIC packages. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. TOTAL NOISE DENSITY AT 1kHz (V/√Hz) 10123-001 10123-078 AD8421 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Gain Selection............................................................................. 20  Applications....................................................................................... 1  Reference Terminal .................................................................... 21  Pin Connection Diagram ................................................................ 1  Input Voltage Range................................................................... 21  General Description ......................................................................... 1  Layout .......................................................................................... 21  Revision History ............................................................................... 2  Input Bias Current Return Path ............................................... 22  Specifications..................................................................................... 3  Input Voltages Beyond the Supply Rails.................................. 22  AR and BR Grades........................................................................ 3  Radio Frequency Interference (RFI)........................................ 23  ARM and BRM Grades................................................................ 5  Calculating the Noise of the Input Stage................................. 23  Absolute Maximum Ratings............................................................ 8  Applications Information .............................................................. 25  Thermal Resistance ...................................................................... 8  Differential Output Configuration .......................................... 25  ESD Caution.................................................................................. 8  Driving an ADC ......................................................................... 26  Pin Configuration and Function Descriptions............................. 9  Outline Dimensions....................................................................... 27  Typical Performance Characteristics ........................................... 10  Ordering Guide .......................................................................... 27  Theory of Operation ...................................................................... 20  Architecture................................................................................. 20  REVISION HISTORY 5/12—Revision 0: Initial Version Rev. 0 | Page 2 of 28 Data Sheet AD8421 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. AR AND BR GRADES Table 1. AR Grade BR Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ V = −10 V to +10 V CM Source Imbalance G = 1 86 94 dB G = 10 106 114 dB G = 100 126 134 dB G = 1000 136 140 dB Over Temperature, G = 1 T = −40°C to +85°C 80 93 dB CMRR at 20 kHz VCM = −10 V to +10 V G = 1 80 80 dB G = 10 90 100 dB G = 100 100 110 dB G = 1000 110 120 dB NOISE 1 Voltage Noise, 1 kHz VIN+, VIN− = 0 V Input Voltage Noise, eni 3 3.2 3 3.2 nV/√Hz Output Voltage Noise, e 60 60 nV/√Hz no Peak to Peak, RTI f = 0.1 Hz to 10 Hz G = 1 2 2 2.2 μV p-p G = 10 0.5 0.5 μV p-p G = 100 to 1000 0.07 0.07 0.09 μV p-p Current Noise Spectral Density f = 1 kHz 200 200 fA/√Hz Peak to Peak, RTI f = 0.1 Hz to 10 Hz 18 18 pA p-p 2 VOLTAGE OFFSET Input Offset Voltage, V V = ±5 V to ±15 V 60 25 μV OSI S Over Temperature T = −40°C to +85°C 86 45 μV A Average TC 0.4 0.2 μV/°C Output Offset Voltage, VOSO 350 250 μV Over Temperature TA = −40°C to +85°C 0.66 0.45 mV Average TC 6 5 μV/°C Offset RTI vs. Supply (PSR) V = ±2.5 V to ±18 V S G = 1 90 120 100 120 dB G = 10 110 120 120 140 dB G = 100 124 130 140 150 dB G = 1000 130 140 140 150 dB INPUT CURRENT Input Bias Current 1 2 0.1 0.5 nA Over Temperature T = −40°C to +85°C 8 6 nA A Average TC 50 50 pA/°C Input Offset Current 0.5 2 0.1 0.5 nA Over Temperature TA = −40°C to +85°C 2.2 0.8 nA Average TC 1 1 pA/°C Rev. 0 | Page 3 of 28 AD8421 Data Sheet AR Grade BR Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G = 1 10 10 MHz G = 10 10 10 MHz G = 100 2 2 MHz G = 1000 0.2 0.2 MHz Settling Time to 0.01% 10 V step G = 1 0.7 0.7 μs G = 10 0.4 0.4 μs G = 100 0.6 0.6 μs G = 1000 5 5 μs Settling Time to 0.001% 10 V step G = 1 1 1 μs G = 10 0.6 0.6 μs G = 100 0.8 0.8 μs G = 1000 6 6 μs Slew Rate G = 1 to 100 35 35 V/μs 3 GAIN G = 1 + (9.9 kΩ/R) G Gain Range 1 10,000 1 10,000 V/V Gain Error V = ±10 V OUT G = 1 0.02 0.01 % G = 10 to 1000 0.2 0.1 % Gain Nonlinearity VOUT = −10 V to +10 V G = 1 R ≥ 2 kΩ 1 1 ppm L R = 600 Ω 1 3 1 3 ppm L G = 10 to 1000 R ≥ 600 Ω 30 50 30 50 ppm L VOUT = −5 V to +5 V 5 10 5 10 ppm 3 Gain vs. Temperature G = 1 5 0.1 1 ppm/°C G > 1 −50 −50 ppm/°C INPUT Input Impedance Differential 30||3 30||3 GΩ||pF Common Mode 30||3 30||3 GΩ||pF 4 Input Operating Voltage Range VS = ±2.5 V to ±18 V −VS + 2.3 +VS − 1.8 −VS + 2.3 +VS − 1.8 V Over Temperature TA = −40°C −VS + 2.5 +VS − 2.0 −VS + 2.5 +VS − 2.0 V TA = +85°C −VS + 2.1 +VS − 1.8 −VS + 2.1 +VS − 1.8 V OUTPUT RL = 2 kΩ Output Swing VS = ±2.5 V to ±18 V −VS + 1.2 +Vs − 1.6 −VS + 1.2 +VS − 1.6 V Over Temperature TA = −40°C to +85°C −VS + 1.2 +Vs − 1.6 −VS + 1.2 +VS − 1.6 V Short-Circuit Current 65 65 mA REFERENCE INPUT RIN 20 20 kΩ IIN VIN+, VIN− = 0 V 20 24 20 24 μA Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 ± 1 ± V/V 0.0001 0.0001 Rev. 0 | Page 4 of 28 Data Sheet AD8421 AR Grade BR Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit POWER SUPPLY Operating Range Dual supply ±2.5 ±18 ±2.5 ±18 V Single supply 5 36 5 36 V Quiescent Current 2 2.3 2 2.3 mA Over Temperature T = −40°C to +85°C 2.6 2.6 mA A TEMPERATURE RANGE For Specified Performance −40 +85 −40 +85 °C 5 Operational −40 +125 −40 +125 °C 1 2 2 2 Total voltage noise = √(e + (e /G) + e ). See the Theory of Operation section for more information. ni no RG 2 Total RTI VOS = (VOSI) + (VOSO/G). 3 These specifications do not include the tolerance of the external gain setting resistor, R . For G > 1, add R errors to the specifications given in this table. G G 4 Input voltage range of the AD8421 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more details. 5 See the Typical Performance Characteristics section for expected operation between 85°C and 125°C. ARM AND BRM GRADES Table 2. ARM Grade BRM Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ V = −10 V to +10 V CM Source Imbalance G = 1 84 92 dB G = 10 104 112 dB G = 100 124 132 dB G = 1000 134 140 dB Over Temperature, G = 1 T = −40°C to +85°C 80 90 dB A CMRR at 20 kHz V = −10 V to +10 V CM G = 1 80 80 dB G = 10 90 90 dB G = 100 100 100 dB G = 1000 100 100 dB NOISE 1 Voltage Noise, 1 kHz VIN+, VIN− = 0 V Input Voltage Noise, eni 3 3.2 3 3.2 nV/√Hz Output Voltage Noise, eno 60 60 nV/√Hz Peak to Peak, RTI f = 0.1 Hz to 10 Hz G = 1 2 2 2.2 μV p-p G = 10 0.5 0.5 μV p-p G = 100 to 1000 0.07 0.07 0.09 μV p-p Current Noise Spectral Density f = 1 kHz 200 200 fA/√Hz Peak to Peak, RTI f = 0.1 Hz to 10 Hz 18 18 pA p-p 2 VOLTAGE OFFSET Input Offset Voltage, VOSI VS = ±5 V to ±15 V 70 50 μV Over Temperature T = −40°C to +85°C 135 135 μV A Average TC 0.9 0.9 μV/°C Output Offset Voltage, VOSO 600 400 μV Over Temperature TA = −40°C to +85°C 1 1 mV Average TC 9 9 μV/°C Rev. 0 | Page 5 of 28 AD8421 Data Sheet ARM Grade BRM Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit Offset RTI vs. Supply (PSR) VS = ±2.5 V to ±18 V G = 1 90 120 100 120 dB G = 10 110 120 120 140 dB G = 100 124 130 140 150 dB G = 1000 130 140 140 150 dB INPUT CURRENT Input Bias Current 1 2 0.1 1 nA Over Temperature TA = −40°C to +85°C 8 6 nA Average TC 50 50 pA/°C Input Offset Current 0.5 2 0.1 1 nA Over Temperature T = −40°C to +85°C 3 1.5 nA A Average TC 1 1 pA/°C DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G = 1 10 10 MHz G = 10 10 10 MHz G = 100 2 2 MHz G = 1000 0.2 0.2 MHz Settling Time 0.01% 10 V step G = 1 0.7 0.7 μs G = 10 0.4 0.4 μs G = 100 0.6 0.6 μs G = 1000 5 5 μs Settling Time 0.001% 10 V step G = 1 1 1 μs G = 10 0.6 0.6 μs G = 100 0.8 0.8 μs G = 1000 6 6 μs Slew Rate G = 1 to 100 35 35 V/μs 3 GAIN G = 1 + (9.9 kΩ/R) G Gain Range 1 10,000 1 10,000 V/V Gain Error VOUT = ±10 V G = 1 0.05 0.02 % G = 10 to 1000 0.3 0.2 % Gain Nonlinearity V = −10 V to +10 V OUT G = 1 R ≥ 2 kΩ 1 1 ppm L R = 600 Ω 1 3 1 3 ppm L G = 10 to 1000 RL ≥ 600 Ω 30 50 30 50 ppm VOUT = −5 V to +5 V 5 10 5 10 ppm 3 Gain vs. Temperature G = 1 5 0.1 1 ppm/°C G > 1 −50 −50 ppm/°C INPUT Input Impedance Differential 30||3 30||3 GΩ||pF Common Mode 30||3 30||3 GΩ||pF Input Operating Voltage VS = ±2.5 V to ±18 V −VS + 2.3 +VS − 1.8 −VS + 2.3 +VS − 1.8 V 4 Range Over Temperature T = −40°C −V + 2.5 +V − 2.0 −V + 2.5 +V − 2.0 V A S S S S T = +85°C −V + 2.1 +V − 1.8 −V + 2.1 +V − 1.8 V A S S S S Rev. 0 | Page 6 of 28 Data Sheet AD8421 ARM Grade BRM Grade Test Conditions/ Parameter Comments Min Typ Max Min Typ Max Unit OUTPUT RL = 2 kΩ Output Swing VS = ±2.5 V to ±18 V −VS + 1.2 +VS − 1.6 −VS + 1.2 +Vs − 1.6 V Over Temperature T = −40°C to +85°C −V + 1.2 +V − 1.6 −V + 1.2 +Vs − 1.6 V A S S S Short-Circuit Current 65 65 mA REFERENCE INPUT RIN 20 20 kΩ IIN VIN+, VIN− = 0 V 20 24 20 24 μA Voltage Range −V +V −V +V V S S S S Reference Gain to Output 1 ± 1 ± V/V 0.0001 0.0001 POWER SUPPLY Operating Range Dual supply ±2.5 ±18 ±2.5 ±18 V Single supply 5 36 5 36 V Quiescent Current 2 2.3 2 2.3 mA Over Temperature TA = −40°C to +85°C 2.6 2.6 mA TEMPERATURE RANGE For Specified Performance −40 +85 −40 +85 °C 5 Operational −40 +125 −40 +125 °C 1 2 2 2 Total voltage noise = √(eni + (eno/G) + eRG ). See the Theory of Operation section for more information. 2 Total RTI V = (V ) + (V /G). OS OSI OSO 3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table. 4 Input voltage range of the AD8421 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more information. 5 See the Typical Performance Characteristics section for expected operation between 85°C and 125°C. Rev. 0 | Page 7 of 28 AD8421 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. θ is specified for a device in free air using a 4-layer JEDEC JA Parameter Rating printed circuit board (PCB). Supply Voltage ±18 V Output Short-Circuit Current Duration Indefinite Table 4. 1 Maximum Voltage at −IN or +IN −V + 40 V S Package θ Unit JA Minimum Voltage at −IN or +IN +VS − 40 V 8-Lead SOIC 107.8 °C/W 2 Maximum Voltage at REF +VS + 0.3 V 8-Lead MSOP 138.6 °C/W Minimum Voltage at REF −VS − 0.3 V Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C ESD CAUTION Maximum Junction Temperature 150°C ESD Human Body Model 2 kV Charged Device Model 1.25 kV Machine Model 0.2 kV 1 For voltages beyond these limits, use input protection resistors. See the Theory of Operation section for more information. 2 There are ESD protection diodes from the reference input to each supply, so REF cannot be driven beyond the supplies in the same way that +IN and −IN can. See the Reference Terminal section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 28 Data Sheet AD8421 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8421 1 8 –IN +V S 2 7 R V G OUT R 3 6 REF G 4 5 +IN –V S TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input Terminal. 2, 3 RG Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (9.9 kΩ/RG). 4 +IN Positive Input Terminal. 5 −V Negative Power Supply Terminal. S 6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level shift the output. 7 VOUT Output Terminal. 8 +VS Positive Power Supply Terminal. Rev. 0 | Page 9 of 28 10123-002 AD8421 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±15 V, VREF = 0 V, RL = 2 kΩ, unless otherwise noted. 600 600 500 500 400 400 300 300 200 200 100 100 0 0 –60 –40 –2006 20 400 –400 –300 –200 –100 0 100 200 300 400 INPUT OFFSET VOLTAGE (µV) OUTPUT OFFSET VOLTAGE (µV) Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Output Offset Voltage 1800 1200 1500 1000 1200 800 900 600 600 400 300 200 0 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 –2.0 –1.5 –1.0 –0.502 0.5 1.0 1.5.0 INPUT BIAS CURRENT (nA) INPUT OFFSET CURRENT (nA) Figure 5. Typical Distribution of Input Bias Current Figure 8. Typical Distribution of Input Offset Current 1600 1400 1400 1200 1200 1000 1000 800 800 600 600 400 400 200 200 0 0 –20 –15 –10 –5 0 5 10 15 20 –120 –90 –60 –30 0 30 60 90 120 PSRR (µV/V) CMRR (µV/V) Figure 9. Typical Distribution of CMRR (G = 1) Figure 6. Typical Distribution of PSRR (G = 1) Rev. 0 | Page 10 of 28 UNITS UNITS UNITS 10123-005 10123-004 10123-003 UNITS UNITS UNITS 10123-007 10123-008 10123-006 Data Sheet AD8421 15 4 G = 1 V = ±15V G = 100 S 3 10 V = ±5V S V = ±12V 2 S 5 1 V = ±2.5V S 0 0 –5 –1 –10 –2 –15 –3 –4 –3 –2 –1 0 1 2 3 4 –15 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 10. Input Common-Mode Voltage vs. Output Voltage; Figure 13. Input Common-Mode Voltage vs. Output Voltage; VS = ±12 V and ±15 V (G = 1) V = ±2.5 V and ±5 V (G = 100) S 4 40 V = 5V G = 1 S V = ±5V S G = 1 30 3 20 2 10 V = ±2.5V 1 S 0 0 –10 –1 –20 –2 –30 –3 –40 –4 –3 –2 –1 0 1 2 3 4 –35–30–25–20–15–10 –5 0 5 101520253035 40 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 11. Input Common-Mode Voltage vs. Output Voltage; Figure 14. Input Overvoltage Performance; G = 1, +V = 5 V, −V = 0 V S S VS = ±2.5 V and ±5 V (G = 1) 15 30 V = ±15V V = ±15V G = 100 S S G = 1 10 20 V = ±12V S 5 10 0 0 –5 –10 –10 –20 –15 –30 –15 –10 –5 0 5 10 15 –25 –20 –15 –10 –5 0 5 10 15 20 25 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 12. Input Common-Mode Voltage vs. Output Voltage; Figure 15. Input Overvoltage Performance; G = 1, VS = ±15 V V = ±12 V and ±15 V (G = 100) S Rev. 0 | Page 11 of 28 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) 10123-010 10123-011 10123-009 INPUT CURRENT (mA) INPUT CURRENT (mA) COMMON-MODE VOLTAGE (V) 10123-012 10123-014 10123-013 AD8421 Data Sheet 160 40 V = 5V S GAIN = 1000 G = 100 30 140 GAIN = 100 20 120 GAIN = 10 10 100 GAIN = 1 0 80 –10 60 –20 40 –30 20 –40 0 –35–30–25–20–15–10 –5 0 5 101520253035 40 0.1 1 10 100 1k 10k 100k 1M INPUT VOLTAGE (V) FREQUENCY (Hz) Figure 16. Input Overvoltage Performance; +VS = 5 V, −VS = 0 V, G = 100 Figure 19. Positive PSRR vs. Frequency 30 160 V = ±15V GAIN = 1000 S G = 100 GAIN = 100 140 20 GAIN = 10 120 10 GAIN = 1 100 0 80 60 –10 40 –20 20 –30 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) INPUT VOLTAGE (V) Figure 17. Input Overvoltage Performance; VS = ±15 V, G = 100 Figure 20. Negative PSRR vs. Frequency 2.5 70 GAIN = 1000 2.0 60 1.5 50 GAIN = 100 1.0 40 0.5 30 GAIN = 10 0 20 –0.5 10 GAIN = 1 –1.0 0 –1.5 –10 –2.0 –20 –2.5 –30 –12–10–8 –6 –4 –2 0246 8 10 12 14 100 1k 10k 100k 1M 10M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 18. Input Bias Current vs. Common-Mode Voltage Figure 21. Gain vs. Frequency Rev. 0 | Page 12 of 28 BIAS CURRENT (nA) INPUT CURRENT (mA) INPUT CURRENT (mA) 10123-017 10123-016 10123-015 GAIN (dB) NEGATIVE PSRR (dB) POSITIVE PSRR (dB) 10123-019 10123-018 10123-020 Data Sheet AD8421 160 6 GAIN = 1000 REPRESENTATIVE SAMPLES GAIN = 100 4 140 2 GAIN = 10 120 0 GAIN = 1 100 –2 80 –4 60 –6 –8 40 0.1 1 10 100 1k 10k 100k –40 –25 –10 5 20 355065 8095 110 125 TEMPERATURE (°C) FREQUENCY (Hz) Figure 22. CMRR vs. Frequency Figure 25. Input Bias Current vs. Temperature 100 160 GAIN = 1000 REPRESENTATIVE SAMPLES GAIN = 1 80 140 60 GAIN = 100 40 120 GAIN = 10 20 100 GAIN = 1 0 –20 80 –40 60 –60 –80 40 0.1 1 10 100 1k 10k 100k –40 –25 –10 5 20 355065 8095 110 125 TEMPERATURE (°C) FREQUENCY (Hz) Figure 23. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 26. Gain vs. Temperature (G = 1) 2.0 15 REPRESENTATIVE SAMPLES GAIN = 1 10 1.5 5 1.0 0 0.5 –5 0 –10 –0.5 –15 05 5 10152025 30 35 40450 –40 –25 –10 5 20 355065 8095 110 125 WARM-UP TIME (Seconds) TEMPERATURE (°C) Figure 24. Change in Input Offset Voltage (V ) vs. Warm-Up Time Figure 27. CMRR vs. Temperature (G = 1) OSI Rev. 0 | Page 13 of 28 CHANGE IN INPUT OFFSET VOLTAGE (µV) CMRR (dB) CMRR (dB) 10123-022 10123-021 10123-023 CMRR (µV/V) GAIN ERROR (µV/V) BIAS CURRENT (nA) 10123-074 10123-025 10123-024 AD8421 Data Sheet 3.0 40 –SR 35 2.5 V = ±15V S 30 2.0 +SR 25 V = ±5V S 1.5 20 15 1.0 10 0.5 5 0 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 28. Supply Current vs. Temperature (G = 1) Figure 31. Slew Rate vs. Temperature, V = ±5 V (G = 1) S 80 +V S –0.5 60 –1.0 I SHORT+ 40 –1.5 20 –2.0 0 –2.5 –20 +2.5 –40 +2.0 –60 +1.5 –40°C –80 +25°C +1.0 +85°C I SHORT– –100 +105°C +0.5 +125°C –V –120 S –40 –25 –10 5 20 35 50 65 80 95 110 125 21 4 6 8 101214 168 SUPPLY VOLTAGE (±V ) TEMPERATURE (°C) S Figure 32. Input Voltage Limit vs. Supply Voltage Figure 29. Short-Circuit Current vs. Temperature (G = 1) 40 +V S –0.5 35 –1.0 –SR 30 –1.5 +SR –2.0 25 –40°C –2.5 +25°C +85°C 20 +105°C +2.5 +125°C 15 +2.0 +1.5 10 +1.0 5 +0.5 –V 0 S –40 –25 –10 5 20 35 50 65 80 95 110 125 02 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (±V ) TEMPERATURE (°C) S Figure 33. Output Voltage Swing vs. Supply Voltage, R = 10 kΩ Figure 30. Slew Rate vs. Temperature, VS = ±15 V (G = 1) L Rev. 0 | Page 14 of 28 SLEW RATE (V/µs) SHORT-CIRCUIT CURRENT (mA) SUPPLY CURRENT (mA) 10123-028 10123-027 10123-026 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) SLEW RATE (V/µs) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 10123-029 10123-031 10123-030 Data Sheet AD8421 +V 5 S GAIN = 1 –0.5 4 –1.0 3 –1.5 2 –2.0 –40°C 1 –2.5 +25°C +85°C 0 +105°C +2.5 +125°C –1 +2.0 –2 +1.5 –3 +1.0 R = 2kΩ L –4 +0.5 R = 10kΩ L –5 –V S –10 –8 –6 –4 –2 0 2 4 6 8 10 02 4 6 8 10 12 14 16 18 20 OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (±V ) S Figure 34. Output Voltage Swing vs. Supply Voltage, R = 600 Ω Figure 37. Gain Nonlinearity (G = 1), R = 10 kΩ, 2 kΩ L L 5 15 GAIN = 1 4 10 3 2 5 –40°C 1 +25°C R = 600Ω L 0 0 +85°C +105°C +125°C –1 –5 –2 –3 –10 –4 –5 –15 –10 –8 –6 –4 –2 0 2 4 6 8 10 100 1k 10k 100k OUTPUT VOLTAGE (V) LOAD (Ω) Figure 35. Output Voltage Swing vs. Load Resistance Figure 38. Gain Nonlinearity (G = 1), R = 600 Ω L +V 100 S GAIN = 1000 –2 80 –4 60 –6 40 –8 –40°C 20 R = 600Ω +25°C L +85°C 0 +105°C +125°C +8 –20 +6 –40 +4 –60 +2 –80 –100 –V S 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 –10 –8 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) OUTPUT CURRENT (A) Figure 36. Output Voltage Swing vs. Output Current Figure 39. Gain Nonlinearity (G = 1000), RL = 600 Ω, VOUT = ±10 V Rev. 0 | Page 15 of 28 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 10123-033 10123-032 10123-034 NONLINEARITY (ppm) NONLINEARITY (ppm) NONLINEARITY (ppm) 10123-072 10123-036 10123-035 AD8421 Data Sheet 100 10k GAIN = 1000 80 60 40 1k 20 R = 600Ω L 0 –20 100 –40 –60 –80 –100 10 –5 –4 –3 –2 –1 01234 5 0.1 1 10 100 1k 10k 100k OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 40. Gain Nonlinearity (G = 1000), RL = 600 Ω, VOUT = ±5 V Figure 43. Current Noise Spectral Density vs. Frequency 1k 100 GAIN = 1 GAIN = 10 10 GAIN = 100 GAIN = 1000 5pA/DIV 1s/DIV 1 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 41. RTI Voltage Noise Spectral Density vs. Frequency Figure 44. 0.1 Hz to 10 Hz Current Noise 30 G = 1000, 40nV/DIV 25 20 15 G = 1, 1µV/DIV 10 5 1s/DIV 0 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 42. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1, G = 1000) Figure 45. Large Signal Frequency Response Rev. 0 | Page 16 of 28 VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz) NONLINEARITY (ppm) 10123-038 10123-073 10123-037 CURRENT NOISE (fA/√Hz) OUTPUT VOLTAGE (V p-p) 10123-040 10123-045 10123-039 Data Sheet AD8421 5V/DIV 5V/DIV 720ns TO 0.01% 3.8µs TO 0.01% 1.12µs TO 0.001% 5.76µs TO 0.001% 0.002%/DIV 0.002%/DIV 1µs/DIV 4µs/DIV Figure 46. Large Signal Pulse Response and Settling Time (G = 1), Figure 49. Large Signal Pulse Response and Settling Time (G = 1000), 10 V Step, V = ±15 V, R = 2 kΩ, C = 100 pF 10 V Step, V = ±15 V, R = 2 kΩ, C = 100 pF S L L S L L 2500 2000 5V/DIV 1500 420ns TO 0.01% 604ns TO 0.001% SETTLED TO 0.001% 1000 0.002%/DIV SETTLED TO 0.01% 500 1µs/DIV GAIN = 1 0 22 4 6 8 10 12 14 16 180 STEP SIZE (V) Figure 47. Large Signal Pulse Response and Settling Time (G = 10), Figure 50. Settling Time vs. Step Size (G = 1), RL = 2 kΩ, CL = 100 pF 10 V Step, V = ±15 V, R = 2 kΩ, C = 100 pF S L L GAIN = 1 5V/DIV 704ns TO 0.01% 764ns TO 0.001% 0.002%/DIV 50mV/DIV 1µs/DIV 1µs/DIV Figure 48. Large Signal Pulse Response and Settling Time (G = 100), Figure 51. Small Signal Pulse Response (G = 1), RL = 600 Ω, CL = 100 pF 10 V Step, V = ±15 V, R = 2 kΩ, C = 100 pF S L L Rev. 0 | Page 17 of 28 10123-043 10123-042 10123-041 SETTLING TIME (ns) 10123-046 10123-044 10123-054 AD8421 Data Sheet 100pF G = 1 GAIN = 10 50pF 20pF NO LOAD 50mV/DIV 1µs/DIV 50mV/DIV 1µs/DIV Figure 52. Small Signal Pulse Response (G = 10), R = 600 Ω, C = 100 pF L L Figure 55. Small Signal Response with Various Capacitive Loads (G = 1), RL = Infinity –40 R ≥ 600Ω V = 10V p-p GAIN = 100 L OUT –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 20mV/DIV 1µs/DIV –150 10 100 1k 10k FREQUENCY (Hz) Figure 56. Second Harmonic Distortion vs. Frequency (G = 1) Figure 53. Small Signal Pulse Response (G = 100), RL = 600 Ω, CL = 100 pF –40 NO LOAD V = 10V p-p GAIN = 1000 OUT –50 R = 2kΩ L R = 600Ω L –60 –70 –80 –90 –100 –110 –120 –130 –140 20mV/DIV 2µs/DIV –150 10 100 1k 10k FREQUENCY (Hz) Figure 54. Small Signal Pulse Response (G = 1000), R = 600 Ω, C = 100 pF Figure 57. Third Harmonic Distortion vs. Frequency (G = 1) L L Rev. 0 | Page 18 of 28 10123-049 10123-048 10123-047 AMPLITUDE (dBc) AMPLITUDE (dBc) 10123-053 10123-055 10123-056 Data Sheet AD8421 –40 –20 NO LOAD V = 10V p-p G = 1 V = 10V p-p OUT OUT –30 R = 2kΩ G = 10 R = 2kΩ L L –50 R = 600Ω G = 100 L –40 G = 1000 –60 –50 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –120 –110 –130 –120 –140 10 100 1k 10k 10 100 1k 10k FREQUENCY (Hz) FREQUENCY (Hz) Figure 58. Second Harmonic Distortion vs. Frequency (G = 1000) Figure 60. THD vs. Frequency –40 R ≥ 600Ω V = 10V p-p OUT L –50 –60 –70 –80 –90 –100 –110 –120 10 100 1k 10k FREQUENCY (Hz) Figure 59. Third Harmonic Distortion vs. Frequency (G = 1000) Rev. 0 | Page 19 of 28 AMPLITUDE (dBc) AMPLITUDE (dBc) 10123-076 10123-075 AMPLITUDE (dBc) 10123-077 AD8421 Data Sheet THEORY OF OPERATION +V S II V B I I B B COMPENSATION COMPENSATION A1 A2 10kΩ C1 C2 +V S 10kΩ NODE 1 A3 OUTPUT NODE 2 +V 10kΩ S R1 R2 –V S 4.95kΩ 4.95kΩ Q1 Q2 10kΩ ESD AND ESD AND +V +V S S REF –IN OVERVOLTAGE superβ superβ OVERVOLTAGE +IN PROTECTION PROTECTION R G NODE 3 NODE 4 –V S I I –V S DIFFERENCE GAIN STAGE AMPLIFIER STAGE Figure 61. Simplified Schematic Users can easily and accurately set the gain using a single ARCHITECTURE standard resistor. The AD8421 is based on the classic 3-op-amp topology. This topology has two stages: a preamplifier to provide differential GAIN SELECTION amplification, followed by a difference amplifier that removes the Placing a resistor across the RG terminals sets the gain of the common-mode voltage. Figure 61 shows a simplified schematic AD8421. The gain can be calculated by referring to Table 6 or of the AD8421. by using the following gain equation: Topologically, Q1, A1, R1 and Q2, A2, R2 can be viewed as 9.9kΩ RG = precision current feedback amplifiers. Input Transistors Q1 and G−1 Q2 are biased at a fixed current so that any input signal forces The AD8421 defaults to G = 1 when no gain resistor is used. To the output voltages of A1 and A2 to change accordingly. The determine the total gain accuracy of the system, add the tolerance differential signal applied to the inputs is replicated across the and gain drift of the RG resistor to the specifications of the AD8421. RG pins. Any current through RG also flows through R1 and R2, When the gain resistor is not used, gain error and gain drift are creating a gained differential voltage between Node 1 and Node 2. minimal. The amplified differential and common-mode signals are applied Table 6. Gains Achieved Using 1% Resistors to a difference amplifier that rejects the common-mode voltage 1% Standard Table Value of R Calculated Gain but preserves the amplified differential voltage. The difference G 10 kΩ 1.99 amplifier employs innovations that result in very low output errors 2.49 kΩ 4.98 such as offset voltage and drift, distortion at various loads, as well 1.1 kΩ 10.00 as output noise. Laser-trimmed resistors allow for a highly accurate 523 Ω 19.93 in-amp with gain error less than 0.01% and CMRR that exceeds 200 Ω 50.50 94 dB (G = 1). The high performance pinout and special attention given to design and layout allow for high CMRR performance 100 Ω 100.0 across a wide frequency and temperature range. 49.9 Ω 199.4 20 Ω 496.0 Using superbeta input transistors and bias current compensation, 10 Ω 991.0 the AD8421 offers extremely high input impedance, low bias cur- 4.99 Ω 1985 rent, low offset current, low current noise, and extremely low voltage noise of 3 nV/√Hz. The current-limiting and overvoltage R Power Dissipation G protection scheme allow the input to go 40 V from the opposite The AD8421 duplicates the differential voltage across its inputs rail at all gains without compromising the noise performance. onto the R resistor. Choose an R resistor size that is sufficient G G The transfer function of the AD8421 is to handle the expected power dissipation at ambient temperature. V = G × (V − V ) + V OUT +IN −IN REF 9.9kΩ where G = 1 + R G Rev. 0 | Page 20 of 28 10123-057 Data Sheet AD8421 Common-Mode Rejection Ratio over Frequency REFERENCE TERMINAL Poor layout can cause some of the common-mode signals to The output voltage of the AD8421 is developed with respect to be converted to differential signals before reaching the in-amp. the potential on the reference terminal. This can be used to sense Such conversions occur when one input path has a frequency the ground at the load, thereby taking advantage of the CMRR to response that is different from the other. To maintain high CMRR reject ground noise or to introduce a precise offset to the signal over frequency, closely match the input source impedance and at the output. For example, a voltage source can be tied to the REF capacitance of each path. Place additional source resistance in pin to level shift the output, allowing the AD8421 to drive a single- the input path (for example, input protection resistors) close to supply ADC. The REF pin is protected with ESD diodes and the in-amp inputs, to minimize the interaction of the resistance should not exceed either +VS or −VS by more than 0.3 V. with parasitic capacitance from the PCB traces. For best performance, maintain a source impedance to the Parasitic capacitance at the gain setting pins (RG) can also affect REF terminal that is below 1 Ω. As shown in Figure 61, the CMRR over frequency. If the board design has a component at reference terminal, REF, is at one end of a 10 kΩ resistor. the gain setting pins (for example, a switch or jumper), choose Additional impedance at the REF terminal adds to this 10 kΩ a component such that the parasitic capacitance is as small as resistor and results in amplification of the signal connected to possible. the positive input. The amplification from the additional R REF can be calculated as follows: Power Supplies and Grounding 2(10 kΩ + RREF)/(20 kΩ + RREF) Use a stable dc voltage to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR. Place a 0.1 μF capacitor as close as possible to each supply pin. INCORRECT CORRECT Because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. Any parasitic inductance in the bypass ground trace works against AD8421 AD8421 the low impedance that is created by the bypass capacitor. As REF REF shown in Figure 64, a 10 μF capacitor can be used farther away V from the device. For these larger value capacitors, which are V intended to be effective at lower frequencies, the current return + path distance is less critical. In most cases, the 10 μF capacitor OP1177 – can be shared by other local precision integrated circuits. +V S Figure 62. Driving the Reference Pin 0.1µF 10µF INPUT VOLTAGE RANGE +IN The 3-op-amp architecture of the AD8421 applies gain in the first stage before removing the common-mode voltage in the V OUT R G AD8421 difference amplifier stage. Internal nodes between the first and LOAD second stages (Node 1 and Node 2 in Figure 61) experience REF –IN a combination of a gained signal, a common-mode signal, and a diode drop. The voltage supplies can limit the combined signal, 0.1µF 10µF even when the individual input and output signals are not limited. –V S Figure 10 through Figure 13 show this limitation in detail. Figure 64. Supply Decoupling, REF, and Output Referred to Local Ground LAYOUT A ground plane layer helps to reduce parasitic inductances, which To ensure optimum performance of the AD8421 at the PCB level, minimizes voltage drops with changes in current. The area of care must be taken in the design of the board layout. The pins of the current path is directly proportional to the magnitude of the AD8421 are arranged in a logical manner to aid in this task. parasitic inductances and, therefore, the impedance of the path at high frequency. Large changes in currents in an inductive 1 –IN 8 +V S decoupling path or ground return create unwanted effects due 2 R 7 V G OUT to the coupling of such changes into the amplifier inputs. 6 R 3 REF G 5 +IN 4 –V S Because load currents flow from the supplies, the load should be AD8421 connected at the same physical location as the bypass capacitor TOP VIEW (Not to Scale) grounds. Figure 63. Pin Configuration Diagram Rev. 0 | Page 21 of 28 10123-059 10123-058 10123-060 AD8421 Data Sheet Reference Pin protection required at all gains. For example, if +V = +5 V and S −V = −8 V, the part can safely withstand voltages from −35 V to S The output voltage of the AD8421 is developed with respect to +32 V. the potential on the reference terminal. Ensure that REF is tied to the appropriate local ground. The remaining AD8421 terminals should be kept within the supplies. All terminals of the AD8421 are protected against ESD. INPUT BIAS CURRENT RETURN PATH Input Voltages Beyond the Maximum Ratings The input bias current of the AD8421 must have a return path For applications where the AD8421 encounters voltages beyond the to ground. When using a floating source without a current return limits in the Absolute Maximum Ratings table, external protection path (such as a thermocouple), create a current return path as is required. This external protection depends on the duration of shown in Figure 65. the overvoltage event and the noise performance that is required. INCORRECT CORRECT +V +V S S For short-lived events, transient protectors (such as metal oxide varistors (MOVs)), may be all that is required. +V +V S S R PROTECT AD8421 AD8421 + + I I V V IN+ IN+ REF REF – – AD8421 AD8421 R PROTECT –V –V + S S + V –V –V IN– S S V IN– TRANSFORMER TRANSFORMER – – +V +V S S TRANSIENT PROTECTION SIMPLE CONTINUOUS PROTECTION +V S +V +V S S R R PROTECT PROTECT I + + AD8421 AD8421 I V V IN+ IN+ –V – – S REF REF AD8421 AD8421 +V S 10MΩ R R PROTECT PROTECT + + –V –V S S –V –V V S V S IN– IN– –V – – THERMOCOUPLE THERMOCOUPLE S LOW NOISE CONTINUOUS LOW NOISE CONTINUOUS +V +V S S OPTION 1 OPTION 2 C C Figure 67. Input Protection Options for Input Voltages Beyond Absolute Maximum Ratings 1 R f = HIGH-PASS AD8421 AD8421 2πRC For longer events, use resistors in series with the inputs, combined C C REF REF with diodes. To avoid degrading bias current performance, low R leakage diodes such as the BAV199 or FJH1100 are recommended. The diodes prevent the voltage at the input of the amplifier from –V –V S S exceeding the maximum ratings, and the resistors limit the current CAPACITIVELY COUPLED CAPACITIVELY COUPLED into the diodes. Because most external diodes can easily handle Figure 65. Creating an Input Bias Current Return Path 100 mA or more, resistor values do not need to be large and, INPUT VOLTAGES BEYOND THE SUPPLY RAILS therefore, have a minimal impact on noise performance. The AD8421 has very robust inputs. It typically does not need At the expense of some noise performance, another solution is additional input protection, as shown in Figure 66. to use series resistors. In the case of overvoltage, current into +V S the AD8421 inputs is internally limited. Although the AD8421 + inputs must be kept within the limits defined in the Absolute I V IN+ – Maximum Ratings section, the I × R drop across the protection AD8421 resistor increases the maximum voltage that the system can withstand, as follows: + –V S V IN+ – For positive input signals MOST APPLICATIONS VMAX_NEW = (40 V + Negative Supply) + IIN × RPROTECT Figure 66. Typical Application; No Input Protection Required For negative input signals The AD8421 inputs are current limited; therefore, input voltages VMIN_NEW = (Positive Supply − 40 V) − IOUT × RPROTECT can be up to 40 V from the opposite supply rail, with no input Rev. 0 | Page 22 of 28 10123-062 10123-061 10123-063 Data Sheet AD8421 Overvoltage performance is shown in Figure 14, Figure 15, To achieve low noise and sufficient RFI filtering, the use of chip Figure 16, and Figure 17. The AD8421 inputs can withstand ferrite beads is recommended. Ferrite beads increase their impe- a current of 40 mA at room temperature for at least a day. This dance with frequency, thus leaving the signal of interest unaffected time is cumulative over the life of the device. If long periods of while preventing RF interference to reach the amplifier. They also overvoltage are expected, the use of an external protection method help to eliminate the need for large resistor values in the filter, is recommended. Under extreme input conditions, the output thus minimizing the system’s input-referred noise. The selection of the amplifier may invert. of the appropriate ferrite bead and capacitor values is a function of the interference frequency, input lead length, and RF power. RADIO FREQUENCY INTERFERENCE (RFI) For best results, place the RFI filter network as close as possible RF rectification is often a problem when amplifiers are used in to the amplifier. Layout is critical to ensure that RF signals are applications that have strong RF signals. The problem is intensified not picked up on the traces after the filter. If RF interference is if long leads or PCB traces are required to connect the amplifier too strong to be filtered sufficiently, shielding is recommended. to the signal source. The disturbance can appear as a dc offset voltage or a train of pulses. The resistors used for the RFI filter can be the same as those used for input protection. High frequency signals can be filtered with a low-pass filter network at the input of the instrumentation amplifier, as shown CALCULATING THE NOISE OF THE INPUT STAGE in Figure 68. The total noise of the amplifier front end depends on much more +V S than the 3.2 nV/√Hz specification of this data sheet. The three main contributors to noise are: the source resistance, the voltage 0.1µF 10µF noise of the instrumentation amplifier, and the current noise of C C the instrumentation amplifier. 1nF L* R +IN In the following calculations, noise is referred to the input (RTI). 33Ω V In other words, all sources of noise are calculated as if the source C OUT D AD8421 10nF appeared at the amplifier input. To calculate the noise referred L* R REF to the amplifier output (RTO), multiply the RTI noise by the –IN 33Ω C C gain of the instru-mentation amplifier. 1nF Source Resistance Noise 0.1µF 10µF Any sensor connected to the AD8421 has some output resistance. –V S There may also be resistance placed in series with inputs for pro- *CHIP FERRITE BEAD. tection from either overvoltage or radio frequency interference. Figure 68. RFI Suppression This combined resistance is labeled R1 and R2 in Figure 69. Any resistor, no matter how well made, has an intrinsic level of noise. The choice of resistor and capacitor values depends on the This noise is proportional to the square root of the resistor value. desired trade-off between noise, input impedance at high At room temperature, the value is approximately equal to frequencies, CMRR, signal bandwidth, and RFI immunity. An 4 nV/√Hz × √(resistor value in kΩ). RC network limits both the differential and common-mode bandwidth, as shown in the following equations: SENSOR 1 FilterFrequency = DIFF 2πR(2C + C ) D C R R1 G AD8421 1 FilterFrequency = CM 2πRC C R2 where CD ≥ 10 CC. Figure 69. Source Resistance from Sensor and Protection Resistors C affects the differential signal, and C affects the common- D C For example, assume that the combined sensor and protection mode signal. A mismatch between R × C at the positive input C resistance is 4 kΩ on the positive input and 1 kΩ on the negative and R × C at the negative input degrades the CMRR of the C input. Then the total noise from the input resistance is AD8421. By using a value of CD that is one order of magnitude larger than CC, the effect of the mismatch is reduced and CMRR 2 2 (4× 4) +(4× 1) = 64+16= 8.9 nV/√Hz performance is improved near the cutoff frequencies. Rev. 0 | Page 23 of 28 10123-067 10123-065 AD8421 Data Sheet Voltage Noise of the Instrumentation Amplifier For example, if the R1 source resistance in Figure 69 is 4 kΩ, and the R2 source resistance is 1 kΩ, the total effect from the The voltage noise of the instrumentation amplifier is calculated current noise is calculated as follows: using three parameters: the device output noise, the input noise, and the RG resistor noise. It is calculated as follows: 2 2 () 4×0.2 +(1×0.2) = 0.8 nV/√Hz Total Voltage Noise = Total Noise Density Calculation 2 2 2 (Output Noise /G) +(InputNoise) +(Noise of R Resistor) G To determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current For example, for a gain of 100, the gain resistor is 100 Ω. Therefore, noise contribution by the sum of squares method. the voltage noise of the in-amp is For example, if the R1 source resistance in Figure 69 is 4 kΩ, the 2 2 2 R2 source resistance is 1 kΩ, and the gain of the in-amp is 100, () 60/100 + 3.2 +(4× 0.1) = 3.5 nV/√Hz the total noise, referred to input, is Current Noise of the Instrumentation Amplifier 2 2 2 Current noise is converted to a voltage by the source resistance. 8.9 + 3.5 + 0.8 = 9.6 nV/√Hz The effect of current noise can be calculated by multiplying the specified current noise of the in-amp by the value of the source resistance. Rev. 0 | Page 24 of 28 Data Sheet AD8421 APPLICATIONS INFORMATION Although the dc performance and resistor matching of the op amp DIFFERENTIAL OUTPUT CONFIGURATION affect the dc common-mode output accuracy, such errors are Figure 70 shows an example of how to configure the AD8421 for likely to be rejected by the next device in the signal chain and, differential output. therefore, typically have little effect on overall system accuracy. +IN Because this circuit is susceptible to instability, a capacitor is AD8421 +OUT included to limit the effective op amp bandwidth. This capacitor –IN can be omitted if the amplifier pairing is stable. 10kΩ REF V BIAS The open-loop gain and phase of any amplifier may vary with process variation and temperature. Additional phase lag can be – + introduced by resistive or capacitive loading. To guarantee 10kΩ OP AMP 12pF stability, the value of the capacitor in Figure 70 should be determined with a sample of circuits by evaluating the small signal pulse response of the circuit with load at the extremes of the –OUT output dynamic range. Figure 70. Differential Output Configuration with Op Amp The ambient temperature should also be varied over the expected The differential output voltage is set by the following equation: range to evaluate its effect on stability. The voltage at +OUT may V = V − V = Gain × (V − V ) DIFF_OUT +OUT −OUT +IN −IN still have some overshoot after the circuit is tuned because the The common-mode output is set by the following equation: AD8421 output amplifier responds faster than the op amp. A 12 pF capacitor is a good starting point. VCM_OUT = (V+OUT + V−OUT)/2 = VBIAS For best large signal ac performance, use an op amp with a high The advantage of this circuit is that the dc differential accuracy slew rate to match the AD8421 performance of 35 V/μs. High depends on the AD8421, not on the op amp or the resistors. In bandwidth is not essential because the system bandwidth is limited addition, this circuit takes advantage of the precise control that the by the RC feedback. Some good choices for op amps are the AD8421 has of its output voltage relative to the reference voltage. AD8610, ADA4627-1, AD8510, and the ADA4898-1. Rev. 0 | Page 25 of 28 10123-066 AD8421 Data Sheet frequency, and set the filter cutoff to settle to ½ LSB in one DRIVING AN ADC sampling period for a full-scale step. For additional considerations, The Class AB output stage, low noise and distortion, and high refer to the data sheet of the ADC in use. bandwidth and slew rate make the AD8421 a good choice for driving an ADC in a data acquisition system that requires front- In a gain-of-10 configuration, the AD8421 has approximately end gain, high CMRR, and dc precision. Figure 71 shows the 8 nV/√Hz voltage noise RTI (See the Calculating the Noise of AD8421, in a gain-of-10 configuration, driving the AD7685, the Input Stage section.) The front-end gain makes the system a 16-bit, 250 kSPS pseudodifferential SAR ADC. The RC low-pass ten times more sensitive to input signals, with only a 7.5 dB reduction of SNR. The high current output and load regulation filter that is shown between the AD8421 and the AD7685 has of the ADR435 allow the AD7685 to be powered directly from the several purposes. It isolates the amplifier output from excessive reference without the need to provide another analog supply rail. loading from the dynamic ADC inputs, reduces the noise The reference pin buffer may be any low power, unity-gain stable, bandwidth of the amplifier, and provides overload protection for the AD7685 analog inputs. The filter cutoff can be determined dc precision op amp with less than approximately 25 nV/√Hz of empirically. To achieve the best ac performance, keep the impe- wideband noise, such as the OP1177. Not all proper decoupling is dance magnitude greater than 1 kΩ at the maximum input signal shown in Figure 71. Take care to follow decoupling guidelines for both amplifiers and the ADR435. +5V 10Ω +12V ADR435 10kΩ 0.1µF 1µF 2.5V ±250mV +12V 10kΩ +IN G = 10 REF VDD VIO 100Ω SDI 1.1kΩ IN+ AD8421 3nF SCK REF 3- OR 4-WIRE INTERFACE AD7685 –IN SDO –12V IN– CNV GND 2.5V 10µF 5kΩ Figure 71. AD8421 Driving an ADC 0 SNR 81.12dB THD –100.91dB –20 SFDR 90.71dB –40 –60 –80 –100 –120 –140 –160 0 25 50 75 100 125 FREQUENCY (kHz) Figure 72. Typical Spectrum of the AD8421 (G = 10) Driving the AD7685 Rev. 0 | Page 26 of 28 AMPLITUDE (dB OF FULL SCALE) 10123-071 10123-070 Data Sheet AD8421 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 73. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 74. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8421ARZ −40°C to +85°C 8-Lead SOIC_N, standard grade R-8 AD8421ARZ-R7 −40°C to +85°C 8-Lead SOIC_N, standard grade, 7” Tape and Reel, R-8 AD8421ARZ-RL −40°C to +85°C 8-Lead SOIC_N, standard grade, 13” Tape and Reel R-8 AD8421BRZ −40°C to +85°C 8-Lead SOIC_N, high performance grade R-8 AD8421BRZ-R7 −40°C to +85°C 8-Lead SOIC_N, high performance grade, 7” Tape and Reel R-8 AD8421BRZ-RL −40°C to +85°C 8-Lead SOIC_N, high performance grade, 13” Tape and Reel R-8 AD8421ARMZ −40°C to +85°C 8-Lead MSOP, standard grade RM-8 Y49 AD8421ARMZ-R7 −40°C to +85°C 8-Lead MSOP, standard grade, 7” Tape and Reel RM-8 Y49 AD8421ARMZ-RL −40°C to +85°C 8-Lead MSOP, standard grade, 13” Tape and Reel RM-8 Y49 AD8421BRMZ −40°C to +85°C 8-Lead MSOP, high performance grade RM-8 Y4A AD8421BRMZ-R7 −40°C to +85°C 8-Lead MSOP, high performance grade, 7” Tape and Reel RM-8 Y4A AD8421BRMZ-RL −40°C to +85°C 8-Lead MSOP, high performance grade, 13” Tape and Reel RM-8 Y4A 1 Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 10-07-2009-B 012407-A AD8421 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10123-0-5/12(0) Rev. 0 | Page 28 of 28