ANALOG DEVICES AD8398A

Single Port VDSL2 Line Driver with Shutdown AD8398A FEATURES FUNCTIONAL BLOCK DIAGRAM Voltage feedback Wide output swing 18.4 V p-p differential, R = 20 Ω from 12 V supply LOAD, DIFF High output current NC 1 12 NC Linear output current of 450 mA peak – – −IN A 2 11−IN B +IN A 3 + + 10 +IN B Low distortion GND 4 9PD1 −65 dBc for Profile 8b @ 20.4 dBm −55 dBc for Profile 17a @ 14.5 dBm High speed 85 MHz bandwidth (A = 5) V DIFF NC = NO CONNECT Figure 1. Thermally Enhanced, 4 mm × 4 mm, 16-Lead LFCSP_WQ APPLICATIONS ADSL2+/VDSL2 CO/CPE line drivers TYPICAL APPLICATION DIAGRAM PLC line drivers Consumer xDSL modems Twisted pair line drivers TIP 1/2 AD8398A V * MID RING 1/2 AD8398A + V V CC EE = *V MID 2 Figure 2. Typical VDSL2 Application GENERAL DESCRIPTION The AD8398A comprises two high speed, voltage feedback The AD8398A incorporates power management functionality operational amplifiers. When configured as a differential line via two CMOS-compatible control pins, PD0 and PD1. These driver, the AD8398A is an ideal choice for ADSL2+, VDSL2, and pins select one of four operating modes: full power, medium power line communications (PLC) applications. It has high power, low power, or complete power-down. In the power-down output current, high bandwidth, and fast slew rate, combined mode, the quiescent current drops to 0.7 mA. with exceptional multitone power ratio (MTPR) and common- The AD8398A operates in the industrial temperature range of mode stability. The AD8398A is available in a thermally enhanced −40°C to +85°C. 4 mm × 4 mm, 16-lead LFCSP. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07760-001 07760-002 16 OUT A NC 5 NC 6 15 NC 14 V V 7 EE CC PD0 8 13 OUT B AD8398A TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ..............................................6  Applications....................................................................................... 1  Applications Information .................................................................8  Functional Block Diagram .............................................................. 1  Power Control Modes of Operation ...........................................8  Typical Application Diagram .......................................................... 1  Exposed Thermal Pad Connections ...........................................8  General Description ......................................................................... 1  Power Supply Bypassing...............................................................8  Revision History ............................................................................... 2  Board Layout..................................................................................8  Specifications..................................................................................... 3  Multitone Power Ratio..................................................................9  Absolute Maximum Ratings............................................................ 4  Lightning and AC Power Fault....................................................9  Thermal Resistance ...................................................................... 4  Outline Dimensions....................................................................... 10  Maximum Power Dissipation ..................................................... 4  Ordering Guide .......................................................................... 10  ESD Caution.................................................................................. 4  Pin Configuration and Function Descriptions............................. 5  REVISION HISTORY 9/10—Rev. C to Rev. D Change to General Description Section ........................................ 1 3/10—Rev. B to Rev. C Changes to Figure 14........................................................................ 9 12/09—Rev. A to Rev. B Changes to Figure 13, Figure 14, and Figure 15 ........................... 9 10/09—Rev. Sp0 to Rev. A Changed R to R Throughout........................................ 1 LOAD LOAD, Diff Changes to DC Performance, Differential Input Offset Voltage Parameter, Table 1 .............................................................. 3 Changes to Figure 4.......................................................................... 5 Changes to Figure 8 and Figure 9................................................... 6 Changes to Exposed Thermal Pad Connections Section............ 8 11/08—Revision Sp0: Initial Version Rev. D | Page 2 of 12 AD8398A SPECIFICATIONS VS = 12 V, ±6 V at TA = 25°C, AV DIFF = 5, RLOAD, DIFF = 20 Ω, PD1 = 0, PD0 = 0, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth A = 5, V = 2 V peak, measured differentially V DIFF OUT PD1 = 0, PD0 = 0 85 MHz PD1 = 0, PD0 = 1 85 MHz PD1 = 1, PD0 = 0 75 MHz Slew Rate V = 4 V peak, measured differentially 600 V/μs OUT NOISE/DISTORTION PERFORMANCE MTPR Profile 8b at 20.4 dBm in VDSL2 application −65 dBc Profile 17a at 14.5 dBm in VDSL2 application −55 dBc Off Isolation PD1 = 1, PD0 = 1 −80 dBc Input Voltage Noise f = 100 kHz 4.8 nV/√Hz Input Current Noise f = 100 kHz 0.9 pA/√Hz Differential Output Voltage Noise f = 100 kHz in VDSL2 application 120 nV/√Hz DC PERFORMANCE Differential Input Offset Voltage −2 ±0.1 +2 mV Input Offset Voltage 16 55 mV Input Bias Current 0.5 1 μA Open-Loop Gain 63 dB Common-Mode Rejection Measured differentially −100 −74 dB INPUT CHARACTERISTICS Input Resistance f < 100 kHz 1.9 MΩ OUTPUT CHARACTERISTICS Differential Swing 17.6 18.4 V p-p Linear Peak Output Current VDSL2 at 20.4 dBm, MTPR = −65 dBc 450 mA peak POWER SUPPLY Operating Range Dual supply ±6 V Single supply 12 V Supply Current PD1 = 0, PD0 = 0 29 33.2 37 mA PD1 = 0, PD0 = 1 20 22.9 25.5 mA PD1 = 1, PD0 = 0 12 13.3 14.5 mA PD1 = 1, PD0 = 1 0.7 1.1 mA Power Supply Rejection Measured differentially −94 −74 dB POWER-DOWN PINS PD1, PD0 V Referenced to GND 0.8 V IL PD1, PD0 V Referenced to GND 2 V IH PD1, PD0 Bias Current PD1, PD0 = 0 V 15 30 μA PD1, PD0 = 3 V 6 17 μA Enable Time PD1, PD0 = (1, 1) − (0, 0) 60 μs Disable Time PD1, PD0 = (0, 0) − (1, 1) 600 μs Rev. D | Page 3 of 12 AD8398A ABSOLUTE MAXIMUM RATINGS Table 2. MAXIMUM POWER DISSIPATION Parameter Rating The maximum safe power dissipation for the AD8398A is limited Power Supplies (V − V) 13.2 V CC EE by its junction temperature (T ) on the die. The maximum safe J Power Dissipation (T − T )/θ J MAX A JA TJ of plastic encapsulated devices, as determined by the glass Storage Temperature Range −65°C to +125°C transition temperature of the plastic, is 150°C. Temporarily Operating Temperature Range −40°C to +85°C exceeding this limit may cause a shift in the parametric Lead Temperature (Soldering, 10 sec) 300°C performance due to a change in the stresses exerted on the Junction Temperature 150°C die by the package. Exceeding this limit for an extended period can result in device failure. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Figure 3 shows the maximum safe power dissipation in the rating only; functional operation of the device at these or any package vs. the ambient temperature for the 16-lead LFCSP_WQ other conditions above those indicated in the operational on a 4-layer board with six vias connecting the exposed pad to section of this specification is not implied. Exposure to absolute the GND plane layer. maximum rating conditions for extended periods may affect 6 T = 150°C J device reliability. 5 THERMAL RESISTANCE θ is specified with the device soldered on a JEDEC circuit JA 4 board and the thermal pad connected to the GND plane layer using six vias. 3 Table 3. Thermal Resistance 2 Package Type θJA Unit 16-Lead LFCSP_WQ 35.6 °C/W 1 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 AMBIENT TEMPERATURE (°C) Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature, 4-Layer JEDEC Board with Six Thermal Vias ESD CAUTION Rev. D | Page 4 of 12 MAXIMUM POWER DISSIPATION (W) 07760-003 AD8398A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 12 NC −IN A 2 11 −IN B AD8398A +IN A 3 10 +IN B 4 9 PD1 GND TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT 2. EXPOSED PADDLE (EPAD) IS FLOATING, NOT ELECTRICALLY CONNECTED INTERNALLY. Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1, 5, 6, 12, 15 NC No Connect. 2 −IN A Amplifier A Inverting Input. 3 +IN A Amplifier A Noninverting Input. 4 GND Ground. 7 VEE Negative Power Supply Input. 8 PD0 Power Mode Control. 9 PD1 Power Mode Control. 10 +IN B Amplifier B Noninverting Input. 11 −IN B Amplifier B Inverting Input. 13 OUT B Amplifier B Output. 14 VCC Positive Power Supply Input. 16 OUT A Amplifier A Output. EPAD Exposed Paddle (EPAD) The exposed paddle is electrically isolated. Rev. D | Page 5 of 12 07760-004 NC 5 16 OUT A NC 6 15 NC V 7 14 V EE CC PD0 8 13 OUT B AD8398A TYPICAL PERFORMANCE CHARACTERISTICS VCC = 6 V, VEE = −6 V, unless otherwise stated. 21 18 15 DIFFERENTIAL 12 9 1/2 6 AD8398A 3 V * COMMON-MODE MID R = 20Ω 0 LOAD, DIFF –3 –6 PD1 = 0, PD0 = 0 1/2 PD1 = 0, PD0 = 1 –9 PD1 = 1, PD0 = 0 AD8398A –12 0.1 1 10 100 1000 + V V CC EE = *V MID 2 FREQUENCY (MHz) Figure 5. Small Signal Differential and Common-Mode Frequency Response; Figure 8. Typical Differential Application Circuit AV DIFF = 5 (See the Application Circuit in Figure 8) RLOAD, DIFF = 20 Ω 18 DIFFERENTIAL 15 12 9 6 1/2 3 COMMON-MODE 0 AD8398A –3 V * MID R = 20Ω LOAD, DIFF –6 –9 –12 1/2 PD1 = 0, PD0 = 0 –15 PD1 = 0, PD0 = 1 –18 AD8398A PD1 = 1, PD0 = 0 –21 0.1 1 10 100 1000 + V V CC EE = *V FREQUENCY (MHz) MID 2 Figure 6. Small Signal Differential and Common-Mode Frequency Response Figure 9. Typical Differential Application Circuit with Positive Feedback (See the Application Circuit in Figure 9) R = 20 Ω LOAD, DIFF 30 DIFFERENTIAL 20 10 0 TIP 1/2 PD1 = 0, PD0 = 0 –10 PD1 = 0, PD0 = 1 AD8398A PD1 = 1, PD0 = 0 –20 V * MID –30 –40 COMMON-MODE –50 RING 1/2 –60 AD8398A –70 + 0.1 1 10 100 1000 V V CC EE = *V MID 2 FREQUENCY (MHz) Figure 10. Typical VDSL2 Application Circuit Figure 7. Small Signal Differential and Common-Mode Frequency Response (See the Application Circuit in Figure 10) Rev. D | Page 6 of 12 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 07760-019 07760-018 07760-017 07760-014 07760-016 07760-015 AD8398A 1000 1000 900 800 100 700 VDSL2 PROFILE 17a VDSL2 PROFILE 8b PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 600 10 500 400 1 10 12 14 16 18 20 0.01 0.1 1 10 100 OUTPUT POWER (dBm) FREQUENCY (MHz) Figure 11. Internal Power Dissipation vs. Output Power Figure 12. Differential Output Voltage Noise vs. Frequency in a Typical VDSL2 Application Rev. D | Page 7 of 12 INTERNAL POWER DISSIPATION (mW) 07760-005 VOLTAGE NOISE (nV/√Hz) 07760-007 AD8398A APPLICATIONS INFORMATION BOARD LAYOUT POWER CONTROL MODES OF OPERATION As is the case with all high speed applications, careful attention The AD8398A features four power modes: full power, medium to printed circuit board (PCB) layout details prevents associated power, low power, and complete power-down. Two CMOS- board parasitics from becoming problematic. Proper RF design compatible logic pins (PD0 and PD1) select the power mode. technique is mandatory. The power modes and associated logic states are listed in Table 5. The PCB has a ground plane covering all unused portions of the Table 5. Power Modes component side of the board to provide a low impedance return PD1 PD0 Power Mode Total Supply Current (mA) path. Removing the ground plane on all layers from the area 0 0 Full power 33.2 near the input and output pins of the AD8398A reduces stray 0 1 Medium power 22.9 capacitance. 1 0 Low power 13.3 Signal lines connecting the feedback and gain resistors should 1 1 Power-down 0.7 be as short as possible to minimize the inductance and stray capacitance associated with these traces. Place termination resistors EXPOSED THERMAL PAD CONNECTIONS and loads as close as possible to their respective inputs and outputs. To ensure adequate heat transfer away from the die, connect To minimize coupling (crosstalk) through the board, keep input the exposed thermal pad to a solid plane layer with low thermal and output traces as far apart as possible. Wherever there are resistance. To maximize the operating life of the AD8398A, the complementary signals, provide a symmetrical layout to maximize thermal design of the system should be kept below the junction balanced performance. temperature of 125°C. Although it is electrically isolated, the thermal pad typically connects to the ground plane layer. POWER SUPPLY BYPASSING The AD8398A typically operates on ±6 V or +12 V supplies. Power the AD8398A circuit with a well-regulated, properly decoupled power supply. To minimize supply voltage ripple and power dissipation, use high quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic capacitors (MLCCs). Place a decoupling 0.1 μF MLCC no more than ⅛ inch away from each of the power supply pins. In addition, a 10 μF tantalum capacitor is recommended to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the AD8398A outputs. Lay out bypass capacitors to keep return currents away from the inputs of the amplifiers. This layout minimizes any voltage drops that can develop due to ground currents flowing through the ground plane. Rev. D | Page 8 of 12 AD8398A 0 MULTITONE POWER RATIO –10 The discrete multitone (DMT) signal used in xDSL systems –20 carries data in discrete tones or bins that appear in the frequency –30 domain in evenly spaced 4.3125 kHz intervals. In applications using this type of waveform, multitone power ratio (MTPR) is –40 a commonly used measure of linearity. Generally, designers are –50 concerned with two types of MTPR: in band and out of band. –60 In-band MTPR is defined as the measured difference from the –70 peak of one tone that is loaded with data to the peak of an adjacent –80 tone that is intentionally left empty. Out-of-band MTPR is defined as the spurious emissions that occur in the receive bands. –90 Transmit band power and receive band MTPR are shown in –100 0 0.5 1.0 1.5 2.0 2.5 3.0 Figure 13, Figure 14, and Figure 15 for Profile 17a, Profile 8b, FREQUENCY (MHz) and ADSL2+, respectively. Figure 15. MTPR of a Typical ADSL2+ DMT Test Signal, 0 V = ±6 V, Output Power = 20.4 dBm S –10 LIGHTNING AND AC POWER FAULT –20 DSL line drivers are transformer-coupled to the twisted pair –30 telephone line. In this environment, the AD8398A may be –40 subject to large line transients resulting from events such as –50 lightning strikes or downed power lines. Additional circuitry is required to protect the AD8398A from possible damage due –60 to these events. –70 –80 –90 –100 042861 102 14 16 18 20 FREQUENCY (MHz) Figure 13. MTPR of a Typical VDSL2 Profile 17a DMT Test Signal, VS = ±6 V, Output Power = 14.5 dBm 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 01 23 45 67 89 10 FREQUENCY (MHz) Figure 14. MTPR of a Typical VDSL2 Profile 8b DMT Test Signal, VS = ±6 V, Output Power = 20.4 dBm Rev. D | Page 9 of 12 OUTPUT POWER (dBm/Hz) OUTPUT POWER (dB) 07760-010 07760-020 OUTPUT POWER (dB) 07760-012 AD8398A OUTLINE DIMENSIONS 4.10 0.35 4.00 SQ 0.30 3.90 PIN 1 0.25 INDICATOR 0.65 13 16 1 BSC 12 EXPOSED 2.40 PAD 2.35 SQ 2.30 9 8 5 4 0.20 MIN 0.45 TOP VIEW BOTTOM VIEW 0.40 0.35 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TOJEDEC STANDARDS MO-220-WGGD Figure 16. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-20) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8398AACPZ-R2 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-20 AD8398AACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-20 AD8398AACPZ-RL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-20 1 Z = RoHS Compliant Part. Rev. D | Page 10 of 12 PIN 1 INDICATOR 101408-A AD8398A NOTES Rev. D | Page 11 of 12 AD8398A NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07760-0-9/10(D) Rev. D | Page 12 of 12