ANALOG DEVICES AD8396

Low Power, High Output Current, Dual-Port ADSL/ADSL2+ Line Driver AD8396 FEATURES PIN CONFIGURATION 2 differential DSL channels comprised of current feedback, high output current amplifiers Integrated feedback and gain resistors Integrated biasing network 1 12 VONA INPA Ideal for use as ADSL/ADSL2+ dual-channel Central Office INNA 2 AD8396 11 DGND (CO) line drivers TOP DGND 3 10 VOPB VIEW Low power consumption INPB 4 9 VONB Dual-supply operation from ±6 V to ±12 V Single-supply operation from 12 V to 24 V 10.8 mA quiescent supply current in full power mode 1.4 mA quiescent supply current in shutdown mode Less than 700 mW internal power dissipation while driving Figure 1. 20.4 dBm line power, 1:1 transformer High output voltage and current drive VCC 43.4 V p-p differential output voltage Low distortion −66 dBc typical MTPR @ 20.4 dBm, 26 kHz to 2.2 MHz INPA VOPA VCC High speed: 170 V/μs differential slew rate 4kΩ A = 13 VCOM-A V APPLICATIONS 4kΩ ADSL/ADSL2+ CO line drivers VEE VONA INNA GENERAL DESCRIPTION The AD8396 is comprised of four high output current, low VEE power consumption operational amplifiers. It is particularly Figure 2. Channel A Internal Schematics well suited for the CO driver interface in digital subscriber line systems, such as ADSL and ADSL2+. The driver can deliver 20.4 dBm to a line while compensating for losses due to hybrid insertion and back-termination resistors. The low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the AD8396 to be used as the CO line driver in ADSL and other xDSL systems. The AD8396 is available in a 4 mm × 4 mm 16-lead LFCSP. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07022-001 07022-002 INNB 5 16 VCOM-A B 6 PD_A VCOM- 15 PD_B 7 14 VCC VEE 8 13 VOPA AD8396 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ..............................................6  Applications ....................................................................................... 1  Theory of Operation .........................................................................8  General Description ......................................................................... 1  Applications Information .................................................................9  Pin Configuration ............................................................................. 1  Supplies, Grounding, and Layout ................................................9  Revision History ............................................................................... 2  Power Management ......................................................................9  Specif ica t ions ..................................................................................... 3  Typical ADSL/ADSL2+ Application ...........................................9  Absolute Maximum Ratings ............................................................ 4  Multitone Power Ratio (MTPR) ..................................................9  Thermal Resistance ...................................................................... 4  Lightning and AC Power Fault ................................................. 10  Maximum Power Dissipation ..................................................... 4  Outline Dimensions ....................................................................... 11  ESD Caution .................................................................................. 4  Ordering Guide .......................................................................... 11  Pin Configuration and Function Descriptions ............................. 5  REVISION HISTORY 8/09—Revision C: Initial Version Rev. C | Page 2 of 12 AD8396 SPECIFICATIONS (VCC − VEE) = 24 V, RL = 100 Ω, GDIFF = 13 (fixed), PD = (0), T = 25°C, typical DSL application circuit, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE −3 dB Small-Signal Bandwidth 8 MHz V = 0.1 V p-p, differential OUT −3 dB Large-Signal Bandwidth 8 MHz VOUT = 2 V p-p, differential Slew Rate 170 V/μs VOUT = 4 V p-p, differential Differential Gain 12.8 13 13.2 V/V NOISE/DISTORTION PERFORMANCE Second Harmonic Distortion −90 dBc fC = 2 MHz, VOUT = 2 V p-p, differential Third Harmonic Distortion −62 dBc fC = 2 MHz, VOUT = 2 V p-p, differential Multitone Input Power Ratio (MTPR) −66 dBc 26 kHz to 2.2 MHz, Z = 100 Ω, differential LINE load Differential Output Noise 140 nV/√Hz f = 10 kHz INPUT CHARACTERISTICS RTO Offset Voltage −15 −0.7 +15 mV Single-ended −15 +0.3 +15 mV Differential RTO Offset Voltage @ PD = (1) −30 +0.1 +30 mV Differential Input Bias Current −5 −1.5 +5 μA Input Resistance 8 kΩ Differential Input Capacitance 1 pF Differential OUTPUT CHARACTERISTICS Differential Output Voltage Swing 42.6 43.4 44 V p-p ΔV , R = 100 Ω OUT L Single-Ended Output Voltage Swing 21.3 21.7 22 V p-p ΔV , R = 50 Ω OUT L Output Leakage Current −100 +100 μA PD = (1) POWER SUPPLY Operating Range, Dual Supply ±6 ±12 V Operating Range, Single Supply 12 24 V Total Quiescent Current PD = (0) 9.0 10.8 13.0 mA PD = (1) Shutdown State 0 1.4 3.0 mA Common-Mode Voltage −10 +0.2 +10 mV V CM PD = (0) Threshold 0.8 V (0) = 0 V PD = (1) Threshold 1.6 V (1) = 5 V PD = (0) Input Current −100 −47 +100 μA (0) = 0 V PD = (1) Input Current −100 +1 +100 μA (1) = 5 V +Power Supply Rejection Ratio −80 −60 dB ΔV /ΔV , ΔV = ±1 V, differential OS, DM (RTI) CC CC −Power Supply Rejection Ratio −80 −60 dB ΔV /ΔV , ΔV = ±1 V, differential OS, DM (RTI) EE EE Rev. C | Page 3 of 12 AD8396 ABSOLUTE MAXIMUM RATINGS Figure 3 shows the maximum power dissipation in the package Table 2. vs. the ambient temperature for the 16-lead LFCSP on a JEDEC Parameter Rating standard 4-layer board. θJA values are approximations. Supply Voltage, V − V 26.4 V CC EE 3.5 T = 150°C Power Dissipation See Figure 3 J 3.0 Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C 2.5 Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C 2.0 Stresses above those listed under Absolute Maximum Ratings 1.5 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any 1.0 other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute 0.5 maximum rating conditions for extended periods may affect 0 device reliability. –25 –15 –5 5 1525 354555 6575 85 AMBIENT TEMPERATURE (°C) THERMAL RESISTANCE Figure 3. Maximum Power Dissipation vs. θ is specified in still air with exposed pad soldered to 4-layer JA Ambient Temperature for a 4-Layer Board JEDEC test board. θ is specified at the exposed pad. JC The power dissipated in the package (P ) is the sum of the D quiescent power dissipation and the power dissipated in the Table 3. package due to the load drive for all outputs. The quiescent Package Type θJA θJC Unit power is the voltage between the supply pins (V ) times the S 16-Lead LFCSP 56 9.1 °C/W quiescent current (IS). Assuming that the load RL is referenced to midsupply, the total drive power is VS/2 × IOUT, part of which MAXIMUM POWER DISSIPATION is dissipated in the package and part in the load (VOUT × IOUT). The maximum safe power dissipation for the AD8396 is limited RMS output voltages should be considered. If R is referenced to L by its junction temperature on the die. V , as in single-supply operation, the total power is V × I . EE S OUT The maximum safe junction temperature of plastic encapsulated In single supply with R to V , worst case is V = V /2. L EE OUT S devices, as determined by the glass transition temperature of the Airflow increases heat dissipation, effectively reducing θ . In JA plastic, is 150°C. Exceeding this limit can temporarily cause a shift addition, more copper in direct contact with the package leads in the parametric performance due to a change in the stresses from PCB traces, through-holes, ground, and power planes exerted on the die by the package. Exceeding this limit for an reduces θJA. extended period can result in device failure. ESD CAUTION Rev. C | Page 4 of 12 MAXIMUM POWER DISSIPATION (W) 07022-003 AD8396 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INPA 1 12 VONA INNA 2 AD8396 11 DGND TOP DGND 3 10 VOPB VIEW INPB 4 9 VONB NOTE THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 INPA Port A Input P 2 INNA Port A Input N 3, 11 DGND Ground 4 INPB Port B Input P 5 INNB Port B Input N 6 VCOM-B Port B Bias 7 PD_B Port B Shutdown 8 VEE Negative Power Supply 9 VONB Port B Output N 10 VOPB Port B Output P 12 VONA Port A Output N 13 VOPA Port A Output P 14 VCC Positive Power Supply 15 PD_A Port A Shutdown 16 VCOM-A Port A Bias Exposed Pad No Connection Rev. C | Page 5 of 12 07022-004 INNB 5 16 VCOM-A 6 15 PD_A VCOM-B PD_B 7 14 VCC VEE 8 13 VOPA AD8396 TYPICAL PERFORMANCE CHARACTERISTICS 2 –30 1 –40 0 –50 –1 –2 0.1V p-p –60 –3 –70 –4 –5 2V p-p –80 –6 –90 –7 –8 –100 01 0.1 1 1000 0.01 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Differential Gain vs. Frequency, RL = 100 Ω Figure 8. Crosstalk vs. Frequency, Typical ADSL/ADSL2+ Application Circuit, VOUT = 2 V p-p, RL = 100 Ω 45 6 2.0 PD PULSE 40 5 1.5 35 4 1.0 30 3 0.5 25 OUTPUT 2 0 20 1 –0.5 15 0 –1.0 10 –1 –1.5 5 0 –2 –2.0 01 10 20 30 40 50 60 70 80 900002 2468 10 12 14 16 180 LOAD (Ω) TIME (μs) Figure 6. DC Differential Output Swing vs. Load Figure 9. Power-Down/Power-Up Transition 160 1000 900 140 800 120 700 100 600 80 500 400 60 300 40 200 20 100 0 0 0.01 0.1 1 10 10 12 14 16 18 20 22 FREQUENCY (MHz) OUTPUT POWER (dBm) Figure 7. Internal Power Consumption vs. Output Power, Figure 10. Differential Output Noise vs. Frequency, Typical ADSL/ADSL2+ Application Circuit, 100 Ω Resistive Load Only Typical ADSL/ADSL2+ Application Circuit Rev. C | Page 6 of 12 INTERNAL POWER CONSUMPTION (mW) OUTPUT SWING (V p-p) NORMALIZED GAIN (dB) 07022-007 07022-006 07022-005 V (V) PD NOISE (nV/ Hz) CROSSTALK (dB) 07022-010 07022-008 V (V) OUT 07022-009 AD8396 20 –40 V = ±12V S –50 15 V = ±10V S –60 10 –70 5 –80 0 –90 –5 –100 –10 –110 02 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8.0 0.1 1 10 TIME (μs) FREQUENCY (MHz) Figure 11. Output Overdrive Recovery, Typical ADSL/ADSL2+ Figure 12. Feedthrough vs. Frequency, Application Circuit, VOUT = 3.3 VRMS, CF = 5.47, RL = 100 Ω Typical ADSL/ADSL2+ Application Circuit, VOUT = 2 V p-p, RL = 100 Ω Rev. C | Page 7 of 12 AMPLITUDE (V) 07022-011 FEEDTHROUGH (dB) 07022-012 AD8396 THEORY OF OPERATION Because G × RIN << RF for low gains, a current feedback amplifier The AD8396 is a current feedback amplifier with high output has relatively constant bandwidth vs. gain. The 3 dB point is set current capability. With a current feedback amplifier, the when |TZ| = RF. current into the inverting input is the feedback signal, and the open-loop behavior is that of a transimpedance, dVO/dIIN or TZ. In a nonideal amplifier, there are additional poles that contribute excess phase, and there is a value for R below which the amplifier F The open-loop transimpedance is analogous to the open-loop is unstable. Tolerance for peaking and desired flatness determines voltage gain of a voltage feedback amplifier. Figure 13 shows a the optimum R in each application. F simplified model of a current feedback amplifier. Because R is IN R F proportional to 1/g , the equivalent voltage gain is T × g , m Z m where gm is the transconductance of the input stage. Basic R G analysis of the follower with the gain circuit yields R IN V T (S) T Z O V Z OUT I IN = G× V T (S)+ (G× R )+ R R N IN Z IN F V IN where: G = 1 + RF/RG Figure 13. Simplified Block Diagram R = 1/g ≈ 50 Ω IN m Rev. C | Page 8 of 12 07022-013 AD8396 APPLICATIONS INFORMATION MULTITONE POWER RATIO (MTPR) SUPPLIES, GROUNDING, AND LAYOUT The DMT signal used in ADSL/ADSL2+ systems carries data in The AD8396 can be powered from either single or dual supplies, discrete tones or bins, which appear in the frequency domain in with the total supply voltage ranging from 12 V to 24 V. For evenly spaced 4.3125 kHz intervals. In applications using this type optimum performance, use well-regulated low ripple supplies. of waveform, MTPR is a commonly used measure of linearity. As with all high speed amplifiers, pay close attention to supply Generally, designers are concerned with two types of MTPR: decoupling, grounding, and overall board layout. Provide low in-band and out-of-band. In-band MTPR is defined as the frequency supply decoupling with 10 μF tantalum capacitors measured difference from the peak of one tone that is loaded from each supply to ground. In addition, decouple all supply with data to the peak of an adjacent tone that is intentionally pins with 0.1 μF quality ceramic chip capacitors placed as close left empty. Out-of-band MTPR is more loosely defined as the as possible to the driver. Use an internal low impedance ground spurious emissions that occur in the receive band located between plane to provide a common ground point for all driver and 25.875 kHz and the first downstream tone at 138 kHz. Figure 15 decoupling capacitor ground requirements. Whenever possible, and Figure 16 show the AD8396 in-band MTPR for a 5.5 crest use separate ground planes for analog and digital circuitry. factor waveform for empty bins in the ADSL and extended Follow high speed layout techniques to minimize parasitic ADSL2+ bandwidths. capacitance. 0 Keep input and output traces as short as possible and as far –10 apart from each other as practical to minimize crosstalk. Keep –20 all differential signal traces as symmetrical as possible. –30 POWER MANAGEMENT –40 –73dBc A digitally programmable logic pin switches each port of the –50 AD8396 between active bias and shutdown states. The PD_A –60 pin controls Port A and the PD_B pin controls Port B. These –70 pins can be controlled directly with either 3.3 V or 5 V CMOS –80 logic with the DGND pins as a reference. If left unconnected, –90 the PD pins float high, placing the amplifier in the shutdown state. See the Specifications section for the quiescent current for –100 642.131 644.503 646.875 649.247 651.619 each of the available bias states. FREQUENCY (kHz) TYPICAL ADSL/ADSL2+ APPLICATION Figure 15. In-Band MTPR at 646.875 kHz In a typical ADSL/ADSL2+ application, a differential line driver takes the signal from the analog front end (AFE) and drives it 0 onto the twisted pair telephone line. Referring to the typical –10 circuit representation in Figure 14, the differential input appears –20 at V and V from the AFE, while the differential output is IN+ IN− –30 transformer coupled to the telephone line at TIP and RING. The common-mode operating point, generally midway between –40 –68dBc the supplies, is set internally and is available at VCOM. –50 –60 V + R IN+ m –70 VCC TIP – –80 4kΩ R OUT –90 1:N VCOM –100 0.1µF 4kΩ 1.9618 1.9641 1.9665 1.9689 1.9712 – R m RING FREQUENCY (MHz) VEE + V IN– Figure 16. In-Band MTPR at 1.9665 MHz Figure 14. Typical ADSL/ADSL2+ Application Circuit Rev. C | Page 9 of 12 07022-014 MAGNITUDE (dBm) MAGNITUDE (dBm) 07022-015 07022-016 AD8396 LIGHTNING AND AC POWER FAULT When the AD8396 is an ADSL/ADSL2+ line driver, it is transformer coupled to the twisted pair telephone line. In this environment, the AD8396 is subject to large line transients, resulting from events, such as lightning strikes or downed power lines. Additional circuitry is required to protect the AD8396 from damage due to these events. Rev. C | Page 10 of 12 AD8396 OUTLINE DIMENSIONS 4.10 0.35 4.00 SQ 0.30 3.90 0.25 PIN 1 INDICATOR 13 16 0.65 12 1 BSC EXPOSED 2.60 PAD 2.50 SQ 2.40 9 4 8 5 0.50 TOP VIEW BOTTOM VIEW 0.40 0.30 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 17. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm, Very Very Thin Quad (CP-16-26) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD8396ACPZ-R2 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-26 1 AD8396ACPZ-RL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-26 1 AD8396ACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-26 1 Z = RoHS Compliant Part. Rev. C | Page 11 of 12 PIN 1 INDICATOR 042709-A AD8396 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07022-0-8/09(C) Rev. C | Page 12 of 12