ANALOG DEVICES AD8392A

Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2+ Line Driver AD8392A FEATURES PIN CONFIGURATIONS Four current feedback, high current amplifiers V 1 28 GND EE Ideal for use as ADSL/ADSL2+ dual-channel central office PD0 1, 2 2 27 NC (CO) line drivers PD1 1, 2 3 26 NC Low power operation +V 1 4 25 +V 2 IN IN 1 2 –V 1 5 24 –V 2 IN Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V) IN V 1 6 23 V 2 OUT OUT Less than 3 mA/amp quiescent supply current for full V 7 22 NC CC AD8392A power ADSL/ADSL2+ CO applications (20.4 dBm line NC 8 21 V CC power, 5.5 CF) V 3 9 20 V 4 OUT OUT Three active power modes plus shutdown –V 3 10 19 –V 4 IN IN 34 +V 3 11 18 High output voltage and current drive IN +V 4 IN 12 17 NC PD1 3, 4 500 mA peak output drive current NC 13 16 PD0 3, 4 42.6 V p-p differential output voltage 14 15 GND V EE Low distortion NC = NO CONNECT −93 dBc @1 MHz second harmonic Figure 1. AD8392AARE, 28-Lead TSSOP/EP −103 dBc @ 1 MHz third harmonic High speed: 515 V/μs differential slew rate Additional functionality of AD8392AACP On-chip, common-mode voltage generation APPLICATIONS 32 31 30 29 28 27 26 25 24 NC 1 NC ADSL/ADSL2+ CO line drivers 1 2 23 –V 2 –V 1 2 IN IN XDSL line drives V 2 V 1 3 22 OUT OUT V 4 21 NC CC AD8392A V GENERAL DESCRIPTION 5 20 NC CC V 4 6 19 V 3 OUT OUT The AD8392A is comprised of four high output current, low 7 18 –V 4 –V 3 IN IN 3 4 power consumption, operational amplifiers. It is particularly 17 NC 8 NC 910 11 12 13 14 15 16 well suited for the CO driver interface in digital subscriber line systems, such as ADSL and ADSL2+. The driver is capable of providing enough power to deliver 20.4 dBm to a line, while compensating for losses due to hybrid insertion and back NC = NO CONNECT termination resistors. Figure 2. AD8392AACP, 5 mm × 5 mm, 32-Lead LFCSP The AD8392A is available in two thermally enhanced packages, a 28-lead TSSOP/EP (AD8392AARE) and a 5 mm × 5 mm, 32-lead LFCSP (AD8392AACP). Four bias modes are available via the use of two digital bits (PD1, PD0). Additionally, the AD8392AACP provides VCOM pins for on-chip, common-mode voltage generation. The low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the AD8392A to be used as the CO line drivers in ADSL and other xDSL systems. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. +V 3 +V 1 IN IN NC PD1 1, 2 V 3, 4 PD0 1, 2 COM V GND EE V EE GND PD0 3, 4 V 1, 2 COM PD1 3, 4 NC +V 4 +V 2 IN IN 06477-001 06477-002 AD8392A TABLE OF CONTENTS Features .............................................................................................. 1 Applications........................................................................................8 Applications....................................................................................... 1 Supplies, Grounding, and Layout................................................8 General Description ......................................................................... 1 Power Management ......................................................................8 Pin Configurations ........................................................................... 1 Thermal Considerations...............................................................8 Specifications..................................................................................... 3 Typical ADSL/ADSL2+ Application...........................................9 Absolute Maximum Ratings............................................................ 4 Multitone Power Ratio............................................................... 10 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 11 ESD Caution.................................................................................. 4 Ordering Guide .......................................................................... 11 Typical Performance Characteristics ............................................. 5 Theory of Operation ........................................................................ 7 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 12 AD8392A SPECIFICATIONS VS = ±12 V or +24 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth 25 37 MHz V = 0.1 V p-p, R = 2 kΩ OUT F −3 dB Large Signal Bandwidth 23 30 MHz VOUT = 4 V p-p, RF = 2 kΩ Peaking 0.06 dB VOUT = 0.1 V p-p, RF = 2 kΩ Slew Rate 515 V/μs VOUT = 20 V p-p, RF = 2 kΩ NOISE/DISTORTION PERFORMANCE Second Harmonic Distortion −93 dBc fC = 1 MHz, VOUT = 2 V p-p Third Harmonic Distortion −103 dBc fC = 1 MHz, VOUT = 2 V p-p Multitone Input Power Ratio 70 dBc 26 kHz to 2.2 MHz, Z = 100 Ω differential load LINE Voltage Noise (RTI) 2.5 nV/√Hz f = 10 kHz +Input Current Noise 7.6 pA/√Hz f = 10 kHz −Input Current Noise 12.5 pA/√Hz f = 10 kHz INPUT CHARACTERISTICS RTI Offset Voltage −4 ±2 +4 mV V+IN − V−IN +Input Bias Current 2 7 μA −Input Bias Current 3 10 μA Input Resistance 8 MΩ Input Capacitance 1 pF Common-Mode Rejection Ratio 63 66 dB (ΔV )/(ΔV ) OS, DM (RTI) IN, CM OUTPUT CHARACTERISTICS Differential Output Voltage Swing 41.2 42.6 V p-p ΔV OUT Single-Ended Output Voltage Swing 20.6 21.3 V p-p ΔVOUT, RL = 50 Ω Linear Output Current 500 mA RL = 10 Ω, fC = 100 kHz POWER SUPPLY Operating Range (Dual Supply) ±5 ±12 V Operating Range (Single Supply) 10 24 V Total Quiescent Current PD1, PD0 = (0, 0) 5.8 6.5 mA/amp PD1, PD0 = (0, 1) 3.0 3.5 mA/amp PD1, PD0 = (1, 0) 2.6 3.0 mA/amp PD1, PD0 = (1, 1) (Shutdown State) 0.4 0.08 mA/amp PD = 0 Threshold 0.8 V PD = 1 Threshold 1.8 V +Power Supply Rejection Ratio 72 74 dB ΔV /ΔV , ΔV = ±1 V OS, DM (RTI) CC CC −Power Supply Rejection Ratio 65 69 dB ΔV /ΔV , ΔV = ±1 V OS, DM (RTI) EE EE Rev. 0 | Page 3 of 12 AD8392A ABSOLUTE MAXIMUM RATINGS RMS output voltages should be considered. If RL is referenced Table 2. to VS− as in single-supply operation, the total power is VS × IOUT. Parameter Rating Supply Voltage ±13 V (+26 V) In single supply with RL to VS−, worst case is VOUT = VS/2. Power Dissipation See Figure 3 Airflow increases heat dissipation, effectively reducing θJA. In Storage Temperature Range −65°C to +150°C addition, more metal directly in contact with the package leads Operating Temperature Range −40°C to +85°C from metal traces, through holes, ground, and power planes Lead Temperature (Soldering 10 sec) 300°C reduces the θ . JA Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings Figure 3 shows the maximum safe power dissipation in the may cause permanent damage to the device. This is a stress package vs. the ambient temperature for the LFCSP-32 and rating only; functional operation of the device at these or any TSSOP-28/EP packages on a JEDEC standard 4-layer board. other conditions above those indicated in the operational θJA values are approximations. section of this specification is not implied. Exposure to absolute 7 maximum rating conditions for extended periods may affect T = 150°C J device reliability. 6 THERMAL RESISTANCE 5 LFCSP-32 θ is specified for the worst-case conditions, that is, θ is specified JA JA 4 for the device soldered in the circuit board for surface-mount TSSOP-28/EP packages. 3 2 Table 3. Package Type θJA Unit 1 LFCSP-32 (CP) 27.27 °C/W TSSOP-28/EP (RE) 35.33 °C/W 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Maximum Power Dissipation Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board The power dissipated in the package (P ) is the sum of the D See the Thermal Considerations section for additional thermal quiescent power dissipation and the power dissipated in the design guidance. package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the ESD CAUTION quiescent current (IS). Assuming that the load (RL) is midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (V × I ). OUT OUT Rev. 0 | Page 4 of 12 MAXIMUM POWER DISSIPATION (W) 06477-003 AD8392A TYPICAL PERFORMANCE CHARACTERISTICS 900 0 850 –20 800 PD (0, 0) 750 –40 700 PD (0, 1) –60 650 600 PD (1, 0) –80 550 –100 500 450 –120 15 16 17 18 19 20 21 100k 1M 10M 100M 1G OUTPUT POWER (dBm) FREQUENCY (Hz) Figure 4. Power Consumption vs. Output Power (138 kHz to 2.2 MHz), Figure 7. Signal Feedthrough vs. Frequency ADSL/ADSL2+ Circuit (Figure 15), VS = ±12 V, RLOAD = 100 Ω, CF = 5.5 VS = ±12 V, G = +5, VIN = 800 mV p-p, PD (1, 1), RF = 2 kΩ 15 10 PD (0, 0) 5 PD (0, 1) 0 2 –5 PD (1, 0) –10 1 –15 –20 10k 100k 1M 10M 100M 1G CH1 500mV CH2 500mV 100ns FREQUENCY (Hz) Figure 8. Power-Up Time: PD (1, 1) to PD (0, 0) Figure 5. Small Signal Frequency Response V = ±12 V, R = 100 Ω, G = +5, V = 1 V p-p, R = 2 kΩ VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 100 mV p-p, RF = 2 kΩ S LOAD OUT F 15 10 PD (0, 0) 5 0 2 –5 PD (0, 1) –10 1 PD (1, 0) –15 –20 10k 100k 1M 10M 100M 1G CH1 500mV CH2 500mV 400ns FREQUENCY (Hz) Figure 9. Power-Down Time: PD (0, 0) to PD (1, 1) Figure 6. Large Signal Frequency Response V = ±12 V, R = 100 Ω, G = +5, V = 1 V p-p, R = 2 kΩ VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 4 V p-p, RF = 2 kΩ S LOAD OUT F Rev. 0 | Page 5 of 12 GAIN (dB) GAIN (dB) POWER CONSUMPTION (mW) 06477-045 06477-049 06477-046 SIGNAL FEEDTHROUGH (dB) 06477-041 06477-042 06477-048 AD8392A 100 INPUT CHANNEL 1 OUTPUT 10 CHANNEL 2 PD (0, 0) 1 2 PD (0, 1) PD (1, 0) 0.1 0.01 10k 100k 1M 10M 100M 1G CH1 200mV CH2 2V 400ns FREQUENCY (Hz) Figure 10. Output Overdrive Recovery, ADSL/ADSL2+ Circuit (Figure 15), Figure 13. Output Impedance vs. Frequency DMT Waveform, V = ±12 V V = ±12 V, G = +5, R = 2 kΩ S S F 0 –10 –20 –30 49.9Ω DIFF CHANNEL 1, 2 –40 –50 2kΩ DIFF CHANNEL 3, 4 –60 499Ω 100Ω 2kΩ –70 –80 –90 –100 49.9Ω 100k 1M 10M 100M FREQUENCY (Hz) Figure 14. Dual Differential Driver Circuit Figure 11. Crosstalk vs. Frequency, Dual Differential Driver Circuit (Figure 14), VS = ±12 V, VIN = 800 mV p-p 45 1.78kΩ 40 35 634Ω 0.01µF 4.99Ω 30 77Ω 87Ω 2kΩ 25 V 1µF 100Ω CM 2kΩ 20 77Ω 87Ω 4.99Ω 15 0.01µF 634Ω 10 0 10 20 30 40 50 60 70 80 90 100 1.78kΩ LOAD RESISTANCE (Ω) Figure 12. Differential Output Swing vs. RLOAD Figure 15. ADSL/ADSL2+ Circuit Dual Differential Driver Circuit (Figure 14) Rev. 0 | Page 6 of 12 CROSSTALK (dB) DIFFERENTIAL OUTPUT (V p-p) 06477-040 06477-054 06477-025 OUTPUT IMPEDANCE (Ω) 06477-053 06477-021 06477-047 AD8392A THEORY OF OPERATION The AD8392A is a current feedback amplifier with high Of course, for a real amplifier there are additional poles that (500 mA) output current capability. With a current feedback contribute excess phase, and there is a value for RF below which amplifier, the current into the inverting input is the feedback the amplifier is unstable. Tolerance for peaking and desired signal, and the open-loop behavior is that of a transimpedance, flatness determines the optimum RF in each application. dVO/dIIN or TZ. R F The open-loop transimpedance is analogous to the open-loop R G voltage gain of a voltage feedback amplifier. Figure 16 shows a R IN simplified model of a current feedback amplifier. Because R is IN T Z V I OUT IN proportional to 1/gm, the equivalent voltage gain is TZ × gm, R N where gm is the transconductance of the input stage. Basic V IN analysis of the follower with gain circuit yields V T() S O Z =G× Figure 16. Simplified Block Diagram V T() S +G×R +R IN Z IN F The AD8392A is capable of delivering 500 mA of output where: current while swinging to within 2 V of either power supply R rail. The AD8392A also has a power management system F G=1 + included on-chip. It features four user-programmable power R G levels (three active power modes as well as the provision for 1 R = ≈ 50 Ω complete shutdown). IN g m Because G × R << R for low gains, a current feedback IN F amplifier has relatively constant bandwidth vs. gain, the 3 dB point being set when |T | = R . Z F Rev. 0 | Page 7 of 12 06477-022 AD8392A APPLICATIONS SUPPLIES, GROUNDING, AND LAYOUT The information in Table 3 and Figure 3 is based on a standard JEDEC 4-layer board and a maximum die temperature of 150°C. The AD8392A can be powered from either single or dual To provide additional guidance and design suggestions, a supplies, with the total supply voltage ranging from 10 V to thermal study was performed under a set of conditions more 24 V. For optimum performance, a well regulated low ripple closely aligned with an actual ADSL/ADSL2+ application. supply should be used. In a typical ADSL/ADSL2+ line card, component density As with all high speed amplifiers, close attention should be paid usually dictates that most of the copper plane used for thermal to supply decoupling, grounding, and overall board layout. Low dissipation be internal. Additionally, each ADSL/ADSL2+ port frequency supply decoupling should be provided with 10 μF may be allotted only 1 square inch, or even less, of board space. tantalum capacitors from each supply to ground. In addition, all For these reasons, a special thermal test board was constructed supply pins should be decoupled with 0.1 μF quality ceramic for this study. The 4-layer board measured approximately chip capacitors placed as close as possible to the driver. An 4 inches × 4 inches and contained two internal 1 oz copper internal low impedance ground plane should be used to provide ground planes, each measuring 2 inches × 3 inches. The top a common ground point for all driver and decoupling capacitor layer contained signal traces and an exposed copper strip ground requirements. Whenever possible, separate ground ¼ inch × 3 inches to accommodate heat sinking, with no planes should be used for analog and digital circuitry. other copper on the top or bottom of the board. High speed layout techniques should be followed to minimize Three 28-lead TSSOPs were placed on the board representing parasitic capacitance around the inverting inputs. Some practical six ADSL channels, or one channel per square inch of copper, examples of these techniques are keeping feedback traces as with each channel dissipating 700 mW on-chip (1.4 W per short as possible and clearing away ground plane in the area of package). The die temperature is then measured in still air and the inverting inputs. Input and output traces should be kept in a wind tunnel with calibrated airflow of 100 LFM, 200 LFM, short and as far apart from each other as practical to avoid and 400 LFM. Figure 17 shows the power dissipation vs. the crosstalk. When used as a differential driver, all differential ambient temperature for each airflow condition. The figure signal traces should be kept as symmetrical as possible. assumes a maximum die temperature of 135°C. No heat sink POWER MANAGEMENT was used. The AD8392A can be configured in any of three active bias 4.5 T = 135°C J states as well as a shutdown state via the use of two sets of 4.0 digitally programmable logic pins. Pin PD0 (1, 2) and Pin PD1 400LFM (1, 2) control Amplifier 1 and Amplifier 2, while PD0 (3, 4) and 3.5 Pin PD1 (3, 4) control Amplifier 3 and Amplifier 4. These pins 200LFM can be controlled directly with either 3.3 V or 5 V CMOS logic 3.0 by using the GND pins as a reference. If left unconnected, the 2.5 PD pins float low, placing the amplifier in the full bias mode. STILL AIR Refer to the Specifications for the per amplifier quiescent 100LFM 2.0 current for each of the available bias states. 1.5 As is shown in Figure 13, the AD8392A exhibits low output impedance for the three active states. The shutdown state 1.0 5 1525 354555657585 (PD1, PD0 = 1, 1) provides a high impedance output. AMBIENT TEMPERATURE (°C) Figure 17. Power Dissipation vs. Ambient THERMAL CONSIDERATIONS Temperature and Air Flow 28-Lead TSSOP/EP When using a quad, high output current amplifier, such as the This data is only provided as guidance to assist in the thermal AD8392A, special consideration should be given to system level design process. Due diligence should be performed with regards thermal design. In applications such as the ADSL/ADSL2+, to power dissipation because there are many factors that can the AD8392A could be required to dissipate as much as 1.4 W affect thermal performance. or more on-chip. Under these conditions, particular attention should be paid to the thermal design to maintain safe operating temperatures on the die. To aid in the thermal design, the thermal information in the Thermal Resistance section can be combined with what follows here. Rev. 0 | Page 8 of 12 POWER DISSIPATION (W) 06477-051 AD8392A TYPICAL ADSL/ADSL2+ APPLICATION Additional definitions for calculating resistor values include: In a typical ADSL/ADSL2+ application, a differential line driver Value Definition is used to take the signal from the analog front end (AFE) and VOA Voltage at the amplifier outputs drive it onto the twisted pair telephone line. Referring to the k Matching resistance reduction factor typical circuit representation in Figure 18, the differential input AV Gain from V to transformer primary IN appears at V and V from the AFE, while the differential IN+ IN− Negative feedback factor β output is transformer coupled to the telephone line at tip and Positive feedback factor α ring. The common-mode operating point, generally midway Note: R1 must be calculated before β and α. between the supplies, is set through VCOM. R3 2R V (1+k) V m LINE LINE R4 V = k= A = V OA V V OA IN+ R NV N V L IN P TIP R m R1 R β= α = β(1−k) BIAS R2 R1+ 2R2 R R IN OUT V 1:N COM R1 With the above known quantities and definitions, the remaining R2 resistors can readily be calculated. R BIAS R 2V R2 m RING P V P R1= R4 V V OA V −V IN– OA P R (V −V ) R3 IN IN P R4= 2V Figure 18. Typical ADSL/ADSL2+ Application Circuit IN A R4(2R1R +R1R − αR1R − 2αR2R ) V m L L L In ADSL/ADSL2+ applications, it is common practice to R3= αR() R1+ 2R2 conserve power by using positive feedback to synthesize the L output resistance, thereby lowering the required ohmic value αR3R4 of the line matching resistors, R . The circuit in Figure 18 is m R = BIAS R4− α() R3+R4 somewhat unique in that the positive feedback introduced via R3 has the effect of synthesizing the input resistance as well. After building the circuit with the closest 1% resistor values, The following definitions and equations can be used to calculate the actual gain, input resistance, and output resistance can be the resistor values necessary to obtain the desired gain, input verified with the following equations. resistance, and output resistance for a given application. For N simplicity, the following calculations assume a lossless GAIN = () V toLINE IN R4 R4 R4 ⎛ ⎞ transformer. β() k+1 1+ + − ⎜ ⎟ R3 R R3 ⎝ BIAS⎠ The following values are used in the design equations and are 2 assumed already known or chosen by the designer. R = IN 2R +R 1 ⎛ ⎞ m L Value Definition ⎜ ⎟ −A β V ⎜ ⎟ R4 R4R L ⎝ ⎠ VIN Differential input voltage R Desired differential input resistance 2 IN 2R N m R = N Transformer turns ratio OUT ⎛ ⎞ V LINE Differential output voltage at tip and ring ⎜ ⎟ ⎛ R4R ⎞ R1+ 2R2 BIAS ⎜ ⎟ ⎜ ⎟ Rm Each is typically 5% to 15% of the transformer reflected 1− ⎜ ⎟ R4R R1() R4+R ⎜ ⎟ BIAS BIAS line impedance ⎝ ⎠ R3+ ⎜ ⎟ R4+R ⎝ BIAS⎠ R2 Recommended in the amplifier data sheet V Voltage at the + inputs to the amplifier, approximately P ½ V (must be less than V for positive input resistance) IN IN RL Transformer reflected line impedance Rev. 0 | Page 9 of 12 06477-024 AD8392A 0 MULTITONE POWER RATIO –10 The DMT signal used in ADSL/ADSL2+ systems carries data in –20 discrete tones or bins, which appear in the frequency domain in –30 evenly spaced 4.3125 kHz intervals. In applications using this type of waveform, multitone power ratio (MTPR) is a commonly –40 used measure of linearity. MTPR is defined as the measured –50 difference from the peak of one tone that is loaded with data to –60 the peak of an adjacent tone that is intentionally left empty. –70 Figure 19 and Figure 20 show the AD8392A MTPR for a 5.5 –80 crest factor waveform for empty bins in the ADSL and extended ADSL2+ bandwidths. –90 –100 CENTER 1.9664kHz SPAN 10kHz Figure 20. MTPR at 1.966 MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 646.9kHz SPAN 10kHz Figure 19. MTPR at 647 kHz Rev. 0 | Page 10 of 12 (dBm) 06477-043 (dBm) 06477-044 AD8392A OUTLINE DIMENSIONS 9.80 3.55 9.70 3.50 9.60 3.45 28 15 4.50 3.05 EXPOSED 6.40 PAD 4.40 3.00 BSC (Pins Up) 4.30 2.95 1 14 TOP VIEW BOTTOM VIEW 1.05 1.20 MAX 1.00 8° 0.80 0° 0.20 0.15 0.65 BSC 0.30 0.75 SEATING 0.09 0.05 0.19 PLANE 0.60 COPLANARITY 0.45 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AET Figure 21. 28-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP] (RE-28-1) Dimensions shown in millimeters 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP EXPOSED 3.25 4.75 VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP 0.05 MAX 1.00 0.02 NOM 0.85 0.30 COPLANARITY 0.80 0.20 REF 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD8392AAREZ −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1 1 AD8392AAREZ-RL −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1 1 AD8392AAREZ-R7 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP/EP) RE-28-1 1 AD8392AACPZ-R2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 1 AD8392AACPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 1 AD8392AACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 1 Z = Pb-free part. Rev. 0 | Page 11 of 12 050806-A AD8392A NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06477-0-10/06(0) Rev. 0 | Page 12 of 12