ANALOG DEVICES AD8376

Ultralow Distortion IF Dual VGA AD8376 FEATURES FUNCTIONAL BLOCK DIAGRAM A4 A3 A2 A1 A0 VCCA GNDA Dual independent digitally controlled VGAs Bandwidth of 700 MHz (−3 dB) CHANNEL A GAIN Gain range: −4 dB to +20 dB AD8376 DECODER Step size: 1 dB ± 0.2 dB OPA+ Differential input and output IPA+ OPA+ Noise figure: 8.7 dB @ maximum gain POST-AMP α Output IP3 of ~50 dBm at 200 MHz IPA– OPA– Output P1dB of 20 dBm at 200 MHz OPA– VCMA ENBA Dual parallel 5-bit control interface ENBB Provides constant SFDR vs. gain VCMB OPB+ Power-down control IPB+ OPB+ Single 5 V supply operation POST-AMP α 32-lead, 5 mm x 5 mm LFCSP IPB– OPB– OPB– APPLICATIONS CHANNEL B Differential ADC drivers GAIN DECODER Main and diversity IF sampling receivers Wideband multichannel receivers B4 B3 B2 B1 B0 VCCB GNDB Instrumentation Figure 1. GENERAL DESCRIPTION The AD8376 is a dual channel, digitally controlled, variable gain AD8376 consumes less than 5 mA and offers excellent input-to- wide bandwidth amplifier that provides precise gain control, output isolation, lower than −50 dB at 200 MHz. high IP3, and low noise figure. The excellent distortion perform- Fabricated on an Analog Devices, Inc., high speed SiGe process, ance and high signal bandwidth make the AD8376 an excellent the AD8376 is supplied in a compact, thermally enhanced, gain control device for a variety of receiver applications. 5 mm × 5mm 32-lead LFCSP package and operates over the Using an advanced high speed SiGe process and incorporating temperature range of −40°C to +85°C. proprietary distortion cancellation techniques, the AD8376 –40 65 achieves 50 dBm output IP3 at 200 MHz. –50 60 The AD8376 provides a broad 24 dB gain range with 1 dB resolution. The gain of each channel is adjusted through –60 55 dedicated 5-pin control interfaces and can be driven using OIP3 –70 50 standard TTL levels. The open-collector outputs provide a flexible interface, allowing the overall signal gain to be set by –80 45 the loading impedance. Thus, the signal voltage gain is directly HD2 proportional to the load. –90 40 Each channel of the AD8376 can be individually powered on by HD3 –100 35 applying the appropriate logic level to the ENBA and ENBB power enable pins. The quiescent current of the AD8376 is –110 30 40 60 80 100 120 140 160 180 200 typically 130 mA per channel. When powered down, the FREQUENCY (MHz) Figure 2. Harmonic Distortion and Output IP3 vs. Frequency Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. HARMONIC DISTORTION (dBc), OUTPUT @ 2V p-p OIP3 (dBm), OUTPUT @ 3dBm/TONE 06725-001 06725-052 AD8376 TABLE OF CONTENTS Features .............................................................................................. 1 Basic Structure............................................................................ 12 Applications....................................................................................... 1 Applications..................................................................................... 13 Functional Block Diagram .............................................................. 1 Basic Connections...................................................................... 13 General Description ......................................................................... 1 Single-Ended-to-Differential Conversion............................... 13 Revision History ............................................................................... 2 Broadband Operation................................................................ 15 Specifications..................................................................................... 3 ADC Interfacing......................................................................... 15 Absolute Maximum Ratings............................................................ 5 Layout Considerations............................................................... 18 ESD Caution.................................................................................. 5 Characterization Test Circuits.................................................. 18 Pin Configuration and Function Descriptions............................. 6 Evaluation Board........................................................................ 19 Typical Performance Characteristics ............................................. 7 Outline Dimensions....................................................................... 23 Circuit Description......................................................................... 12 Ordering Guide .......................................................................... 23 REVISION HISTORY 10/10—Rev. 0 to Rev. A Changes to Figure 3 and Table 4..................................................... 6 Changes to Figure 36...................................................................... 14 Added Exposed Pad Notation to Outline Dimensions ............. 23 8/07—Revision 0: Initial Version Rev. A | Page 2 of 24 AD8376 SPECIFICATIONS VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, both channels enabled, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V < 2 V p-p (5.2 dBm) 700 MHz OUT Slew Rate 5 V/ns INPUT STAGE Pin IPA+ and Pin IPA−, Pin IPB+ and Pin IPB− Maximum Input Swing For linear operation (A = −4 dB) 8.5 V p-p V Differential Input Resistance Differential 120 150 165 Ω Common-Mode Input Voltage 1.85 V CMRR Gain code = 00000 45.5 dB GAIN Amplifier Transconductance Gain code = 00000 0.060 0.067 0.074 S Maximum Voltage Gain Gain code = 00000 20 dB Minimum Voltage Gain Gain code ≥ 11000 −4 dB Gain Step Size From gain code = 00000 to 11000 0.93 0.98 1.02 dB Gain Flatness All gain codes, 20% fractional bandwidth for fC < 200 MHz 0.18 dB Gain Temperature Sensitivity Gain code = 00000 8 mdB/°C Gain Step Response For VIN = 100 mV p-p, gain code = 10100 to 00000 5 ns OUTPUT STAGE Pin OPA+ and Pin OPA−, Pin OPB+ and Pin OPB− Output Voltage Swing At P1dB, gain code = 00000 13.1 V p-p Output Impedance Differential 16||0.8 kΩ||pF Channel Isolation Measured at differential output for differential input 73 dB applied to alternate channel (referred to output) NOISE/HARMONIC PERFORMANCE 46 MHz Gain code = 00000 Noise Figure 8.7 dB Second Harmonic VOUT = 2 V p-p −92 dBc Third Harmonic VOUT = 2 V p-p −94 dBc Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm Output 1 dB Compression Point 21.3 dBm 70 MHz Gain code = 00000 Noise Figure 8.7 dB Second Harmonic VOUT = 2 V p-p −89 dBc Third Harmonic VOUT = 2 V p-p −95 dBc Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm Output 1 dB Compression Point 21.4 dBm 140 MHz Gain code = 00000 Noise Figure 8.7 dB Second Harmonic VOUT = 2 V p-p −87 dBc Third Harmonic VOUT = 2 V p-p −97 dBc Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm Output 1 dB Compression Point 21.6 dBm 200 MHz Gain code = 00000 Noise Figure 8.7 dB Second Harmonic VOUT = 2 V p-p −82 dBc Third Harmonic VOUT = 2 V p-p −91 dBc Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm Output 1 dB Compression Point 20.9 dBm Rev. A | Page 3 of 24 AD8376 Parameter Conditions Min Typ Max Unit POWER INTERFACE Supply Voltage 4.5 5.0 5.5 V VCC and Output Quiescent Current Thermal connection made to exposed paddle under device 245 250 255 mA with Both Channels Enabled vs. Temperature −40°C ≤ T ≤ +85°C 285 mA A Power-Down Current, Both Channels ENBA and ENBB Low 5.4 mA vs. Temperature −40°C ≤ TA ≤ +85°C 7 mA POWER-UP/GAIN CONTROL Pin A0 to Pin A4, Pin B0 to Pin B4, Pin ENBA, and Pin ENBB VIH Minimum voltage for a logic high 1.6 V VIL Maximum voltage for a logic low 0.8 V Logic Input Bias Current 900 nA Table 2. Gain Code vs. Voltage Gain Look-Up Table 5-Bit Binary Gain Code Voltage Gain (dB) 5-Bit Binary Gain Code Voltage Gain (dB) 00000 +20 01101 +7 00001 +19 01110 +6 00010 +18 01111 +5 00011 +17 10000 +4 00100 +16 10001 +3 00101 +15 10010 +2 00110 +14 10011 +1 00111 +13 10100 0 01000 +12 10101 −1 01001 +11 10110 −2 01010 +10 10111 −3 01011 +9 11000 −4 01100 +8 >11000 −4 Rev. A | Page 4 of 24 AD8376 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Supply Voltage, V 5.5 V POS other conditions above those indicated in the operational ENBA, ENBB, A0 to A4, B0 to B4 −0.6 V to (V + −0.6 V) POS section of this specification is not implied. Exposure to absolute Input Voltage, V , V −0.15 V to +4.15 V IN+ IN− maximum rating conditions for extended periods may affect DC Common Mode VCMA, VCMB ± 0.25 V device reliability. VCMA, VCMB ± 6 mA Internal Power Dissipation 1.6 W θ (Exposed Paddle Soldered Down) 34.6°C/W JA ESD CAUTION θ (At Exposed Paddle) 3.6°C/W JC Maximum Junction Temperature 140°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Rev. A | Page 5 of 24 AD8376 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A2 1 24 OPA+ PIN 1 A3 2 23 OPA– INDICATOR A4 3 22 ENBA VCMA 4 AD8376 21 GNDA VCMB 5 20 GNDB TOP VIEW B4 6 (Not to Scale) 19 ENBB B3 7 18 OPB– B2 8 17 OPB+ NOTES 1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GROUND. SOLDER TO A LOW IMPEDANCE GROUND PLANE. Figure 3. 32-Lead LFCSP Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 A2 MSB − 2 for the Gain Control Interface for Channel A. 2 A3 MSB − 1 for the Gain Control Interface for Channel A. 3 A4 MSB for the 5-Bit Gain Control Interface for Channel A. 4 VCMA Channel A Input Common-Mode Voltage. Typically bypassed to ground through capacitor. 5 VCMB Channel B Input Common-Mode Voltage. Typically bypassed to ground through capacitor. 6 B4 MSB for the 5-Bit Gain Control Interface for Channel B. 7 B3 MSB − 1 for the Gain Control Interface for Channel B. 8 B2 MSB − 2 for the Gain Control Interface for Channel B. 9 B1 LSB + 1 for the Gain Control Interface for Channel B. 10 B0 LSB for the Gain Control Interface for Channel B. 11 IPB+ Channel B Positive Input. 12 IPB− Channel B Negative Input. 13, 20 GNDB Device Common (DC Ground) for Channel B. 14 VCCB Positive Supply Pin for Channel B. Should be bypassed to ground using suitable bypass capacitor. 15, 17 OPB+ Positive Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal. 16, 18 OPB− Negative Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal. 19 ENBB Power Enable Pin for Channel B. Channel B is enabled with a logic high and disabled with a logic low. 21, 28 GNDA Device Common (DC Ground) for Channel A. 22 ENBA Power Enable Pin for Channel A. Channel A is enabled with a logic high and disabled with a logic low. 23, 25 OPA− Negative Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal. 24, 26 OPA+ Positive Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal. 27 VCCA Positive Supply Pins for Channel A. Should be bypassed to ground using suitable bypass capacitor. 29 IPA− Channel A Negative Input. 30 IPA+ Channel A Positive Input. 31 A0 LSB for the Gain Control Interface for Channel A. 32 A1 LSB + 1 for the Gain Control Interface for Channel A. Exposed Pad Internally connected to ground. Solder to a low impedance ground plane. Rev. A | Page 6 of 24 06725-002 B1 9 32 A1 B0 10 31 A0 IPB+ 11 30 IPA+ IPB– 12 29 IPA– GNDB 13 28 GNDA VCCB 14 27 VCCA OPB+ 15 26 OPA+ OPB– 16 25 OPA– AD8376 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted. 25 1.0 46MHz, +5V 0.8 70MHz, +5V 20 140MHz, +5V 0.6 15 0.4 0.2 10 0 5 –0.2 –0.4 0 –0.6 –5 –0.8 –10 –1.0 –4 0 5 10 15 20 –4 0 5 10 15 20 11000 10100 01111 01010 00101 00000 11000 10100 01111 01010 00101 00000 GAIN CODE GAIN CODE Figure 4. Gain vs. Gain Code at 46 MHz, 70 MHz, and 140 MHz Figure 7. Gain Step Error, Frequency 140 MHz 25 20dB 25 19dB 18dB 17dB INPUT MAX 20 16dB RATING 20 15dB BOUNDARY 14dB 15 13dB 12dB 200MHz 11dB 15 10dB 140MHz 10 9dB 70MHz 8dB 46MHz 7dB 5 6dB 10 5dB 4dB 0 3dB 2dB 1dB 5 0dB –5 –1dB –2dB –3dB –10 –4dB 0 10 100 1000 –4 1 6 11 16 21 FREQUENCY (MHz) GAIN (dB) Figure 5. Gain vs. Frequency Response Figure 8. P1dB vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz 10 25 9 25°C 8 85°C 7 –40°C 20 6 5 4 3 15 2 +25°C 1 +85°C 0 –40°C –1 –2 10 –3 –4 –5 –6 5 –7 –8 –9 –10 0 –4 0 5 10 15 20 46 100 150 200 250 300 350 400 450 500 11000 10100 01111 01010 00101 00000 FREQUENCY (MHz) GAIN CODE Figure 6. Gain Error over Temperature at 140 MHz Figure 9. P1dB vs. Frequency at Maximum Gain, Three Temperatures Rev. A | Page 7 of 24 GAIN (dB) GAIN ERROR (dB) GAIN (dB) 06725-003 06725-005 06725-004 GAIN ERROR (dB) OP1dB (dBm) OP1dB (dBm) 06725-007 06725-008 06725-006 AD8376 52 55 65 +25°C 20dB A = +20dB V 51 –40°C 20dB +85°C 20dB A = +10dB 50 60 50 V +25°C 0dB A = 20dB V –40°C 0dB 49 +85°C 0dB A = 0dB V 45 55 48 47 40 50 46 A = 0dB V 45 A = –4dB V 44 35 45 43 30 40 42 41 40 25 35 30 50 70 90 110 130 150 170 190 210 –3 –2 –1 0 1 2 3 4 5 FREQUENCY (MHz) P PER TONE (dBm) OUT Figure 13. Output Third-Order Intercept vs. Power, Figure 10. Output Third-Order Intercept at Four Gains, Frequency 140 MHz, Three Temperatures Output Level at 3 dBm/Tone –70 52 46MHz 51 70MHz –75 140MHz 50 200MHz –80 49 A = +20dB V 48 –85 47 A = 0dB A = +10dB V V –90 46 45 –95 44 –100 43 A = –4dB V 42 –105 41 40 –110 –4 1 6 11 16 –4 –3 –2 –1 0 1 2 3 4 5 6 GAIN (dB) P (dBm) OUT Figure 11. Output Third-Order Intercept vs. Power Figure 14. Two-Tone Output IMD vs. Gain at Four Gains, Frequency 140 MHz at 46 MHz, 70 MHz, 140 MHz, and 200 MHz, Output Level at 3 dBm/Tone 70 –70 65 –75 60 –80 55 –85 +25°C +85°C 50 –90 –40°C –40°C +85°C 45 –95 +25°C 40 –100 35 –105 30 –110 40 60 80 100 120 140 160 180 200 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Output Third-Order Intercept vs. Frequency, Figure 15. Two-Tone Output IMD vs. Frequency, Three Temperatures, Output Level at 3 dBm/Tone Three Temperatures, Output Level at 3 dBm/Tone Rev. A | Page 8 of 24 OIP3 (dBm) OIP3 (dBm) OIP3 (dBm) 06725-011 06725-010 06725-009 OIP3 (dBm) IMD3 (dBc) IMD3 (dBc) 06725-013 OIP3 (dBm) 06725-014 06725-012 AD8376 –75 –65 –80 –70 HD2 –40°C HD2 –4dB –80 HD2 0dB –70 –85 –75 HD2 +85°C HD2 +10dB HD2 +20dB –85 –75 –90 –80 HD2 +25°C –90 –80 –95 –85 –95 –85 –100 –90 HD3 –4dB HD3 0dB HD3 –40°C –100 –90 –105 –95 HD3 +10dB HD3 +20dB HD3 +85°C –105 –95 –110 –100 HD3 +25°C –110 –100 –115 –105 –115 –105 –120 –110 40 60 80 100 120 140 160 180 200 –5 –4 –3 –2 –1 0 1 2 3 4 5 FREQUENCY (MHz) P (dBm) OUT Figure 16. Harmonic Distortion vs. Frequency at Four Gain Codes, Figure 19. Harmonic Distortion vs. Power, Frequency 140 MHz, V = 2 V p-p Three Temperatures OUT 40 –80 –60 HD2_+20dB HD2_+10dB –65 –85 35 HD2_0dB HD2_–M4dB –90 –70 30 –95 –75 25 –100 –80 –105 –85 20 HD3_+20dB HD3_+10dB –110 –90 HD3_0dB 15 46MHz HD3_–4dB –95 70MHz –115 140MHz 10 200MHz –120 –100 5 –105 –125 –130 –110 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 –4 –2 0 2 4 6 8 10 12 14 16 18 20 GAIN (dB) P (dBm) OUT Figure 17. Harmonic Distortion vs. Power at Four Gain Codes, Figure 20. NF vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz Frequency 140 MHz –70 45 HD2 +25°C HD3 +25°C 40 –75 HD2 –40°C A = –4dB HD3 –40°C V 35 HD2 +85°C –80 HD3 +85°C 30 –85 A = 0dB V 25 –90 20 A = +10dB V –95 15 –100 10 A = +20dB V –105 5 –110 0 40 60 80 100 120 140 160 180 200 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. Harmonic Distortion vs. Frequency, Three Temperatures, Figure 21. NF vs. Frequency VOUT = 2 V p-p Rev. A | Page 9 of 24 HARMONIC DISTORTION HD2 (dBc) HARMONIC DISTORTION HD2 (dBc) HARMONIC DISTORTION HD2 AND HD3 (dBc) 06725-017 HARMONIC DISTORTION HD3 (dBc) HARMONIC DISTORTION HD3 (dBc) 06725-016 06725-015 HARMONIC DISTORTION HD2 (dBc) NOISE FIGURE (dB) NOISE FIGURE (dB) 06725-019 06725-020 HARMONIC DISTORTION HD3 (dBc) 06725-018 AD8376 REF3 POSITION –600mV/DIV REF3 SCALE 500mV 0pF 10pF EACH SIDE INPUT 2 R1 R3 1 CH1 500mV Ω CH2 500mV Ω M10.0ns 10.0GS/s IT 10.0ps/pt M2.5ns 20.0GS/s IT 10.0ps/pt A CH1 960mV REF3 500mV 2.5ns A CH4 28.0mV Figure 22. Gain Step Time Domain Response Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB REF1 POSITION –1.08/DIV REF1 SCALE OUTPUT 50mV RISE (C2) 1.339ns FALL(C2) 1.367ns INPUT 2 2 REF1 1 CH2 500mV M2.5ns 20Gsps A CH2 –590mV CH1 500mV Ω CH2 500mV Ω M20.0ns 10.0GS/s IT 20.0ps/pt REF1 50.0mV IT 2.5ps/pt A CH1 960mV Figure 23. ENBL Time Domain Response Figure 26. Large Signal Pulse Response 0 180 REF1 POSITION –420mV/DIV REF1 SCALE –5 120 2V 0pF 10pF EACH SIDE –10 60 INPUT –15 0 R1 R3 R4 –60 –20 –120 –25 –180 –30 M2.5ns 20.0GS/s IT 10.0ps/pt 10 100 1000 REF 1 2.0V 2.5ns A CH4 28.0mV FREQUENCY (MHz) Figure 27. S11 vs. Frequency Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB Rev. A | Page 10 of 24 06725-023 06725-022 06725-021 S11 MAG (dB) 06725-024 06725-025 S11 PHASE (Degrees) 06725-026 AD8376 0 –10 –20 –20 –30 –40 A = –4dB V –40 A = 0dB V –50 –60 –60 –80 –70 A = +10dB V –100 A = +20dB V –80 –120 –90 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 28. Reverse Isolation vs. Frequency Figure 31. Channel Isolation (Output to Output) vs. Frequency 0 60 –10 50 –20 –30 40 –40 –50 30 –60 20 –70 –80 10 –90 –100 0 10 100 1000 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. Off-State Isolation vs. Frequency Figure 32. Common-Mode Rejection Ratio vs. Frequency 1.00E–09 9.00E–10 0dB, 5V, 25°C 8.00E–10 +10dB, 5V, 25°C +20dB, 5V, 25°C 7.00E–10 –4dB, 5V, 25°C 6.00E–10 5.00E–10 4.00E–10 3.00E–10 2.00E–10 1.00E–10 0.00E+00 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) Figure 30. Group Delay vs. Frequency at Gain Rev. A | Page 11 of 24 DELAY (Seconds) S12 (dB) ISOLATION (dB) 06725-028 06725-027 06725-029 ISOLATION (dB) CMRR (dB) 06725-031 06725-032 AD8376 CIRCUIT DESCRIPTION The dependency of the gain on the load is due to the open- BASIC STRUCTURE collector architecture of the output stage. The AD8376 is a dual differential variable gain amplifier with each amplifier consisting of a 150 Ω digitally controlled passive The dc current to the outputs of each amplifier is supplied attenuator followed by a highly linear transconductance through two external chokes. The inductance of the chokes and amplifier. the resistance of the load determine the low frequency pole of the amplifier. The parasitic capacitance of the chokes adds to 1/2 AD8376 ATTENUATOR MUX BUFFERS the output capacitance of the part. This total capacitance in IP+ parallel with the load resistance sets the high frequency pole of OP+ the device. Generally, the larger the inductance of the choke, the gm CORE VCM AMP higher its parasitic capacitance. Therefore, the value and type of OP– the choke should be chosen keeping this trade-off in mind. IP– For operation frequency of 15 MHz to 700 MHz driving a 150 Ω load, 1 μH chokes with SRF of 160 MHz or higher are A0 TO A4 DIGITAL recommended (such as 0805LS-102XJBB from Coilcraft). SELECT The supply current of each amplifier consists of about 50 mA Figure 33. Simplified Schematic through the VCC pin and 80 mA through the two chokes Input System combined. The latter increases with temperature at about The dc voltage level at the inputs of the AD8376 is set by an 2.5 mA per 10°C. internal voltage reference circuit to about 2 V. This reference is Each amplifier has two output pins for each polarity, and they accessible at VCMA and VCMB and can be used to source or are oriented in an alternating fashion. When designing the sink 100 μA. For cases where a common-mode signal is applied board, care should be taken to minimize the parasitic capaci- to the inputs, such as in a single-ended application, an external tance due to the routing that connects the corresponding capacitor between VCMA/VCMB and ground is required. The outputs together. A good practice is to avoid any ground or capacitor improves the linearity performance of the part in this power plane under this routing region and under the chokes to mode. This capacitor should be sized to provide a reactance of minimize the parasitic capacitance. 10 Ω or less at the lowest frequency of operation. If the applied Gain Control common-mode signal is dc, its amplitude should be limited to 0.25 V from VCMA/VCMB (VCMA or VCMB ± 0.25 V). Each Two independent 5-bit binary codes change each attenuator device can be powered down by pulling the ENBA or ENBB pin setting in 1 dB steps such that the gain of each amplifier down to below 0.8 V. In the powered down mode, the total changes from +20 dB (Code 0) to −4 dB (Code 24 and higher). current reduces to 3 mA (typical). The dc level at the inputs and The noise figure of each amplifier is about 8 dB at maximum at VCMA/VCMB remains at about 2 V, regardless of the state of gain setting, and it increases as the gain is reduced. The increase the ENBA of ENBB pin. in noise figure is equal to the reduction in gain. The linearity of Output Amplifier the part measured at the output is first-order independent of the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately The gain is based on a 150 Ω differential load and varies as R is L 50 dBm into 150 Ω load at 140 MHz (3 dBm per tone). At gain changed per the following equations: settings below 0 dB, it drops to approximately 45 dBm. Voltage Gain = 20 × (log(R /150) + 1) L and Power Gain = 10 × (log(RL/150) + 2) Rev. A | Page 12 of 24 06725-033 AD8376 APPLICATIONS +5V BASIC CONNECTIONS VCM 0.1µF Figure 36 shows the basic connections for operating the AD8376. A voltage between 4.5 V and 5.5 V should be applied 1µH 1µH 150Ω 0.1µF 0.1µF to the supply pins. Each supply pin should be decoupled with at 1/2 least one low inductance, surface-mount ceramic capacitor of 50Ω 150Ω AD8376 0.1µF 0.1µF 0.1 μF placed as close as possible to the device. AC The outputs of the AD8376 are open collectors that need to be 37.5Ω 5 pulled up to the positive supply with 1 μH RF chokes. The differ- ential outputs are biased to the positive supply and require ac- A0 TO A4 coupling capacitors, preferably 0.1 μF. Similarly, the input pins Figure 34. Single-Ended-to-Differential Conversion Featuring ½ of the AD8376 are at bias voltages of about 2 V above ground and should be ac- coupled as well. The ac-coupling capacitors and the RF chokes are the principle limitations for operation at low frequencies. –60 To enable each channel of the AD8376, the ENBA or ENBB pin –65 must be pulled high. Taking ENBA or ENBB low puts the HD2 –70 channels of the AD8376 in sleep mode, reducing current consumption to approximately 5 mA per channel at ambient. –75 SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION –80 The AD8376 can be configured as a single-ended input to –85 differential output driver, as shown in Figure 34. A 150 Ω resistor in parallel with the input impedance of input pin –90 HD3 provides an impedance matching of 50 Ω. The voltage gain and –95 the bandwidth of this configuration, using a 150 Ω load, remains the same as when using a differential input. –100 02 50 100 15000 FREQUENCY (MHz) Using a single-ended input decreases the power gain by 3 dB Figure 35. Harmonic Distortion vs. Frequency of and limits distortion cancellation. Consequently, the second- Single-Ended-to-Differential Conversion order distortion is degraded. The third-order distortion remains low to 200 MHz, as shown in Figure 35. Rev. A | Page 13 of 24 HARMONIC DISTORTION (dBc) 06725-035 06725-036 AD8376 BALANCED SOURCE R R S S AC 2 2 +V S CHANNEL A PARALLEL 0.1µF 0.1µF 0.1µF 10µF CONTROL INTERFACE 1µH 1µH 32 31 30 29 28 27 26 25 A1 A0 IPA+ IPA– GNDA VCCA OPA+ OPA– 0.1µF 1 A2 OPA+ 24 BALANCED R L LOAD 2 A3 OPA– 23 0.1µF 3 A4 ENBA 22 0.1µF 4 VCMA GNDA 21 AD8376 5 VCMB GNDB 20 0.1µF 6 B4 +V ENBB 19 S 7 B3 OPB– 18 0.1µF 8 B2 OPB+ 17 BALANCED R L LOAD B1 B0 IPB+ IPB– GNDB VCCB OPB+ OPB– 910 11 12 13 14 15 16 0.1µF 1µH CHANNEL B PARALLEL 1µH 0.1µF 0.1µF CONTROL INTERFACE +V S 0.1µF 10µF R R S S AC 2 2 BALANCED SOURCE Figure 36. Basic Connections Rev. A | Page 14 of 24 06725-034 AD8376 For example, in the extreme case where the load is assumed to BROADBAND OPERATION be high impedance, R = ∞, the equation for R1 reduces to R1 = L The AD8376 uses an open-collector output structure that 75 Ω. Using the equation for VR, the applied voltage should be requires dc bias through an external bias network. Typically, VR = 8 V. The measured single-tone low frequency harmonic choke inductors are used to provide bias to the open-collector distortion for a 2 V p-p output using 75 Ω resistive pull-ups is outputs. Choke inductors work well at signal frequencies where provided in Figure 38. the impedance of the choke is substantially larger than the –80 target ac load impedance. In broadband applications, it may not be possible to find large enough choke inductors that offer –82 enough reactance at the lowest frequency of interest while HD2 –84 offering a high enough self resonant frequency (SRF) to support the maximum bandwidth available from the device. The circuit –86 in Figure 37 can be used when frequency response below –88 10 MHz is desired. This circuit replaces the bias chokes with bias resistors. The bias resistor has the disadvantage of a greater HD3 –90 IR drop, and requires a supply rail that is several volts above the –92 local 5 V supply used to power the device. Additionally, it is necessary to account for the ac loading effect of the bias –94 resistors when designing the output interface. Whereas the gain –96 of the AD8376 is load dependent, RL in parallel with R1 + R2 0 5 10 15 20 FREQUENCY (MHz) should equal the optimum 150 Ω target load impedance to Figure 38. Harmonic Distortion vs. Frequency Using Resistive Pull-Ups provide the expected ac performance depicted in the data sheet. Additionally, to ensure good output balance and even-order ADC INTERFACING distortion performance, it is essential that R1 = R2. The AD8376 is a high output linearity variable gain amplifier SET TO that is optimized for ADC interfacing. The output IP3 and noise 5V VR 5V floor essentially remain constant vs. the 24 dB available gain 37.5Ω R1 0.1µF 0.1µF range. This is a valuable feature in a variable gain receiver where ETC1-1-13 it is desirable to maintain a constant instantaneous dynamic 1/2 50Ω RL AD8376 0.1µF 0.1µF range as the receiver gain is modified. The output noise density is typically around 20 nV/√Hz, which is comparable to 14-/16- 37.5Ω R2 bit sensitivity limits. The two-tone IP3 performance of the 5 AD8376 is typically around 50 dBm. This results in SFDR levels VR A0 TO A4 of better than 86 dB when driving the AD9445 up to 140 MHz. Figure 37. Single-Ended Broadband Operation with Resistive Pull-Ups There are several options available to the designer when using Using the formula for R1 (Equation 1), the values of R1 = R2 the AD8376. The open-collector output provides the capability that provide a total presented load impedance of 150 Ω can be of driving a variety of loads. Figure 39 shows a simplified wide- found. The required voltage applied to the bias resistors, VR, band interface with the AD8376 driving a AD9445. The AD9445 can be found by using the VR formula (Equation 2). is a 14-bit 125 MSPS analog-to-digital converter with a buffered 75× R wideband input, which presents a 2 kΩ||3 pF differential load L R1= (1) impedance and requires a 2 V p-p differential input swing to R − 150 L reach full scale. and −3 VR= R1× 40× 10 + 5 (2) B0 TO B4 5V 5 L 1µH (SERIES) 0.1µF 0.1µF 0.1µF ETC1-1-13 33Ω VIN+ 5V 14 50Ω 1/2 37.5Ω 82Ω AD9445 L 1µH AD8376 14-BIT ADC 0.1µF 0.1µF (SERIES) 0.1µF 33Ω VIN– 37.5Ω 82Ω 5 A0 TO A4 Figure 39. Wideband ADC Interfacing Example Featuring ½ of the AD8376 and the AD9445 Rev. A | Page 15 of 24 06725-037 HARMONIC DISTORTION (dBc) 06725-039 06725-038 AD8376 For optimum performance, the AD8376 should be driven The addition of the series inductors L (series) in Figure 39 differentially using an input balun or impedance transformer. extends the bandwidth of the system and provides response Figure 39 uses a wideband 1:1 transmission line balun followed flatness. Using 100 nH inductors as L (series), the wideband system response of Figure 41 is obtained. The wideband by two 37.5 Ω resistors in parallel with the 150 Ω input imped- ance of the AD8376 to provide a 50 Ω differential terminated frequency response is an advantage in broadband applications input impedance. This provides a wideband match to a 50 Ω such as predistortion receiver designs and instrumentation source. The open-collector outputs of the AD8376 are biased applications. However, by designing for a wide analog input through the two 1 μH inductors and are ac-coupled to the two frequency range, the cascaded SNR performance is somewhat 82 Ω load resistors. The 82 Ω load resistors in parallel with the degraded due to high frequency noise aliasing into the wanted series-terminated ADC impedance yields the target 150 Ω Nyquist zone. differential load impedance, which is recommended to provide 0 the specified gain accuracy of the device. The load resistors are –1 ac-coupled from the AD9445 to avoid common-mode dc –2 loading. The 33 Ω series resistors help to improve the isolation –3 between the AD8376 and any switching currents present at the –4 analog-to-digital sample and hold input circuitry. 1 –5 0 SNR = 64.93dBc –10 –6 SFDR = 86.37dBc FIRST POINT = –2.93dBFs –20 NOISE FLOOR = –108.1dB END POINT = –9.66dBFs –7 FUND = –1.053dBFs MID POINT = –2.33dBFs –30 SECOND = –86.18dBc MIN = –9.66dBFs –40 –8 THIRD = –86.22dBc MAX = –1.91dBFs –50 –9 –60 –70 –10 20 48 76 104 132 160 188 216 244 272 300 –80 2 3 FREQUENCY (MHz) –90 + 4 5 6 Figure 41. Measured Frequency Response of Wideband –100 ADC Interface Depicted in Figure 39 –110 –120 An alternative narrow-band approach is presented in Figure 42. –130 By designing a narrow band-pass antialiasing filter between the –140 AD8376 and the target ADC, the output noise of the AD8376 –150 0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 outside of the intended Nyquist zone can be attenuated, helping FREQUENCY (MHz) to preserve the available SNR of the ADC. In general, the SNR Figure 40. Measured Single-Tone Performance of the Circuit in Figure 39 for a 100 MHz Input Signal improves several dB when including a reasonable order antialias- ing filter. In this example, a low loss 1:3 input transformer is used The circuit depicted in Figure 39 provides variable gain, to match the AD8376’s 150 Ω balanced input to a 50 Ω unbal- isolation, and source matching for the AD9445. Using this anced source, resulting in minimum insertion loss at the input. circuit with the AD8376 in a gain of 20 dB (maximum gain), an SFDR performance of 86 dBc is achieved at 100 MHz, as indicated in Figure 40. Rev. A | Page 16 of 24 (dBFS) 06725-040 (dBFS) 06725-041 AD8376 Figure 42 is optimized for driving some of Analog Devices at dc, which introduces a zero into the transfer function. In popular unbuffered ADCs, such as the AD9246, AD9640, addition, the ac coupling capacitors and the bias chokes introduce and AD6655. Table 5 includes antialiasing filter component additional zeros into the transfer function. The final overall frequency response takes on a band-pass characteristic, helping recommendations for popular IF sampling center frequencies. Inductor L5 works in parallel with the on-chip ADC input to reject noise outside of the intended Nyquist zone. Table 5 capacitance and a portion of the capacitance presented by C4 to provides initial suggestions for prototyping purposes. Some form a resonant tank circuit. The resonant tank helps to ensure empirical optimization may be needed to help compensate for the ADC input looks like a real resistance at the target center actual PCB parasitics. frequency. Additionally, the L5 inductor shorts the ADC inputs 1µH 1nF 1nF L1 L3 1:3 AD9246 1/2 50Ω 165Ω C4 L5 301Ω C2 CML AD9640 AD8376 1nF 165Ω AD6655 L1 L3 1nF 5 1µH A0 TO A4 Figure 42. Narrow-Band IF Sampling Solution for Unbuffered ADC Applications Table 5. Interface Filter Recommendations for Various IF Sampling Frequencies Center Frequency 1 dB Bandwidth L1 C2 L3 C4 L5 96 MHz 27 MHz 390 nH 5.6 pF 390 nH 25 pF 100 nH 140 MHz 30 MHz 330 nH 3.3 pF 330 nH 20 pF 56 nH 170 MHz 32 MHz 270 nH 2.7 pF 270 nH 20 pF 39 nH 211 MHz 32 MHz 220 nH 2.2 pF 220 nH 18 pF 27 nH Rev. A | Page 17 of 24 06725-042 AD8376 +9V LAYOUT CONSIDERATIONS Each amplifier has two output pins for each polarity, and they 96Ω 96Ω are oriented in an alternating fashion. When designing the 25Ω 0.1µF 0.1µF TC3-1T 330Ω board, care should be taken to minimize the parasitic capaci- 1/2 T1 50Ω tance due to the routing that connects the corresponding AD8376 50Ω outputs together. A good practice is to avoid any ground or 330Ω AC 0.1µF 0.1µF 25Ω 5 power plane under this routing region and under the chokes to minimize the parasitic capacitance. A0 TO A4 Figure 44. Test Circuit for Time Domain Measurements CHARACTERIZATION TEST CIRCUITS Differential-to-Differential Characterization The S-parameter characterization for the AD8376 was performed using a dedicated differential input to differential output characterization board. Figure 45 shows the layout of the characterization board. The board was designed for optimum impedance matching into a 75 Ω system. Because both the input and output impedances of the AD8376 are 150 Ω differ- entially, 75 Ω impedance runs were used to match 75 Ω network analyzer port impedances. On-board 1 μH inductors were used for output biasing, and the output board traces were designed for minimum capacitance. +5V L1 L2 1µH 1µH 0.1µF 0.1µF 75Ω 75Ω 1/2 AC 75Ω TRACES 75Ω TRACES AC AD8376 75Ω 75Ω 0.1µF 0.1µF 5 A0 TO A4 Figure 43. Test Circuit for S-Parameters on Dedicated 75 Ω Differential-to-Differential Board Figure 45. Differential-to-Differential Characterization Board Circuit Side Layout +5V L1 L2 1µH 1µH C1 C3 R4 R1 0.1µF 0.1µF 25Ω TC3-1T 62Ω ETC1-1-13 1/2 T1 PAD LOSS = 11dB T2 50Ω 50Ω AD8376 R2 R3 AC C2 C4 62Ω 25Ω 0.1µF 0.1µF 5 A0 TO A4 Figure 46. Test Circuit for Distortion, Gain, and Noise Rev. A | Page 18 of 24 06725-050 06725-043 06275-044 06725-051 AD8376 The output pins of the AD8376 require supply biasing with EVALUATION BOARD 1 μH RF chokes. Both the input and output pins must be ac- Figure 47 shows the schematic of the AD8376 evaluation board. coupled. These pins are converted to single-ended with a pair of The silkscreen and layout of the component and circuit sides baluns (Mini-Circuits® TC3-1T+ and M/A-COM ETC1-1-13). are shown in Figure 48 through Figure 51. The board is powered The baluns at the input, T1 and T2, are used to transform 50 Ω by a single supply in the 4. 5 V to 5.5 V range. The power supply source impedances to the desired 150 Ω reference levels. The is decoupled by 10 μF and 0.1 μF capacitors at each power supply output baluns, T3 and T4, and the matching components are pin. Additional decoupling, in the form of a series resistor or configured to provide 150 Ω to 50 Ω impedance transformations inductor at the supply pins, can also be added. Table 6 details with insertion losses of about 11 dB. the various configuration options of the evaluation board. Rev. A | Page 19 of 24 AD8376 Figure 47. AD8376 Evaluation Board Schematic Rev. A | Page 20 of 24 R1 R2 0Ω INPA INNA C60 R91 T1 0.1µF VXA 0Ω VXB TC3-1T+ R72 R71 R70 VXA VPOS R10 R9 0Ω 0Ω R90 VPOS C2 C1 0Ω 1 1 1 1 1 VPOS 0.1µF 0.1µF C20 C21 C22 WA4 WA3 WA2 WA1 WA0 10µF 0.1µF 0.1µF C66 0 0 0 0 0 C67 0.1µF R16 0.1µF C13 R15 0Ω 0.1µF 0Ω L2 L1 32 31 30 29 28 27 26 25 1µH 1µH R25 A1 A0 IPA+ IPA– GNDA VCCA OPA+ OPA– C8 R20 30.9Ω 0.1µF 61.9Ω ETC1-1-13 OPA+ 24 1 A2 OUTPA T3 R30 R24 2 A3 OPA– 23 R62 R19 R23 C7 OUTNA VPOS R13 61.9Ω 0.1µF 30.9Ω C62 R29 0Ω 3 A4 ENBA 22 0.1µF 0Ω C11 C5 0.1µF PUA 4 VCMA GNDA 21 AD8376 VPOS 5 VCMB GNDB 20 PUB C12 R14 0.1µF 0Ω 6 B4 ENBB 19 C6 7 B3 OPB– 18 R26 C9 R21 30.9Ω 0.1µF 61.9Ω ETC1-1-13 8 B2 OPB+ 17 OUTPB T4 R31 R27 B1 B0 IPB+ IPB– GNDB VCCB OPB+ OPB– R63 R22 910 11 12 13 14 15 16 R28 C10 OUTNB VPOS 61.9Ω 30.9Ω 0.1µF R32 C63 0Ω 0.1µF L4 L3 1µH 1µH C14 R18 R17 0.1µF 0Ω 0 0 0 0 0 0Ω C3 WB4 WB3 WB2 WB1 WB0 C4 0.1µF 0.1µF C64 C65 VPOS 1 1 1 1 1 0.1µF 0.1µF R12 VPOS R11 0Ω 0Ω VXB R73 R74 R75 T2 C61 TC3-1T+ 0.1µF INPB INNB R4 R3 0Ω 06725-045 AD8376 Table 6. Evaluation Board Configuration Options Components Function Default Conditions C13, C14, C20 to C22, Power Supply Decoupling. Nominal supply decoupling consists a C20 = 10 μF (size 3528) C64 to C67, R90, R91 10 μF capacitor to ground followed by 0.1 μF capacitors to ground C13, C14 = 0.1 μF (size 0402) positioned as close to the device as possible. C21, C22, C64 to C67 = 0.1 μF (size 0603) R90, R91 = 0 Ω (size 0603) T1, T2, C1 to C4, C61, C62, Input Interface. T1 and T2 are 3:1 impedance ratio baluns to T1, T2 = TC3-1+ (Mini-Circuits) R1 to R4, R9 to R12, transform a 50 Ω single-ended input into a 150 Ω balanced C1 to C4, C60, C61 = 0.1 μF (size 0402) R70 to R75 differential signal. R1 and R4 ground one side of the differential drive R1, R4, R9 to R12 = 0 Ω (size 0402) interface for single-ended applications. R9 to R12 and R70 to R75 are R2, R3, R70 to R75 = open (size 0402) provided for generic placement of matching components. C1 to C4 are dc blocks. T3, T4, C7 to C10, Output Interface. C7 to C10 are dc blocks. L1 to L4 provide dc biases C7 to C10 = 0.1 μF (size 0402) L1 to L4, R15 to R32, for the outputs. R19 to R28 are provided for generic placement of L1 to L4 = 1 μH (size 0805) R62, R63, C62, C63 matching components. The evaluation board is configured to T3, T4 = ETC1-1-13 (M/A-COM) provide a 150 Ω to 50 Ω impedance transformation with an insertion R19 to R22 = 61.9 Ω (size 0402) loss of about 11 dB. T3 and T4 are 1:1 impedance ratio baluns to R23, R25, R26, R28 = 30.9 Ω (size 0402) transform the balanced differential signals to single-ended signals. R15 to R18 = 0 Ω (size 0603) R29 and R32 ground one side of the differential output interface for R29, R32 = 0 Ω (size 0402) single-ended applications. R24, R27, R30, R31, R62, R63 = open (size 0402) C62, C63 = 0.1 μF (size 0402) PUA, PUB, R13, R14, Enable Interface. The AD8376 is enabled by applying a logic high PUA, PUB = installed C5, C6 voltage to the ENBA pin for Channel A or the ENBB pin for Channel B. R13, R14 = 0 Ω (size 0603) Channel A is enabled when the PUA switch is set in the up position, C5, C6 = open (size 0603) connecting the ENBA pin to VPOS. Likewise, Channel B is enabled when the PUB switch is set in the up position, connecting the ENBB pin to VPOS. Both channels are disabled by setting the switches to the down position, connecting the ENBA and ENBB pins to GND. WA0 to WA4, WB0 to WB4 Parallel Interface Control. Used to hardwire A0 through A4 and B0 WA0 to WA4, WB0 to WB4 = installed through B4 to the desired gain. The bank of switches WA0 to WA4 set the binary gain code for Channel A. The bank of switches WB0 to WB4 set the binary gain code for Channel B. WA0 and WB0 represent the LSB for each of the respective channels. C11, C12 Voltage Reference. Input common-mode voltage ac-coupled to C11, C12 = 0.1 μF (size 0402) ground by 0.1 μF capacitors, C11 and C12. Rev. A | Page 21 of 24 AD8376 \ Figure 48. Component Side Silkscreen Figure 50. Component Side Layout Figure 49. Circuit Side Silkscreen Figure 51. Circuit Side Layout Rev. A | Page 22 of 24 06725-047 06725-046 06725-049 06725-048 AD8376 OUTLINE DIMENSIONS 5.00 0.60MAX BSCSQ 0.60MAX PIN1 INDICATOR 25 32 1 24 PIN1 INDICATOR 0.50 BSC TOP 3.25 4.75 EXPOSED VIEW BSCSQ PAD 3.10SQ (BOTTOMVIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25MIN 0.80MAX 3.50REF 12°MAX 0.65TYP 0.05MAX FORPROPERCONNECTIONOF THEEXPOSEDPAD,REFERTO 1.00 0.02NOM THEPINCONFIGURATIONAND 0.85 0.30 FUNCTIONDESCRIPTIONS COPLANARITY 0.80 0.20REF SECTIONOFTHISDATASHEET. 0.23 0.08 SEATING 0.18 PLANE COMPLIANTTOJEDECSTANDARDSMO-220-VHHD-2 Figure 52. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8376ACPZ-WP −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] , Waffle Pack CP-32-2 AD8376ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel CP-32-2 AD8376-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 23 of 24 011708-A AD8376 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06725-0-10/10(A) Rev. A | Page 24 of 24