ANALOG DEVICES AD8375

Ultralow Distortion IF VGA AD8375 FEATURES FUNCTIONAL BLOCK DIAGRAM VPOS COMM Bandwidth of 630 MHz (−3 dB) Gain range: −4 dB to +20 dB VCOM PWUP Step size: 1 dB ± 0.2 dB AD8375 OUT+ Differential input and output Noise figure: 8 dB @ maximum gain VIN+ OUT+ Output IP3 of ~50 dBm at 200 MHz POST-AMP α Output P1dB of 19 dBm at 200 MHz OUT– VIN– Provides constant SFDR vs. gain OUT– Parallel 5-bit control interface REGISTERS Power-down feature AND GAIN DECODER Single 5 V supply operation 24-lead, 4 mm × 4 mm LFCSP APPLICATIONS A4 A3 A2 A1 A0 Figure 1. Differential ADC drivers High IF sampling receivers Wideband multichannel receivers Instrumentation GENERAL DESCRIPTION The AD8375 is a digitally controlled, variable gain, wide Fabricated on an Analog Devices, Inc., high speed SiGe process, bandwidth amplifier that provides precise gain control, high the AD8375 is supplied in a compact, thermally enhanced, IP3, and low noise figure. The excellent distortion performance 4 mm × 4 mm, 24-lead LFCSP package and operates over the and high signal bandwidth make the AD8375 an excellent gain temperature range of −40°C to +85°C. control device for a variety of receiver applications. –40 65 Using an advanced high speed SiGe process and incorporating –50 60 proprietary distortion cancellation techniques, the AD8375 achieves 50 dBm output IP3 at 200 MHz. –60 55 OIP3 The AD8375 provides a broad 24 dB gain range with 1 dB –70 50 resolution. The gain is adjusted through a 5-pin control interface and can be driven using standard TTL levels. The open-collector –80 45 outputs provide a flexible interface, allowing the overall signal HD2 –90 40 gain to be set by the loading impedance. Thus, the signal voltage gain is directly proportional to the load. HD3 –100 35 The AD8375 is powered on by applying the appropriate logic –110 30 level to the PWUP pin. The quiescent current of the AD8375 is 40 60 80 100 120 140 160 180 200 typically 130 mA. When powered down, the AD8375 consumes FREQUENCY (MHz) less than 5 mA and offers excellent input-to-output isolation. Figure 2. Harmonic Distortion and Output IP3 vs. Frequency Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. HARMONIC DISTORTION (dBc), OUTPUT @ 2V p-p OIP3 (dBm), OUTPUT @ 3dBm/TONE 06724-001 06724-052 AD8375 TABLE OF CONTENTS Features .............................................................................................. 1 Basic Structure............................................................................ 12 Applications....................................................................................... 1 Applications..................................................................................... 13 Functional Block Diagram .............................................................. 1 Basic Connections...................................................................... 13 General Description ......................................................................... 1 Single-Ended-to-Differential Conversion............................... 13 Revision History ............................................................................... 2 Broadband Operation................................................................ 14 Specifications..................................................................................... 3 ADC Interfacing......................................................................... 14 Absolute Maximum Ratings............................................................ 5 Layout Considerations............................................................... 17 ESD Caution.................................................................................. 5 Characterization Test Circuits .................................................. 17 Pin Configuration and Function Descriptions............................. 6 Evaluation Board........................................................................ 18 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 22 Circuit Description......................................................................... 12 Ordering Guide .......................................................................... 22 REVISION HISTORY 8/07—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8375 SPECIFICATIONS VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V < 2 V p-p (5.2 dBm) 630 MHz OUT Slew Rate 5 V/ns INPUT STAGE Pin VIN+ and Pin VIN− Maximum Input Swing For linear operation (A = −4 dB) 8.5 V p-p V Differential Input Resistance Differential 125 150 165 Ω Common-Mode Input Voltage 1.9 V CMRR Gain code = 00000 55 dB GAIN Amplifier Transconductance Gain code = 00000 0.060 0.067 0.074 S Maximum Voltage Gain Gain code = 00000 20 dB Minimum Voltage Gain Gain code ≥ 11000 −4 dB Gain Step Size From gain code = 00000 to 11000 0.89 0.98 1.01 dB Gain Flatness All gain codes, 20% fractional bandwidth for fC < 200 MHz 0.12 dB Gain Temperature Sensitivity Gain code = 00000 8 mdB/°C Gain Step Response For VIN = 100 mV p-p, gain code = 10100 to 00000 5 ns OUTPUT STAGE Pin VOUT+ and Pin VOUT− Output Voltage Swing At P1dB, gain code = 00000 12.6 V p-p Output Impedance Differential 16||0.8 kΩ||pF NOISE/HARMONIC PERFORMANCE 46 MHz Gain code = 00000 Noise Figure 8.3 dB Second Harmonic V = 2 V p-p −92 dBc OUT Third Harmonic V = 2 V p-p −94 dBc OUT Output IP3 2 MHz spacing, +3 dBm per tone 50 dBm Output 1 dB Compression Point 22 dBm 70 MHz Gain code = 00000 Noise Figure 8.3 dB Second Harmonic V = 2 V p-p −98 dBc OUT Third Harmonic V = 2 V p-p −95 dBc OUT Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm Output 1 dB Compression Point 22 dBm 140 MHz Gain code = 00000 Noise Figure 8.3 dB Second Harmonic V = 2 V p-p −90 dBc OUT Third Harmonic VOUT = 2 V p-p −100 dBc Output IP3 2 MHz spacing, 3 dBm per tone 51 dBm Output 1 dB Compression Point 20 dBm 200 MHz Gain code = 00000 Noise Figure 8.3 dB Second Harmonic V = 2 V p-p −85 dBc OUT Third Harmonic VOUT = 2 V p-p −92 dBc Output IP3 2 MHz spacing, 3 dBm per tone 50 dBm Output 1 dB Compression Point 19 dBm Rev. 0 | Page 3 of 24 AD8375 Parameter Conditions Min Typ Max Unit POWER INTERFACE Supply Voltage 4.5 5.0 5.5 V VPOS and Output Quiescent Current Thermal connection made to exposed paddle under device 120 125 130 mA vs. Temperature −40°C ≤ T ≤ +85°C 150 mA A Power-Down Current PWUP low 2.5 mA vs. Temperature −40°C ≤T ≤ +85°C 3 mA A POWER-UP/GAIN CONTROL Pin A0 to Pin A4, Pin PWUP V Minimum voltage for a logic high 1.6 V IH VIL Maximum voltage for a logic low 0.8 V Logic Input Bias Current 900 nA Table 2. Gain Code vs. Voltage Gain Look-Up Table 5-Bit Binary Gain Code Voltage Gain (dB) 5-Bit Binary Gain Code Voltage Gain (dB) 00000 +20 01101 +7 00001 +19 01110 +6 00010 +18 01111 +5 00011 +17 10000 +4 00100 +16 10001 +3 00101 +15 10010 +2 00110 +14 10011 +1 00111 +13 10100 0 01000 +12 10101 −1 01001 +11 10110 −2 01010 +10 10111 −3 01011 +9 11000 −4 01100 +8 >11000 −4 Rev. 0 | Page 4 of 24 AD8375 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Supply Voltage, V 5.5 V POS other conditions above those indicated in the operational PWUP, A0 to A4 −0.6 V to (V + 0.6 V) POS section of this specification is not implied. Exposure to absolute Input Voltage, V , V −0.15 V to +4.15 V IN+ IN− maximum rating conditions for extended periods may affect DC Common Mode VCOM ± 0.25 V device reliability. VCOM ±6 mA Internal Power Dissipation 825 mW θ (Exposed Paddle Soldered Down) 63.6°C/W JA ESD CAUTION θ (At Exposed Paddle) 14.6°C/W JC Maximum Junction Temperature 130°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Rev. 0 | Page 5 of 24 AD8375 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR VCOM 1 18 VOUT– VIN+ 2 17 VOUT+ VIN– 3 16 VOUT– AD8375 A4 4 15 VOUT+ TOP VIEW A3 5 14 COMM (Not to Scale) A2 6 13 VPOS Figure 3. 24-Lead LFCSP Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VCOM Common-Mode Pin. Typically bypassed to ground using external capacitor. 2 VIN+ Voltage Input Positive. 3 VIN− Voltage Input Negative. 4 A4 MSB for the 5-Bit Gain Control Interface. 5 A3 MSB − 1 for the Gain Control Interface. 6 A2 MSB − 2 for the Gain Control Interface. 7 A1 LSB + 1 for the Gain Control Interface. 8 A0 LSB for the 5-Bit Gain Control Interface. 9, 10, 12, 13, 23 VPOS Positive Supply Pins. Should be bypassed to ground using suitable bypass capacitor. 11, 14, 20, 21, 22, 24 COMM Device Common (DC Ground). 15, 17 VOUT+ Positive Output Pins (Open Collector). Require dc bias of +5 V nominal. 16, 18 VOUT− Negative Output Pins (Open Collector). Require dc bias of +5 V nominal. 19 PWUP Chip Enable Pin. Enabled with a logic high and disabled with a logic low. Rev. 0 | Page 6 of 24 06724-002 A1 7 24 COMM A0 8 23 VPOS VPOS 9 22 COMM VPOS 10 21 COMM COMM 11 20 COMM VPOS 12 19 PWUP AD8375 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted. 25 1.0 46MHz 0.8 70MHz 20 140MHz 0.6 200MHz 15 0.4 0.2 10 0 5 –0.2 –0.4 0 –0.6 –5 –0.8 –10 –1.0 –4 0 5 10 15 20 –4 0 5 10 15 20 11000 10100 01111 01010 00101 00000 11000 10100 01111 01010 00101 10100 GAIN CODE GAIN CODE Figure 4. Gain vs. Gain Code at 46 MHz, 70 MHz, 140 MHz, and 200 MHz Figure 7. Gain Step Error, Frequency 140 MHz 25 20dB 25 19dB 18dB 17dB INPUT MAX 20 16dB RATING 20 15dB BOUNDARY 14dB 15 13dB 200MHz 12dB 11dB 140MHz 15 10dB 10 70MHz 9dB 46MHz 8dB 7dB 5 6dB 10 5dB 4dB 0 3dB 2dB 1dB 5 0dB –5 –1dB –2dB –3dB –10 –4dB 0 10 100 1000 –4 1 6 11 16 21 FREQUENCY (MHz) GAIN (dB) Figure 5. Gain vs. Frequency Response Figure 8. P1dB vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz 10 25 25°C 8 85°C –40°C 6 20 4 15 2 +25°C +85°C 0 –40°C –2 10 –4 –6 5 –8 0 –10 –4 0 5 10 15 20 46 100 150 200 250 300 350 400 450 500 11000 10100 01111 01010 00101 00000 FREQUENCY (MHz) GAIN CODE Figure 9. P1dB vs. Frequency at Maximum Gain, Three Temperatures Figure 6. Gain Error over Temperature at 140 MHz Rev. 0 | Page 7 of 24 GAIN (dB) GAIN ERROR (dB) GAIN (dB) 06724-003 06724-005 06724-004 GAIN ERROR (dB) OP1dB (dBm) OP1dB (dBm) 06724-007 06724-008 06724-006 AD8375 52 55 65 +25°C 20dB A = +20dB V 51 –40°C 20dB +85°C 20dB 50 60 50 A = +10dB +25°C 0dB V A = 20dB V –40°C 0dB A = 0dB V 49 +85°C 0dB 48 45 55 47 46 40 50 A = –4dB V A = 0dB V 45 44 35 45 43 42 30 40 41 40 25 35 30 50 70 90 110 130 150 170 190 210 –3 –2 –1 01 2345 FREQUENCY (MHz) P PER TONE (dBm) OUT Figure 10. Output Third-Order Intercept at Four Gains, Figure 13. Output Third-Order Intercept vs. Power, Output Level at 3 dBm/Tone Frequency 140 MHz, Three Temperatures 52 –70 46MHz 51 70MHz A = +20dB –75 V 140MHz 50 200MHz –80 49 A = +10dB V 48 –85 47 A = 0dB V –90 46 45 –95 44 A = –4dB V 43 –100 42 –105 41 40 –110 –4 –3 –2 –1 0 1 2 3 4 5 6 –4 1 6 11 16 GAIN (dB) P (dBm) OUT Figure 14. Two-Tone Output IMD vs. Gain Figure 11. Output Third-Order Intercept vs. Power at 46 MHz, 70 MHz, 140 MHz, and 200 MHz, Output Level at 3 dBm/Tone at Four Gains, Frequency 140 MHz –70 70 –75 65 –80 60 –85 55 +25°C +85°C –90 50 –40°C –40°C +85°C –95 45 +25°C –100 40 –105 35 –110 30 40 60 80 100 120 140 160 180 200 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Two-Tone Output IMD vs. Frequency, Figure 12. Output Third-Order Intercept vs. Frequency, Three Temperatures, Output Level at 3 dBm/Tone Three Temperatures, Output Level at 3 dBm/Tone Rev. 0 | Page 8 of 24 OIP3 (dBm) OIP3 (dBm) OIP3 (dBm) 06274-010 06724-011 06724-009 OIP3 (dBm) IMD3 (dBc) IMD3 (dBc) 06724-013 06724-014 OIP3 (dBm) 06724-012 AD8375 –75 –65 –85 –70 HD2 –4dB HD2 0dB –80 –70 –90 –75 HD2 +10dB HD2 +85°C HD2 +20dB –85 HD3 –4dB –75 –95 –80 HD2 +25°C HD3 0dB HD3 +10dB –90 –80 –100 –85 HD3 +20dB HD2 –40°C –95 –85 –105 –90 –100 –90 –110 HD3 –40°C –95 –105 –95 –115 –100 HD3 +85°C HD3 +25°C –110 –100 –120 –105 –115 –105 –125 –110 40 60 80 100 120 140 160 180 200 –5 –4 –3 –2 –1 0 1234 5 FREQUENCY (MHz) P (dBm) OUT Figure 16. Harmonic Distortion vs. Frequency at Four Gain Codes, Figure 19. Harmonic Distortion vs. Power, Frequency 140 MHz, VOUT = 2 V p-p Three Temperatures –75 –60 35 HD2 +20dB –80 –65 HD2 +10dB 30 HD2 0dB –70 –85 HD2 –4dB 25 –75 –90 –95 –80 20 –85 –100 HD3 +20dB 15 –90 –105 HD3 +10dB 46MHz HD3 0dB 70MHz –95 –110 HD3 –4dB 10 140MHz 200MHz –100 –115 5 –105 –120 0 –110 –125 –4 –2 0 2 4 6 8 1012 14 16 1820 –5 –4 –3 –2 –1 0 1 2 3 4 5 GAIN (dB) P (dBm) OUT Figure 17. Harmonic Distortion vs. Power at Four Gain Codes, Figure 20. NF vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz Frequency 140 MHz –80 45 HD2 +25°C HD3 +25°C 40 HD2 –40°C HD3 –40°C –85 A = –4dB V 35 HD2 +85°C HD3 +85°C A = 0dB V 30 –90 25 A = +10dB V 20 –95 15 A = +20dB V 10 –100 5 0 –105 40 60 80 100 120 140 160 180 200 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. Harmonic Distortion vs. Frequency, Three Temperatures, Figure 21. NF vs. Frequency V = 2 V p-p OUT Rev. 0 | Page 9 of 24 HARMONIC DISTORTION HD2 (dBc) HARMONIC DISTORTION HD2 (dBc) HARMONIC DISTORTION HD2 AND HD3 (dBc) 06274-017 HARMONIC DISTORTION HD3 (dBc) HARMONIC DISTORTION HD3 (dBc) 06724-016 06724-015 HARMONIC DISTORTION HD2 (dBc) NOISE FIGURE (dB) NOISE FIGURE (dB) 06724-019 06724-020 HARMONIC DISTORTION HD3 (dBc) 06724-018 AD8375 REF3 POSITION –600mV/DIV REF3 SCALE 500mV 0pF 10pF EACH SIDE INPUT 2 R1 R3 1 CH1 500mV Ω CH2 500mV Ω M10.0ns 10.0GS/s IT 10.0ps/pt M2.5ns 20.0GS/s IT 10.0ps/pt A CH1 960mV REF3 500mV 2.5ns A CH4 28.0mV Figure 22. Gain Step Time Domain Response Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB REF1 POSITION –1.02/DIV REF1 SCALE OUTPUT 50mV RISE (C2) 1.384ns FALL(C2) 1.39ns INPUT 2 2 REF1 1 CH1 500mV Ω CH2 500mV Ω M20.0ns 10.0GS/s IT 20.0ps/pt CH2 500mV M2.5ns 20Gsps A CH2 –610mV A CH1 960mV REF1 50.0mV IT 2.5ps/pt Figure 23. ENBL Time Domain Response Figure 26. Large Signal Pulse Response 0 180 REF1 POSITION –420mV/DIV REF1 SCALE –5 120 2V 0pF 10pF EACH SIDE –10 60 INPUT –15 0 R1 R3 R4 –60 –20 –120 –25 –180 –30 M2.5ns 20.0GS/s IT 10.0ps/pt 10 100 1000 REF1 2.0V 2.5ns A CH4 28.0mV FREQUENCY (MHz) Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB Figure 27. S11 vs. Frequency Rev. 0 | Page 10 of 24 06724-023 06724-022 06724-021 S11 MAG (dB) 06724-024 06724-025 S11 PHASE (Degrees) 06724-026 AD8375 0 1.00E–09 9.00E–10 –20 8.00E–10 +20dB +10dB 7.00E–10 0dB –40 –4dB 6.00E–10 –60 5.00E–10 4.00E–10 –80 3.00E–10 2.00E–10 –100 1.00E–10 –120 0.00E+00 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 28. Reverse Isolation vs. Frequency Figure 30. Group Delay vs. Frequency at Gain 80 0 70 –20 60 –40 50 40 –60 30 –80 20 –100 10 –120 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. Off-State Isolation vs. Frequency Figure 31. Common-Mode Rejection Ratio vs. Frequency Rev. 0 | Page 11 of 24 ISOLATION (dB) S12 (dB) 06724-028 06724-027 DELAY (Seconds) CMRR (dB) 06724-031 06724-029 AD8375 CIRCUIT DESCRIPTION The dependency of the gain on the load is due to the open- BASIC STRUCTURE collector architecture of the output stage. The AD8375 is a differential variable gain amplifier consisting of a 150 Ω digitally controlled passive attenuator followed by a The dc current to the outputs of the amplifier is supplied highly linear transconductance amplifier. through two external chokes. The inductance of the chokes and the resistance of the load determine the low frequency pole of AD8375 ATTENUATOR MUX BUFFERS the amplifier. The parasitic capacitance of the chokes adds to VIN+ the output capacitance of the part. This total capacitance in VOUT+ parallel with the load resistance sets the high frequency pole of gm CORE VCOM AMP the device. Generally, the larger the inductance of the choke, the VOUT– VIN– higher its parasitic capacitance. Therefore, the value and type of the choke should be chosen keeping this trade-off in mind. For operation frequency of 15 MHz to 700 MHz driving a A0 TO A4 DIGITAL 150 Ω load, 1 μH chokes with SRF of 160 MHz or higher are SELECT recommended (such as 0805LS-102XJBB from Coilcraft). Figure 32. Simplified Schematic The supply current consists of about 50 mA through the VCC Input System pin and 80 mA through the two chokes combined. The latter The dc voltage level at the inputs of the AD8375 is set by an increases with temperature at about 2.5 mA per 10°C. internal voltage reference circuit to about 2 V. This reference is There are two output pins for each polarity and they are accessible at VCOM and can be used to source or sink 100 μA. oriented in an alternating fashion. When designing the board, For cases where a common-mode signal is applied to the inputs, care should be taken to minimize the parasitic capacitance due such as in a single-ended application, an external capacitor to the routing that connects the corresponding outputs together. between VCOM and ground is required. The capacitor improves A good practice is to avoid any ground or power plane under the linearity performance of the part in this mode. This capacitor this routing region and under the chokes to minimize the should be sized to provide a reactance of 10 Ω or less at the parasitic capacitance. lowest frequency of operation. If the applied common-mode signal is dc, its amplitude should be limited to 0.25 V from Gain Control VCOM (VCOM ± 0.25 V). A 5-bit binary code changes the attenuator setting in 1 dB steps The device can be powered down by pulling the PWUP pin such that the gain of the device changes from 20 dB (Code 0) to down to below 0.8 V. In the powered down mode, the total −4 dB (Code 24 and higher). current reduces to 3 mA (typical). The dc level at the inputs and The noise figure of the device is about 8 dB at maximum gain at VCOM remains at about 2 V, regardless of the state of the setting and it increases as the gain is reduced. The increase in PWUP pin. noise figure is equal to the reduction in gain. The linearity of Output Amplifier the part measured at the output is first-order independent of the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately The gain is based on a 150 Ω differential load and varies as R is L 50 dBm into 150 Ω load at 140 MHz (3 dBm per tone). At gain changed per the following equations: settings below 0 dB, it drops to approximately 45 dBm. Voltage Gain = 20 × (log(RL/150) + 1) and Power Gain = 10 × (log(R /150) + 2) L Rev. 0 | Page 12 of 24 06724-032 AD8375 APPLICATIONS +5V BASIC CONNECTIONS VCM 0.1µF Figure 35 shows the basic connections for operating the AD8375. A voltage between 4.5 V and 5.5 V should be applied 1µH 1µH 150Ω 0.1µF 0.1µF to the supply pins. Each supply pin should be decoupled with at least one low inductance, surface-mount ceramic capacitor of 50Ω 150Ω AD8375 0.1µF 0.1µF 0.1 μF placed as close as possible to the device. AC The outputs of the AD8375 are open collectors that need to be 37.5Ω 5 pulled up to the positive supply with 1 μH RF chokes. The differential outputs are biased to the positive supply and require A0 TO A4 ac coupling capacitors, preferably 0.1 μF. Similarly, the input Figure 33. Single-Ended-to-Differential Conversion pins are at bias voltages of about 2 V above ground and should Using a single-ended input decreases the power gain by 3 dB be ac-coupled as well. The ac coupling capacitors and the RF and limits distortion cancellation. Consequently, the second- chokes are the principle limitations for operation at low order distortion is degraded. The third-order distortion remains frequencies. low to 200 MHz, as shown in Figure 34. To enable the AD8375, the PWUP pin must be pulled high. –60 Taking PWUP low puts the AD8375 in sleep mode, reducing –65 current consumption to 5 mA at ambient. HD2 –70 SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION –75 The AD8375 can be configured as a single-ended input to differential output driver as shown in Figure 33. A 150 Ω –80 resistor in parallel with the input impedance of input pin –85 provides an impedance matching of 50 Ω. The voltage gain and the bandwidth of this configuration, using a 150 Ω load, –90 remains the same as when using a differential input. HD3 –95 –100 0 50 100 150 200 FREQUENCY (MHz) Figure 34. Harmonic Distortion vs. Frequency of Single-Ended-to-Differential Conversion +V S 0.1µF 10µF 1µH 24 23 22 21 20 19 COMM VPOS COMM COMM COMM PWUP 0.1µF 0.1µF 1 VCOM VOUT– 18 R 0.1µF S 2 2 VIN+ VOUT+ 17 BALANCED BALANCED R AC L 1µH SOURCE LOAD 3 VIN– VOUT– 16 R S AD8375 0.1µF 2 0.1µF 4 A4 VOUT+ 15 5 A3 COMM 14 6 A2 VPOS 13 A1 A0 VPOS VPOS COMM VPOS 78 9 10 11 12 +V S PARALLEL CONTROL INTERFACE 0.1µF 0.1µF Figure 35. Basic Connections Rev. 0 | Page 13 of 24 HARMONIC DISTORTION (dBc) 06724-034 06724-035 06724-036 AD8375 For example, in the extreme case where the load is assumed to BROADBAND OPERATION be high impedance, R = ∞, the equation for R1 reduces to R1 = L The AD8375 uses an open-collector output structure that 75 Ω. Using the equation for VR, the applied voltage should be requires dc bias through an external bias network. Typically, VR = 8 V. The measured single-tone low frequency harmonic choke inductors are used to provide bias to the open-collector distortion for a 2 V p-p output using 75 Ω resistive pull-ups is outputs. Choke inductors work well at signal frequencies where provided in Figure 37. the impedance of the choke is substantially larger than the target –80 ac load impedance. In broadband applications, it may not be possible to find large enough choke inductors that offer enough –82 reactance at the lowest frequency of interest while offering a HD2 –84 high enough self resonant frequency (SRF) to support the maximum bandwidth available from the device. The circuit in –86 Figure 36 can be used when frequency response below 10 MHz –88 is desired. This circuit replaces the bias chokes with bias resistors. HD3 –90 The bias resistor has the disadvantage of a greater IR drop, and requires a supply rail that is several volts above the local 5 V –92 supply used to power the device. Additionally, it is necessary –94 to account for the ac loading effect of the bias resistors when designing the output interface. Whereas the gain of the AD8375 –96 0 5 10 15 20 is load dependent, RL, in parallel with R1 + R2, should equal the FREQUENCY (MHz) optimum 150 Ω target load impedance to provide the expected Figure 37. Harmonic Distortion vs. Frequency Using Resistive Pull-Ups ac performance depicted in the data sheet. Additionally, to ensure good output balance and even-order distortion ADC INTERFACING performance, it is essential that R1 = R2. The AD8375 is a high output linearity variable gain amplifier SET TO that is optimized for ADC interfacing. The output IP3 and noise 5V VR 5V floor essentially remain constant vs. the 24 dB available gain 37.5Ω R1 range. This is a valuable feature in a variable gain receiver where 0.1µF 0.1µF ETC1-1-13 it is desirable to maintain a constant instantaneous dynamic 50Ω RL AD8375 range as the receiver gain is modified. The output noise density 0.1µF 0.1µF is typically around 20 nV/√Hz, which is comparable to 14-/16- 37.5Ω R2 bit sensitivity limits. The two-tone IP3 performance of the 5 AD8375 is typically around 50 dBm. This results in SFDR levels VR A0 TO A4 of better than 86 dB when driving the AD9445 up to 140 MHz. Figure 36. Single-Ended Broadband Operation with Resistive Pull-Ups There are several options available to the designer when using Using the formula for R1 (Equation 1), the values of R1 = R2 the AD8375. The open-collector output provides the capability that provide a total presented load impedance of 150 Ω can be of driving a variety of loads. Figure 38 shows a simplified found. The required voltage applied to the bias resistors, VR, wideband interface with the AD8375 driving a AD9445. The can be found by using the VR formula (Equation 2). AD9445 is a 14-bit 125 MSPS analog-to-digital converter with a 75× R buffered wideband input, which presents a 2 kΩ differential L R1= (1) load impedance and requires a 2 V p-p differential input swing R − 150 L to reach full scale. and −3 VR= R1× 40× 10 + 5 (2) 5V L 1µH (SERIES) 0.1µF 0.1µF 0.1µF ETC1-1-13 33Ω VIN+ 5V 14 50Ω 37.5Ω 82Ω AD9445 L AD8375 1µH 14-BIT ADC 0.1µF 0.1µF (SERIES) 0.1µF 33Ω VIN– 37.5Ω 82Ω 5 A0 TO A4 Figure 38. Wideband ADC Interfacing Example Featuring the AD9445 Rev. 0 | Page 14 of 24 06724-037 HARMONIC DISTORTION (dBc) 06724-039 06724-038 AD8375 For optimum performance, the AD8375 should be driven The addition of the series inductors L (series) in Figure 38 differentially using an input balun or impedance transformer. extends the bandwidth of the system and provides response Figure 38 uses a wideband 1:1 transmission line balun followed flatness. Using 100 nH inductors as L (series), the wideband by two 37.5 Ω resistors in parallel with the 150 Ω input imped- system response of Figure 40 is obtained. The wideband ance of the AD8375 to provide a 50 Ω differential terminated frequency response is an advantage in broadband applications input impedance. This provides a wideband match to a 50 Ω such as predistortion receiver designs and instrumentation source. The open-collector outputs of the AD8375 are biased applications. However, by designing for a wide analog input through the two 1 μH inductors and are ac-coupled to the two frequency range, the cascaded SNR performance is somewhat 82 Ω load resistors. The 82 Ω load resistors in parallel with the degraded due to high frequency noise aliasing into the wanted series-terminated ADC impedance yields the target 150 Ω Nyquist zone. differential load impedance, which is recommended to provide 0 the specified gain accuracy of the device. The load resistors are –1 ac-coupled from the AD9445 to avoid common-mode dc –2 loading. The 33 Ω series resistors help to improve the isolation –3 between the AD8375 and any switching currents present at the –4 analog-to-digital sample and hold input circuitry. –5 1 0 SNR = 64.93dBc –6 –10 FIRST POINT = –2.93dBFs SFDR = 86.37dBc END POINT = –9.66dBFs –20 NOISE FLOOR = –108.1dB –7 MID POINT = –2.33dBFs FUND = –1.053dBFs –30 MIN = –9.66dBFs SECOND = –86.18dBc –8 –40 MAX = –1.91dBFs THIRD = –86.22dBc –50 –9 –60 –10 –70 20 48 76 104 132 160 188 216 244 272 300 –80 FREQUENCY (MHz) 2 3 –90 + 4 5 Figure 40. Measured Frequency Response of Wideband 6 –100 ADC Interface Depicted in Figure 38 –110 –120 An alternative narrow-band approach is presented in Figure 41. –130 By designing a narrow band-pass antialiasing filter between the –140 AD8375 and the target ADC, the output noise of the AD8375 –150 0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 outside of the intended Nyquist zone can be attenuated, helping FREQUENCY (MHz) to preserve the available SNR of the ADC. In general, the SNR Figure 39. Measured Single-Tone Performance of the Circuit in Figure 38 for a 100 MHz Input Signal improves several dB when including a reasonable order antialias- ing filter. In this example, a low loss 1:3 input transformer is used The circuit depicted in Figure 38 provides variable gain, to match the AD8375’s 150 Ω balanced input to a 50 Ω unbal- isolation and source matching for the AD9445. Using this anced source, resulting in minimum insertion loss at the input. circuit with the AD8375 in a gain of 20 dB (maximum gain) an SFDR performance of 86 dBc is achieved at 100 MHz, as indicated in Figure 39. Rev. 0 | Page 15 of 24 (dBFS) 06724-040 (dBFs) 06724-041 AD8375 Figure 41 is optimized for driving some of Analog Devices at dc, which introduces a zero into the transfer function. In popular unbuffered ADCs, such as the AD9246, AD9640, addition, the ac coupling capacitors and the bias chokes and AD6655. Table 5 includes antialiasing filter component introduce additional zeros into the transfer function. The final recommendations for popular IF sampling center frequencies. overall frequency response takes on a band-pass characteristic, Inductor L5 works in parallel with the on-chip ADC input helping to reject noise outside of the intended Nyquist zone. capacitance and a portion of the capacitance presented by C4 to Table 5 provides initial suggestions for prototyping purposes. form a resonant tank circuit. The resonant tank helps to ensure Some empirical optimization may be needed to help compensate the ADC input looks like a real resistance at the target center for actual PCB parasitics. frequency. Additionally, the L5 inductor shorts the ADC inputs 1µH 1nF 1nF L1 L3 1:3 AD9246 165Ω 50Ω AD8375 C2 C4 L5 AD9640 301Ω CML 1nF 165Ω AD6655 L1 L3 1nF 1µH 5 A0 TO A4 Figure 41. Narrow-Band IF Sampling Solution for Unbuffered ADC Application Table 5. Interface Filter Recommendations for Various IF Sampling Frequencies Center Frequency 1 dB Bandwidth L1 C2 L3 C4 L5 96 MHz 27 MHz 390 nH 5.6 pF 390 nH 25 pF 100 nH 140 MHz 30 MHz 330 nH 3.3 pF 330 nH 20 pF 56 nH 170 MHz 32 MHz 270 nH 2.7 pF 270 nH 20 pF 39 nH 211 MHz 32 MHz 220 nH 2.2 pF 220 nH 18 pF 27 nH Rev. 0 | Page 16 of 24 06724-042 AD8375 +9V LAYOUT CONSIDERATIONS There are two output pins for each polarity, and they are 96Ω 96Ω oriented in an alternating fashion. When designing the board, 25Ω 0.1µF 0.1µF TC3-1T 330Ω care should be taken to minimize the parasitic capacitance due T1 50Ω AD8375 to the routing that connects the corresponding outputs together. 50Ω A good practice is to avoid any ground or power plane under 330Ω AC 0.1µF 0.1µF 25Ω 5 this routing region and under the chokes to minimize the parasitic capacitance. A0 TO A4 Figure 43. Test Circuit for Time Domain Measurements CHARACTERIZATION TEST CIRCUITS Differential-to-Differential Characterization The S-parameter characterization for the AD8375 was performed using a dedicated differential input to differential output characterization board. Figure 44 shows the layout of characterization board. The board was designed for optimum impedance matching into a 75 Ω system. Because both the input and output impedances of the AD8375 are 150 Ω differentially, 75 Ω impedance runs were used to match 75 Ω network analyzer port impedances. On-board 1 μH inductors were used for output biasing, and the output board traces were designed for minimum capacitance. +5V L1 L2 1µH 1µH 0.1µF 0.1µF 75Ω 75Ω AC 75Ω TRACES 75Ω TRACES AC AD8375 75Ω 75Ω 0.1µF 0.1µF 5 A0 TO A4 Figure 42. Test Circuit for S-Parameters on Dedicated 75 Ω Differential-to-Differential Board Figure 44. Differential-to-Differential Characterization Board Circuit Side Layout +5V L1 L2 1µH 1µH C3 C1 R1 R4 0.1µF 0.1µF TC3-1T 62Ω 25Ω ETC1-1-13 T1 PAD LOSS = 11dB T2 AD8375 50Ω 50Ω R3 R2 AC C2 C4 25Ω 62Ω 0.1µF 0.1µF 5 A0 TO A4 Figure 45. Test Circuit for Distortion, Gain, and Noise Rev. 0 | Page 17 of 24 06724-046 06724-043 06724-044 06724-047 AD8375 The output pins of the AD8375 require supply biasing with EVALUATION BOARD 1 μH RF chokes. Both the input and output pins must be ac- Figure 46 shows the schematic of the AD8375 evaluation board. coupled. These pins are converted to single-ended with a pair of The silkscreen and layout of the component and circuit sides baluns (Mini-Circuits TC3-1T+ and M/A-COM ETC1-1-13). are shown in Figure 47 through Figure 50. The board is powered The balun at the input, T1, is used to transform a 50 Ω source by a single supply in the 4.5 V to 5.5 V range. The power supply impedance to the desired 150 Ω reference level. The output is decoupled by 10 μF and 0.1 μF capacitors at each power supply balun, T3, and the matching components are configured to pin. Additional decoupling, in the form of a series resistor or provide a 150 Ω to 50 Ω impedance transformation with an inductor at the supply pins, can also be added. Table 6 details insertion loss of about 11 dB. the various configuration options of the evaluation board. Rev. 0 | Page 18 of 24 AD8375 Figure 46. AD8375 Evaluation Board Schematic Rev. 0 | Page 19 of 24 VPOS VXA R91 PU 0Ω VPOS R13 0Ω C64 0.1µF C63 C5 0.1µF VPOS R16 R15 0Ω 0Ω L2 L1 24 23 22 21 20 19 1µH 1µH C11 R25 COMM VPOS COMM COMM COMM PWUP C8 R20 0.1µF 30.9Ω T3 0.1µF 61.9Ω ETC1-1-13 1 VCOM VOUT– 18 OUTN C1 R30 R9 R24 R1 R70 0.1µF 0Ω 0Ω TC3-1T+ INP 2 VIN+ VOUT+ 17 R62 R19 R23 C7 OUTP VPOS T1 R71 61.9Ω 30.9Ω 0.1µF C62 R29 3 VIN– VOUT– 16 0.1µF R10 INN R2 C60 C2 AD8375 R72 0Ω 0.1µF 0Ω 0.1µF 4 A4 VOUT+ 15 5 A3 COMM 14 6 A2 VPOS 13 A1 A0 VPOS VPOS COMM VPOS 78 9 10 11 12 VPOS WA4 WA3 WA2 WA1 WA0 C20 C14 C13 10µF 0.1µF 0.1µF VPOS 06724-045 AD8375 Table 6. Evaluation Board Configuration Options Components Function Default Conditions C13, C14, C20, Power Supply Decoupling. Nominal supply decoupling consists a 10 μF C20 = 10 μF (size 3528) C63, C64, R91 capacitor to ground followed by 0.1 μF capacitors to ground positioned as C13, C14, C63, C64 = 0.1 μF close to the device as possible. (size 0402) R91 = 0 Ω (size 0402) T1 = TC3-1+ (Mini-Circuits) T1, C1, C2, C60, Input Interface. T1 is a 3:1 impedance ratio balun to transform a 50 Ω single- R1, R2, R9, R10, ended input into a 150 Ω balanced differential signal. R2 grounds one side of C1, C2, C60 = 0.1 μF (size 0402) R70 to R72 the differential drive interface for single-ended applications. R9, R10, and R70 R2, R9, R10 = 0 Ω (size 0402) to R72 are provided for generic placement of matching components. C1 and R1, R70 to R72 = open (size 0402) C2 are dc blocks. T3, C7, C8, C62 Output Interface. C7 and C8 are dc blocks. L1 and L2 provide dc biases for the T3 = ETC1-1-13 (M/A-COM) L1, L2, R15, R16, output. R19, R20, and R23 to R25 are provided for generic placement of C7, C8, C62 = 0.1 μF (size 0402) R19, R20, R23 to R25, matching components. The evaluation board is configured to provide a 150 Ω L1, L2 = 1 μH (size 0805) R29, R30, R62 to 50 Ω impedance transformation with an insertion loss of about 11 dB. T3 is R19, R20 = 61.9 Ω (size 0402) a 1:1 impedance ratio balun to transform the balanced differential signal to a R23, R25 = 30.9 Ω (size 0402) single-ended signal. R30 grounds one side of the differential output interface R15, R16 = 0 Ω (size 0603) for single-ended applications. R30 = 0 Ω (size 0402) R24, R29, R62 = open (size 0402) PU, R13, C5 Enable Interface. The AD8375 is enabled by applying a logic high voltage to PU = installed the PWUP pin. The device is disabled when the PU switch is set in the position R13 = 0 Ω (size 0603) closest to the PU label, connecting the PWUP pin to ground. The device is C5 = open (size 0603) enabled when the PU switch is set in the opposite position, connecting the PWUP to VPOS. WA0 to WA4 Parallel Interface Control. Used to hardwire A0 through A4 to the desired gain. WA0 to WA4 = installed The bank of switches, WA4 to WA0, set the binary gain code. WA4 represents the LSB. WA0 represents the MSB. C11 Voltage Reference. Input common-mode voltage ac-coupled to ground by C11 = 0.1 μF (size 0402) 0.1 μF capacitor, C11. Rev. 0 | Page 20 of 24 AD8375 Figure 47. Component Side Silkscreen Figure 49. Component Side Layout Figure 50. Circuit Side Layout Figure 48. Circuit Side Silkscreen Rev. 0 | Page 21 of 24 06724-049 06724-048 06724-051 06724-050 AD8375 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 1 19 24 PIN 1 18 0.50 INDICATOR 2.25 BSC TOP 3.75 EXPOSED VIEW 2.10 SQ BSC SQ PAD (BOTTOM VIEW) 1.95 0.50 13 6 0.40 12 7 0.30 0.25 MIN 0.80 MAX 2.50 REF 1.00 12° MAX 0.65TYP 0.85 0.05 MAX 0.80 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.08 0.23 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 Figure 51. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-24-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD8375ACPZ-WP −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack CP-24-1 1 AD8375ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Reel CP-24-1 1 AD8375-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 22 of 24 AD8375 NOTES Rev. 0 | Page 23 of 24 AD8375 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06724-0-8/07(0) TTTT Rev. 0 | Page 24 of 24