ANALOG DEVICES AD8372

41 dB Range, 1 dB Step Size, Programmable Dual VGA AD8372 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual independent digitally controlled VGA ENB1 REF1 AD8372 Differential input and output IPC1 OPC1 150 Ω differential input INC1 ONC1 Open-collector differential output CHANNEL 1 POSTAMP RXT1 7.8 dB noise figure to 100 MHz @ maximum gain CLK2 CLK1 HD2/HD3 better than 77 dBc for 1 V p-p differential output REGISTERS SDO1 SDO2 AND −3 dB bandwidth of 130 MHz SDI1 SDI2 GAIN DECODER 41 dB gain range LCH1 LCH2 1 dB step size ± 0.2 dB RXT2 Serial 8-bit bidirectional SPI control interface OPC2 IPC2 Wide input dynamic range INC2 ONC2 Pin-programmable output stage CHANNEL 2 POSTAMP ENB2 REF2 Power-down feature Figure 1. Single 5 V supply: 106 mA per channel 32-lead LFCSP, 5 mm × 5 mm package APPLICATIONS Differential ADC drivers CMTS upstream direct sampling receivers CATV modem signal scaling Generic RF/IF gain stages Single-ended-to-differential conversion GENERAL DESCRIPTION The AD8372 is a dual, digitally controlled, variable gain setting resistors can be adjusted to manipulate the gain and amplifier (VGA) that provides precise gain control, high IP3, distortion performance of each channel. This is a flexible and low noise figure. The excellent distortion performance and feature in applications where it is desirable to trade off distortion moderate signal bandwidth make the AD8372 a suitable performance for lower power consumption. gain control device for a variety of multichannel receiver The AD8372 is powered on by applying the appropriate logic applications. level to the ENB1, ENB2 pins. When powered down, the AD8372 For wide input dynamic range applications, the AD8372 consumes less than 2.6 mA and offers excellent input-to-output provides a broad 41 dB gain range. The gain is programmed isolation. The gain setting is preserved when powered down. through a bidirectional 4-pin serial interface. The serial inter- Fabricated on an Analog Devices, Inc., high frequency BiCMOS face consists of a clock, latch, data input, and data output lines process, the AD8372 provides precise gain adjustment capabilities for each channel. with good distortion performance. The quiescent current of the The AD8372 provides the ability to set the transconductance of AD8372 is typically 106 mA per channel. The AD8372 amplifier the output stage using a single external resistor. The RXT1 and comes in a compact, thermally enhanced 5 mm × 5 mm 32-lead RXT2 pins provide a band gap derived stable reference voltage LFCSP package and operates over the temperature range of of 1.56 V. Typically 2.0 kΩ shunt resistors to ground are used to −40°C to +85°C. set the maximum gain to a nominal value of 31 dB. The current Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07051-001 AD8372 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ..............................................8  Applications....................................................................................... 1  Theory of Operation ...................................................................... 10  Functional Block Diagram .............................................................. 1  Single-Ended and Differential Signals..................................... 10  General Description ......................................................................... 1  Passive Filter Techniques........................................................... 10  Revision History ............................................................................... 2  Digital Gain Control .................................................................. 10  Specifications..................................................................................... 3  Driving Analog-to-Digital Converters.................................... 10  Serial Control Interface Timing ................................................. 5  Evaluation Board Schematic ......................................................... 12  Absolute Maximum Ratings............................................................ 6  Outline Dimensions....................................................................... 13  ESD Caution.................................................................................. 6  Ordering Guide .......................................................................... 13  Pin Configuration and Function Descriptions............................. 7  REVISION HISTORY 6/11—Rev. A to Rev. B Changes to Table 4............................................................................ 6 Changes to Figure 4 and Table 5..................................................... 7 Added Exposed Pad Notation to Outline Dimensions ............. 13 Changes to Ordering Guide .......................................................... 13 5/08—Rev. 0 to Rev. A Changes to Features and Figure 1................................................... 1 Changes to Figure 2 and Figure 3................................................... 5 Changes to Figure 9.......................................................................... 8 Changes to Figure 16...................................................................... 12 11/07—Revision 0: Initial Version Rev. B | Page 2 of 16 AD8372 SPECIFICATIONS VS = 5 V, T = 25°C, ZS = 150 Ω, ZL = 250 Ω at 35 MHz, 1 V p-p differential output, RXT1 = RXT2 = 2.0 kΩ, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V < 1 V p-p, C < 3pF 130 MHz OUT LOAD INPUT STAGE Pin IPC1, Pin INC1, Pin IPC2, and Pin INC2 Maximum Input Swing at Each Input Pin 5 V p-p Input Resistance Differential 150 Ω Common-Mode Input Voltage 2.4 V CMRR Gain code = 1x101010 (max gain) 55 dB GAIN Maximum Voltage Gain Gain code = 1x101010 32 dB Minimum Voltage Gain Gain code = 1x000001 −9 dB Gain Step Size From gain code 1x000001 to 1x101010 1.0 dB Gain Step Accuracy From gain code 1x000001 to 1x101010 ±0.3 dB Gain Flatness Gain code = 1x101010, from 5 MHz to 65MHz 0.7 dB Gain Temperature Sensitivity Gain code = 1x101010 7.5 mdB/°C Step Response For 6 dB gain step, 10% settling 20 ns OUTPUT STAGE Pin OPC1, Pin ONC1, Pin OPC2, and Pin ONC2 Output Voltage Swing At P1dB, gain code = 1x101010 9 V p-p Output Resistance Differential 3.5 kΩ Channel Isolation Measured at differential output for differential input 55 dB applied to alternate channel NOISE/HARMONIC PERFORMANCE 5 MHz Gain code = 1x101010 (max gain) Noise Figure 7.8 dB Second Harmonic 79 dBc Third Harmonic 91 dBc Output IP3 32 dBm Output 1 dB Compression Point 18.2 dBm 35 MHz Gain code = 1x101010 (max gain) Noise Figure 7.8 dB Second Harmonic 79 dBc Third Harmonic 87 dBc Output IP3 35 dBm Output 1 dB Compression Point 18.1 dBm 65 MHz Gain code = 1x101010 (max gain) Noise Figure 7.9 dB Second Harmonic 78 dBc Third Harmonic 85 dBc Output IP3 35 dBm Output 1 dB Compression Point 17.9 dBm 85 MHz Gain code = 1x101010 Noise Figure 8.1 dB Second Harmonic 77 dBc Third Harmonic 85 dBc Output IP3 35 dBm Output 1 dB Compression Point 17.7 dBm Rev. B | Page 3 of 16 AD8372 Parameter Conditions Min Typ Max Unit POWER INTERFACE Supply Voltage 4.5 5.5 V Quiescent Current per Channel Thermal connection made to exposed paddle under 106 mA device vs. Temperature −40°C ≤ T ≤ +85°C 135 mA A Power-Down Current, Both Channels ENB1 and ENB2 low 1.2 mA vs. Temperature −40°C ≤ TA ≤ +85°C 1.3 mA ENABLE INTERFACE Pin ENB1 and Pin ENB2 Enable Threshold Minimum voltage to enable the device 0.8 V ENB1, ENB2 Input Bias Current ENB1, ENB2 = 0 V 400 nA GAIN CONTROL INTERFACE Pin CLK1, Pin CLK2, Pin SDI1, Pin SDI2, Pin SDO1, Pin SDO2, Pin LCH1, and Pin LCH2 VIH Minimum voltage for a logic high 2.4 V Input Bias Current 400 nA Serial Port Output Feedthrough Worse-case feedthrough from CLK1, CLK2, SDI1, −60 dB SDI2, SDO1, SDO2, LCH1, LCH2 to OPC1 and ONC2, or OPC2 and ONC2 Table 2. Gain Code vs. Voltage Gain Look-Up Table 1 1 8-Bit Binary Gain Code Voltage Gain (dB) 8-Bit Binary Gain Code Voltage Gain (dB) RW DC 000000 < −60 RW DC 010110 +12 RW DC 000001 −9 RW DC 010111 +13 RW DC 000010 −8 RW DC 011000 +14 RW DC 000011 −7 RW DC 011001 +15 RW DC 000100 −6 RW DC 011010 +16 RW DC 000101 −5 RW DC 011011 +17 RW DC 000110 −4 RW DC 011100 +18 RW DC 000111 −3 RW DC 011101 +19 RW DC 001000 −2 RW DC 011110 +20 RW DC 001001 −1 RW DC 011111 +21 RW DC 001010 0 RW DC 100000 +22 RW DC 001011 +1 RW DC 100001 +23 RW DC 001100 +2 RW DC 100010 +24 RW DC 001101 +3 RW DC 100011 +25 RW DC 001110 +4 RW DC 100100 +26 RW DC 001111 +5 RW DC 100101 +27 RW DC 010000 +6 RW DC 100110 +28 RW DC 010001 +7 RW DC 100111 +29 RW DC 010010 +8 RW DC 101000 +30 RW DC 010011 +9 RW DC 101001 +31 RW DC 010100 +10 RW DC 101010 +32 RW DC 010101 +11 RW DC 101011 < −60 1 RW is the read/write bit. RW = 0 for read mode; RW = 1 for write mode. DC is the don’t care bit. Rev. B | Page 4 of 16 AD8372 SERIAL CONTROL INTERFACE TIMING t t CLK PW CLK1 OR CLK2 t LH t LS LCH1 OR LCH2 t t DS DH SDI1 OR SDI2 WRITE BIT DON'T CARE LSB LSB + 1 LSB + 2 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE GAIN WORD BIT IS THEN REGISTERED INTO THE SDI PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK. Figure 2. Write Mode Timing Diagram t t LH t PW CLK t D CLK1 OR CLK2 t LS LCH1 OR LCH2 t t DS DH READ BIT DC DC DC DC DC DC DC SDI1 OR SDI2 SDO1 OR SDO2 LSB LSB + 1 LSB + 2 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE GAIN WORD BIT IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK. Figure 3. Read Mode Timing Diagram Table 3. Serial Programming Timing Parameters Parameter Min Unit Clock Pulse Width (t ) 10 ns PW Clock Period (tCK) 20 ns Write Mode Setup Time Data vs. Clock (t) 0.0 ns DS Hold Time Data vs. Clock (t) 1.6 ns DH Setup Time Latch vs. Clock (t) −1.8 ns LS Hold Time Latch vs. Clock (tLH) 2.0 ns Read Mode Clock to Data Out (tD) 4.5 ns Rev. B | Page 5 of 16 07051-003 07051-004 AD8372 ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Supply Voltage, V 5.5 V S other conditions above those indicated in the operational ENB1, ENB2, SDI1, SDI2, SDO1, SDO2, CLK1, DGDx − 0.5 V to CLK2, LCH1, LCH2 VS + 500 mV section of this specification is not implied. Exposure to absolute Input Voltage, VIPC1, VINC1, VIPC2, VINC2 AGDx − 0.5 V to maximum rating conditions for extended periods may affect VS + 500 mV device reliability. Internal Power Dissipation 1.4 W 1, 2 θ (Exposed Paddle Soldered Down) 34.6°C/W JA 2 θ (At Exposed Paddle) 3.6°C/W ESD CAUTION JC Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C 1 Still air. 2 All values are modeled using a standard 4-layer JEDEC test board with the pad soldered to the board and thermal vias in the board. Rev. B | Page 6 of 16 AD8372 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVS1 1 24 OPC1 PIN 1 LCH1 2 23 ONC1 INDICATOR SDI1 3 22 AGD1 CLK1 4 21 SDO1 AD8372 CLK2 5 20 SDO2 TOP VIEW SDI2 6 19 AGD2 (Not to Scale) LCH2 7 18 ONC2 DVS2 8 17 OPC2 NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO AGD1 AND AGD2. Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 DVS1 Digital Supply Pin for Channel 1 2 LCH1 Latch Input for Channel 1 3 SDI1 Serial Data Input for Channel 1 4 CLK1 Clock Input for Channel 1 5 CLK2 Clock Input for Channel 2 6 SDI2 Serial Data Input for Channel 2 7 LCH2 Serial Data Input for Channel 2 Latch Input for Channel 2 8 DVS2 Digital Supply Pin for Channel 2 9 DGD2 Digital Ground for Channel 2 10 INC2 Negative Input for Channel 2 11 IPC2 Positive Input for Channel 2 12 REF2 Reference Voltage for Channel 2 13 RXT2 External Bias Setting Resistor Connection for Channel 2 14 AGD2 Analog Ground for Channel 2 15 ENB2 Chip Enable Pin for Channel 2 16 AVS2 Analog Supply Pin for Channel 2 17 OPC2 Positive Output for Channel 2 18 ONC2 Negative Output for Channel 2 19 AGD2 Analog Ground for Channel 2 20 SDO2 Serial Data Output for Channel 2 21 SDO1 Serial Data Output for Channel 1 22 AGD1 Analog Ground for Channel 1 23 ONC1 Negative Output for Channel 1 24 OPC1 Positive Output for Channel 1 25 AVS1 Analog Supply Pin for Channel 1 26 ENB1 Chip Enable Pin for Channel 1 27 AGD1 Analog Ground for Channel 1 28 RXT1 External Bias Setting Resistor Connection for Channel 1 29 REF1 Reference Voltage for Channel 1 30 IPC1 Positive Input for Channel 1 31 INC1 Negative Input for Channel 1 32 DGD1 Digital Ground for Channel 1 EPAD Exposed Pad. The exposed pad should be connected to AGD1 and AGD2. Rev. B | Page 7 of 16 07051-002 9 32 DGD1 DGD2 INC2 10 31 INC1 IPC2 11 30 IPC1 REF2 12 29 REF1 RXT2 13 28 RXT1 AGD2 14 27 AGD1 ENB2 15 26 ENB1 AVS2 16 25 AVS1 AD8372 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, ZS = 150 Ω, ZL = 250 Ω, 1 V p-p differential output, both channels enabled, unless otherwise noted. 40 20 30 19 20 +25°C 18 10 +85°C –40°C 0 17 –10 16 –20 –30 15 0 10 203040 50 607080 90 1M 10M 100M 1G FREQUENCY (MHz) FREQUENCY (Hz) Figure 8. P1dB, Maximum Gain Figure 5. Gain vs. Frequency by Gain Code (All Codes), Differential In, Differential Out –60 180 9 8 160 –65 7 140 –70 120 6 –75 HD2 100 5 –80 80 4 –85 HD3 60 3 –90 40 2 –95 20 1 0 0 –100 0 50 100 150 200 250 300 0 1020 30 40506070 80 90 FREQUENCY (MHz) FREQUENCY (MHz) nd rd Figure 9. Input Equivalent Parallel Impedance Figure 6. 2 and 3 Harmonic Distortion 70 100 90 60 80 OIP2 – A = 32 V 50 70 OIP2 – A = 10 V 60 40 OIP2 – A = –9 V 50 30 40 OIP3 – A = 10 OIP3 – A = 32 V V 30 20 OIP3 – A = –9 V 20 10 10 0 0 0 10 2030 405060 7080 90 100 0 1020 30 40506070 80 90 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. CMRR vs. Frequency Figure 7. OIP2 and OIP3 Rev. B | Page 8 of 16 OIP2/OIP3 (dBm) HARMONIC DISTORTION (dBc) VOLTAGE GAIN (dB) 07051-007 07051-006 07051-005 RESISTANCE (Ω) CMRR (dB) OUTPUT REFERRED P1dB (dBm) CAPACITANCE (pF) 07051-010 07051-008 07051-009 AD8372 50 45 A = 0dB V 40 35 A = 10dB V 30 25 A = 20dB V 20 15 A = 32dB 10 V 5 0 20ns/DIV 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) Figure 11. Noise Figure vs. Frequency Figure 13. AD8372 Response to 6 dB Step Change in Gain (Gain Register Setting 36 to Setting 42); Falling Edge Shown is Serial Clock Input Edge 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 1M 10M 100M 1G FREQUENCY (Hz) Figure 12. Isolation, Input to Opposite Output at Maximum Gain (To calculate output to output gain, subtract 29 dB from this plot) Rev. B | Page 9 of 16 (dB) NOISE FIGURE (dB) 07051-013 07051-012 07051-011 AD8372 THEORY OF OPERATION The AD8372 is a dual differential variable gain amplifier. Each primarily to the use of differential signaling techniques to amplifier consists of a 150 Ω digitally controlled 6 dB attenuator cancel various distortion components in the device. In addition, followed by a 1 dB vernier and a fixed gain transconductance all ac characterization is done using differential signal paths. amplifier. Using this device with either the input or the output in a single- ended circuit significantly degrades the overall performance of The differential output on each amplifier consists of a pair of the AD8372. open-collector transistors. It is recommended that each open- collector output be biased to +5 V with a high value inductor. PASSIVE FILTER TECHNIQUES A 33 μH inductor, such as the Coilcraft® 1812LS-333XJL, is an The AD8372 has a 100 Ω differential input impedance. For excellent choice for this component. A 250 Ω resistor should be optimal performance, the differential output load should be placed across the differential outputs to provide a current-to- 250 Ω. When designing passive filters around the AD8372, voltage conversion and as a source impedance for passive these impedances must be taken into account. filtering, post AD8372. DIGITAL GAIN CONTROL The gain for each side is based on a 250 Ω differential load and The digital gain control interface consists of the following pins: varies as the R changes per the following equations: LOAD SDI, SDO, CLK, and LATCH. The interface is active when the Gain = 20log(R /250), for voltage gain LOAD LATCH pin is shifted low. Gain words are written into the Gain = 10log(RLOAD/250), for power gain AD8372 via the SDI pin, and read back from the SDO pin. The first bit clocked into the data input pin determines whether the The dependency of the gain on the load is due to the open- interface is in write or read mode. The second bit is a don’t care collector output stage that is biased using external chokes. The bit, while the remaining six bits program the gain. In read inductance of the chokes and the resistance of the load deter- mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB. mine the low frequency pole of the amplifier. The high frequency The gain can be programmed between −9 dB and 32 dB in 1 dB pole is set by the parasitic capacitance of the chokes and outputs steps. Timing details are given in Figure 2 and Figure 3. The in parallel with the output resistance. gain code is given in Table 2. The total supply current of 106 mA per side consists of 70 mA DRIVING ANALOG-TO-DIGITAL CONVERTERS for the combined outputs and about 36 mA through the power supply pins. Each side has an external resistor (REXT) to ground The AD8372 is designed with the intention of driving high to set the transconductance of the output stage. For optimum speed, high dynamic range ADCs. The circuit in Figure 14 distortion, 106 mA total current per side is recommended, represents a simplified front end of one-half of the AD8372 dual making the R value about 2.0 kΩ. Each side has a 2.4 V EXT VGA driving an AD9445 14-bit, 125 MHz analog-to-digital reference pin and that same common-mode voltage appears on converter (ADC). The input of the AD8372 is driven the inputs. This reference should be decoupled using a 0.1 μF differentially using a 1:3 impedance ratio transformer, which capacitor. The part can be powered down to less than 2.6 mA by also matches the 150 Ω input resistance to a 50 Ω source. The setting the ENB pin low for the appropriate side. open-collector outputs are biased through the 33 μH inductors and are ac-coupled from the 142 Ω load resistors that, in The noise figure of the AD8372 is 7.8 dB at maximum gain and parallel with the 2 kΩ input resistance of the ADC, provide a increases as the gain is reduced. The increase in noise figure is 250 Ω load for gain accuracy. equal to the reduction in gain. The ADC is ac-coupled from the 142 Ω resistors to negate a dc The linearity of the part measured at the output is first-order effect on the input common-mode voltage of the AD9445. independent of the gain setting. Including the series 33 Ω resistors improves the isolation of the Layout considerations should include minimizing capacitance AD8372 from the switching currents caused by the ADC input on the outputs by avoiding ground planes under the chokes, and sample and hold. The AD9445 represents a 2 kΩ differential equalizing the output line lengths for phase balance. load and requires a 2 V p-p signal when VREF = 1 V for a full- SINGLE-ENDED AND DIFFERENTIAL SIGNALS scale output. This circuit provides variable gain, isolation, and source matching for the AD9445. Using this circuit with the The AD8372 is designed to be used by applying differential AD8372 in a gain of 32 dB (maximum gain), an SFDR signals to the inputs and using the differential output drive of performance of 74.5 dBc is achieved at 85 MHz (see Figure 15). the device to drive the next device in the signal chain. The excellent distortion performance of the AD8372 is due Rev. B | Page 10 of 16 AD8372 5V 5V 33µH 142Ω 0.1µF 0.1µF 0.1µF 1:3 33Ω VIN+ ½ 14 AD9445 AD8372 14-BIT ADC 50Ω VGA VIN– 33Ω 0.1µF 0.1µF 0.1µF AC 33µH 142Ω 5V Figure 14. AD8372 Driving an AD9445 ADC 0 1 FUND: –1.053dBFS SNR: 58.12dBc –10 2ND: –74.55dBc SNRFS: 59.18dBc 3RD: –86.45dBc THD: –73.99dBc –20 4TH: –91.35dBc SINAD: 58.01dBc –30 5TH: –89.57dBc SFDR: 74.73dBc 6TH: –91.15dBc WO SPUR: –85.5dBc –40 NOISE FLOOR: –101.3dB –50 –60 2 –70 –80 3 5 6 4 –90 –100 –110 –120 –130 ENCODE: 105MHz FUND LEAK: 100 SAMPLES: 32768 HARM LEAK: 3 –140 ANALOG: 19.8766MHz DC LEAK: 6 –150 0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 FREQUENCY (MHz) Figure 15. 74.5 dBc SFDR Performance of the AD8372 Driving the AD9445 ADC Rev. B | Page 11 of 16 (dBc) CKL1 SD01 ENA1 07051-019 07051-018 AD8372 EVALUATION BOARD SCHEMATIC INC2 IPC1 INC1 IPC2 Figure 16. AD8372 Evaluation Board Schematic Rev. B | Page 12 of 16 AD8372 CHAR BD AGND AGND R11 R12 R15 H1-1 TBD R0603 0 H1-7 0 R0603 R0603 C21 50 OHMS C8 H1-15 0.1UF R47 1NF C0603 AGND AGND C0603 AGND 50 OHMS 0.1UF AGND TBD R31 R32 C0603 C17 R44 R0603 DGND DGND TBD TBD T2 R2 24.9_1% R0603 R0603 R0603 R9 1:3 2K W2 75 OHMS H1-3 R0603 R0603 100 OHMS 100 OHMS R29 R0603 R35 R0603 0 0 C6 75 OHMS R0603 AGND R16 113 0 AGND C0603 TBD R39 R40 C0603 0.1UF T4 C0603 1NF C27 3 4 0 TBD 10K 0.1UF OPC1 C0603 DGND R0603 R21 2 DGND R0603 R0603 C11 R10 1 6 AGND AGND H1-15 TBD H1-4 R18 SEC PRI 50 OHMS C0603 C0603 C16 R0603 R0603 C0603 0.1UF AGND H1-15 0 0.1UF 0.1UF 100 OHMS C7 C26 R36 C25 R30 C32 TBD ONC1 75 OHMS L1 R0603 R0603 C0603 AGND 0 113 33UH 100 OHMS C15 50 OHMS 1812 DGND C0603 L2 DGND 75 OHMS 33UH 0.1UF C0603 R8 R43 1812 C18 0.1UF DGND H1-5 AGND 24.9_1% R0603 32 31 30 29 28 27 26 25 R22 R0603 0 C5 0 R23 AGND TBD R0603 C0603 0 100 OHMS R0603 1 24 DGND DVS1 OPC1 DGND R7 2 23 LCH1 ONC1 H1-11 3 22 SDI1 AGD1 AGND 100 OHMS R0603 0 4 21 C4 CLK1 Z1 SDO1 SDO1 5 AD8372 20 CLK2 SDO2 SDO2 TBD C0603 6 19 SDI2 AGD2 AGND 100 OHMS 7 18 DGND LCH2 ONC2 DGND 8 17 R6 DVS2 OCP2 AGND R0603 100 OHMS H1-10 R46 C0603 R0603 R14 0 0 24.9_1% 0.1UF SDO1 C3 R0603 R25 R28 R0603 H1-6 R0603 C28 0 R0603 9 10 11 12 13 14 15 16 0 TBD R37 C10 100 OHMS C0603 R24 0 TBD DGND C0603 R0603 AGND DGND DGND 75 OHMS L4 113 AGND 50 OHMS 75 OHMS R5 AGND 33UH T3 L3 1812 C0603 3 4 H1-9 ONC2 R0603 33UH 0.1UF R26 2 0 C22 R13 1812 C29 TBD 1 6 C2 C24 0.1UF SEC PRI R0603 0.1UF H1-12 SDO2 TBD C0603 C19 R0603 AGND C0603 C0603 0 H1-15 R38 C9 0.1UF R27 C0603 C23 DGND TBD OPC2 DGND R41 R42 R0603 R0603 0.1UF C0603 H1-15 R4 0 C0603 AGND 113 0 0 AGND 100 OHMS AGND 50 OHMS H1-1 R0603 R0603 75 OHMS R0603 0.1UF 0 R45 C0603 C20 75 OHMS C14 C1 0.1UF R34 24.9_1% C0603 1NF R33 R0603 C0603 TBD T1 C12 1:3 TBD R17 R0603 R49 R0603 R1 AGND AGND DGND DGND R0603 2K C0603 H1-7 H1-13 AGND 10K R0603 AGND 1NF R0603 0 W1 50 OHMS AGND R3 50 OHMS 0 0.1UF AGND R0603 C0603 C13 R19 R20 VDD VSS R48 0 TES TLOOP TE STLOOP 0 TBD R0603 AGND DGND ORANGE R0603 RED R0603 AGND C33 C34 AGND P1 1 H1-13 AGND L6 3528 L5 P1 2 H1-3 H1-15 3528 TBD TBD P2 B11 H1-13 C1206 P1 3 C1206 10UF P2 A1 P2 A11 H1-13 P2 B1 AGND H1-4 10UF DGND AGND P2 B12 H1-14 H1-15 P2 A2 P2 A12 P2 B2 P1 4 AGND H1-1 H1-14 H1-1 H1-5 DGND P1 14 H1-1 P2 B13 H1-6 P2 A3 P2 A13 H1-6 P2 B3 H1-12 P1 5 H1-6 P1 15 P2 B14 H1-5 P2 A4 P2 A14 H1-5 P2 B4 H1-6 P1 6 H1-12 P1 16 P2 B15 H1-4 P2 A5 H1-9 P2 A15 H1-4 P2 B5 H1-9 P1 7 H1-11 P1 20 P1 17 P2 B16 H1-3 P1 8 P2 A6 H1-10 P2 A16 H1-3 P2 B6 H1-10 H1-10 P1 21 P1 18 P2 B17 H1-15 P2 A7 P2 A17 P2 B7 P1 9 H1-11 H1-15 H1-11 H1-9 P1 22 P1 19 P2 B18 H1-16 P2 A8 H1-12 P2 A18 H1-16 P2 B8 H1-12 P1 10 P1 23 P2 B19 P2 A9 H1-7 P2 A19 P2 B9 H1-7 P1 11 P1 24 P2 B20 AGND P2 A10 H1-8 P2 A20 P2 B10 H1-8 P1 12 H1-6 P1 25 AGND P1 13 H1-12 W8 W7 W6 W5 W4 W3 4 3 2 3 4 6 1 2 PRI SEC 1 6 SEC PRI DGD2 DGD1 INC2 INC1 IPC2 IPC1 REF2 REF1 RXT2 RXT1 ADG2 AGD1 AGND ENB2 ENB1 AVS2 AVS1 07051-014 AD8372 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP 3.25 4.75 EXPOSED VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 0.30 FUNCTION DESCRIPTIONS COPLANARITY 0.80 0.20 REF SECTION OF THIS DATA SHEET. 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 17. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Temperature Package Ordering 1 Model Range Package Description Option Quantity AD8372ACPZ-WP −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack CP-32-2 36 AD8372ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape CP-32-2 1,500 and Reel AD8372-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 13 of 16 011708-A AD8372 NOTES Rev. B | Page 14 of 16 AD8372 NOTES Rev. B | Page 15 of 16 AD8372 NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07051-0-6/11(B) Rev. B | Page 16 of 16