ANALOG DEVICES AD8370

LF to 750 MHz, Digitally Controlled VGA Data Sheet AD8370 FEATURES FUNCTIONAL BLOCK DIAGRAM Programmable low and high gain (<2 dB resolution) VCCI VCCO VCCO 3 11 6 Low range: −11 dB to +17 dB High range: 6 dB to 34 dB 4 PWUP BIAS CELL 5 VOCM Differential input and output ICOM 2 7 OCOM 200 Ω differential input 100 Ω differential output 1 8 INHI OPHI PRE OUTPUT TRANSCONDUCTANCE 7 dB noise figure @ maximum gain AMP AMP 16 9 INLO OPLO Two-tone IP3 of 35 dBm @ 70 MHz −3 dB bandwidth of 750 MHz ICOM 15 10 OCOM SHIFT REGISTER 40 dB precision gain range AND LATCHES Serial 8-bit digital interface AD8370 Wide input dynamic range 14 13 12 DATA CLCK LTCH Power-down feature Single 3 V to 5 V supply Figure 1. 70 40 CODE = LAST 7 BITS OF GAIN CODE APPLICATIONS (NO MSB) 60 30 Differential ADC drivers HIGH GAIN MODE IF sampling receivers 50 20 RF/IF gain stages LOW GAIN MODE Cable and video applications 40 10  GAIN  0.409 SAW filter interfacing  CODE HIGH GAIN MODE 30 0 Single-ended-to-differential conversion 20 –10 GENERAL DESCRIPTION  GAIN  0.059 10 –20  CODE The AD8370 is a low cost, digitally controlled, variable gain LOW GAIN MODE amplifier (VGA) that provides precision gain control, high IP3, 0 –30 0 1020 3040 50 60 70 80 90 100 110 120 130 and low noise figure. The excellent distortion performance and GAIN CODE wide bandwidth make the AD8370 a suitable gain control Figure 2. Gain vs. Gain Code at 70 MHz device for modern receiver designs. For wide input, dynamic range applications, the AD8370 provides Gain control of the AD8370 is through a serial 8-bit gain control two input ranges: high gain mode and low gain mode. A vernier, word. The MSB selects between the two gain ranges, and the 7-bit, transconductance (gm) stage provides 28 dB of gain range remaining 7 bits adjust the overall gain in precise linear gain steps. at better than 2 dB resolution and 22 dB of gain range at better than Fabricated on the ADI high speed XFCB process, the high 1 dB resolution. A second gain range, 17 dB higher than the first, bandwidth of the AD8370 provides high frequency and low can be selected to provide improved noise performance. distortion. The quiescent current of the AD8370 is 78 mA The AD8370 is powered on by applying the appropriate logic typically. The AD8370 amplifier comes in a compact, thermally level to the PWUP pin. When powered down, the AD8370 enhanced 16-lead TSSOP package and operates over the consumes less than 4 mA and offers excellent input to output temperature range of −40°C to +85°C. isolation. The gain setting is preserved when operating in a power-down mode. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. VOLTAGE GAIN (V/V) 03692-002 VOLTAGE GAIN (dB) 03692-001 AD8370 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Connections ...................................................................... 15 Applications ....................................................................................... 1 Gain Codes .................................................................................. 15 General Description ......................................................................... 1 Power-Up Feature ....................................................................... 15 Functional Block Diagram .............................................................. 1 Choosing Between Gain Ranges .............................................. 16 Revision History ............................................................................... 2 Layout and Operating Considerations .................................... 16 Specifications ..................................................................................... 3 Package Considerations ............................................................. 17 Absolute Maximum Ratings ............................................................ 5 Single-Ended-to-Differential Conversion ............................... 17 ESD Caution .................................................................................. 5 DC-Coupled Operation............................................................. 18 Pin Configuration and Function Descriptions ............................. 6 ADC Interfacing ......................................................................... 19 Typical Performance Characteristics ............................................. 7 3 V Operation ............................................................................. 20 Theory of Operation ...................................................................... 13 Evaluation Board and Software .................................................... 22 Block Architecture ...................................................................... 13 Appendix ......................................................................................... 25 Preamplifier ................................................................................. 13 Characterization Equipment..................................................... 25 Transconductance Stage ............................................................ 13 Composite Waveform Assumption .......................................... 25 Output Amplifier ........................................................................ 14 Definitions of Selected Parameters .......................................... 25 Digital Interface and Timing .................................................... 14 Outline Dimensions ....................................................................... 28 Applications ..................................................................................... 15 Ordering Guide .......................................................................... 28 REVISION HISTORY 12/11—Rev. A to Rev. B Changes to Slew Rate Parameters, Table 1 .................................... 3 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 7/05—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Figure 11 and Figure 15 ............................................... 8 Added Figure 12; Renumbered Sequentially ................................ 8 Added Figure 16; Renumbered Sequentially ................................ 9 Changes to Evaluation Board and Software Section .................. 22 Changes to Figure 60 ...................................................................... 23 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 1/04—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD8370 SPECIFICATIONS VS = 5 V, T = 25°C, ZS = 200 Ω, ZL = 100 Ω at gain code HG127, 70 MHz, 1 V p-p differential output, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V < 1 V p-p 750 MHz OUT Slew Rate Gain Code HG127, RL = 1 kΩ, AD8370 in compression 5.75 V/ns Gain Code LG127, RL = 1 kΩ, VOUT = 2 V p-p 3.5 V/ns INPUT STAGE Pins INHI and IHLO Maximum Input Gain Code LG2, 1 dB compression 3.2 V p-p Input Resistance Differential 200 Ω Common-Mode Input Range 3.2 V p-p CMRR Differential, f = 10 MHz, Gain Code LG127 77 dB Input Noise Spectral Density 1.9 nV/√Hz GAIN Maximum Voltage Gain High Gain Mode Gain Code = HG127 34 dB 52 V/V Low Gain Mode Gain Code = LG127 17 dB 7.4 V/V Minimum Voltage Gain High Gain Mode Gain Code = HG1 −8 dB 0.4 V/V Low Gain Mode Gain Code = LG1 −25 dB 0.06 V/V Gain Step Size High Gain Mode 0.408 (V/V)/Code Low Gain Mode 0.056 (V/V)/Code Gain Temperature Sensitivity Gain Code = HG127 –2 mdB/°C Step Response For 6 dB gain step, settled to 10% of final value 20 ns OUTPUT INTERFACE Pins OPHI and OPLO Output Voltage Swing R ≥ 1 kΩ (1 dB compression) 8.4 V p-p L Output Resistance Differential 95 Ω Output Differential Offset VINHI = VINLO, over all gain codes ±60 mV NOISE/HARMONIC PERFORMANCE 10 MHz Gain Flatness Within ±10 MHz of 10 MHz ±0.01 dB Noise Figure 7.2 dB 1 Second Harmonic V = 2 V p-p −77 dBc OUT 1 Third Harmonic V = 2 V p-p −77 dBc OUT Output IP3 35 dBm Output 1 dB Compression Point 17 dBm 70 MHz Gain Flatness Within ±10 MHz of 70 MHz ±0.02 dB Noise Figure 7.2 dB 1 Second Harmonic V = 2 V p-p −65 dBc OUT 1 Third Harmonic VOUT = 2 V p-p −62 dBc Output IP3 35 dBm Output 1 dB Compression Point 17 dBm Rev. B | Page 3 of 28 AD8370 Data Sheet Parameter Conditions Min Typ Max Unit 140 MHz Gain Flatness Within ±10 MHz of 140 MHz ±0.03 dB Noise Figure 7.2 dB 1 Second Harmonic V = 2 V p-p −54 dBc OUT 1 Third Harmonic V = 2 V p-p −50 dBc OUT Output IP3 33 dBm Output 1 dB Compression Point 17 dBm 190 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.03 dB Noise Figure 7.2 dB 1 Second Harmonic V = 2 V p-p −43 dBc OUT 1 Third Harmonic VOUT = 2 V p-p −43 dBc Output IP3 33 dBm Output 1 dB Compression Point 17 dBm 240 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB Noise Figure 7.4 dB 1 Second Harmonic VOUT = 2 V p-p –28 dBc 1 Third Harmonic VOUT = 2 V p-p –33 dBc Output IP3 32 dBm Output 1 dB Compression Point 17 dBm 380 MHz Gain Flatness Within ±10 MHz of 240 MHz ±0.04 dB Noise Figure 8.1 dB Output IP3 27 dBm Output 1 dB Compression Point 14 dBm POWER-INTERFACE 2 Supply Voltage 3.0 5.5 V 3 Quiescent Current PWUP High, GC = LG127, R = ∞, 4 seconds after 72.5 79 85.5 mA L power-on, thermal connection made to exposed paddle under device 4 vs. Temperature −40°C ≤ TA ≤ +85°C 105 mA Total Supply Current PWUP High, VOUT = 1 V p-p, ZL = 100 Ω reactive, 82 mA GC = LG127 (includes load current) Power-Down Current PWUP low 3.7 mA 4 vs. Temperature −40°C ≤T ≤ +85°C 5 mA A POWER-UP INTERFACE Pin PWUP 4 Power-Up Threshold Voltage to enable the device 1.8 V 4 Power-Down Threshold Voltage to disable the device 0.8 V PWUP Input Bias Current PWUP = 0 V 400 nA GAIN CONTROL INTERFACE Pins CLCK, DATA, and LTCH 4 VIH Voltage for a logic high 1.8 V 4 VIL Voltage for a logic low 0.8 V Input Bias Current 900 nA 1 Refer to Figure 22 for performance into a lighter load. 2 See the 3 V Operation section for more information. 3 Minimum and maximum specified limits for this parameter are guaranteed by production test. 4 Minimum or maximum specified limit for this parameter is a 6-sigma value and not guaranteed by production test. Rev. B | Page 4 of 28 Data Sheet AD8370 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage, V 5.5 V S rating only; functional operation of the device at these or any PWUP, DATA, CLCK, LTCH V + 500 mV S other conditions above those listed in the operational sections Differential Input Voltage, 2 V of this specification is not implied. Exposure to absolute VINHI – VINLO maximum rating conditions for extended periods may affect Common-Mode Input Voltage, VS + 500 mV (max), device reliability. VINHI or VINLO, with Respect to VICOM – 500 mV, ICOM or OCOM V – 500 mV (min) OCOM Internal Power Dissipation 575 mW θJA (Exposed Paddle Soldered Down) 30°C/W θJA (Exposed Paddle Not Soldered Down) 95°C/W θJC (At Exposed Paddle) 9°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature Range 235°C (Soldering 60 sec) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 5 of 28 AD8370 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INHI 1 16 INLO 2 15 ICOM ICOM 3 14 VCCI DATA AD8370 PWUP 4 13 CLCK TOP VIEW (Not to Scale) 5 12 VOCM LTCH 6 11 VCCO VCCO OCOM 7 10 OCOM OPHI 8 9 OPLO Figure 3.16-Lead TSSOP Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 INHI Balanced Differential Input. Internally biased. 2, 15, PADDLE ICOM Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad on the bottom of the device. 3 VCCI Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. 4 PWUP Power Enable Pin. Device is operational when PWUP is pulled high. 5 VOCM Common-Mode Output Voltage Pin. The midsupply ((VVCCO − VOCOM)/2) common-mode voltage is delivered to this pin for external bypassing for additional common-mode supply decoupling. This can be achieved with a bypass capacitor to ground. This pin is an output only and is not to be driven externally. 6, 11 VCCO Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. 7, 10 OCOM Output Common. Connect to a low impedance ground. 8 OPHI Balanced Differential Output. Biased to midsupply. 9 OPLO Balanced Differential Output. Biased to midsupply. 12 LTCH Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data in shift register is latched on the next high-going edge. 13 CLCK Serial Clock Input Pin. 14 DATA Serial Data Input Pin. 16 INLO Balanced Differential Input. Internally biased. Rev. B | Page 6 of 28 03692-003 Data Sheet AD8370 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, ZS = 200 Ω, ZL = 100 Ω, T = 25°C, unless otherwise noted. 40 70 40 HIGH GAIN CODES SHOWN WITH DASHED LINES CODE = LAST 7 BITS OF GAIN CODE HG127 (NO MSB) 35 60 30 HG77 30 HIGH GAIN MODE HG102 HG51 50 20 25 LG127 HG25 20 LOW GAIN MODE 40 10 ∆ GAIN LG90 ≅ 0.409 15 ∆ CODE HG18 HIGH GAIN MODE HG9 30 0 10 LG36 5 20 –10 HG3 0 ∆ GAIN ≅ 0.059 LG18 10 –20 LG9 ∆ CODE –5 LOW GAIN MODE LOW GAIN CODES SHOWN WITH SOLID LINES –10 0 –30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 10 100 1000 GAIN CODE FREQUENCY (MHz) Figure 4. Gain vs. Gain Code at 70 MHz Figure 7. Frequency Response vs. Gain Code 40 50 30 40 +25°C UNIT CONVERSION NOTE FOR HIGH GAIN MODE 100Ω LOAD: dBVrms = dBm–10dB 35 25 35 45 LOW GAIN MODE 30 20 30 40 +85°C 25 15 25 35 20 10 20 30 –40°C 15 5 15 25 SHADING INDICATES ±3σ FROM THE SHADING INDICATES ±3σ FROM THE 10 0 MEAN. DATA BASED ON 30 PARTS MEAN. DATA BASED ON 30 PARTS FROM TWO BATCH LOTS. FROM TWO BATCH LOTS. 10 20 –5 0 50 100 150 200 250 300 350 400 5 0 20 40 60 80 100 120 140 FREQUENCY (MHz) GAIN CODE Figure 5. Output Third-Order Intercept vs. Gain Code at 70 MHz Figure 8. Output Third-Order Intercept vs. Frequency at Maximum Gain 25 45 40 20 35 LG127 30 15 380MHz 25 LOW GAIN MODE 10 HG18 20 70MHz HG127 15 5 380MHz HIGH GAIN MODE 10 70MHz 0 5 0 100 200 300 400 500 600 0 20 40 60 80 100 120 140 FREQUENCY (MHz) GAIN CODE Figure 6. Noise Figure vs. Gain Code at 70 MHz Figure 9. Noise Figure vs. Frequency at Various Gains Rev. B | Page 7 of 28 OUTPUT IP3 (dBm) NOISE FIGURE (dB) VOLTAGE GAIN (V/V) 03692-006 03692-004 VOLTAGE GAIN (dB) OUTPUT IP3 (dBV rms) 03692-068 OUTPUT IP3 (dBm) +25°C NOISE FIGURE (dB) VOLTAGE GAIN (dB) 03692-009 03692-007 OUTPUT IP3 (dBm) –40°C, +85°C 03692-069 AD8370 Data Sheet 20 2.0 LOW GAIN MODE 100Ω LOAD 1.5 16 HIGH GAIN MODE 1.0 LOW GAIN MODE 12 1kΩ LOAD 0.5 HIGH GAIN MODE –40°C 8 0 4 +85°C –0.5 UNIT CONVERSION NOTE: 0 –1.0 FOR 100Ω LOAD: dBV rms = dBm–10dB FOR 1kΩ LOAD: dBV rms = dBm ERROR AT –40°C AND +85°C WITH RESPECT TO +25°C. –1.5 SHADING INDICATES ±3σ FROM THE MEAN. DATA –4 SHADING INDICATES ±3σ FROM THE BASED ON 30 PARTS FROM ONE BATCH LOT. MEAN. DATA BASED ON 30 PARTS –2.0 FROM TWO BATCH LOTS. –8 10 100 1000 0 20 40 60 80 100 120 140 FREQUENCY (MHz) GAIN CODE Figure 10. Output P1dB vs. Gain Code at 70 MHz Figure 13. Gain Error over Temperature vs. Frequency, RL = 100 Ω 0 –50 18 20 +25°C, 100Ω LOAD –10 –60 +85°C, 100Ω LOAD 16 18 –20 –70 HIGH GAIN MODE 16 14 –30 –80 UNIT CONVERSION NOTE: –40 –90 14 12 RE 100Ω LOAD: dBV rms = dBm – 10dB RE 1kΩ LOAD: dBV rms = dBm –50 –100 –40°C, 100Ω LOAD 12 10 +25°C, 1kΩ LOAD –60 –110 10 8 –70 –120 +85°C, 1kΩ LOAD LOW GAIN MODE –80 –130 8 6 SHADING INDICATES ±3σ FROM THE MEAN. DATA BASED ON 30 –90 –140 PARTS FROM TWO BATCH LOTS. –40°C, 1kΩ LOAD 0 20 40 60 80 100 120 140 6 4 0 50 100 150 200 250 300 350 400 GAIN CODE FREQUENCY (MHz) Figure 11. Two-Tone Output IMD3 vs. Gain Code at 70 MHz, Figure 14. Output P1dB vs. Frequency RL = 1 kΩ, V = 2 V p-p Composite Differential OUT 35 25 –50 –52 –54 30 20 –56 –58 25 15 HIGH GAIN –60 MODE –62 20 10 –64 –66 15 5 –68 LOW GAIN –40°C MODE –70 10 0 –72 –74 +25°C 5 –5 –76 –78 +85°C 0 –10 –80 –82 –5 –15 –84 0 50 100 150 200 250 300 350 400 0 20 40 60 80 100 120 140 GAIN CODE FREQUENCY (MHz) Figure 15. Two-Tone Output IMD3 vs. Frequency at Maximum Gain, Figure 12. Output Third-Order Intercept vs. Gain Code at 70 MHz, R = 1 kΩ, V = 2 V p-p Composite Differential RL = 1 kΩ, VOUT = 2 V p-p Composite Differential L OUT Rev. B | Page 8 of 28 OUTPUT P1dB (dB) LOW GAIN MODE OUTPUT IMD (dBc) OUTPUT IP3 (dBm) 03692-010 HIGH GAIN MODE OUTPUT IMD (dBc) OUTPUT IP3 (dBV rms) 03692-005 03692-011 OUTPUT P1dB (dBm) –40°C, +85°C GAIN ERROR (dB) OUTPUT IMD (dBc) 03692-012 03692-014 OUTPUT P1dB (dBm) +25°C 03692-013 Data Sheet AD8370 90 34 24 32 22 120 60 1GHz +85°C 30 20 28 18 150 30 –40°C 26 16 +25°C S 22 24 14 5MHz 180 0 22 12 20 10 330 210 18 8 S 11 16 6 240 300 14 4 0 50 100 150 200 250 300 350 400 270 FREQUENCY (MHz) Figure 16. Output Third-Order Intercept vs. Frequency at Maximum Gain, Figure 19. Input and Output Reflection Coefficients, S11 and S22, RL = 1 kΩ, VOUT = 2 V p-p Composite Differential ZO = 100 Ω Differential 250 100 2.0 16 DIFFERENT GAIN CODES REPRESENTED 1.5 R+jX FORMAT 200 50 1.0 0.5 150 0 –40°C 0 +85°C 100 –50 –0.5 –1.0 50 –100 ERROR AT –40°C AND +85°C WITH RESPECT TO +25°C. –1.5 SHADING INDICATES ±3σ FROM THE MEAN. DATA BASED ON 30 PARTS FROM ONE BATCH LOT. –2.0 0 –150 0 100 200 300 400 500 600 700 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. Gain Error over Temperature vs. Frequency, RL = 1 kΩ Figure 20. Input Resistance and Reactance vs. Frequency 0 0 LOW GAIN R = 1kΩ L –10 –10 HIGH GAIN R = 1kΩ L –20 –20 –30 LOW GAIN, R = 1kΩ –30 HIGH GAIN R = 100Ω L L LOW GAIN R = 100Ω L –40 –40 HIGH GAIN, R = 100Ω LOW GAIN, R = 100Ω L L –50 –50 –60 –60 –70 –70 –80 –80 HIGH GAIN, R = 1kΩ L –90 –90 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 GAIN CODE GAIN CODE Figure 18. Second-Order Harmonic Distortion vs. Gain Code at 70 MHz, Figure 21. Third-Order Harmonic Distortion vs. Gain Code at 70 MHz, VOUT = 2 V p-p Differential VOUT = 2 V p-p Differential Rev. B | Page 9 of 28 OUTPUT IP3 (dBm) HARMONIC DISTORTION (dBc) GAIN ERROR (dB) 03692-016 03692-015 OUTPUT IP3 (dBV rms) 03692-008 HARMONIC DISTORTION (dBc) RESISTANCE (Ω) 03692-017 03692-019 REACTANCE (jΩ) 03692-018 AD8370 Data Sheet 0 120 110 –10 HD R = 100Ω 2 L 100 –20 HD R = 100Ω 90 3 L –30 80 –40 70 –50 HD R = 1kΩ 60 3 L –60 50 –70 40 HD R = 1kΩ 2 L –80 30 –90 20 0 50 100 150 200 250 300 350 400 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. Harmonic Distortion vs. Frequency at Maximum Gain, Figure 25. Power Supply Rejection Ratio vs. Frequency at Maximum Gain V = 2 V p-p Composite Differential OUT 120 80 0 FORWARD TRANSMISSION, HG0 –20 100 60 FORWARD TRANSMISSION, LG0 –40 80 40 –60 60 20 40 0 –80 16 DIFFERENT GAIN 20 –20 –100 FORWARD TRANSMISSION, PWUP LOW CODES REPRESENTED R+jX FORMAT REVERSE TRANSMISSION, HG127 0 –40 –120 0 100 200 300 400 500 600 700 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. Output Resistance and Reactance vs. Frequency Figure 26. Various Forms of Isolation vs. Frequency 860 1400 R = 1kΩ L 840 1300 HIGH GAIN MODE 820 1200 800 1100 780 1000 R = 100Ω L 760 900 LOW GAIN MODE 740 800 720 700 700 600 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 100 200 300 400 500 600 700 800 900 GAIN CODE FREQUENCY (MHz) Figure 24. Group Delay vs. Gain Code at 70 MHz Figure 27. Group Delay vs. Frequency at Maximum Gain Rev. B | Page 10 of 28 GROUP DELAY (ps) RESISTANCE (Ω) HARMONIC DISTORTION (dBc) 03692-020 03692-022 REACTANCE (jΩ) 03692-021 GROUP DELAY (ps) ISOLATION (dB) PSRR (dB) 03692-025 03692-024 03692-023 Data Sheet AD8370 80 DIFFERENTIAL OUTPUT (50mV/DIV) 70 LG32, LG127 60 ZERO HG32, HG127 50 40 PWUP (2V/DIV) 30 GAIN CODE HG127 20 10 GND INPUT = –30dBm, 70MHz 100 AVERAGES 0 10 100 1000 FREQUENCY (MHz) TIME (40ns/DIV) Figure 28. Common-Mode Rejection Ratio vs. Frequency Figure 31. PWUP Time Domain Response 12 DIFFERENTIAL OUTPUT (10mV/DIV) 10 ZERO 8 6dB GAIN STEP (HG36 TO LG127) LG127 6 LTCH (2V/DIV) 4 HG18 2 HG127 GND INPUT = –30dBm, 70MHz NO AVERAGING 0 10 110 210 310 410 510 610 FREQUENCY (MHz) TIME (20ns/DIV) Figure 32. Gain Step Time Domain Response Figure 29. Input Referred Noise Spectral Density vs. Frequency at Various Gains V DIFFERENTIAL OUT V OPHI V OPLO DIFFERENTIAL V OUT DIFFERENTIAL V IN GND GND TIME (2ns/DIV) TIME (2ns/DIV) Figure 30. DC-Coupled Large Signal Pulse Response Figure 33. Overdrive Recovery Rev. B | Page 11 of 28 VOLTAGE (600mV/DIV) NOISE SPECTRAL DENSITY (nV/ Hz) CMRR (dB) 03692-028 03692-027 03692-026 VOLTAGE (1V/DIV) 03692-030 03692-029 03692-031 AD8370 Data Sheet 85 2.75 80 2.70 +85°C 75 2.65 +25°C 70 2.60 LOW GAIN 65 2.55 HIGH GAIN 60 2.50 –40°C 55 2.45 LOW GAIN MODE HIGH GAIN MODE 50 2.40 0 16 32 48 64 80 96 112 128 0 32 64 96 0 32 64 96 128 GAIN CODE GAIN CODE Figure 34. Supply Current vs. Gain Code Figure 36. Common-Mode Output Voltage vs. Gain Code at Various Temperatures 35 MEAN: 51.9 σ: 0.518 30 25 DATA FROM 136 PARTS FROM ONE BATCH LOT 20 15 10 5 0 50 51 52 53 54 55 GAIN (V/V) Figure 35. Distribution of Voltage Gain, HG127, 70 MHz, RL = 100 Ω Rev. B | Page 12 of 28 COUNT SUPPLY CURRENT (mA) 03692-032 03692-033 V (V) CM 03692-034 Data Sheet AD8370 THEORY OF OPERATION set by passive components. See Figure 38 for a simplified The AD8370 is a low cost, digitally controlled, fine adjustment schematic of the input interface. variable gain amplifier (VGA) that provides both high IP3 and low noise figure. The AD8370 is fabricated on an ADI proprietary 1mA high performance 25 GHz silicon bipolar process. The –3 dB bandwidth is approximately 750 MHz throughout the variable gain range. The typical quiescent current of the AD8370 is 78 mA. A power-down feature reduces the current to less than INHI/INLO 4 mA. The input impedance is approximately 200 Ω differential, 2kΩ VCC/2 and the output impedance is approximately 100 Ω differential to be compatible with saw filters and matching networks used in intermediate frequency (IF) radio applications. Because there is no feedback between the input and output and stages within the amplifier, the input amplifier is isolated from variations in output loading and from subsequent impedance changes, and 1mA excellent input to output isolation is realized. Excellent distortion Figure 38. INHI/INLO Simplified Schematic performance and wide bandwidth make the AD8370 a suitable gain control device for modern differential receiver designs. The TRANSCONDUCTANCE STAGE AD8370 differential input and output configuration is ideally The digitally controlled g section has 42 dB of controllable suited to fully differential signal chain circuit designs, although m it can be adapted to single-ended system applications, if required. gain and makes gain adjustments within each gain range. The step size resolution ranges from a fine ~ 0.07 dB up to a coarse BLOCK ARCHITECTURE 6 dB per bit, depending on the gain code. As shown in Figure 39, The three basic building blocks of the AD8370 are a high/low of the 42 dB total range, 28 dB has resolution of better than gain selectable input preamplifier, a digitally controlled 2 dB, and 22 dB has resolution of better than 1 dB. transconductance (g ) block, and a fixed gain output stage. m Figure 39 shows typical input levels that can be applied to this VCCI VCCO VCCO amplifier at different gain settings. The maximum input was 3 11 6 determined by finding the 1 dB compression or expansion point 4 5 PWUP BIAS CELL VOCM of the VOUT/VSOURCE gain. Note that this is not VOUT/VIN. In this 2 ICOM 7 OCOM way, the change in the input impedance of the device is also INHI 1 8 OPHI taken into account. PRE OUTPUT TRANSCONDUCTANCE AMP AMP 16 9 3.2 INLO OPLO ICOM 15 10 OCOM 2.8 <0.5dB SHIFT REGISTER RES LOW GAIN AND LATCHES <1dB 2.4 AD8370 RES HIGH GAIN 34dB 14 13 12 GAIN DATA CLCK LTCH 2.0 17dB <0.5dB GAIN Figure 37. Functional Block Diagram <2dB RESOLUTION 1.6 RES 12dB PREAMPLIFIER 1.2 GAIN <1dB 0.1dB GAIN RES There are two selectable input preamplifiers. Selection is made 6dB 0.8 GAIN <2dB by the most significant bit (MSB) of the serial gain control data- –5dB GAIN RES 0.4 –8dB GAIN word. In the high gain mode, the overall device gain is 7.1 V/V –11dB GAIN (17 dB) above the low gain setting. The two preamplifiers give –25dB GAIN 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 the AD8370 the ability to accommodate a wide range of input V [V peak] (V) SOURCE amplitudes. The overlap between the two gain ranges allows the user some flexibility based on noise and distortion demands. Figure 39. Gain Resolution and Nominal Input and Output Range over the Gain Range See the Choosing Between Gain Ranges section for more information. The input impedance is approximately 200 Ω differential, regardless of which preamplifier is selected. Note that the input impedance is formed by using active circuit elements and is not Rev. B | Page 13 of 28 03692-035 V [V peak] (V) OUT 03692-036 03692-037 AD8370 Data Sheet Table 4. Serial Programming Timing Parameters OUTPUT AMPLIFIER Parameter Min Unit The output impedance is approximately 100 Ω differential and, Clock Pulse Width (TPW) 25 ns like the input preamplifier, this impedance is formed using Clock Period (TCK) 50 ns active circuit elements. See Figure 40 for a simplified schematic Setup Time Data vs. Clock (T ) 10 ns DS of the output interface. Setup Time Latch vs. Clock (T ) 20 ns ES Hold Time Latch vs. Clock (T ) 10 ns EH 10µA OPHI/OPLO 740Ω VCC/2 CLCK/DATA/LTCH/PWUP Figure 42. Simplified Circuit for Digital Inputs Figure 40. OPHI/OPLO Simplified Circuit The gain of the output amplifier, and thus the AD8370 as a whole, is load dependent. The following equation can be used to predict the gain deviation of the AD8370 from that at 100 Ω as the load is varied. VOCM 75Ω 1.98 VCC/2 GainDeviation= 98 1+ R LOAD For example, if R is 1 kΩ, the gain is a factor of 1.80 (5.12 dB) LOAD above that at 100 Ω, all other things being equal. If RLOAD is 50 Figure 43. Simplified Circuit for VOCM Output Ω, the gain is a factor of 0.669 (3.49 dB) below that at 100 Ω. DIGITAL INTERFACE AND TIMING The digital control port uses a standard TTL interface. The 8-bit control word is read in a serial fashion when the LTCH pin is held low. The levels presented to the DATA pin are read on each rising edge of the CLCK signal. Figure 41 illustrates the timing diagram for the control interface. Minimum values for timing parameters are presented in Table 4. Figure 42 is a simplified schematic of the digital input pins. T DS DATA MSB MSB-1 MSB-2 MSB-3 LSB+3 LSB+2 LSB+1 LSB (PIN 14) T CK T PW CLCK (PIN 13) T EH T ES LTCH (PIN 12) Figure 41. Digital Timing Diagram Rev. B | Page 14 of 28 03692-038 03692-039 03692-040 03692-041 Data Sheet AD8370 APPLICATIONS BASIC CONNECTIONS GAIN CODES Figure 44 shows the minimum connections required for basic The AD8370’s two gain ranges are referred to as high gain (HG) operation of the AD8370. Supply voltages between 3.0 V and and low gain (LG). Within each range, there are 128 possible 5.5 V are allowed. The supply to the VCCO and VCCI pins gain codes. Therefore, the minimum gain in the low gain range should be decoupled with at least one low inductance, surface- is given by the nomenclature LG0 whereas the maximum gain mount ceramic capacitor of 0.1 μF placed as close as possible to in that range is given by LG127. The same is true for the high the device. gain range. Both LG0 and HG0 essentially turn off the variable transconductance stage, and thus no output is available with SERIAL CONTROL INTERFACE these codes (see Figure 26). 1nF 1nF The theoretical linear voltage gain can be expressed with respect R S 16 15 14 13 12 11 10 9 to the gain code as 2 A = GainCode Vernier (1 + (PreGain − 1) MSB) V BALANCED BALANCED R SOURCE L AD8370 LOAD where: R S AV is the linear voltage gain. 1 23 4 5 67 8 2 GainCode is the digital gain control word minus the MSB 1nF 1nF 1nF (the final 7 bits). 100pF 100pF 0.1F 0.1F Vernier = 0.055744 V/V FERRITE FERRITE PreGain = 7.079458 V/V BEAD BEAD +V (3.0V TO 5.0V) S MSB is the most significant bit of the 8-bit gain control word. Figure 44. Basic Connections The MSB sets the device in either high gain mode (MSB = 1) or low gain mode (MSB = 0). The AD8370 is designed to be used in differential signal chains. Differential signaling allows improved even-order harmonic For example, a gain control word of HG45 (or 10101101 binary) cancellation and better common-mode immunity than can be results in a theoretical linear voltage gain of 17.76 V/V, achieved using a single-ended design. To fully exploit these calculated as benefits, it is necessary to drive and load the device in a balanced manner. This requires some care to ensure that the 45 × 0.055744 × (1 + (7.079458 − 1) × 1) common-mode impedance values presented to each set of Increments or decrements in gain within either gain range are inputs and outputs are balanced. Driving the device with an simply a matter of operating on the GainCode. Six –dB gain unbalanced source can degrade the common-mode rejection steps, which are equivalent to doubling or halving the linear ratio. Loading the device with an unbalanced load can cause voltage gain, are accomplished by doubling or halving the degradation to even-order harmonic distortion and premature GainCode. output compression. In general, optimum designs are fully balanced, although the AD8370 still provides impressive When power is first applied to the AD8370, the device is performance when used in an unbalanced environment. programmed to code LG0 to avoid overdriving the circuitry following it. The AD8370 is a fine adjustment, VGA. The gain control transfer function is linear in voltage gain. On a decibel scale, POWER-UP FEATURE this results in the logarithmic transfer functions shown in The power-up feature does not affect the GainCode, and the Figure 4. At the low end of the gain transfer function, the slope gain setting is preserved when in power-down mode. Powering is steep, providing a rather coarse control function. At the high down the AD8370 (bringing PWUP low while power is still end of the gain control range, the decibel step size decreases, applied to the device) does not erase or change the GainCode allowing precise gain adjustment. from the AD8370, and the same gain code is in place when the device is powered up, that is, when PWUP is brought high again. Removing power from the device all together and reapplying, however, reprograms to LG0. Rev. B | Page 15 of 28 INHI INLO ICOM ICOM VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM OPHI OPLO 03692-042 AD8370 Data Sheet gain is increased beyond this point, which explains the knee in CHOOSING BETWEEN GAIN RANGES the OIP3 curve. The IIP3 curve has a knee for the same reason; There is some overlap between the two gain ranges; users can however, as the gain is increased beyond the knee, the IIP3 choose which one is most appropriate for their needs. When starts to decrease rather than increase. This is because in this deciding which preamp to use, consider resolution, noise, region OIP3 is constant, therefore the higher the gain, the lower linearity, and spurious-free dynamic range (SFDR). The most the IIP3. The two gain ranges have equal SFDR at important points to keep in mind are approximately 13 dB power gain. • The low gain range has better gain resolution. LAYOUT AND OPERATING CONSIDERATIONS • The high gain range has a better noise figure. Each input and output pin of the AD8370 presents either a • The high gain range has better linearity and SFDR at 100 Ω or 50 Ω impedance relative to their respective ac grounds. higher gains. To ensure that signal integrity is not seriously impaired by the printed circuit board, the relevant connection traces should • Conversely, the low gain range has higher SFDR at lower provide an appropriate characteristic impedance to the ground gains. plane. This can be achieved through proper layout. Figure 45 provides a summary of noise, OIP3, IIP3, and SFDR When laying out an RF trace with a controlled impedance, as a function of device power gain. SFDR is defined as consider the following: 2 SFDR= (IIP3− NF− N ) S • Space the ground plane to either side of the signal trace at 3 least three line-widths away to ensure that a microstrip where: (vertical dielectric) line is formed, rather than a coplanar (lateral dielectric) waveguide. IIP3 is the input third-order intercept point, the output • Ensure that the width of the microstrip line is constant and intercept point in dBm minus the gain in dB. that there are as few discontinuities as possible, such as NF is the noise figure in dB. component pads, along the length of the line. Width variations cause impedance discontinuities in the line and N is source resistor noise, –174 dBm for a 1 Hz bandwidth at S may result in unwanted reflections. 300°K (27°C). • Do not use silkscreen over the signal line because it alters −23 In general, NS = 10 log10(kTB), where k = 1.374 ×10 , T is the the line impedance. temperature in degrees Kelvin, and B is the noise bandwidth in Keep the length of the input and output connection lines as Hertz. short as possible. 50 180 Figure 46 shows the cross section of a PC board, and Table 5 NF LOW GAIN 40 170 OIP3 HIGH GAIN show the dimensions that provide a 100 Ω line impedance for OIP3 LOW GAIN FR-4 board material with εr = 4.6. 30 160 IIP3 LOW GAIN Table 5. 20 150 IIP3 HIGH GAIN 100 Ω 50 Ω 10 140 W 22 mils 13 mils NF HIGH GAIN H 53 mils 8 mils 0 130 T 2 mils 2 mils –10 120 SFDR LOW GAIN –20 110 SFDR HIGH GAIN 3W W 3W –30 100 T –30 –20 –10 0 10 20 30 40 POWER GAIN (dB) E H R Figure 45. OIP3, IIP3, NF, and SFDR Variation with Gain As the gain increases, the input amplitude required to deliver Figure 46. Cross-Sectional View of a PC Board the same output amplitude is reduced. This results in less It possible to approximate a 100 Ω trace on a board designed distortion at the input stage, and therefore the OIP3 increases. with the 50 Ω dimensions above by removing the ground plane At some point, the distortion of the input stage becomes small within 3 line-widths of the area directly below the trace. enough such that the nonlinearity of the output stage becomes dominant. The OIP3 does not improve significantly because the Rev. B | Page 16 of 28 NOISE FIGURE (dB); OIP3 AND IIP3 (dBm) SFDR (dB) 03692-043 03692-044 Data Sheet AD8370 1 nF capacitors for C presents a capacitive reactance of AC The AD8370 contains both digital and analog sections. Care −j1.6 Ω on each input node at 100 MHz. This attenuates the should be taken to ensure that the digital and analog sections applied input voltage by 0.003 dB. If 10 pF capacitors had been are adequately isolated on the PC board. The use of separate selected, the voltage delivered to the input would be reduced ground planes for each section connected at only one point via by 2.1 dB when operating with a 200 Ω source impedance. a ferrite bead inductor ensures that the digital pulses do not adversely affect the analog section of the AD8370. 0.5 Due to the nature of the AD8370’s circuit design, care must be taken to minimize parasitic capacitance on the input and output. HIGH GAIN MODE (GAIN CODE HG255) 0 The AD8370 could become unstable with more than a few pF of shunt capacitance on each input. Using resistors in series with input pins is recommended under conditions of high source capacitance. –0.5 LOW GAIN MODE High transient and noise levels on the power supply, ground, (GAIN CODE LG127) and digital inputs can, under some circumstances, reprogram the –1.0 AD8370 to an unintended gain code. This further reinforces the 0 100 200 300 400 500 need for proper supply bypassing and decoupling. The user FREQUENCY (MHz) should also be aware that probing the AD8370 and associated Figure 48. Differential Output Balance for a Single-Ended Input Drive at Maximum Gain (R = 1 kΩ, C = 10 nF) L AC circuitry during circuit debug may also induce the same effect. Figure 48 illustrates the differential balance at the output for a PACKAGE CONSIDERATIONS single-ended input drive for multiple gain codes. The differential The package of the AD8370 is a compact, thermally enhanced balance is better than 0.5 dB for signal frequencies less than TSSOP 16-lead design. A large exposed paddle on the bottom of 250 MHz. Figure 49 depicts the differential balance over the the device provides both a thermal benefit and a low inductance entire gain range at 10 MHz. The balance is degraded for lower path to ground for the circuit. To make proper use of this pack- gain settings because the finite common gain allows some of the aging feature, the PCB needs to make contact directly under the input signal applied to INHI to pass directly through to the device, connected to an ac/dc common ground reference with OPLO pin. At higher gain settings, the differential gain dominates as many vias as possible to lower the inductance and thermal and balance is restored. impedance. 0.6 LOW GAIN MODE HIGH GAIN MODE SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION 0.5 SERIAL CONTROL INTERFACE C C AC AC 0.4 R S 16 15 14 13 12 11 10 9 0.3 SINGLE- ENDED SOURCE 0.2 R L AD8370 0.1 1 2 3 4 5 6 7 8 0 0 32 64 96 0 32 64 96 128 C AC C AC GAIN CODE 1nF 0.1µF 0.1µF Figure 49. Differential Output Balance at 10 MHz for a Single-Ended Drive vs. +V S Gain Code (R = 1 kΩ, C = 10 nF) L AC Figure 47. Single-Ended-to-Differential Conversion Even though the amplifier is no longer being driven in a balanced manner, the distortion performance remains adequate for most The AD8370 is primarily designed for differential signal inter- applications. Figure 50 illustrates the harmonic distortion facing. The device can be used for single-ended-to-differential performance of the circuit in Figure 47 over the entire gain range. conversion simply by terminating the unused input to ground using a capacitor as depicted in Figure 47. The ac coupling capacitors should be selected such that their reactance is negligible at the frequency of operation. For example, using Rev. B | Page 17 of 28 INHI INLO ICOM ICOM VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM OPHI OPLO 03692-045 DIFFERENTIAL BALANCE (dB) DIFFERENTIAL BALANCE (dB) 03692-047 03692-046 AD8370 Data Sheet SERIAL CONTROL If the amplifier is driven in single-ended mode, the input INTERFACE V OCM impedance varies depending on the value of the resistor used to terminate the other input as 499Ω 100Ω 16 15 14 13 12 11 10 9 +5V RinSE = RinDIFF + RTERM 499Ω where RTERM is the termination resistor connected to the other R T R input. L AD8138 AD8370 –40 499Ω 1 2 3 4 5 6 7 8 R S –50 R T 2 499Ω 100Ω V OCM 1nF 1nF –60 +5V HD2 HD2 0.1µF –70 SINGLE-ENDED GROUND REFERENCED SOURCE –80 Figure 52. DC Coupling the AD8370. The AD8138 is used as a unity-gain level HD3 HD3 shifting amplifier to lift the common-mode level of the source to midsupply. –90 The AD8370 is also a dc accurate VGA. The common-mode dc LOW GAIN MODE HIGH GAIN MODE voltage present at the output pins is internally set to midsupply –100 0 32 64 96 0 32 64 96 128 using what is essentially a buffered resistive divider network GAIN CODE connected between the positive supply rail and the common Figure 50. Harmonic Distortion of the Circuit in Figure 47 (ground) pins. The input pins are at a slightly higher dc potential, typically 250 mV to 550 mV above the output pins, depending DC-COUPLED OPERATION on gain setting. In a typical single-supply application, it is –2.5V necessary to raise the common-mode reference level of the SERIAL CONTROL INTERFACE 0V 1nF source and load to roughly midsupply to maintain symmetric swing and to avoid sinking or sourcing strong bias currents R T from the input and output pins. It is possible to use balanced R S 16 15 14 13 12 11 10 9 dual supplies to allow ground referenced source and load, as SINGLE- shown in Figure 51. By connecting the VOCM pin and unused ENDED GROUND input to ground, the input and output common-mode potentials REFERENCED R L AD8370 SOURCE are forced to virtual ground. This allows direct coupling of ground referenced source and loads. The initial differential input offset is typically only a few 100 µV. Over temperature, 1 2 3 4 5 6 7 8 the input offset could be as high as a few tens of mVs. If precise 0V dc accuracy is needed over temperature and time, it may be –2.5V 1nF necessary to periodically measure the input offset and to apply 0.1µF +2.5V the necessary opposing offset to the unused differential input, 0.1µF canceling the resulting output offset. To address situations where dual supplies are not convenient, a Figure 51. DC Coupling the AD8370. Dual supplies are used to set the input and output common-mode levels to 0 V. second option is presented in Figure 52. The AD8138 differential amplifier is used to translate the common-mode level of the driving source to midsupply, which allows dc accurate performance with a ground-referenced source without the need for dual supplies. The bandwidth of the solution in Figure 52 is limited by the gain-bandwidth product of the AD8138. The normalized frequency response of both implementations is shown in Figure 53. Rev. B | Page 18 of 28 HARMONIC DISTORTION (dBc) INHI INLO ICOM ICOM VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM OPHI OPLO 03692-048 03692-049 V OCM INHI INLO ICOM ICOM VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM OPHI OPLO 03692-050 Data Sheet AD8370 10 Often it is wise to include input and output parasitic suppression 8 resistors, R and R . Parasitic suppressing resistors help to IP OP 6 prevent resonant effects that occur as a result of internal bond- AD8370 WITH AD8138 SINGLE 4 wire inductance, pad to substrate capacitance, and stray +5V SUPPLY capacitance of the printed circuit board trace artwork. If 2 omitted, undesirable settling characteristics may be observed. 0 Typically, only 10 Ω to 25 Ω of series resistance is all that is –2 needed to help dampen resonant effects. Considering that most AD8370 USING DUAL –4 ADCs present a relatively high input impedance, very little ±2.5V SUPPLY –6 signal is lost across the R and R series resistors. IP OP –8 Depending on the input impedance presented by the input –10 system of the ADC, it may be desirable to terminate the ADC 1 10 100 1k 10k 100k 1M 10M 100M 1G input down to a lower impedance by using a terminating FREQUENCY (Hz) resistor, RT. The high frequency response of the AD8370 Figure 53. Normalized Frequency Response of the Two Solutions in Figure 51 and Figure 52 exhibits greater peaking when driving very light loads. In addition, the terminating resistor helps to better define the ADC INTERFACING input impedance at the ADC input. Any part-to-part variability Although the AD8370 is designed to provide a 100 Ω output of ADC input impedance is reduced when shunting down the source impedance, the device is capable of driving a variety ADC inputs by using a moderate tolerance terminating resistor of loads while maintaining reasonable gain and distortion (typically a 1% value is acceptable). performance. A common application for the AD8370 is ADC After defining reasonable values for coupling capacitors, driving in IF sampling receivers and broadband wide dynamic suppressing resistors, and the terminating resistor, it is time to range digitizers. The wide gain adjustment range allows the use design the intermediate filter network. The example in of lower resolution ADCs. Figure 54 illustrates a typical ADC Figure 54 suggests a second-order, low-pass filter network interface network. comprised of series inductors and a shunt capacitor. The order R C Z R OP AC S IP and type of filter network used depends on the desired high frequency rejection required for the ADC interface, as well as V AD8370 IN on pass-band ripple and group delay. In some situations, the Z R P T 100Ω Z ADC IN signal spectra may already be sufficiently band-limited such V IN that no additional filter network is necessary, in which case ZS would simply be a short and ZP would be an open. In other R C Z R V OCM OP AC S IP situations, it may be necessary to have a rather high-order antialiasing filter to help minimize unwanted high frequency Figure 54. Generic ADC Interface spectra from being aliased down into the first Nyquist zone of the ADC. Many factors need to be considered before defining component values used in the interface network, such as the desired frequency To properly design the filter network, it is necessary to consider range of operation, the input swing, and input impedance of the the overall source and load impedance presented by the AD8370 ADC. AC coupling capacitors, CAC, should be used to block any and ADC input, including the additional resistive contribution potential dc offsets present at the AD8370 outputs, which would of suppression and terminating resistors. The filter design can otherwise consume the available low-end range of the ADC. then be handled by using a single-ended equivalent circuit, as The C capacitors should be large enough so that they present AC shown in Figure 55. A variety of references that address filter negligible reactance over the intended frequency range of synthesis are available. Most provide tables for various filter operation. The VOCM pin may serve as an external reference types and orders, indicating the normalized inductor and for ADCs that do not include an on-board reference. In either capacitor values for a 1 Hz cutoff frequency and 1 Ω load. After case, it is suggested that the VOCM pin be decoupled to ground scaling the normalized prototype element values by the actual through a moderately large bypassing capacitor (1 nF to 10 nF) desired cut-off frequency and load impedance, it is simply a to help minimize wideband noise pick-up. matter of splitting series element reactances in half to realize the final balanced filter network component values. Rev. B | Page 19 of 28 NORMALIZED RESPONSE (dB) 03692-051 03692-052 AD8370 Data Sheet SOURCE LOAD A complete design example is shown in Figure 58. The AD8370 R Z S S is configured for single-ended-to-differential conversion with SINGLE-ENDED the input terminated down to present a single-ended 75 Ω input. V Z R S P L EQUIVALENT A sixth-order Chebyshev differential filter is used to interface the output of the AD8370 to the input of the AD9430 R Z S S 170 MSPS, 12-bit ADC. The filter minimizes aliasing effects 2 2 and improves harmonic distortion performance. R L 2 BALANCED V S Z P CONFIGURATION R L The input of the AD9430 is terminated with a 1.5 kΩ resistor so 2 that the overall load presented to the filter network is ~1 kΩ. R Z S S 2 2 The variable gain of the AD8370 extends the useable dynamic range of the ADC. The measured intermodulation distortion of Figure 55. Single-Ended-to-Differential Network Conversion the combination is presented in Figure 57 at 42 MHz. As an example, a second-order, Butterworth, low-pass filter 0 design is presented where the differential load impedance is –10 1200 Ω, and the padded source impedance of the AD8370 is –20 assumed to be 120 Ω. The normalized series inductor value for –30 the 10-to-1, load-to-source impedance ratio is 0.074 H, and the –40 normalized shunt capacitor is 14.814 F. For a 70 MHz cutoff –50 –60 frequency, the single-ended equivalent circuit consists of a –70 200 nH series inductor followed by a 27 pF capacitor. To realize –80 the balanced equivalent, simply split the 200 nH inductor in –90 half to realize the network shown in Figure 56. –100 R S –110 R = = 0.1 S L = 0.074H R N L –120 NORMALIZED –130 V C 14.814F R = 1Ω S SINGLE-ENDED 0 10 20 30 40 50 60 70 N L EQUIVALENT FREQUENCY (MHz) f = 1Hz C Figure 57. FFT Plot of Two-Tone Intermodulation Distortion at 42 MHz for the Circuit in Figure 58 R = 120Ω 200nH S In Figure 57, the intermodulation products are comparable to DE-NORMALIZED the noise floor of the ADC. The spurious-free dynamic range of V SINGLE-ENDED 27pF R = 1200Ω S L EQUIVALENT the combination is better than 66 dB for a 70 MHz measurement bandwidth. f = 70MHz C 3 V OPERATION R S = 60Ω 100nH 2 It is possible to operate the AD8370 at voltages as low as 3 V R L = 600Ω 2 BALANCED with only minor performance degradation. Table 6 gives typical V 27pF S CONFIGURATION R L = 600Ω specifications for operation at 3 V. 2 R 100nH S = 60Ω Table 6. 2 Parameter Typical (70 MHz, RL = 100 Ω) Figure 56. Second-Order, Butterworth, Low-Pass Filter Design Example Output IP3 +23.5 dBm P1dB +12.7 dBm −3 dB Bandwidth 650 MHz (HG 127) IMD3 −82 dBc (R = 1 kΩ) L Rev. B | Page 20 of 28 03692-053 03692-054 dBFS 03692-055 Data Sheet AD8370 SERIAL CONTROL INTERFACE FROM 75Ω Tx-LINE C AC C 100nF AC 68nH 180nH 220nH 25Ω V A IN R 120Ω S 100nF 16 15 14 13 12 11 10 9 27pF 39pF 27pF 1.5kΩ AD8370 AD9430 1 2 3 4 5 6 7 8 C AC 25Ω 68nH 180nH 220nH V B IN C AC 100nF 1nF 100nF 0.1µF 0.1µF +V S Figure 58. ADC Interface Example Rev. B | Page 21 of 28 INHI INLO ICOM ICOM VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM OPHI OPLO 03692-056 AD8370 Data Sheet EVALUATION BOARD AND SOFTWARE The evaluation board allows quick testing of the AD8370 by The evaluation board comes with the AD8370 control software using standard 50 Ω test equipment. The schematic is shown in that allows serial gain control from most computers. The Figure 59. Transformers T1 and T2 are used to transform 50 Ω evaluation board is connected via a cable to the parallel port of source and load impedances to the desired input and output the computer. Adjusting the appropriate slider bar in the control reference levels. The top and bottom layers are shown in software automatically updates the gain code of the AD8370 in Figure 63 and Figure 64. The ground plane was removed under either a linear or linear-in-dB fashion. the traces between T1 and Pins INHI and INLO to approximate a 100 Ω characteristic impedance. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 D-SUB 25 PIN MALE L2* C9 OPEN R7 R6 R5 1kΩ 1kΩ 1kΩ C1 C3 1nF 1nF TC4-1W JTX-2-10T T1 T2 IN+ 50Ω Tx LINE 50Ω Tx LINE OUT+ 16 15 14 13 12 11 10 9 R2 R4 IN– 50Ω Tx LINE 50Ω Tx LINE OUT– 0Ω 0Ω 1:4 2:1 AD8370 R1 R3 0Ω 0Ω 1 2 3 4 5 6 7 8 C2 C4 1nF 1nF C8 C5 0.1µF 0.1µF C6 SW1 1µF PWUP L1* VOCM +V S R9 C7 GND R8 49.9Ω OPEN 0.1µF C10 OPEN 1 2 3 4 5 GND P2 *EMI SUPPRESSION FERRITE V HZ1206E601R-00 S Figure 59. AD8370 Evaluation Board Schematic Rev. B | Page 22 of 28 INHI INLO ICOM ICOM VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM OPHI OPLO 03692-057 Data Sheet AD8370 Figure 60. Evaluation Software Table 7. AD8370 Evaluation Board Configuration Options Component Function Default Condition VS, GND, VOCM Power Interface Vector Pins. Apply supply voltage between VS and GND. The VOCM Not applicable pin allows external monitoring of the common-mode input and output bias levels. SW1, R8, Device Enable. Set to Position B to power up the device. When in Position A, the PWUP SW1 = installed C10, PWUP pin is connected to the PWUP vector pin. The PWUP pin allows external power cycling R8 = 49.9 Ω (Size 0805) of the device. R8 and C10 are provided to allow for proper cable termination. C10 = open (Size 0805) P1, R5, R6, Serial Control Interfaces. The evaluation board can be controlled using most PCs. P1 = installed Windows®-based control software is shipped with the evaluation kit. A 25-pin, D-sub R5, R6, R7 = 1 kΩ (Size 0603) R7, C9 connector cable is required to connect the PC to the evaluation board. It may be C9 = open (Size 0603) necessary to use a capacitor on the clock line, depending on the quality of the PC port signals. A 1 nF capacitor for C9 is usually sufficient for reducing clock overshoot. J1, J2, J6, J7 Input and Output Signal Connectors. These SMA connectors provide a convenient way Not applicable to interface the evaluation board with 50 Ω test equipment. Typically, the device is evaluated using a single-ended source and load. The source should connect to J1 (IN+), and the load should connect to J6 (OUT+). C1, C2, C3, C4 AC Coupling Capacitors. Provide ac coupling of the input and output signals. C1, C2, C3, C4 = 1 nF (Size 0603) T1, T2 Impedance Transformers. T1 provides a 50 Ω to 200 Ω impedance transformation. T1 = TC4 −1W (Mini-Circuits) T2 provides a 100 Ω to 50 Ω impedance transformation. T2 = JTX−2−10T (Mini-Circuits) R1, R2, R3, R4 Single-Ended or Differential. R2 and R4 are used to ground the center tap of the R1, R2, R3, R4 = 0 Ω (Size 0603) secondary windings on transformers T1 and T2. R1 and R3 should be used to ground J2 and J7 when used in single-ended applications. C5, C6, C7, Power Supply Decoupling. Nominal supply decoupling consists of a ferrite bead C6 = 1 µF (Size 0805) C8 L1, L2 series inductor followed by a 1 µF capacitor to ground followed by a 0.1 µF capacitor C5, C7, C8 = 0.1 µF (Size 0603) to ground positioned as close to the device as possible. C7 provides additional L1, L2 = HZ1206E601R-00 decoupling of the input common-mode voltage. L1 provides high frequency (Steward, Size 1206) isolation between the input and output power supply. L2 provides high frequency isolation between the analog and digital ground. Rev. B | Page 23 of 28 03692-058 AD8370 Data Sheet Figure 61. Evaluation Board Top Silkscreen Figure 63. Evaluation Board Top Figure 62. Evaluation Board Bottom Silkscreen Figure 64. Evaluation Board Bottom Rev. B | Page 24 of 28 03692-060 03692-059 03692-062 03692-061 Data Sheet AD8370 APPENDIX CHARACTERIZATION EQUIPMENT DEFINITIONS OF SELECTED PARAMETERS An Agilent N4441A Balanced-Measurement System was used to Common-mode rejection ratio (Figure 28) has been defined for obtain the gain, phase, group delay, reverse isolation, CMRR, this characterization effort as and s-parameter information contained in this data sheet. With Differential Mode Gain the exception of the s-parameter information, T-attenuator pads Common Mode Gain were used to match the 50 Ω impedance of this instrument’s ports to the AD8370. An Agilent 4795A Spectrum Analyzer was used where the numerator is the gain into a differential load at the to obtain nonlinear measurements IMD, IP3, and P1dB through output due to a differential source at the input, and the matching baluns and/or attenuator networks. Various other denominator is the gain into a differential-mode load at the measurements were taken with setups shown in this section. output due to a common-mode source at the input. In terms of mixed-mode s-parameters, this equates to COMPOSITE WAVEFORM ASSUMPTION The nonlinear two-tone measurements made for this data sheet, SDD21 that is, IMD and IP3, are based on the assumption of a fixed SDC21 value composite waveform at the output, generally 1 V p-p. The frequencies of interest dictate the use of RF test equipment, and More information on mixed-mode s-parameters can be because this equipment is generally not designed to work in obtained in a reference by Bockelman, D.E. and Eisenstadt, W.R., Combined Differential and Common-Mode Scattering units of volts, but rather watts and dBm, an assumption was Parameters: Theory and Simulation. IEEE Transactions on made to facilitate equipment setup and operation. Two sinusoidal tones can be represented as Microwave Theory and Techniques, v 43, n 7, 1530 (July 1995). V1 = V sin (2∏f1t) Reverse isolation (Figure 26) is defined as SDD12. V = V sin (2∏f t) Power supply rejection ratio (PSRR) is defined as 2 2 A dm The RMS average voltage of one tone is A s 2 T 1 1 (V) dt= ∫ 1 where A is the differential mode forward gain (SDD21), and dm T 2 0 A is the gain from the power supply pins (VCCI and VCCO, s taken together) to the output (OPLO and OPHI, taken where T is the period of the waveform. The RMS average differentially), corrected for impedance mismatch. The voltage of the two-tone composite signal is following reference provides more information: Gray, P.R., 2 T 1 Hurst, P.J., Lewis, S.H. and Meyer, R.G., Analysis and Design of (V +V) dt= 1 1 ∫ 2 th T Analog Integrated Circuits, 4 Edition, John Wiley & Sons, Inc., 0 page 422. It can be shown that the average power of this composite waveform is twice (3 dB) that of the single tone. This also means that the composite peak-to-peak voltage is twice (6 dB) that of a single tone. This principle can be used to set correct input amplitudes from generators scaled in dBm and is correct if the two tones are of equal amplitude and are reasonably close in frequency. Rev. B | Page 25 of 28 AD8370 Data Sheet –22.5dB PORT 1 PORT 1 SERIAL DATA SOURCE BIAS TEE SERIAL DATA CONNECTION SOURCE TO PORT 1 V 5.0V S 1nF 1nF T1 T2 PORT 2 MINI- 1nF 1nF MINI- 16 15 14 13 12 11 10 9 CIRCUITS CIRCUITS PORT 2 TC4-1W TC2-1T 16 15 14 13 12 11 10 9 MINI- 0Ω CIRCUITS TC2-1T AD8370 200Ω AD8370 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1nF 1nF 1nF 1nF 1nF V 5.0V V 5.0V S S 1µF 1nF 1µF 1nF 1nF Figure 65. PSRR Adm Test Setup Figure 66. PSRR A Test Setup s TEKTRONIX TDS5104 DPO OSCILLOSCOPE 50Ω 50Ω 50Ω 50Ω HP8133A AUX IN INPUT INPUT INPUT INPUT 3GHz PULSE GENERATOR 3dB TRIG ATTEN 6dB SERIAL DATA OUT SPLITTER SOURCE V 5.0V S 475Ω 3dB 2dB ATTEN ATTEN 52.3Ω 16 15 14 13 12 11 10 9 3dB ATTEN 200Ω AD8370 6dB OUT SPLITTER 1 2 3 4 5 6 7 8 475Ω 2dB 3dB ATTEN ATTEN 52.3Ω V 5.0V S 1µF 1nF 1nF 1nF 1µF V 5.0V S Figure 67. DC Pulse Response and Overdrive Recovery Test Setup Rev. B | Page 26 of 28 INHI INLO ICOM ICOM VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM OPHI OPLO AGILENT 8753D NETWORK ANALYZER 03692-063 INHI INLO ICOM ICOM VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO INHI INLO OCOM OCOM ICOM ICOM OPHI OPLO VCCI DATA PWUP CLCK VOCM LTCH VCCO VCCO OCOM OCOM OPHI OPLO 03692-065 AGILENT 8753D NETWORK ANALYZER 03692-064 Data Sheet AD8370 AGILENT 8648D TEKTRONIX SERIAL DATA SIGNAL TDS5104 DPO SOURCE GENERATOR OSCILLOSCOPE TEKTRONIX RF OUT P6205 ACTIVE 50Ω INPUT FET PROBE V 5.0V S 475Ω 1nF 1nF T1 T2 50Ω INPUT MINI- MINI- 16 15 14 13 12 11 10 9 CIRCUITS CIRCUITS TC4-1W JTX-2-10T 0Ω 105Ω AD8370 1 2 3 4 5 6 7 8 475Ω 1nF 1nF V 5.0V V 5.0V S S 1µF 1nF 1µF 1nF 1nF Figure 68. Gain Step Time Domain Response Test Setup AGILENT 8648D TEKTRONIX SERIAL DATA SIGNAL TDS5104 DPO SOURCE GENERATOR OSCILLOSCOPE 10MHz REF OUT RF OUT V 5.0V S 1nF 1nF 475Ω T1 T2 50Ω INPUT MINI- MINI- 16 15 14 13 12 11 10 9 CIRCUITS CIRCUITS TC4-1W JTX-2-10T 0Ω 105Ω AD8370 1 2 3 4 5 6 7 8 475Ω 1nF 1nF TEKTRONIX 10MHz IN OUTPUT P6205 ACTIVE 50Ω INPUT FET PROBE V 5.0V V 5.0V AGILENT 33250A S S FUNCTION/ARBITRARY 1µF 1nF 1µF 1nF WAVEFORM GENERATOR 52.3Ω 1nF Figure 69. PWUP Response Time Domain Test Setup Rev. B | Page 27 of 28 INHI INLO ICOM ICOM VCCI DATA INHI INLO PWUP CLCK ICOM ICOM VOCM LTCH VCCI DATA VCCO VCCO PWUP CLCK OCOM OCOM VOCM LTCH OPHI OPLO VCCO VCCO OCOM OCOM OPHI OPLO 03692-066 03692-067 AD8370 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 3.05 4.50 EXPOSED TOP 6.40 PAD 3.00 SQ 4.40 VIEW BSC (Pins Up) 2.95 4.30 1 8 BOTTOM VIEW 0.65 BSC 1.05 1.20 MAX 1.00 8° 0.80 0° 0.15 0.20 0.30 0.75 SEATING 0.09 0.05 0.19 PLANE 0.60 COPLANARITY 0.45 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-ABT Figure 70. 16-Lead Thin Shrink Small Outline Package with Exposed Pad [TSSOP_EP] (RE-16-2) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8370ARE-REEL7 16-lead TSSOP_EP, 7” Tape and Reel RE-16-2 –40°C to +85°C AD8370AREZ 16-lead TSSOP_EP, Tube RE-16-2 –40°C to +85°C AD8370AREZ-RL7 16-lead TSSOP_EP, 7” Tape and Reel RE-16-2 –40°C to +85°C AD8370-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. © 2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03692–0–12/11(B) Rev. B | Page 28 of 28 050806-A