ANALOG DEVICES AD8368

800 MHz, Linear-in-dB VGA with AGC Detector AD8368 FEATURES FUNCTIONAL BLOCK DIAGRAM VPSO MODE VPSO VPSI VPSI VPSI VPSI VPSI Analog variable gain range: −12 dB to +22 dB 10 21 9 11 12 22 23 13 Linear-in-dB scaling: 37.5 dB/V ICOM 16 AD8368 3 dB bandwidth: 800 MHz @ VGAIN = 0.5 V OCOM 6 Integrated rms detector GAIN 1 GAIN INTERPOLATOR FIXED-GAIN OUTPUT 24 ENBL P1dB: 16 dBm @ 140 MHz AMPLIFIER BUFFER OCOM 7 Output IP3: 33 dBm @ 140 MHz 8 OUTP g STAGES m Noise figure at maximum gain: 9.5 dB @ 140 MHz 3 HPFL 0dB –2dB –4dB –36dB 4 DECL Input and output impedances: 50 Ω REF INPT 19 14 DECL Single-supply voltage from 4.5 V to 5.5 V 50Ω ICOM 17 – DECL 15 DECL RoHS-compliant, 24-lead LFCSP 2 X ICOM 18 ATTENUATOR LADDER + ICOM 20 2 5 APPLICATIONS DETO DETI Complete IF AGC amplifiers Figure 1. Gain trimming and leveling Cellular base stations Point-to-point radio links RF instrumentation GENERAL DESCRIPTION The AD8368 is a variable gain amplifier (VGA) with analog By connecting MODE to ground and using the on-board rms linear-in-dB gain control that can be used from low frequencies detector, the AD8368 can be configured as a complete to 800 MHz. Its excellent gain range, conformance, and flatness automatic gain control (AGC) system with RSSI. The output are attributed to the Analog Devices, Inc., X-AMP® architecture, power is accurately leveled to the internal default setpoint of an innovative technique for implementing high performance 63 mV rms (−11 dBm referenced to 50 Ω), independent of the variable gain control. waveform crest factor. Because the uncommitted detector input is available at DETI, the AGC loop can level the signal at The gain range of −12 dB to +22 dB is scaled accurately to the AD8368 output or at any other point in the signal chain 37.5 dB/V with excellent conformance error. The AD8368 has over a maximum input power range of 34 dB. Furthermore, the a 3 dB bandwidth of 800 MHz that is nominally independent setpoint level can be raised by dividing down the output signal of gain setting. At 140 MHz, the OIP3 is 33 dBm at maximum before applying it to the detector. gain. The output noise floor is −143 dBm/Hz, which corresponds to a 9.5 dB noise figure at maximum gain. The single-ended The AD8368 operates from a supply voltage of 4.5 V to 5.5 V input and output impedances are nominally 50 Ω. and consumes 60 mA of current. It can be fully powered down to <3 mA by grounding the ENBL pin. The AD8368 is fabricated The gain of the AD8368 can be configured to be an increasing using the Analog Devices proprietary SiGe SOI complementary or decreasing function of the gain control voltage depending bipolar IC process. It is available in a 24-lead LFCSP and on whether the MODE pin is pulled to the positive supply or operates over the industrial temperature range of −40°C to to ground, respectively. When MODE is pulled high, the +85°C. Application boards are available upon request. AD8368 operates as a typical VGA with increasing gain. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05907-001 AD8368 TABLE OF CONTENTS Features ............................................................................................ 1  Fixed-Gain Stage and Output Buffer ..................................... 12  Applications ..................................................................................... 1  Output Offset Correction ........................................................ 12  Functional Block Diagram ............................................................ 1  Input and Output Impedances ............................................... 12  General Description ....................................................................... 1  Gain Control Interface ............................................................ 13  Revision History ............................................................................. 2  Applications Information ............................................................ 14  Specif ica t ions ................................................................................... 3  VGA Operation ........................................................................ 14  Absolute Maximum Ratings .......................................................... 5  AGC Operation ........................................................................ 14  ESD Caution ................................................................................ 5  Stability and Layout Considerations ...................................... 16  Pin Configuration and Function Descriptions ........................... 6  Evaluation Board .......................................................................... 17  Typical Performance Characteristics ........................................... 7  Outline Dimensions ..................................................................... 19  Circuit Description ....................................................................... 12  Ordering Guide ........................................................................ 19  Input Attenuator and Interpolator ......................................... 12  REVISION HISTORY 9/08—Rev. A to Rev. B 4/06—Revision 0: Initial Version Added Stability and Layout Considerations Section ................. 16 Changes to Evaluation Board Section, Figure 40, and Table 6 .............................................................................................. 17 Added Figure 41, Figure 42, Figure 43, and Figure 44; Renumbered Sequentially .............................................................. 18 Added Exposed Pad Notation to Outline Dimensions ............. 19 10/07—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Figure 4 to Figure 6 ...................................................... 7 Changes to Figure 16 ........................................................................ 9 Changes to Figure 31 ...................................................................... 12 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 Rev. B | Page 2 of 20 AD8368 SPECIFICATIONS VS = 5 V, TA = 25°C, system impedance Z0 = 50 Ω, VMODE = 5 V, RF input = 140 MHz, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions OVERALL FUNCTION Frequency Range LF 800 MHz 3 dB bandwidth Maximum Input 3 VP To avoid input overload 1 Maximum Output 2 V To avoid clipping P AC Input Impedance 50 Ω From INPT to ICOM AC Output Impedance 50 Ω From OUTP to OCOM GAIN CONTROL INTERFACE (GAIN) Gain Span 34 dB Gain Scaling 37.5 dB/V VMODE = 5 V, 50 mV ≤ VGAIN ≤ 950 mV −38 dB/V VMODE = 0 V, 50 mV ≤ VGAIN ≤ 950 mV Gain Accuracy dB ±0.4 100 mV ≤ V ≤ 900 mV GAIN Maximum Gain 22 dB V = 1 V GAIN Minimum Gain −12 dB VGAIN = 0 V VGAIN Range 0 1 V Gain Step Response 100 ns For 6 dB gain step Gain Input Bias Current −2 μA f = 70 MHz Noise Figure 9.5 dB Maximum gain Output IP3 34 dBm f = 70 MHz, f = 71 MHz, V = 1 V, 0 dBm per output tone 1 2 GAIN 1 Output P1dB 16 dBm V = 0 V, V = 0 V GAIN MODE f = 140 MHz Noise Figure 9.5 dB Maximum gain Output IP3 33 dBm f = 140 MHz, f = 141 MHz, V = 1 V, 0 dBm per output tone 1 2 GAIN 1 Output P1dB 16 dBm VGAIN = 0 V, VMODE = 0 V f = 240 MHz Noise Figure 9.7 dB Maximum gain Output IP3 33 dBm f1 = 240 MHz, f2 = 241 MHz, VGAIN = 1 V, 0 dBm per output tone 1 Output P1dB 15 dBm VGAIN = 0 V, VMODE = 0 V f = 380 MHz Noise Figure 10 dB Maximum gain Output IP3 29 dBm f1 = 380 MHz, f2 = 381 MHz, VGAIN = 1 V, 0 dBm per output tone 1 Output P1dB 13 dBm VGAIN = 0 V, VMODE = 0 V 1 Operation at compression is not recommended due to adverse distortion components. Rev. B | Page 3 of 20 AD8368 V = 5 V, T = 25°C, system impedance Z = 50 Ω, V = 5 V, RF input = 140 MHz, unless otherwise noted. S A 0 MODE Table 2. Parameter Min Typ Max Unit Conditions SQUARE LAW DETECTOR (DETI, DETO) Output Setpoint −11 dBm OUTP connected to DETI DETI DC Bias Level to ICOM VS/2 V DETI Impedance 710 Ω 0.6 pF 1 DETO Output Range 0.1 V/2 V S AGC Step Response 30 μs For −6 dB input power step (C = 1 nF) DETO MODE CONTROL INTERFACE (MODE) MODE Threshold 3.5 V MODE Input Bias Current 50 μA POWER INTERFACE (VPSI, VPSO) Supply Voltage 4.5 5 5.5 V Total Supply Current 60 mA ENBL high Disable Current 2 mA ENBL low ENABLE INTERFACE (ENBL) Enable Threshold 2.5 V Enable Response Time 1.5 μs Time delay following off-to-on transition until output reaches 90% of final value 3 μs Time delay following on-to-off transition until supply current is less than 5 mA ENBL Input Bias Current 150 μA V = 5 V ENBL 1 Refer to AGC Operation section. Rev. B | Page 4 of 20 AD8368 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage (VPSO, VPSI) 5.5 V other conditions above those indicated in the operational ENBL and MODE Select Voltage 5.5 V section of this specification is not implied. Exposure to absolute RF Input Level 20 dBm maximum rating conditions for extended periods may affect Internal Power Dissipation 440 mW device reliability. θJA 52°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C ESD CAUTION Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Rev. B | Page 5 of 20 AD8368 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 GAIN 1 18 ICOM DETO 2 17 ICOM HPFL 3 AD8368 16 ICOM TOP VIEW DECL 4 15 DECL (Not to Scale) DETI 5 14 DECL OCOM 6 13 VPSI 78 9 10 11 12 NOTES 1. EXPOSED PAD. CONNECT EPAD TO LOW IMPEDANCE GROUND. Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 GAIN Gain Control. 2 DETO Detector Output. Provides an output error current for the AGC function. 3 HPFL High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the internal output offset control loop that controls the minimum usable input frequency. 4, 14, 15 DECL Decoupling Pin. Nominally ~VS/2. Decoupling capacitance may need to be adjusted for AGC operation (see the Applications Information section). 5 DETI Detector Input. DC level referenced to DECL pin. 6, 7 OCOM Connect OCOM to low impedance ground. 8 OUTP Signal Output. Must be ac-coupled. 9, 10 VPSO Positive Supply Voltage, 4.5 V to 5.5 V. VPSO and VPSI must be connected together externally and properly bypassed. 11, 12, 13, 22, 23 VPSI Positive Supply Voltage, 4.5 V to 5.5 V. VPSO and VPSI must be connected together externally and properly bypassed. 16, 17, 18, 20 ICOM Connect ICOM to low impedance ground. 19 INPT Signal Input. Must be ac-coupled. 21 MODE Gain Direction Control. High for positive slope. Low for negative slope. 24 ENBL Apply a Positive Voltage (2.5 V ≤ V ≤ VPSI) to Activate Device. ENBL EPAD Exposed Pad. Connect the exposed pad to low impedance ground. Rev. B | Page 6 of 20 OCOM ENBL OUTP VPSI VPSO VPSI VPSO MODE VPSI ICOM VPSI INPT 05907-002 AD8368 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, T = 25°C, system impedance Z0 = 50 Ω, MODE = 5 V, unless otherwise noted. 25 25 4 240MHz 20 1V 20 3 15 15 2 0.75V +85°C 10 10 1 5 0.5V 5 0 0 0 –1 –5 +25°C 0.25V –40°C –5 –2 –10 0V –10 –3 –15 –20 –15 –4 10 100 1000 0 0.2 0.4 0.6 0.8 1.0 FREQUENCY (MHz) V (V) GAIN Figure 3. S21 vs. Frequency by V GAIN Figure 6. Gain and Conformance Error vs. VGAIN (f = 240 MHz) 25 4 25 4 70MHz 380MHz 20 3 20 3 15 2 15 2 +85°C +85°C 10 1 10 1 5 0 5 0 0 –1 +25°C 0 –1 –40°C +25°C –40°C –5 –2 –5 –2 –10 –3 –10 –3 –15 –4 –15 –4 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 V (V) V (V) GAIN GAIN Figure 4. Gain and Conformance Error vs. V (f = 70 MHz) Figure 7. Gain and Conformance Error vs. V (f = 380 MHz) GAIN GAIN 25 4 0.7 140MHz 0.6 20 3 0.5 15 2 V GAIN 0.4 +85°C 0.3 10 1 0.2 V OUTP 5 0 0.1 0 –1 0 +25°C –40°C –0.1 –5 –2 –0.2 –10 –3 –0.3 –15 –4 –0.4 0 0.2 0.4 0.6 0.8 1.0 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 V (V) TIME (µs) GAIN Figure 8. Gain Step Time Domain Response (6 dB Gain Step) Figure 5. Gain and Conformance Error vs. VGAIN (f = 140 MHz) Rev. B | Page 7 of 20 GAIN (dB) GAIN (dB) S21 (dB) 05907-003 CONFORMANCE ERROR (dB) CONFORMANCE ERROR (dB) 05907-005 05907-004 GAIN (dB) GAIN (dB) AMPLITUDE (V) 05907-008 CONFORMANCE ERROR (dB) CONFORMANCE ERROR (dB) 05907-007 05907-006 AD8368 40 20 +85°C +85°C 18 35 +25°C 16 30 14 +25°C 25 12 –40°C 20 10 –40°C 8 15 6 10 4 5 2 0 0 70 110 150 190 230 270 310 350 380 70 110 150 190 230 270 310 350 380 RF INPUT (MHz) RF INPUT (MHz) Figure 9. Output Third-Order Intercept vs. RF Input Frequency at Figure 12. Output 1dB Compression Point vs. RF Input Frequency at Maximum Gain (VMODE = 0 V) Maximum Gain (VMODE = 0 V) 40 20 70MHz 140MHz 70MHz 140MHz 18 35 16 30 14 25 12 380MHz 240MHz 240MHz 380MHz 20 10 8 15 6 10 4 5 2 0 0 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 V (V) V (V) GAIN GAIN Figure 10. Output Third-Order Intercept vs. V (V = 0 V) Figure 13. Output 1dB Compression Point vs. V (V = 0 V) GAIN MODE GAIN MODE 0 20 5.5V 18 –10 16 –20 14 –30 5.0V 12 4.5V –40 10 380MHz 240MHz 8 –50 6 –60 4 –70 2 140MHz 70MHz –80 0 0 0.2 0.4 0.6 0.8 1.0 70 110 150 190 230 270 310 350 380 V (V) RF INPUT (MHz) GAIN Figure 14. Output 1dB Compression Point vs. RF Input Frequency by Figure 11. Third-Order IMD vs. V GAIN Supply Voltage at Maximum Gain (VMODE = 0 V) (Output Power = 0 dBm per Tone, V = 0 V) MODE Rev. B | Page 8 of 20 THIRD-ORDER IMD (dBc) OUTPUT THIRD-ORDER INTERCEPT (dBm) OUTPUT THIRD-ORDER INTERCEPT (dBm) 05907-011 05907-010 05907-009 OUTPUT 1dB COMPRESSION (dBm) OUTPUT 1dB COMPRESSION (dBm) OUTPUT 1dB COMPRESSION (dBm) 05907-014 05907-012 05907-013 AD8368 50 45 40 35 30 V = 0.75V GAIN 25 V = 0V GAIN V = 1V GAIN 20 15 V = 0.25V GAIN 10 V = 0.5V GAIN 5 0 10 100 1000 FREQUENCY (MHz) Figure 15. Noise Figure vs. Frequency at Maximum Gain (VMODE = 0 V) Figure 18. Input Reflection Coefficient vs. Frequency 50 0 45 –5 40 –10 35 –15 30 25 –20 20 –25 15 –30 70MHz 10 140MHz 240MHz –35 V = 1V 5 GAIN 380MHz V = 0V GAIN 0 –40 01 0.2 0.4 0.6 0.8.0 10 100 1000 V (V) FREQUENCY (MHz) GAIN Figure 16. Noise Figure vs. V (V = 0 V) GAIN MODE Figure 19. Output Return Loss vs. Frequency 0 –5 V = 0.5V GAIN –10 V = 0.75V GAIN –15 = 1V V GAIN V = 1V –20 GAIN –25 –30 V = 0V V = 0V GAIN GAIN –35 V = 0.25V GAIN –40 10 100 1000 FREQUENCY (MHz) Figure 17. Input Return Loss vs. Frequency Figure 20. Output Reflection Coefficient vs. Frequency Rev. B | Page 9 of 20 INPUT RETURN LOSS (dB) NOISE FIGURE (dB) NOISE FIGURE (dB) 05907-015 05907-017 05907-016 OUTPUT RETURN LOSS (dB) 05907-020 05907-018 05907-019 AD8368 1.0 1.0 1.0 1.0 0.9 0.8 0.9 0.8 0.8 0.6 0.8 0.6 +85°C 0.7 0.4 0.7 0.4 0.6 0.2 0.6 0.2 0.5 0 0.5 0 –40°C –40°C +85°C 0.4 –0.2 0.4 –0.2 +25°C +25°C 0.3 –0.4 0.3 –0.4 +25°C –40°C 0.2 –0.6 0.2 –0.6 0.1 –0.8 0.1 –0.8 –40°C +85°C +25°C +85°C 0 –1.0 0 –1.0 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –40 –35 –30 –25 –20 –15 –10 –5 0 5 RF INPUT (dBm) RF INPUT (dBm) Figure 21. RSSI (VDETO) and Conformance Error vs. Input Power (f = 70 MHz) Figure 24. RSSI (VDETO) and Conformance Error vs. Input Power (f = 380 MHz) 1.0 1.0 V RSSI 0.9 0.8 0.8 0.6 0.7 0.4 V OUTP 0.6 0.2 0.5 0 +25°C +85°C 0.4 –0.2 –40°C 0.3 –0.4 –40°C 0.2 –0.6 0.1 –0.8 +25°C +85°C 0 –1.0 CH2 50mV Ω CH3 100mV Ω M20µs 500MS/s A CH1 410mV –40 –35 –30 –25 –20 –15 –10 –5 0 5 2.0ns/PT RF INPUT (dBm) Figure 22. RSSI (VDETO) and Conformance Error vs. Input Power (f = 140 MHz) Figure 25. AGC Time Domain Response (3 dB Power Step, CDETO = 1 nF) 1.0 1.0 80 8 0.9 0.8 70 7 0.8 0.6 4.5V 60 6 0.7 0.4 50 5 0.6 0.2 5.5V 5.5V 5.0V 0.5 0 40 4 +85°C +25°C 0.4 –0.2 30 3 –40°C 5.0V 0.3 –0.4 –40°C 20 2 0.2 –0.6 10 1 0.1 –0.8 4.5V +25°C +85°C 0 –1.0 0 0 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –40 –20 0 20 40 60 80 RF INPUT (dBm) TEMPERATURE (°C) Figure 26. Supply Current and Disable Current vs. Temperature Figure 23. RSSI (VDETO) and Conformance Error vs. Input Power (f = 240 MHz) Rev. B | Page 10 of 20 RSSI (V) RSSI (V) RSSI (V) CONFORMANCE ERROR (dB) CONFORMANCE ERROR (dB) CONFORMANCE ERROR (dB) 05907-023 05907-022 05907-021 RSSI (V) SUPPLY CURRENT (mA) AMPLITUDE (V) 05907-025 DISABLE CURRENT (mA) 05907-026 CONFORMANCE ERROR (dB) 05907-024 AD8368 50 V ENBL 40 V OUTP 30 20 10 0 CH2 500mV Ω CH3 5V Ω M2.0µs 250MS/s A CH3 0.0V –15.0 –14.7 –14.4 –14.1 –13.8 –13.5 4.0ns/PT INTERCEPT (dB) Figure 27. ENBL Response Time Figure 29. Gain Intercept Distribution (140 MHz) 50 40 30 20 10 0 36.8 37.0 37.2 37.4 37.6 37.8 38.0 38.2 SLOPE (dB/V) Figure 28. Gain Scaling Distribution (140 MHz) Rev. B | Page 11 of 20 PERCENTAGE (%) AMPLITUDE (V) 05907-027 05907-028 PERCENTAGE (%) 05907-029 AD8368 CIRCUIT DESCRIPTION The AD8368 is a single-ended VGA with a bandwidth of 800 MHz OUTPUT OFFSET CORRECTION and a gain control span of 34 dB ranging from −12 dB to +22 dB. The dc level at the input, INPT, is driven by an internal reference to It incorporates an uncommitted square law detector that can be V /2. The reference is made available at the DECL pin for external S used to form a tight AGC loop around the VGA. Using the decoupling with C . The dc level at the output, OUTP, is DECL Analog Devices patented X-AMP architecture, the AD8368 regulated to the same midsupply reference by an offset correction achieves accurate linear-in-dB gain control with excellent linearity loop independent of gain setting, temperature, and process. The (OIP3) and noise figure (NF). The part also features 50 Ω input low-pass response of this loop creates a high-pass corner frequency and output impedances for ease of use. in the signal path transfer function, which can be set by choosing The main signal path, shown in Figure 30, consists of a variable CDECL and CHPFL. input attenuator followed by a fixed-gain amplifier and output FIXED-GAIN OUTPUT AMPLIFIER BUFFER buffer. This architecture allows for a constant OIP3 and output FROM VOUT INTERPOLATOR noise floor as a function of gain setting. As a result, NF and IIP3 g STAGES m increase 1 dB for every 1 dB decrease in gain, resulting in a part g m with constant dynamic range over gain setting. ×1 V MID MODE HPFL DECL C C HPFL DECL GAIN INTERPOLATOR GAIN FIXED-GAIN OUTPUT AMPLIFIER BUFFER Figure 31. Output Centering Control Loop g STAGES VOUT m The input and output coupling capacitors should be selected to 0dB –2dB –4dB –36dB INPT provide low impedances at the frequencies of interest relative to 50Ω 50 Ω so as not to affect the high-pass corner. In this case, the DECL high-pass corner frequency can be set by either C or C , ATTENUATOR LADDER HPFL DECL which form independent poles in the feedback path of the offset Figure 30. Simplified Block Diagram correction loop. The high-pass corner is determined by the highest INPUT ATTENUATOR AND INTERPOLATOR of these poles, which are given by The input attenuator is built from an 18-section resistor ladder, 0.8 fHP,HPFL(kHz)= providing 2 dB of attenuation at each successive tap point. The (0.005+CHPFL) resistor ladder acts as a linear input attenuator, in addition to 5700 providing an accurate 50 Ω input impedance. The variable fHP,DECL(kHz)= (0.005+CDECL) transconductance (gm) stages are used to select the attenuated signal from the appropriate tap point along the ladder and feed where CHPFL and CDECL are in nF. this signal to the fixed-gain amplifier. To realize a continuous gain When using this method to set the high-pass frequency, the control function from discrete tap points, the gain interpolator other capacitor should be sized such that its pole is at least 30× creates a weighted sum of signals appearing on adjacent tap lower in frequency. In addition, note that C represents the DECL points by carefully controlling the variable g stages. m total decoupling capacitance at the DECL pins. FIXED-GAIN STAGE AND OUTPUT BUFFER INPUT AND OUTPUT IMPEDANCES The weighted sum of the different tap points is fed into the The AD8368 offers single-ended broadband 50 Ω input and fixed-gain stage that drives the output buffer. Because the output impedances. The excellent match to 50 Ω is maintained resistive input attenuator is linear and contributes minimal from part to part, over frequency, and over gain setting. Both noise as a passive termination, the dynamic range as a function the input and output pins must be externally ac-coupled to of gain is determined primarily by the noise and the distortion prevent disruption of the internal dc levels. Sufficiently large of the fixed-gain amplifier. This architecture explains the constant coupling capacitors should be used so that their impedance is OIP3 and constant output noise floor with gain setting and the negligible relative to the 50 Ω presented by the ladder at the corresponding dB-for-dB increase in IIP3 and NF with decreasing input and by the output buffer at the output. gain. The output buffer has 6 dB of gain and provides a broadband 50 Ω single-ended output impedance. Rev. B | Page 12 of 20 05907-033 05907-034 AD8368 25 4 GAIN CONTROL INTERFACE GAIN_H 20 3 The AD8368 has a linear-in-dB gain control interface that can be operated in either a gain-up mode or gain-down mode. In 15 2 the gain-up mode with the MODE pin pulled high, the gain 10 1 ERROR_L increases with increasing gain voltages. In the gain-down mode, with the MODE pin pulled low, the gain decreases with increasing 5 0 gain voltages. In both modes of operation, the gain control 0 –1 ERROR_H slope is maintained at +37.5 dB/V or −38 dB/V (depending on mode selection) over temperature, supply, and process as –5 –2 VGAIN varies from 100 mV to 900 mV. To form an AGC loop –10 –3 with the on-board detector around the VGA, the MODE pin GAIN_L has to be pulled low. –15 –4 01 0.2 0.4 0.6 0.8.0 The gain functions for MODE pulled high and low are given V (V) GAIN respectively by Figure 32. Gain and Conformance Error vs. V GAIN Gain (dB) = 37.5 × V − 14 HIGH GAIN As shown in Figure 32, the gain function can be either an GainLOW (dB) = −38 × VGAIN + 24.8 increasing or decreasing function of VGAIN, depending on the MODE pin. where VGAIN is expressed in volts. Rev. B | Page 13 of 20 GAIN (dB) CONFORMANCE ERROR (dB) 05907-035 AD8368 APPLICATIONS INFORMATION The DECL pin provides the internal midsupply dc reference VGA OPERATION for the AD8368. It should be well decoupled to ground using a The AD8368 is a general-purpose VGA suitable for use in a wide large capacitor with low ESR. The capacitors connected to the variety of applications where accurate, continuous, linear-in-dB HPFL pin and DECL pin are used to control the low-pass gain control over a broad range of frequencies is important. Its corner frequency of the output offset correction loop. The stability over temperature and supply in comparison to other resulting high-pass corner frequency is inversely proportional variable gain techniques can be traced back to the X-AMP to their values. architecture. While having an 800 MHz bandwidth, its low frequency operation can be extended by properly selecting AGC OPERATION CHPFL and CDECL. The AD8368 can be configured as a standalone AGC amplifier The typical connections for using the AD8368 in VGA mode are by using the on-board rms detector, as shown in Figure 34. The illustrated in Figure 33. The input (INPT) and output (OUTP) of detector output, DETO, is an error current representing the the AD8368 should be externally ac-coupled to prevent disrupting difference of squares between the root-mean-square (rms) of the dc levels on the chip. Therefore, a sufficiently large coupling the sensed signal and an internal reference of 63 mV rms. This capacitor should be used such that the series impedance of the error current is integrated on CDETO and connected to the GAIN capacitor is negligible at the frequencies of interest. pin to form the AGC loop. V IN The 63 mV rms reference corresponds to 178 mV p-p for a sine wave but the detector accuracy is maintained for more complex V POS signals, such as Gaussian noise, complex envelopes, and multi- carrier signals with high peak-to-average ratios. V IN V GAIN GAIN ICOM 0V TO 1V V POS DETO ICOM HPFL ICOM 2 REF X – DECL DECL + RSSI GAIN ICOM DETI DECL DETO ICOM AD8368 OCOM VPSI C DETO HPFL ICOM 2 REF X – DECL DECL R2 + DETI DECL V POS R1 AD8368 V OCOM VPSI OUT Figure 33. Typical Connections for VGA Mode for Increasing Gain with Increasing VGAIN (MODE High) V POS The gain control voltage ranging from 0 V to 1 V is applied to V OUT the GAIN pin. The MODE pin controls whether the gain of the Figure 34. AGC Mode of Operation part is an increasing or decreasing function of the gain voltage. The AGC mode of operation requires a specific gain direction. When the MODE pin is pulled high, the gain increases with The gain must fall as VDETO increases to restore the needed increasing gain voltages. When the MODE pin is pulled low, the balance against the setpoint. Therefore, the MODE pin must be gain decreases with increasing gain voltages. The ENBL pin is pulled low. By connecting the signal at OUTP directly to the used to enable or disable the part. ENBL is active high; when detector input (DETI), the output level is driven to the 63 mV ENBL is pulled low, the part is disabled and draws a fraction of rms reference setpoint. the normal supply current. Rev. B | Page 14 of 20 OCOM ENBL OUTP VPSI VPSO VPSI VPSO MODE VPSI ICOM VPSI INPT 05907-036 OCOM ENBL OUTP VPSI VPSO VPSI VPSO MODE VPSI ICOM VPSI INPT 05907-037 AD8368 The output setpoint can be increased using an external resistive Figure 36 shows a plot of the RSSI voltage at DETO as input divider network between OUTP and DETI, referenced to DECL power is swept. as depicted in Figure 34. In this configuration, the rms output 3.0 voltage is forced to (1 + R1/R2) 63 mV rms by the AGC loop. For a 0 dBm (224 mV rms referenced to 50 Ω) output setpoint, 2.5 this ratio is 3.5. After correcting for the input impedance of DETI, the choice of R1 = 226 Ω and R2 = 100 Ω yields a setpoint of 2.0 roughly 0 dBm. This very accurate leveling function is shown in Figure 35, where the rms output is held to within 0.2 dB of the 1.5 0 dBm setpoint for >30 dB range of input levels. 1.0 10 5 0.5 0 0 –40 –30 –20 –10 0 10 20 –5 POWER IN (dBm) –10 Figure 36. Monitoring the GAIN/DETO RSSI Voltage vs. Input Power –15 In some cases, it can be found that, if driven into AGC overload, the AD8368 requires unusually long times to recover; that is, the –20 voltage at DETO remains at an abnormally high value, and the –25 gain is at its lowest value. To avoid this situation, it is recommended that a clamp be placed on the DETO pin, as shown in Figure 37. –30 –40 –30 –20 –10 0 10 20 POWER IN (dBm) Figure 35. Output Power vs. Input Power in AGC Mode at 140 MHz INPT VPSI Note that to achieve the accurate level of AGC output power, ICOM VPSI the DECL capacitor must be adjusted for the corresponding RF frequency. The DECL capacitor value varies depending on board MODE VPSO AD8368 parasitics. Table 5 shows the DECL capacitor value based on the VPSI VPSO evaluation board parasitics. VPSI OUTP C AGC 0.1µF ENBL OCOM Table 5. DECL Capacitor Value IF Frequency (MHz) C4 (pF) C20 (pF) 70 1000 2200 +V S V AGC 140 270 560 240 68 150 RB 380 33 68 Q1 0.5V 2N2907 480 15 39 RA A valuable feature of using a square law detector in AGC mode Figure 37. External Clamp to Prevent AGC Overload is that the RSSI voltage is a true reflection of signal power and The resistive divider network, RA and RB, should be designed can be converted to an absolute power measurement for any such that the base of Q1 is driven to 0.5 V. given source impedance. The RSSI in units of dBm referenced to 50 Ω and based on the voltage available on the DETO pin is given by RSSI = −11 + 20 log10(1 + R1/R2) + 38 × VDETO − 24.8 Rev. B | Page 15 of 20 POWER OUT (dBm) 05907-038 RSSI (V) GAIN ICOM DETO ICOM HPFL ICOM DECL DECL DETI DECL OCOM VPSI 05907-042 05907-039 AD8368 The choice of C is a compromise of averaging time constant, DETO STABILITY AND LAYOUT CONSIDERATIONS response time, and carrier leakage. If C is selected to be too DETO In some applications, the printed circuit board (PCB) parasitic, in small to speed up the response time, the AGC loop could start combination with the source impedance presented by the driving tracking and leveling any amplitude envelope and corrupt the stage, can present some troublesome impedance at high frequency constellation. Figure 38 illustrates a 16 QAM, 100 ksymbols per and can potentially unstablize the amplifier under certain extreme second constellation with a degraded error vector magnitude conditions, such as high gain and high temperature. To avoid such (EVM) of 5%. By increasing CDETO to 0.01 μF, the EVM is scenarios, it is recommended to include a simple parallel RL improved to 1.1%. snubbing network directly at the input terminal of the AD8368. 16 QAM SR 10kHz MEAS SIGNAL Figure 40 depicts an example of this network. The RL network REF –4.9dBm CF 100MHz CONST DIAG formed by R3 and L1 is used to minimize the negative impact 1U due to reflective source conditions at high RF frequencies and ensures the amplifier operates unconditionally stable and maintains the typical device performance. On the underside of the chip scale package, there is an exposed compressed paddle. This paddle is internally connected to the ground of the chip. Solder the paddle to the low impedance ground plane on the PCB to ensure specified electrical performance and to provide thermal relief. It is also recommended that the ground planes on all layers under the paddle be stitched together with vias to reduce thermal impedance. –1U –1.31289U 262.578mU/ 1.31289U Figure 38. Degraded Error Vector Magnitude Performance for 16 QAM at 100 ksymbols per second (C Too Small) DETO Figure 39 illustrates the measured EVM performance for a 16 QAM modulation at 10 Msymbols per second using CDETO = 1 nF. 10 9 8 7 6 5 4 3 2 1 0 –40 –30 –20 –10 0 10 20 POWER IN (dBm) Figure 39. Error Vector Magnitude Performance for 16 QAM 10 Msymbols per second Rev. B | Page 16 of 20 EVM (%) 05907-040 05907-041 AD8368 EVALUATION BOARD The standard evaluation board schematic and layout artwork is presented in Figure 41 through Figure 44. The evaluation board is fabricated on a multilayer FR-4 board, with 50 Ω-controlled impedance transmission lines for the RF input and output traces. The board is powered by a single supply in the 4.5 V to 5.5 V range. The power supply is decoupled by 0.1 μF and 1 nF capacitors at each power supply pin. Additional decoupling, in the form of a series resistor or inductor at the supply pins, can also be added. Table 6 details the various configuration options of the evaluation board. VPOS C20 C2 1nF 5.6pF VPOS1 VPOS2 VPOS3 R3 215Ω C IN VPOS2 R11 INPUT 10nF 0Ω INPT VPSI C11 C14 L1 R1 1nF 0.1µF 10nH ICOM VPSI 10kΩ SW1 VPOS3 R12 LOW MODE VPSO 0Ω AD8368 HI C C12 C15 VPSI VPSO VPOS1 OUT R10 OUTPUT 1nF 0.1µF 10nF 0Ω VPSI OUTP C13 ON SW2 0.1µF ENBL OCOM C10 OFF ENABLE 1nF R2 10kΩ GAIN R31 GAIN OPEN C23 10nF JP4 DET_OUT_TP R32 OPEN DET_IN R35 R30 C1 C6 C4 OPEN OPEN OPEN 1nF 1nF Figure 40. Evaluation Board Table 6. Evaluation Board Configuration Options Component Function Default Conditions R1, R2, R3, L1 Pull-Down Resistors for MODE and ENBL. RL network. Prevent potential instability impact R1 = R2 = 10 kΩ due to PCB parasitics and/or certain extreme conditions (see the Stability and Layout R3 = 215 Ω Considerations section). L1 = 10 nH R10, R11, R12, Supply Decoupling. Jumpers, power supply decoupling resistors, and filter capacitors. R10 = R11 = R12 = 0 Ω C10, C11, C12, C10 = C11 = C12 = 1 nF C13, C14, C15 C13 = C14 = C15 = 0.1 μF CIN RF Input. CIN provides dc block for RF input. CIN = 10 nF COUT RF Output. COUT provides dc block for RF output. COUT = 10 nF R31, R32 Feedback Path for AGC Operation. For a default setpoint of 63 mV rms, set R31 = 0 Ω and R31 = R32 = Open remove R32. For other AGC setpoints, rms voltage = (1 + n) × 63 mV rms, where n = R31/R32. (VGA mode) R35 Populate with 0 Ω to feed detector output RSSI voltage to DET_OUT_TP. R35 = Open C23 Sets the corner frequency of the output offset control loop high-pass filter. C23 = 10 nF C1, R30 Used for driving the detector externally. Set R30 to 50 Ω for matching. Set C1 to be a large C1 = Open ac coupling capacitor. R30 = Open C6 DETO Capacitor. Needs to be made larger for lower data rates (see the AGC Operation section). C6 = 1 nF C20, C2, C4 DECL Capacitor. Needs to be adjusted based on RF frequency in AGC operation (see the C20 = C4 = 1 nF AGC Operation section). C2 = 5.6 pF Rev. B | Page 17 of 20 GAIN ICOM DETO ICOM HPFL ICOM DECL DECL DETI DECL OCOM VPSI 05907-043 AD8368 Component Function Default Conditions JP4 Jumper for AGC Mode of Operation. Provides feedback from the detector output to the JP4 = not populated gain pin. (VGA mode) SW1 Mode Switch. Low mode puts the part in gain-down mode. High mode puts the part in SW1 = JP2 gain-up mode. AGC operation requires gain-down mode. SW2 Power-Down. The part is disabled when the enable pin is tied to ground. SW2 = JP3 Figure 41. Component Side Silkscreen Figure 43. Component Side Layout Figure 44. Circuit Side Layout Figure 42. Circuit Side Silkscreen Rev. B | Page 18 of 20 05907-045 05907-044 05907-047 05907-046 AD8368 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 1 19 24 18 0.50 PIN 1 2.65 BSC TOP INDICATOR 3.75 EXPOSED 2.50 SQ VIEW BSC SQ PA D (BOTTOMVIEW) 2.35 0.50 6 13 0.40 12 7 0.30 0.23 MIN 0.80 MAX 2.50 REF 1.00 12° MAX 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.30 COPLANARITY THE PIN CONFIGURATION AND 0.20 REF 0.08 FUNCTION DESCRIPTIONS 0.23 SEATING SECTION OF THIS DATA SHEET. 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8 Figure 45. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-24-3) Dimensions shown in millimeters ORDERING GUIDE Ordering Model Temperature Range Package Description Package Option Quantity 1 AD8368ACPZ-REEL7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-24-3 1,500 1, 2 AD8368ACPZ-WP −40°C to +85°C 24-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-24-3 64 1 AD8368-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. 2 WP = waffle pack. Rev. B | Page 19 of 20 082908-A AD8368 NOTES ©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05907-0-9/08(B) Rev. B | Page 20 of 20